Wed, 24 Aug 2016 15:38:31 +0800
Add salI_RegL2I_imm in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Tue Aug 23 17:00:34 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Aug 24 15:38:31 2016 +0800 1.3 @@ -9091,6 +9091,24 @@ 1.4 ins_pipe( ialu_regI_regI ); 1.5 %} 1.6 1.7 +instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{ 1.8 + match(Set dst (LShiftI (ConvL2I src) shift)); 1.9 + 1.10 + format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %} 1.11 + ins_encode %{ 1.12 + Register src = $src$$Register; 1.13 + Register dst = $dst$$Register; 1.14 + int shamt = $shift$$constant; 1.15 + 1.16 + if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt); 1.17 + else { 1.18 + __ move(AT, shamt); 1.19 + __ sllv(dst, src, AT); 1.20 + } 1.21 + %} 1.22 + ins_pipe( ialu_regI_regI ); 1.23 +%} 1.24 + 1.25 // Shift Left by 8-bit immediate 1.26 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ 1.27 match(Set dst (LShiftI src shift));