Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
instruction scheduling optimization.
Wed, 03 Aug 2016 01:02:20 +0800
- author
- fujie
- date
- Wed, 03 Aug 2016 01:02:20 +0800
- changeset 50
- 372313324431
- parent 49
- 76cea9141c9d
- child 51
- 9434ecde44bf
instruction scheduling optimization.
| src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Tue Aug 02 17:02:38 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Aug 03 01:02:20 2016 +0800 1.3 @@ -4399,10 +4399,12 @@ 1.4 attributes %{ 1.5 fixed_size_instructions; // Fixed size instructions 1.6 branch_has_delay_slot; // branch have delay slot in gs2 1.7 - max_instructions_per_bundle = 4; // Up to 5 instructions per bundle 1.8 + max_instructions_per_bundle = 1; // 1 instruction per bundle 1.9 + max_bundles_per_cycle = 4; // Up to 4 bundles per cycle 1.10 + bundle_unit_size=4; 1.11 instruction_unit_size = 4; // An instruction is 4 bytes long 1.12 - instruction_fetch_unit_size = 32; // The processor fetches one line 1.13 - instruction_fetch_units = 1; // of 32 bytes 1.14 + instruction_fetch_unit_size = 16; // The processor fetches one line 1.15 + instruction_fetch_units = 1; // of 16 bytes 1.16 1.17 // List of nop instructions 1.18 nops( MachNop ); 1.19 @@ -4411,288 +4413,281 @@ 1.20 //----------RESOURCES---------------------------------------------------------- 1.21 // Resources are the functional units available to the machine 1.22 1.23 - // godson2c pipeline 1.24 - // 4 decoders, a "bundle" is the limit 4 instructions decoded per cycle 1.25 - // 1 load/store ops per cycle, 1 branch, 2 FPU, 1.26 - // 2 ALU op, only ALU0 handles mul/div instructions. 1.27 - resources( D0, D1, D2, D3, DECODE = D0 | D1 | D2 | D3, 1.28 - MEM, BR, FPU0, FPU1, FPU = FPU0 | FPU1, 1.29 - ALU0, ALU1, ALU = ALU0 | ALU1 ); 1.30 - 1.31 + resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR); 1.32 + 1.33 //----------PIPELINE DESCRIPTION----------------------------------------------- 1.34 // Pipeline Description specifies the stages in the machine's pipeline 1.35 - 1.36 - // godson 2c pipeline 1.37 - // i dont know the detail of the godson 2c pipeline, leave it blank now. 1.38 - // by yjl 2/21/2006 1.39 - pipe_desc(S0, S1, S2, S3, S4, S5, S6); 1.40 - 1.41 + 1.42 + // IF: fetch 1.43 + // ID: decode 1.44 + // RD: read 1.45 + // CA: caculate 1.46 + // WB: write back 1.47 + // CM: commit 1.48 + 1.49 + pipe_desc(IF, ID, RD, CA, WB, CM); 1.50 + 1.51 + 1.52 //----------PIPELINE CLASSES--------------------------------------------------- 1.53 // Pipeline Classes describe the stages in which input and output are 1.54 // referenced by the hardware pipeline. 1.55 + 1.56 + //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2 1.57 + pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{ 1.58 + single_instruction; 1.59 + src1 : RD(read); 1.60 + src2 : RD(read); 1.61 + dst : WB(write)+1; 1.62 + DECODE : ID; 1.63 + ALU : CA; 1.64 + %} 1.65 + 1.66 + //No.19 Integer mult operation : dst <-- reg1 mult reg2 1.67 + pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{ 1.68 + src1 : RD(read); 1.69 + src2 : RD(read); 1.70 + dst : WB(write)+5; 1.71 + DECODE : ID; 1.72 + ALU2 : CA; 1.73 + %} 1.74 + 1.75 + pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{ 1.76 + src1 : RD(read); 1.77 + src2 : RD(read); 1.78 + dst : WB(write)+10; 1.79 + DECODE : ID; 1.80 + ALU2 : CA; 1.81 + %} 1.82 + 1.83 + //No.19 Integer div operation : dst <-- reg1 div reg2 1.84 + pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{ 1.85 + src1 : RD(read); 1.86 + src2 : RD(read); 1.87 + dst : WB(write)+10; 1.88 + DECODE : ID; 1.89 + ALU2 : CA; 1.90 + %} 1.91 + 1.92 + //No.19 Integer mod operation : dst <-- reg1 mod reg2 1.93 + pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{ 1.94 + instruction_count(2); 1.95 + src1 : RD(read); 1.96 + src2 : RD(read); 1.97 + dst : WB(write)+10; 1.98 + DECODE : ID; 1.99 + ALU2 : CA; 1.100 + %} 1.101 + 1.102 + //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2 1.103 + pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{ 1.104 + instruction_count(2); 1.105 + src1 : RD(read); 1.106 + src2 : RD(read); 1.107 + dst : WB(write); 1.108 + DECODE : ID; 1.109 + ALU : CA; 1.110 + %} 1.111 + 1.112 + //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16 1.113 + pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{ 1.114 + instruction_count(2); 1.115 + src : RD(read); 1.116 + dst : WB(write); 1.117 + DECODE : ID; 1.118 + ALU : CA; 1.119 + %} 1.120 + 1.121 + //no.16 load Long from memory : 1.122 + pipe_class ialu_loadL(mRegL dst, memory mem) %{ 1.123 + instruction_count(2); 1.124 + mem : RD(read); 1.125 + dst : WB(write)+5; 1.126 + DECODE : ID; 1.127 + MEM : RD; 1.128 + %} 1.129 + 1.130 + //No.17 Store Long to Memory : 1.131 + pipe_class ialu_storeL(mRegL src, memory mem) %{ 1.132 + instruction_count(2); 1.133 + mem : RD(read); 1.134 + src : RD(read); 1.135 + DECODE : ID; 1.136 + MEM : RD; 1.137 + %} 1.138 + 1.139 + //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16 1.140 + pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{ 1.141 + single_instruction; 1.142 + src : RD(read); 1.143 + dst : WB(write); 1.144 + DECODE : ID; 1.145 + ALU : CA; 1.146 + %} 1.147 + 1.148 + //No.3 Integer move operation : dst <-- reg 1.149 + pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{ 1.150 + src : RD(read); 1.151 + dst : WB(write); 1.152 + DECODE : ID; 1.153 + ALU : CA; 1.154 + %} 1.155 1.156 - // COMPILE SKIPPED 1.157 - // Then: _reg 1.158 - // Then: _reg if there is a 2nd register 1.159 - // Then: _long if it's a pair of instructions implementing a long 1.160 - // Then: _fat if it requires the big decoder 1.161 - // Or: _mem if it requires the big decoder and a memory unit. 1.162 - 1.163 - // Integer Load from Memory 1.164 - pipe_class ialu_reg_mem(memory mem, mRegI src) %{ 1.165 - single_instruction; 1.166 - mem : S3(read); 1.167 - src : S5(read); 1.168 - D0 : S0; // big decoder only 1.169 - ALU : S4; // any alu 1.170 - MEM : S3; 1.171 -%} 1.172 - 1.173 -// Integer ALU reg operation 1.174 -pipe_class ialu_reg(mRegI dst) %{ 1.175 - single_instruction; 1.176 - dst : S4(write); 1.177 - dst : S3(read); 1.178 - DECODE : S0; // any decoder 1.179 - ALU : S3; // any alu 1.180 -%} 1.181 - 1.182 -// Long ALU reg-mem operation 1.183 -pipe_class ialu_reg_long_mem(mRegL dst, memory mem) %{ 1.184 - instruction_count(2); 1.185 - dst : S5(write); 1.186 - mem : S3(read); 1.187 - D0 : S0(2); // big decoder only; twice 1.188 - ALU : S4(2); // any 2 alus 1.189 - MEM : S3(2); // both mems 1.190 -%} 1.191 - 1.192 -// Integer ALU reg-reg operation 1.193 -pipe_class ialu_reg_reg(mRegI dst, mRegI src1, mRegI src2) %{ 1.194 - single_instruction; 1.195 - dst : S4(write); 1.196 - src1 : S3(read); 1.197 - src2 : S3(read); 1.198 - DECODE : S0; // any decoder 1.199 - ALU : S3; // any alu 1.200 -%} 1.201 - 1.202 -// Integer ALU reg-reg operation 1.203 -pipe_class ialu_reg_imm(mRegI dst, mRegI src1, immI src2) %{ 1.204 - single_instruction; 1.205 - dst : S4(write); 1.206 - src1 : S3(read); 1.207 - DECODE : S0; // any decoder 1.208 - ALU : S3; // any alu 1.209 -%} 1.210 - 1.211 -// Integer ALU0 reg-reg operation 1.212 -pipe_class ialu_reg_reg_alu0(mRegI dst, mRegI src1, mRegI src2) %{ 1.213 - single_instruction; 1.214 - dst : S4(write); 1.215 - src1 : S3(read); 1.216 - src2 : S3(read); 1.217 - D0 : S0; // Big decoder only 1.218 - ALU0 : S3; // only alu0 1.219 -%} 1.220 - 1.221 -// Integer ALU reg-mem operation 1.222 -pipe_class ialu_reg_reg_mem(mRegI dst,mRegI src1, memory src2) %{ 1.223 - single_instruction; 1.224 - dst : S4(write); 1.225 - src1 : S3(read); 1.226 - src2 : S3(read); 1.227 - D0 : S0; // big decoder only 1.228 - ALU : S4; // any alu 1.229 - MEM : S3; 1.230 -%} 1.231 - 1.232 - 1.233 - // Float reg-mem operation 1.234 -pipe_class fpu_reg_mem(regD dst, memory mem) %{ 1.235 - instruction_count(2); 1.236 - dst : S5(write); 1.237 - mem : S3(read); 1.238 - D0 : S0; // big decoder only 1.239 - DECODE : S1; // any decoder for FPU POP 1.240 - FPU : S4; 1.241 - MEM : S3; // any mem 1.242 -%} 1.243 - 1.244 - 1.245 -// Float reg-reg operation 1.246 -pipe_class fpu_reg_reg(regD dst, regD src1, regD src2) %{ 1.247 - instruction_count(2); 1.248 - dst : S4(write); 1.249 - src1 : S3(read); 1.250 - src2 : S3(read); 1.251 - DECODE : S0(2); // any 2 decoders 1.252 - FPU : S3; 1.253 -%} 1.254 - 1.255 - 1.256 -// Long ALU reg operation using big decoder 1.257 -pipe_class ialu_reg_long_fat(mRegL dst) %{ 1.258 - instruction_count(2); 1.259 - dst : S4(write); 1.260 - dst : S3(read); 1.261 - D0 : S0(2); // big decoder only; twice 1.262 - ALU : S3(2); // any 2 alus 1.263 -%} 1.264 - 1.265 -// UnConditional branch 1.266 -pipe_class pipe_jmp( label labl ) %{ 1.267 - single_instruction; 1.268 - BR : S3; 1.269 -%} 1.270 - 1.271 - 1.272 -// Integer ALU reg operation using big decoder 1.273 -pipe_class ialu_reg_fat(mRegI dst) %{ 1.274 - single_instruction; 1.275 - dst : S4(write); 1.276 - dst : S3(read); 1.277 - D0 : S0; // big decoder only 1.278 - ALU : S3; // any alu 1.279 -%} 1.280 - 1.281 -// Conditional branch 1.282 -pipe_class pipe_branchP( cmpOp cmp, mRegP op1, mRegP op2, label labl ) %{ 1.283 - single_instruction; 1.284 - op1 : S1(read); 1.285 - op2 : S1(read); 1.286 - BR : S3; 1.287 -%} 1.288 - 1.289 -// Generic big/slow expanded idiom 1.290 -pipe_class pipe_slow( ) %{ 1.291 - instruction_count(10); multiple_bundles; force_serialization; 1.292 - fixed_latency(100); 1.293 - D0 : S0(2); 1.294 - MEM : S3(2); 1.295 -%} 1.296 - 1.297 -pipe_class ialu_mem_reg(memory mem, mRegI src) %{ 1.298 - single_instruction; 1.299 - mem : S3(read); 1.300 - src : S5(read); 1.301 - D0 : S0; // big decoder only 1.302 - ALU : S4; // any alu 1.303 - MEM : S3; 1.304 -%} 1.305 - 1.306 - 1.307 -// Integer ALU operation 1.308 -pipe_class ialu_none(mRegI dst) %{ 1.309 - single_instruction; 1.310 - dst : S5(write); 1.311 - ALU : S4; 1.312 -%} 1.313 - 1.314 -// Integer Store to Memory 1.315 -pipe_class ialu_mem_imm(memory mem) %{ 1.316 - single_instruction; 1.317 - mem : S3(read); 1.318 - D0 : S0; // big decoder only 1.319 - ALU : S4; // any alu 1.320 - MEM : S3; 1.321 -%} 1.322 - 1.323 -// Float load constant 1.324 -pipe_class fpu_reg_con(regD dst) %{ 1.325 - instruction_count(2); 1.326 - dst : S5(write); 1.327 - D0 : S0; // big decoder only for the load 1.328 - DECODE : S1; // any decoder for FPU POP 1.329 - FPU : S4; 1.330 - MEM : S3; // any mem 1.331 -%} 1.332 - 1.333 -// Float mem-reg operation 1.334 -pipe_class fpu_mem_reg(memory mem, regD src) %{ 1.335 - instruction_count(2); 1.336 - src : S5(read); 1.337 - mem : S3(read); 1.338 - DECODE : S0; // any decoder for FPU PUSH 1.339 - D0 : S1; // big decoder only 1.340 - FPU : S4; 1.341 - MEM : S3; // any mem 1.342 -%} 1.343 - 1.344 -// Conditional branch 1.345 -pipe_class pipe_jcc( cmpOp cmp, FlagsReg cr, label labl ) %{ 1.346 - single_instruction; 1.347 - cr : S1(read); 1.348 - BR : S3; 1.349 -%} 1.350 - 1.351 -// Allocation idiom 1.352 -pipe_class pipe_cmpxchg( mRegP dst, mRegP heap_ptr ) %{ 1.353 - instruction_count(1); force_serialization; 1.354 - fixed_latency(6); 1.355 - heap_ptr : S3(read); 1.356 - DECODE : S0(3); 1.357 - D0 : S2; 1.358 - MEM : S3; 1.359 - ALU : S3(2); 1.360 - dst : S5(write); 1.361 - BR : S5; 1.362 -%} 1.363 - 1.364 - 1.365 -// The real do-nothing guy 1.366 -pipe_class empty( ) %{ 1.367 - instruction_count(0); 1.368 -%} 1.369 - 1.370 - 1.371 - // Long Store to Memory 1.372 - pipe_class ialu_mem_long_reg(memory mem, mRegL src) %{ 1.373 - instruction_count(2); 1.374 - mem : S3(read); 1.375 - src : S5(read); 1.376 - D0 : S0(2); // big decoder only; twice 1.377 - ALU : S4(2); // any 2 alus 1.378 - MEM : S3(2); // Both mems 1.379 - %} 1.380 - 1.381 - // Long ALU reg-reg operation 1.382 - pipe_class ialu_reg_reg_long(mRegL dst, mRegL src) %{ 1.383 - instruction_count(2); 1.384 - dst : S4(write); 1.385 - src : S3(read); 1.386 - DECODE : S0(2); // any 2 decoders 1.387 - ALU : S3(2); // both alus 1.388 - %} 1.389 - 1.390 -// Long ALU reg operation 1.391 -pipe_class ialu_reg_long(mRegL dst, mRegL src) %{ 1.392 - instruction_count(2); 1.393 - dst : S4(write); 1.394 - src : S3(read); 1.395 - DECODE : S0(2); // any 2 decoders 1.396 - ALU : S3(2); // both alus 1.397 -%} 1.398 - 1.399 - 1.400 -// Conditional move reg-reg 1.401 -pipe_class pipe_cmov_reg( mRegI dst, mRegI src ) %{ 1.402 - single_instruction; 1.403 - dst : S4(write); 1.404 - src : S3(read); 1.405 - DECODE : S0; // any decoder 1.406 -%} 1.407 - 1.408 -// Conditional move reg-reg long 1.409 -pipe_class pipe_cmov_reg_long(mRegL dst, mRegL src) %{ 1.410 - single_instruction; 1.411 - dst : S4(write); 1.412 - src : S3(read); 1.413 - DECODE : S0(2); // any 2 decoders 1.414 -%} 1.415 - 1.416 -%} 1.417 - 1.418 + //No.4 No instructions : do nothing 1.419 + pipe_class empty( ) %{ 1.420 + instruction_count(0); 1.421 + %} 1.422 + 1.423 + //No.5 UnConditional branch : 1.424 + pipe_class pipe_jump( label labl ) %{ 1.425 + multiple_bundles; 1.426 + DECODE : ID; 1.427 + BR : RD; 1.428 + %} 1.429 + 1.430 + //No.6 ALU Conditional branch : 1.431 + pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{ 1.432 + multiple_bundles; 1.433 + src1 : RD(read); 1.434 + src2 : RD(read); 1.435 + DECODE : ID; 1.436 + BR : RD; 1.437 + %} 1.438 + 1.439 + //no.7 load integer from memory : 1.440 + pipe_class ialu_loadI(mRegI dst, memory mem) %{ 1.441 + mem : RD(read); 1.442 + dst : WB(write)+3; 1.443 + DECODE : ID; 1.444 + MEM : RD; 1.445 + %} 1.446 + 1.447 + //No.8 Store Integer to Memory : 1.448 + pipe_class ialu_storeI(mRegI src, memory mem) %{ 1.449 + mem : RD(read); 1.450 + src : RD(read); 1.451 + DECODE : ID; 1.452 + MEM : RD; 1.453 + %} 1.454 + 1.455 + 1.456 + //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2 1.457 + pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{ 1.458 + src1 : RD(read); 1.459 + src2 : RD(read); 1.460 + dst : WB(write); 1.461 + DECODE : ID; 1.462 + FPU : CA; 1.463 + %} 1.464 + 1.465 + //No.22 Floating div operation : dst <-- reg1 div reg2 1.466 + pipe_class fpu_div(regF dst, regF src1, regF src2) %{ 1.467 + src1 : RD(read); 1.468 + src2 : RD(read); 1.469 + dst : WB(write); 1.470 + DECODE : ID; 1.471 + FPU2 : CA; 1.472 + %} 1.473 + 1.474 + pipe_class fcvt_I2D(regD dst, mRegI src) %{ 1.475 + src : RD(read); 1.476 + dst : WB(write); 1.477 + DECODE : ID; 1.478 + FPU1 : CA; 1.479 + %} 1.480 + 1.481 + pipe_class fcvt_D2I(mRegI dst, regD src) %{ 1.482 + src : RD(read); 1.483 + dst : WB(write); 1.484 + DECODE : ID; 1.485 + FPU1 : CA; 1.486 + %} 1.487 + 1.488 + pipe_class pipe_mfc1(mRegI dst, regD src) %{ 1.489 + src : RD(read); 1.490 + dst : WB(write); 1.491 + DECODE : ID; 1.492 + MEM : RD; 1.493 + %} 1.494 + 1.495 + pipe_class pipe_mtc1(regD dst, mRegI src) %{ 1.496 + src : RD(read); 1.497 + dst : WB(write); 1.498 + DECODE : ID; 1.499 + MEM : RD(5); 1.500 + %} 1.501 + 1.502 + //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2 1.503 + pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{ 1.504 + multiple_bundles; 1.505 + src1 : RD(read); 1.506 + src2 : RD(read); 1.507 + dst : WB(write); 1.508 + DECODE : ID; 1.509 + FPU2 : CA; 1.510 + %} 1.511 + 1.512 + //No.11 Load Floating from Memory : 1.513 + pipe_class fpu_loadF(regF dst, memory mem) %{ 1.514 + instruction_count(1); 1.515 + mem : RD(read); 1.516 + dst : WB(write)+3; 1.517 + DECODE : ID; 1.518 + MEM : RD; 1.519 + %} 1.520 + 1.521 + //No.12 Store Floating to Memory : 1.522 + pipe_class fpu_storeF(regF src, memory mem) %{ 1.523 + instruction_count(1); 1.524 + mem : RD(read); 1.525 + src : RD(read); 1.526 + DECODE : ID; 1.527 + MEM : RD; 1.528 + %} 1.529 + 1.530 + //No.13 FPU Conditional branch : 1.531 + pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{ 1.532 + multiple_bundles; 1.533 + src1 : RD(read); 1.534 + src2 : RD(read); 1.535 + DECODE : ID; 1.536 + BR : RD; 1.537 + %} 1.538 + 1.539 +//No.14 Floating FPU reg operation : dst <-- op reg 1.540 + pipe_class fpu1_regF(regF dst, regF src) %{ 1.541 + src : RD(read); 1.542 + dst : WB(write); 1.543 + DECODE : ID; 1.544 + FPU : CA; 1.545 + %} 1.546 + 1.547 + pipe_class long_memory_op() %{ 1.548 + instruction_count(10); multiple_bundles; force_serialization; 1.549 + fixed_latency(30); 1.550 + %} 1.551 + 1.552 + pipe_class simple_call() %{ 1.553 + instruction_count(10); multiple_bundles; force_serialization; 1.554 + fixed_latency(200); 1.555 + BR : RD; 1.556 + %} 1.557 + 1.558 + pipe_class call() %{ 1.559 + instruction_count(10); multiple_bundles; force_serialization; 1.560 + fixed_latency(200); 1.561 + %} 1.562 + 1.563 + //FIXME: 1.564 + //No.9 Piple slow : for multi-instructions 1.565 + pipe_class pipe_slow( ) %{ 1.566 + instruction_count(20); 1.567 + force_serialization; 1.568 + multiple_bundles; 1.569 + fixed_latency(50); 1.570 + %} 1.571 + 1.572 +%} 1.573 + 1.574 1.575 1.576 //----------INSTRUCTIONS------------------------------------------------------- 1.577 @@ -4724,7 +4719,7 @@ 1.578 ins_cost(125); 1.579 format %{ "lw $dst, $mem #@loadI" %} 1.580 ins_encode (load_I_enc(dst, mem)); 1.581 - ins_pipe( ialu_reg_mem ); 1.582 + ins_pipe( ialu_loadI ); 1.583 %} 1.584 1.585 // Load Long. 1.586 @@ -4735,7 +4730,7 @@ 1.587 ins_cost(250); 1.588 format %{ "ld $dst, $mem #@loadL" %} 1.589 ins_encode(load_L_enc(dst, mem)); 1.590 - ins_pipe( ialu_reg_long_mem ); 1.591 + ins_pipe( ialu_loadL ); 1.592 %} 1.593 1.594 // Load Long - UNaligned 1.595 @@ -4746,7 +4741,7 @@ 1.596 ins_cost(450); 1.597 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %} 1.598 ins_encode(load_L_enc(dst, mem)); 1.599 - ins_pipe( ialu_reg_long_mem ); 1.600 + ins_pipe( ialu_loadL ); 1.601 %} 1.602 1.603 // Store Long 1.604 @@ -4757,7 +4752,7 @@ 1.605 ins_cost(200); 1.606 format %{ "sd $mem, $src #@storeL_reg\n" %} 1.607 ins_encode(store_L_reg_enc(mem, src)); 1.608 - ins_pipe( ialu_mem_long_reg ); 1.609 + ins_pipe( ialu_storeL ); 1.610 %} 1.611 1.612 //FIXME:volatile! atomic! 1.613 @@ -4806,7 +4801,7 @@ 1.614 } 1.615 1.616 %} 1.617 - ins_pipe( ialu_mem_long_reg ); 1.618 + ins_pipe( ialu_storeL ); 1.619 %} 1.620 1.621 instruct storeL_immL0(memory mem, immL0 zero) %{ 1.622 @@ -4815,7 +4810,7 @@ 1.623 ins_cost(180); 1.624 format %{ "sd $mem, zero #@storeL_immL0" %} 1.625 ins_encode(store_L_immL0_enc(mem, zero)); 1.626 - ins_pipe( ialu_mem_long_reg ); 1.627 + ins_pipe( ialu_storeL ); 1.628 %} 1.629 1.630 instruct storeL_imm(memory mem, immL src) %{ 1.631 @@ -4824,7 +4819,7 @@ 1.632 ins_cost(200); 1.633 format %{ "sw $mem, $src #@storeL_imm" %} 1.634 ins_encode(store_L_immL_enc(mem, src)); 1.635 - ins_pipe( ialu_mem_long_reg ); 1.636 + ins_pipe( ialu_storeL ); 1.637 %} 1.638 1.639 // Load Compressed Pointer 1.640 @@ -4841,7 +4836,7 @@ 1.641 %} 1.642 */ 1.643 ins_encode (load_N_enc(dst, mem)); 1.644 - ins_pipe(ialu_reg_mem); // XXX 1.645 + ins_pipe( ialu_loadI ); // XXX 1.646 %} 1.647 1.648 // Load Pointer 1.649 @@ -4851,7 +4846,7 @@ 1.650 ins_cost(125); 1.651 format %{ "ld $dst, $mem #@loadP" %} 1.652 ins_encode (load_P_enc(dst, mem)); 1.653 - ins_pipe( ialu_reg_mem ); 1.654 + ins_pipe( ialu_loadI ); 1.655 %} 1.656 1.657 // Load Klass Pointer 1.658 @@ -4861,7 +4856,7 @@ 1.659 ins_cost(125); 1.660 format %{ "MOV $dst,$mem @ loadKlass" %} 1.661 ins_encode (load_P_enc(dst, mem)); 1.662 - ins_pipe( ialu_reg_mem ); 1.663 + ins_pipe( ialu_loadI ); 1.664 %} 1.665 1.666 // Load narrow Klass Pointer 1.667 @@ -4877,7 +4872,7 @@ 1.668 __ lwu($dst$$Register, $mem$$Address); 1.669 %} 1.670 */ 1.671 - ins_pipe(ialu_reg_mem); // XXX 1.672 + ins_pipe( ialu_loadI ); // XXX 1.673 %} 1.674 1.675 // Load Constant 1.676 @@ -4890,7 +4885,7 @@ 1.677 int value = $src$$constant; 1.678 __ move(dst, value); 1.679 %} 1.680 - ins_pipe( ialu_reg_fat ); 1.681 + ins_pipe( ialu_regI_regI ); 1.682 %} 1.683 1.684 1.685 @@ -4904,7 +4899,7 @@ 1.686 Register dst_reg = as_Register($dst$$reg); 1.687 __ li(dst_reg, (long)$src$$constant); 1.688 %} 1.689 - ins_pipe( ialu_reg_long_fat ); 1.690 + ins_pipe( ialu_regL_regL ); 1.691 %} 1.692 1.693 1.694 @@ -4915,7 +4910,7 @@ 1.695 ins_cost(125); 1.696 format %{ "MOV $dst,$mem @ loadRange" %} 1.697 ins_encode(load_I_enc(dst, mem)); 1.698 - ins_pipe( ialu_reg_mem ); 1.699 + ins_pipe( ialu_loadI ); 1.700 %} 1.701 1.702 1.703 @@ -4925,7 +4920,7 @@ 1.704 ins_cost(125); 1.705 format %{ "sd $src, $mem #@storeP" %} 1.706 ins_encode(store_P_reg_enc(mem, src)); 1.707 - ins_pipe( ialu_mem_reg ); 1.708 + ins_pipe( ialu_storeI ); 1.709 %} 1.710 1.711 /* 1.712 @@ -4951,7 +4946,7 @@ 1.713 ins_cost(150); 1.714 format %{ "mov $mem, $src #@storeImmP" %} 1.715 ins_encode(store_P_immP_enc(mem, src)); 1.716 - ins_pipe( ialu_mem_imm ); 1.717 + ins_pipe( ialu_storeI ); 1.718 %} 1.719 1.720 // Store Byte Immediate 1.721 @@ -4961,7 +4956,7 @@ 1.722 ins_cost(150); 1.723 format %{ "movb $mem, $src #@storeImmB" %} 1.724 ins_encode(store_B_immI_enc(mem, src)); 1.725 - ins_pipe( ialu_mem_imm ); 1.726 + ins_pipe( ialu_storeI ); 1.727 %} 1.728 1.729 // Store Compressed Pointer 1.730 @@ -4972,7 +4967,7 @@ 1.731 ins_cost(125); // XXX 1.732 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %} 1.733 ins_encode(store_N_reg_enc(mem, src)); 1.734 - ins_pipe(ialu_mem_reg); 1.735 + ins_pipe( ialu_storeI ); 1.736 %} 1.737 1.738 instruct storeNKlass(memory mem, mRegN src) 1.739 @@ -4982,7 +4977,7 @@ 1.740 ins_cost(125); // XXX 1.741 format %{ "sw $mem, $src\t# compressed klass ptr" %} 1.742 ins_encode(store_N_reg_enc(mem, src)); 1.743 - ins_pipe(ialu_mem_reg); 1.744 + ins_pipe( ialu_storeI ); 1.745 %} 1.746 1.747 instruct storeImmN0(memory mem, immN0 zero) 1.748 @@ -4993,7 +4988,7 @@ 1.749 ins_cost(125); // XXX 1.750 format %{ "storeN0 $mem, R12\t# compressed ptr (R12_heapbase==0)" %} 1.751 ins_encode(storeImmN0_enc(mem, zero)); 1.752 - ins_pipe(ialu_mem_reg); 1.753 + ins_pipe( ialu_storeI ); 1.754 %} 1.755 1.756 instruct storeImmN(memory mem, immN src) 1.757 @@ -5003,7 +4998,7 @@ 1.758 ins_cost(150); // XXX 1.759 format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %} 1.760 ins_encode(storeImmN_enc(mem, src)); 1.761 - ins_pipe(ialu_mem_imm); 1.762 + ins_pipe( ialu_storeI ); 1.763 %} 1.764 1.765 instruct storeImmNKlass(memory mem, immNKlass src) 1.766 @@ -5013,7 +5008,7 @@ 1.767 ins_cost(150); // XXX 1.768 format %{ "sw $mem, $src\t# compressed klass ptr" %} 1.769 ins_encode(storeImmNKlass_enc(mem, src)); 1.770 - ins_pipe(ialu_mem_imm); 1.771 + ins_pipe( ialu_storeI ); 1.772 %} 1.773 1.774 // Store Byte 1.775 @@ -5023,7 +5018,7 @@ 1.776 ins_cost(125); 1.777 format %{ "sb $src, $mem #@storeB" %} 1.778 ins_encode(store_B_reg_enc(mem, src)); 1.779 - ins_pipe( ialu_mem_reg ); 1.780 + ins_pipe( ialu_storeI ); 1.781 %} 1.782 1.783 // Load Byte (8bit signed) 1.784 @@ -5033,7 +5028,7 @@ 1.785 ins_cost(125); 1.786 format %{ "lb $dst, $mem #@loadB" %} 1.787 ins_encode(load_B_enc(dst, mem)); 1.788 - ins_pipe( ialu_reg_mem ); 1.789 + ins_pipe( ialu_loadI ); 1.790 %} 1.791 1.792 // Load Byte (8bit UNsigned) 1.793 @@ -5043,7 +5038,7 @@ 1.794 ins_cost(125); 1.795 format %{ "lbu $dst, $mem #@loadUB" %} 1.796 ins_encode(load_UB_enc(dst, mem)); 1.797 - ins_pipe( ialu_reg_mem ); 1.798 + ins_pipe( ialu_loadI ); 1.799 %} 1.800 1.801 // Load Short (16bit signed) 1.802 @@ -5053,7 +5048,7 @@ 1.803 ins_cost(125); 1.804 format %{ "lh $dst, $mem #@loadS" %} 1.805 ins_encode(load_S_enc(dst, mem)); 1.806 - ins_pipe( ialu_reg_mem ); 1.807 + ins_pipe( ialu_loadI ); 1.808 %} 1.809 1.810 //TODO: check if it is necessery to do 'prefetch' in the future(which means never). LEE 1.811 @@ -5074,7 +5069,7 @@ 1.812 ins_cost(150); 1.813 format %{ "mov $mem, $src #@storeImmI" %} 1.814 ins_encode(store_I_immI_enc(mem, src)); 1.815 - ins_pipe( ialu_mem_imm ); 1.816 + ins_pipe( ialu_storeI ); 1.817 %} 1.818 1.819 // Store Integer 1.820 @@ -5084,7 +5079,7 @@ 1.821 ins_cost(125); 1.822 format %{ "sw $mem, $src #@storeI" %} 1.823 ins_encode(store_I_reg_enc(mem, src)); 1.824 - ins_pipe( ialu_mem_reg ); 1.825 + ins_pipe( ialu_storeI ); 1.826 %} 1.827 1.828 // Load Float 1.829 @@ -5094,7 +5089,7 @@ 1.830 ins_cost(150); 1.831 format %{ "loadF $dst, $mem #@loadF" %} 1.832 ins_encode(load_F_enc(dst, mem)); 1.833 - ins_pipe( fpu_reg_mem ); 1.834 + ins_pipe( ialu_loadI ); 1.835 %} 1.836 1.837 instruct loadConP(mRegP dst, immP src) %{ 1.838 @@ -5132,7 +5127,7 @@ 1.839 } 1.840 %} 1.841 1.842 - ins_pipe( ialu_reg_fat ); 1.843 + ins_pipe( ialu_regI_regI ); 1.844 %} 1.845 1.846 instruct loadConP0(mRegP dst, immP0 src) 1.847 @@ -5145,7 +5140,7 @@ 1.848 Register dst_reg = $dst$$Register; 1.849 __ move(dst_reg, R0); 1.850 %} 1.851 - ins_pipe(ialu_reg); 1.852 + ins_pipe( ialu_regI_regI ); 1.853 %} 1.854 1.855 instruct loadConN0(mRegN dst, immN0 src, FlagsReg cr) %{ 1.856 @@ -5155,7 +5150,7 @@ 1.857 ins_encode %{ 1.858 __ move($dst$$Register, R0); 1.859 %} 1.860 - ins_pipe(ialu_reg); 1.861 + ins_pipe( ialu_regI_regI ); 1.862 %} 1.863 1.864 instruct loadConN(mRegN dst, immN src) %{ 1.865 @@ -5185,7 +5180,7 @@ 1.866 } 1.867 } 1.868 %} 1.869 - ins_pipe(ialu_reg_fat); // XXX 1.870 + ins_pipe( ialu_regI_regI ); // XXX 1.871 %} 1.872 1.873 instruct loadConNKlass(mRegN dst, immNKlass src) %{ 1.874 @@ -5214,7 +5209,7 @@ 1.875 } 1.876 } 1.877 %} 1.878 - ins_pipe(ialu_reg_fat); // XXX 1.879 + ins_pipe( ialu_regI_regI ); // XXX 1.880 %} 1.881 1.882 /* 1.883 @@ -5297,7 +5292,7 @@ 1.884 __ nop(); 1.885 %} 1.886 1.887 - ins_pipe( pipe_jmp ); 1.888 + ins_pipe( pipe_jump ); 1.889 %} 1.890 1.891 // Create exception oop: created by stack-crawling runtime code. 1.892 @@ -5314,7 +5309,7 @@ 1.893 __ block_comment("CreateException is empty in X86/MIPS"); 1.894 %} 1.895 ins_pipe( empty ); 1.896 -// ins_pipe( pipe_jmp ); 1.897 +// ins_pipe( pipe_jump ); 1.898 %} 1.899 1.900 1.901 @@ -5438,7 +5433,7 @@ 1.902 __ jr(T9); 1.903 __ nop(); 1.904 %} 1.905 - ins_pipe( pipe_jmp ); 1.906 + ins_pipe( pipe_jump ); 1.907 %} 1.908 1.909 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{ 1.910 @@ -5505,7 +5500,7 @@ 1.911 %} 1.912 1.913 ins_pc_relative(1); 1.914 - ins_pipe(pipe_branchP); 1.915 + ins_pipe( pipe_alu_branch ); 1.916 %} 1.917 1.918 1.919 @@ -5572,7 +5567,7 @@ 1.920 %} 1.921 1.922 ins_pc_relative(1); 1.923 - ins_pipe(pipe_branchP); 1.924 + ins_pipe( pipe_alu_branch ); 1.925 %} 1.926 1.927 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{ 1.928 @@ -5609,7 +5604,7 @@ 1.929 %} 1.930 //TODO: pipe_branchP or create pipe_branchN LEE 1.931 ins_pc_relative(1); 1.932 - ins_pipe(pipe_branchP); 1.933 + ins_pipe( pipe_alu_branch ); 1.934 %} 1.935 1.936 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{ 1.937 @@ -5673,7 +5668,7 @@ 1.938 __ nop(); 1.939 %} 1.940 ins_pc_relative(1); 1.941 - ins_pipe(pipe_branchP); 1.942 + ins_pipe( pipe_alu_branch ); 1.943 %} 1.944 1.945 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{ 1.946 @@ -5736,7 +5731,7 @@ 1.947 %} 1.948 1.949 ins_pc_relative(1); 1.950 - ins_pipe(pipe_branchP); 1.951 + ins_pipe( pipe_alu_branch ); 1.952 %} 1.953 1.954 1.955 @@ -5801,7 +5796,7 @@ 1.956 %} 1.957 1.958 ins_pc_relative(1); 1.959 - ins_pipe(pipe_branchP); 1.960 + ins_pipe( pipe_alu_branch ); 1.961 %} 1.962 1.963 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{ 1.964 @@ -5864,7 +5859,7 @@ 1.965 %} 1.966 1.967 ins_pc_relative(1); 1.968 - ins_pipe(pipe_branchP); 1.969 + ins_pipe( pipe_alu_branch ); 1.970 %} 1.971 1.972 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{ 1.973 @@ -5925,7 +5920,7 @@ 1.974 %} 1.975 1.976 ins_pc_relative(1); 1.977 - ins_pipe(pipe_branchP); 1.978 + ins_pipe( pipe_alu_branch ); 1.979 %} 1.980 1.981 1.982 @@ -5991,7 +5986,7 @@ 1.983 %} 1.984 1.985 ins_pc_relative(1); 1.986 - ins_pipe(pipe_branchP); 1.987 + ins_pipe( pipe_alu_branch ); 1.988 %} 1.989 1.990 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{ 1.991 @@ -6046,7 +6041,7 @@ 1.992 %} 1.993 1.994 ins_pc_relative(1); 1.995 - ins_pipe(pipe_branchP); 1.996 + ins_pipe( pipe_alu_branch ); 1.997 %} 1.998 1.999 1.1000 @@ -6115,7 +6110,7 @@ 1.1001 %} 1.1002 1.1003 ins_pc_relative(1); 1.1004 - ins_pipe(pipe_branchP); 1.1005 + ins_pipe( pipe_alu_branch ); 1.1006 %} 1.1007 1.1008 1.1009 @@ -6197,7 +6192,7 @@ 1.1010 1.1011 1.1012 ins_pc_relative(1); 1.1013 - ins_pipe(pipe_branchP); 1.1014 + ins_pipe( pipe_alu_branch ); 1.1015 %} 1.1016 1.1017 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{ 1.1018 @@ -6258,7 +6253,7 @@ 1.1019 %} 1.1020 1.1021 ins_pc_relative(1); 1.1022 - ins_pipe(pipe_branchP); 1.1023 + ins_pipe( pipe_alu_branch ); 1.1024 %} 1.1025 1.1026 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{ 1.1027 @@ -6325,7 +6320,7 @@ 1.1028 1.1029 1.1030 ins_pc_relative(1); 1.1031 - ins_pipe(pipe_branchP); 1.1032 + ins_pipe( pipe_alu_branch ); 1.1033 %} 1.1034 1.1035 /* 1.1036 @@ -6589,7 +6584,7 @@ 1.1037 __ move(dst, src); 1.1038 %} 1.1039 ins_cost(10); 1.1040 - ins_pipe(ialu_reg_reg); 1.1041 + ins_pipe( ialu_regI_mov ); 1.1042 %} 1.1043 1.1044 instruct castP2X(mRegL dst, mRegP src ) %{ 1.1045 @@ -6603,7 +6598,7 @@ 1.1046 if(src != dst) 1.1047 __ move(dst, src); 1.1048 %} 1.1049 - ins_pipe( ialu_reg_reg ); 1.1050 + ins_pipe( ialu_regI_mov ); 1.1051 %} 1.1052 1.1053 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{ 1.1054 @@ -6716,7 +6711,7 @@ 1.1055 } 1.1056 %} 1.1057 1.1058 - ins_pipe( pipe_cmov_reg ); 1.1059 + ins_pipe( pipe_slow ); 1.1060 %} 1.1061 1.1062 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ 1.1063 @@ -6770,7 +6765,7 @@ 1.1064 } 1.1065 %} 1.1066 1.1067 - ins_pipe( pipe_cmov_reg ); 1.1068 + ins_pipe( pipe_slow ); 1.1069 %} 1.1070 1.1071 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ 1.1072 @@ -6824,7 +6819,7 @@ 1.1073 } 1.1074 %} 1.1075 1.1076 - ins_pipe( pipe_cmov_reg ); 1.1077 + ins_pipe( pipe_slow ); 1.1078 %} 1.1079 1.1080 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ 1.1081 @@ -6878,7 +6873,7 @@ 1.1082 } 1.1083 %} 1.1084 1.1085 - ins_pipe( pipe_cmov_reg ); 1.1086 + ins_pipe( pipe_slow ); 1.1087 %} 1.1088 1.1089 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ 1.1090 @@ -6932,7 +6927,7 @@ 1.1091 } 1.1092 %} 1.1093 1.1094 - ins_pipe( pipe_cmov_reg ); 1.1095 + ins_pipe( pipe_slow ); 1.1096 %} 1.1097 1.1098 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{ 1.1099 @@ -6981,7 +6976,7 @@ 1.1100 } 1.1101 %} 1.1102 1.1103 - ins_pipe( pipe_cmov_reg ); 1.1104 + ins_pipe( pipe_slow ); 1.1105 %} 1.1106 1.1107 1.1108 @@ -7036,7 +7031,7 @@ 1.1109 } 1.1110 %} 1.1111 1.1112 - ins_pipe( pipe_cmov_reg ); 1.1113 + ins_pipe( pipe_slow ); 1.1114 %} 1.1115 1.1116 1.1117 @@ -7091,7 +7086,7 @@ 1.1118 } 1.1119 %} 1.1120 1.1121 - ins_pipe( pipe_cmov_reg ); 1.1122 + ins_pipe( pipe_slow ); 1.1123 %} 1.1124 1.1125 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ 1.1126 @@ -7145,7 +7140,7 @@ 1.1127 } 1.1128 %} 1.1129 1.1130 - ins_pipe( pipe_cmov_reg ); 1.1131 + ins_pipe( pipe_slow ); 1.1132 %} 1.1133 1.1134 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ 1.1135 @@ -7199,7 +7194,7 @@ 1.1136 } 1.1137 %} 1.1138 1.1139 - ins_pipe( pipe_cmov_reg ); 1.1140 + ins_pipe( pipe_slow ); 1.1141 %} 1.1142 1.1143 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{ 1.1144 @@ -7249,7 +7244,7 @@ 1.1145 } 1.1146 %} 1.1147 1.1148 - ins_pipe( pipe_cmov_reg ); 1.1149 + ins_pipe( pipe_slow ); 1.1150 %} 1.1151 1.1152 1.1153 @@ -7304,7 +7299,7 @@ 1.1154 } 1.1155 %} 1.1156 1.1157 - ins_pipe( pipe_cmov_reg ); 1.1158 + ins_pipe( pipe_slow ); 1.1159 %} 1.1160 1.1161 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ 1.1162 @@ -7358,7 +7353,7 @@ 1.1163 } 1.1164 %} 1.1165 1.1166 - ins_pipe( pipe_cmov_reg ); 1.1167 + ins_pipe( pipe_slow ); 1.1168 %} 1.1169 1.1170 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ 1.1171 @@ -7412,7 +7407,7 @@ 1.1172 } 1.1173 %} 1.1174 1.1175 - ins_pipe( pipe_cmov_reg ); 1.1176 + ins_pipe( pipe_slow ); 1.1177 %} 1.1178 1.1179 1.1180 @@ -7468,7 +7463,7 @@ 1.1181 } 1.1182 %} 1.1183 1.1184 - ins_pipe( pipe_cmov_reg_long ); 1.1185 + ins_pipe( pipe_slow ); 1.1186 %} 1.1187 1.1188 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ 1.1189 @@ -7522,7 +7517,7 @@ 1.1190 } 1.1191 %} 1.1192 1.1193 - ins_pipe( pipe_cmov_reg_long ); 1.1194 + ins_pipe( pipe_slow ); 1.1195 %} 1.1196 1.1197 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ 1.1198 @@ -7576,7 +7571,7 @@ 1.1199 } 1.1200 %} 1.1201 1.1202 - ins_pipe( pipe_cmov_reg ); 1.1203 + ins_pipe( pipe_slow ); 1.1204 %} 1.1205 1.1206 1.1207 @@ -7626,7 +7621,7 @@ 1.1208 } 1.1209 %} 1.1210 1.1211 - ins_pipe( pipe_cmov_reg ); 1.1212 + ins_pipe( pipe_slow ); 1.1213 %} 1.1214 1.1215 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{ 1.1216 @@ -7696,7 +7691,7 @@ 1.1217 } 1.1218 %} 1.1219 1.1220 - ins_pipe( pipe_cmov_reg ); 1.1221 + ins_pipe( pipe_slow ); 1.1222 %} 1.1223 1.1224 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ 1.1225 @@ -8218,7 +8213,7 @@ 1.1226 Register src2 = $src2$$Register; 1.1227 __ addu32(dst, src1, src2); 1.1228 %} 1.1229 - ins_pipe( ialu_reg ); 1.1230 + ins_pipe( ialu_regI_regI ); 1.1231 %} 1.1232 1.1233 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{ 1.1234 @@ -8237,7 +8232,7 @@ 1.1235 __ addu32(dst, src1, AT); 1.1236 } 1.1237 %} 1.1238 - ins_pipe( ialu_reg ); 1.1239 + ins_pipe( ialu_regI_regI ); 1.1240 %} 1.1241 1.1242 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{ 1.1243 @@ -8252,7 +8247,7 @@ 1.1244 __ daddu(dst, src1, src2); 1.1245 %} 1.1246 1.1247 - ins_pipe( ialu_reg_reg ); 1.1248 + ins_pipe( ialu_regI_regI ); 1.1249 %} 1.1250 1.1251 instruct addP_reg_imm(mRegP dst, mRegP src1, immL32 src2) %{ 1.1252 @@ -8272,7 +8267,7 @@ 1.1253 __ daddu(dst, src1, AT); 1.1254 } 1.1255 %} 1.1256 - ins_pipe( ialu_reg_imm ); 1.1257 + ins_pipe( ialu_regI_imm16 ); 1.1258 %} 1.1259 1.1260 // Add Long Register with Register 1.1261 @@ -8289,7 +8284,7 @@ 1.1262 __ daddu(dst_reg, src1_reg, src2_reg); 1.1263 %} 1.1264 1.1265 - ins_pipe( ialu_reg_reg_long ); 1.1266 + ins_pipe( ialu_regL_regL ); 1.1267 %} 1.1268 1.1269 //----------Subtraction Instructions------------------------------------------- 1.1270 @@ -8304,7 +8299,7 @@ 1.1271 Register src2 = $src2$$Register; 1.1272 __ subu32(dst, src1, src2); 1.1273 %} 1.1274 - ins_pipe( ialu_reg ); 1.1275 + ins_pipe( ialu_regI_regI ); 1.1276 %} 1.1277 1.1278 instruct subI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{ 1.1279 @@ -8317,7 +8312,7 @@ 1.1280 __ move(AT, -1 * $src2$$constant); 1.1281 __ addu32(dst, src1, AT); 1.1282 %} 1.1283 - ins_pipe( ialu_reg ); 1.1284 + ins_pipe( ialu_regI_regI ); 1.1285 %} 1.1286 1.1287 // Subtract Long Register with Register. 1.1288 @@ -8332,7 +8327,7 @@ 1.1289 1.1290 __ subu(dst, src1, src2); 1.1291 %} 1.1292 - ins_pipe( ialu_reg_reg_long ); 1.1293 + ins_pipe( ialu_regL_regL ); 1.1294 %} 1.1295 1.1296 // Integer MOD with Register 1.1297 @@ -8350,8 +8345,8 @@ 1.1298 __ mfhi(dst); 1.1299 %} 1.1300 1.1301 - //ins_pipe( ialu_reg_reg_alu0 ); 1.1302 - ins_pipe( ialu_reg ); 1.1303 + //ins_pipe( ialu_mod ); 1.1304 + ins_pipe( ialu_regI_regI ); 1.1305 %} 1.1306 1.1307 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{ 1.1308 @@ -8381,7 +8376,7 @@ 1.1309 1.1310 __ mul(dst, src1, src2); 1.1311 %} 1.1312 - ins_pipe( ialu_reg_reg_alu0 ); 1.1313 + ins_pipe( ialu_mult ); 1.1314 %} 1.1315 1.1316 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{ 1.1317 @@ -8399,7 +8394,7 @@ 1.1318 __ madd(src1, src2); 1.1319 __ mflo(dst); 1.1320 %} 1.1321 - ins_pipe( ialu_reg_reg_alu0 ); 1.1322 + ins_pipe( ialu_mult ); 1.1323 %} 1.1324 1.1325 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ 1.1326 @@ -8421,7 +8416,7 @@ 1.1327 __ nop(); 1.1328 __ mflo(dst); 1.1329 %} 1.1330 - ins_pipe( ialu_reg_reg_alu0 ); 1.1331 + ins_pipe( ialu_mod ); 1.1332 %} 1.1333 1.1334 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{ 1.1335 @@ -8520,7 +8515,7 @@ 1.1336 1.1337 __ add_s(dst, src1, src2); 1.1338 %} 1.1339 - ins_pipe( fpu_reg_reg ); 1.1340 + ins_pipe( fpu_regF_regF ); 1.1341 %} 1.1342 1.1343 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 1.1344 @@ -8533,7 +8528,7 @@ 1.1345 1.1346 __ sub_s(dst, src1, src2); 1.1347 %} 1.1348 - ins_pipe( fpu_reg_reg ); 1.1349 + ins_pipe( fpu_regF_regF ); 1.1350 %} 1.1351 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 1.1352 match(Set dst (AddD src1 src2)); 1.1353 @@ -8545,7 +8540,7 @@ 1.1354 1.1355 __ add_d(dst, src1, src2); 1.1356 %} 1.1357 - ins_pipe( fpu_reg_reg ); 1.1358 + ins_pipe( fpu_regF_regF ); 1.1359 %} 1.1360 1.1361 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 1.1362 @@ -8558,7 +8553,7 @@ 1.1363 1.1364 __ sub_d(dst, src1, src2); 1.1365 %} 1.1366 - ins_pipe( fpu_reg_reg ); 1.1367 + ins_pipe( fpu_regF_regF ); 1.1368 %} 1.1369 1.1370 instruct negF_reg(regF dst, regF src) %{ 1.1371 @@ -8570,7 +8565,7 @@ 1.1372 1.1373 __ neg_s(dst, src); 1.1374 %} 1.1375 - ins_pipe( fpu_reg_reg ); 1.1376 + ins_pipe( fpu_regF_regF ); 1.1377 %} 1.1378 1.1379 instruct negD_reg(regD dst, regD src) %{ 1.1380 @@ -8582,7 +8577,7 @@ 1.1381 1.1382 __ neg_d(dst, src); 1.1383 %} 1.1384 - ins_pipe( fpu_reg_reg ); 1.1385 + ins_pipe( fpu_regF_regF ); 1.1386 %} 1.1387 1.1388 1.1389 @@ -8596,7 +8591,7 @@ 1.1390 1.1391 __ mul_s(dst, src1, src2); 1.1392 %} 1.1393 - ins_pipe( fpu_reg_reg ); 1.1394 + ins_pipe( fpu_regF_regF ); 1.1395 %} 1.1396 1.1397 // Mul two double precision floating piont number 1.1398 @@ -8610,7 +8605,7 @@ 1.1399 1.1400 __ mul_d(dst, src1, src2); 1.1401 %} 1.1402 - ins_pipe( fpu_reg_reg ); 1.1403 + ins_pipe( fpu_regF_regF ); 1.1404 %} 1.1405 1.1406 instruct absF_reg(regF dst, regF src) %{ 1.1407 @@ -8623,7 +8618,7 @@ 1.1408 1.1409 __ abs_s(dst, src); 1.1410 %} 1.1411 - ins_pipe( fpu_reg_reg ); 1.1412 + ins_pipe( fpu_regF_regF ); 1.1413 %} 1.1414 1.1415 1.1416 @@ -8640,7 +8635,7 @@ 1.1417 1.1418 __ abs_d(dst, src); 1.1419 %} 1.1420 - ins_pipe( fpu_reg_reg ); 1.1421 + ins_pipe( fpu_regF_regF ); 1.1422 %} 1.1423 1.1424 instruct sqrtD_reg(regD dst, regD src) %{ 1.1425 @@ -8653,7 +8648,7 @@ 1.1426 1.1427 __ sqrt_d(dst, src); 1.1428 %} 1.1429 - ins_pipe( fpu_reg_reg ); 1.1430 + ins_pipe( fpu_regF_regF ); 1.1431 %} 1.1432 1.1433 //----------------------------------Logical Instructions---------------------- 1.1434 @@ -8673,7 +8668,7 @@ 1.1435 __ move(AT, val); 1.1436 __ andr(dst, src, AT); 1.1437 %} 1.1438 - ins_pipe( ialu_reg ); 1.1439 + ins_pipe( ialu_regI_regI ); 1.1440 %} 1.1441 1.1442 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{ 1.1443 @@ -8688,7 +8683,7 @@ 1.1444 1.1445 __ andi(dst, src, val); 1.1446 %} 1.1447 - ins_pipe( ialu_reg ); 1.1448 + ins_pipe( ialu_regI_regI ); 1.1449 %} 1.1450 1.1451 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ 1.1452 @@ -8701,7 +8696,7 @@ 1.1453 Register src2 = $src2$$Register; 1.1454 __ andr(dst, src1, src2); 1.1455 %} 1.1456 - ins_pipe( ialu_reg ); 1.1457 + ins_pipe( ialu_regI_regI ); 1.1458 %} 1.1459 1.1460 // And Long Register with Register 1.1461 @@ -8715,7 +8710,7 @@ 1.1462 1.1463 __ andr(dst_reg, src1_reg, src2_reg); 1.1464 %} 1.1465 - ins_pipe( ialu_reg_reg_long ); 1.1466 + ins_pipe( ialu_regL_regL ); 1.1467 %} 1.1468 1.1469 // Or Long Register with Register 1.1470 @@ -8729,7 +8724,7 @@ 1.1471 1.1472 __ orr(dst_reg, src1_reg, src2_reg); 1.1473 %} 1.1474 - ins_pipe( ialu_reg_reg_long ); 1.1475 + ins_pipe( ialu_regL_regL ); 1.1476 %} 1.1477 1.1478 // Xor Long Register with Register 1.1479 @@ -8743,7 +8738,7 @@ 1.1480 1.1481 __ xorr(dst_reg, src1_reg, src2_reg); 1.1482 %} 1.1483 - ins_pipe( ialu_reg_reg_long ); 1.1484 + ins_pipe( ialu_regL_regL ); 1.1485 %} 1.1486 1.1487 // Shift Left by 8-bit immediate 1.1488 @@ -8770,7 +8765,7 @@ 1.1489 __ sllv(dst, src, AT); 1.1490 } 1.1491 %} 1.1492 - ins_pipe( ialu_reg ); 1.1493 + ins_pipe( ialu_regI_regI ); 1.1494 %} 1.1495 1.1496 // Shift Left by 8-bit immediate 1.1497 @@ -8784,7 +8779,7 @@ 1.1498 Register shamt = $shift$$Register; 1.1499 __ sllv(dst, src, shamt); 1.1500 %} 1.1501 - ins_pipe( ialu_reg ); 1.1502 + ins_pipe( ialu_regI_regI ); 1.1503 %} 1.1504 1.1505 1.1506 @@ -8807,7 +8802,7 @@ 1.1507 __ dsllv(dst_reg, src_reg, AT); 1.1508 } 1.1509 %} 1.1510 - ins_pipe( ialu_reg_long ); 1.1511 + ins_pipe( ialu_regL_regL ); 1.1512 %} 1.1513 1.1514 1.1515 @@ -8826,7 +8821,7 @@ 1.1516 __ andi(creg, creg, 0x3f); 1.1517 __ dsllv(dst_reg, src_reg, creg); 1.1518 %} 1.1519 - ins_pipe( ialu_reg_long ); 1.1520 + ins_pipe( ialu_regL_regL ); 1.1521 %} 1.1522 1.1523 // Shift Right Long 1.1524 @@ -8847,7 +8842,7 @@ 1.1525 __ dsrav(dst_reg, src_reg, AT); 1.1526 } 1.1527 %} 1.1528 - ins_pipe( ialu_reg_long ); 1.1529 + ins_pipe( ialu_regL_regL ); 1.1530 %} 1.1531 1.1532 // Shift Right Long arithmetically 1.1533 @@ -8865,7 +8860,7 @@ 1.1534 __ andi(creg, creg, 0x3f); 1.1535 __ dsrav(dst_reg, src_reg, creg); 1.1536 %} 1.1537 - ins_pipe( ialu_reg_long ); 1.1538 + ins_pipe( ialu_regL_regL ); 1.1539 %} 1.1540 1.1541 // Shift Right Long logically 1.1542 @@ -8883,7 +8878,7 @@ 1.1543 __ andi(creg, creg, 0x3f); 1.1544 __ dsrlv(dst_reg, src_reg, creg); 1.1545 %} 1.1546 - ins_pipe( ialu_reg_long ); 1.1547 + ins_pipe( ialu_regL_regL ); 1.1548 %} 1.1549 1.1550 1.1551 @@ -8902,7 +8897,7 @@ 1.1552 __ sll(dst, dst, 0); /* long -> int */ 1.1553 %} 1.1554 1.1555 - ins_pipe( ialu_reg_reg ); 1.1556 + ins_pipe( ialu_regI_regI ); 1.1557 %} 1.1558 1.1559 // Or Instructions 1.1560 @@ -8918,7 +8913,7 @@ 1.1561 __ orr(dst, src1, src2); 1.1562 %} 1.1563 1.1564 - ins_pipe( ialu_reg_reg ); 1.1565 + ins_pipe( ialu_regI_regI ); 1.1566 %} 1.1567 1.1568 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{ 1.1569 @@ -8932,7 +8927,7 @@ 1.1570 __ orr(dst, src1, src2); 1.1571 %} 1.1572 1.1573 - ins_pipe( ialu_reg_reg ); 1.1574 + ins_pipe( ialu_regI_regI ); 1.1575 %} 1.1576 1.1577 // Logical Shift Right by 8-bit immediate 1.1578 @@ -8953,7 +8948,7 @@ 1.1579 __ srlv(dst, src, AT); 1.1580 } 1.1581 %} 1.1582 - ins_pipe( ialu_reg ); 1.1583 + ins_pipe( ialu_regI_regI ); 1.1584 %} 1.1585 1.1586 // Logical Shift Right 1.1587 @@ -8967,7 +8962,7 @@ 1.1588 Register shift = $shift$$Register; 1.1589 __ srlv(dst, src, shift); 1.1590 %} 1.1591 - ins_pipe( ialu_reg ); 1.1592 + ins_pipe( ialu_regI_regI ); 1.1593 %} 1.1594 1.1595 1.1596 @@ -8982,7 +8977,7 @@ 1.1597 int shift = $shift$$constant; 1.1598 __ sra(dst, src, shift); 1.1599 %} 1.1600 - ins_pipe( ialu_reg ); 1.1601 + ins_pipe( ialu_regI_regI ); 1.1602 %} 1.1603 1.1604 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ 1.1605 @@ -8996,7 +8991,7 @@ 1.1606 Register shift = $shift$$Register; 1.1607 __ srav(dst, src, shift); 1.1608 %} 1.1609 - ins_pipe( ialu_reg ); 1.1610 + ins_pipe( ialu_regI_regI ); 1.1611 %} 1.1612 1.1613 //----------Convert Int to Boolean--------------------------------------------- 1.1614 @@ -9009,7 +9004,7 @@ 1.1615 Register src = $src$$Register; 1.1616 __ move(dst, src); 1.1617 %} 1.1618 - ins_pipe( ialu_reg_reg ); 1.1619 + ins_pipe( ialu_regI_regI ); 1.1620 %} 1.1621 1.1622 instruct ci2b(mRegI dst, mRegI src) %{ 1.1623 @@ -9032,7 +9027,7 @@ 1.1624 __ addu(dst, dst, AT); 1.1625 %} 1.1626 1.1627 - ins_pipe( ialu_reg_reg_long ); 1.1628 + ins_pipe( ialu_regL_regL ); 1.1629 %} 1.1630 1.1631 1.1632 @@ -9056,7 +9051,7 @@ 1.1633 1.1634 if(dst != src) __ sll(dst, src, 0); 1.1635 %} 1.1636 - ins_pipe( ialu_reg_reg_long ); 1.1637 + ins_pipe( ialu_regL_regL ); 1.1638 %} 1.1639 1.1640 1.1641 @@ -9072,7 +9067,7 @@ 1.1642 __ dsra32(dst, dst, 0); 1.1643 %} 1.1644 1.1645 - ins_pipe( ialu_reg_reg ); 1.1646 + ins_pipe( ialu_regI_regI ); 1.1647 %} 1.1648 1.1649 instruct convL2D_reg( regD dst, mRegL src ) %{ 1.1650 @@ -9224,7 +9219,7 @@ 1.1651 __ cvt_s_w(dst, dst); 1.1652 %} 1.1653 1.1654 - ins_pipe( fpu_reg_reg ); 1.1655 + ins_pipe( fpu_regF_regF ); 1.1656 %} 1.1657 1.1658 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{ 1.1659 @@ -9252,7 +9247,7 @@ 1.1660 __ addu(dst, src, R0); 1.1661 %} 1.1662 // ins_encode( enc_Copy( dst, src) ); 1.1663 - ins_pipe( ialu_reg_reg ); 1.1664 + ins_pipe( ialu_regI_regI ); 1.1665 %} 1.1666 1.1667 //FIXME 1.1668 @@ -9275,7 +9270,7 @@ 1.1669 __ addu(dst, dst, AT); 1.1670 %} 1.1671 1.1672 - ins_pipe( ialu_reg_reg_long ); 1.1673 + ins_pipe( ialu_regL_regL ); 1.1674 %} 1.1675 1.1676 instruct convP2B( mRegI dst, mRegP src ) %{ 1.1677 @@ -9296,7 +9291,7 @@ 1.1678 __ mtc1(src, dst); 1.1679 __ cvt_d_w(dst, dst); 1.1680 %} 1.1681 - ins_pipe( fpu_reg_reg ); 1.1682 + ins_pipe( fpu_regF_regF ); 1.1683 %} 1.1684 1.1685 instruct convF2I_reg_reg(mRegI dst, regF src) %{ 1.1686 @@ -9308,7 +9303,7 @@ 1.1687 1.1688 __ cvt_d_s(dst, src); 1.1689 %} 1.1690 - ins_pipe( fpu_reg_reg ); 1.1691 + ins_pipe( fpu_regF_regF ); 1.1692 %} 1.1693 1.1694 instruct convF2D_reg_reg(regD dst, regF src) %{ 1.1695 @@ -9320,7 +9315,7 @@ 1.1696 1.1697 __ cvt_d_s(dst, src); 1.1698 %} 1.1699 - ins_pipe( fpu_reg_reg ); 1.1700 + ins_pipe( fpu_regF_regF ); 1.1701 %} 1.1702 1.1703 instruct convD2F_reg_reg(regF dst, regD src) %{ 1.1704 @@ -9332,7 +9327,7 @@ 1.1705 1.1706 __ cvt_s_d(dst, src); 1.1707 %} 1.1708 - ins_pipe( fpu_reg_reg ); 1.1709 + ins_pipe( fpu_regF_regF ); 1.1710 %} 1.1711 1.1712 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 1.1713 @@ -9377,7 +9372,7 @@ 1.1714 } 1.1715 __ encode_heap_oop(dst); 1.1716 %} 1.1717 - ins_pipe(ialu_reg_long); 1.1718 + ins_pipe( ialu_regL_regL ); 1.1719 %} 1.1720 1.1721 instruct encodeHeapOop_not_null(mRegN dst, mRegP src, FlagsReg cr) %{ 1.1722 @@ -9388,7 +9383,7 @@ 1.1723 ins_encode %{ 1.1724 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); 1.1725 %} 1.1726 - ins_pipe(ialu_reg_long); 1.1727 + ins_pipe( ialu_regL_regL ); 1.1728 %} 1.1729 1.1730 instruct decodeHeapOop(mRegP dst, mRegN src) %{ 1.1731 @@ -9404,7 +9399,7 @@ 1.1732 } 1.1733 __ decode_heap_oop(d); 1.1734 %} 1.1735 - ins_pipe(ialu_reg_long); 1.1736 + ins_pipe( ialu_regL_regL ); 1.1737 %} 1.1738 1.1739 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{ 1.1740 @@ -9421,7 +9416,7 @@ 1.1741 __ decode_heap_oop_not_null(d); 1.1742 } 1.1743 %} 1.1744 - ins_pipe(ialu_reg_long); 1.1745 + ins_pipe( ialu_regL_regL ); 1.1746 %} 1.1747 1.1748 instruct encodeKlass_not_null(mRegN dst, mRegP src, FlagsReg cr) %{ 1.1749 @@ -9431,7 +9426,7 @@ 1.1750 ins_encode %{ 1.1751 __ encode_klass_not_null($dst$$Register, $src$$Register); 1.1752 %} 1.1753 - ins_pipe(ialu_reg_long); 1.1754 + ins_pipe( ialu_regL_regL ); 1.1755 %} 1.1756 1.1757 instruct decodeKlass_not_null(mRegP dst, mRegN src, FlagsReg cr) %{ 1.1758 @@ -9447,7 +9442,7 @@ 1.1759 __ decode_klass_not_null(d); 1.1760 } 1.1761 %} 1.1762 - ins_pipe(ialu_reg_long); 1.1763 + ins_pipe( ialu_regL_regL ); 1.1764 %} 1.1765 1.1766 //FIXME 1.1767 @@ -9465,7 +9460,7 @@ 1.1768 #endif 1.1769 %} 1.1770 1.1771 - ins_pipe(ialu_none); 1.1772 + ins_pipe( ialu_loadI ); 1.1773 %} 1.1774 1.1775 1.1776 @@ -9506,7 +9501,7 @@ 1.1777 __ nop(); 1.1778 %} 1.1779 1.1780 - ins_pipe( pipe_jmp ); 1.1781 + ins_pipe( pipe_jump ); 1.1782 %} 1.1783 1.1784 1.1785 @@ -9527,7 +9522,7 @@ 1.1786 __ nop(); 1.1787 %} 1.1788 1.1789 - ins_pipe( pipe_jmp ); 1.1790 + ins_pipe( pipe_jump ); 1.1791 ins_pc_relative(1); 1.1792 %} 1.1793 1.1794 @@ -9561,7 +9556,7 @@ 1.1795 __ jr(target); 1.1796 __ nop(); 1.1797 %} 1.1798 - ins_pipe( pipe_jmp ); 1.1799 + ins_pipe( pipe_jump ); 1.1800 %} 1.1801 1.1802 // ============================================================================ 1.1803 @@ -9643,7 +9638,7 @@ 1.1804 // opcode(0xB7, 0x0F); 1.1805 // ins_encode( OpcS, OpcP, RegMem(dst,mem)); 1.1806 ins_encode(load_C_enc(dst, mem)); 1.1807 - ins_pipe( ialu_reg_mem ); 1.1808 + ins_pipe( ialu_loadI ); 1.1809 %} 1.1810 1.1811 // Store Char (16bit unsigned) 1.1812 @@ -9653,7 +9648,7 @@ 1.1813 ins_cost(125); 1.1814 format %{ "storeC $src,$mem @ storeC" %} 1.1815 ins_encode(store_C_reg_enc(mem, src)); 1.1816 - ins_pipe( ialu_reg_mem ); 1.1817 + ins_pipe( ialu_loadI ); 1.1818 %} 1.1819 1.1820 1.1821 @@ -9667,7 +9662,7 @@ 1.1822 1.1823 __ mtc1(R0, dst); 1.1824 %} 1.1825 - ins_pipe( fpu_reg_con ); 1.1826 + ins_pipe( fpu_loadF ); 1.1827 %} 1.1828 1.1829 1.1830 @@ -9686,7 +9681,7 @@ 1.1831 __ li(AT, const_addr); 1.1832 __ lwc1(dst, AT, 0); 1.1833 %} 1.1834 - ins_pipe( fpu_reg_con ); 1.1835 + ins_pipe( fpu_loadF ); 1.1836 %} 1.1837 1.1838 1.1839 @@ -9700,7 +9695,7 @@ 1.1840 1.1841 __ dmtc1(R0, dst); 1.1842 %} 1.1843 - ins_pipe( fpu_reg_con ); 1.1844 + ins_pipe( fpu_loadF ); 1.1845 %} 1.1846 1.1847 instruct loadConD(regD dst, immD src) %{ 1.1848 @@ -9719,7 +9714,7 @@ 1.1849 __ li(AT, const_addr); 1.1850 __ ldc1(dst_reg, AT, 0); 1.1851 %} 1.1852 - ins_pipe( fpu_reg_con ); 1.1853 + ins_pipe( fpu_loadF ); 1.1854 %} 1.1855 1.1856 // Store register Float value (it is faster than store from FPU register) 1.1857 @@ -9729,7 +9724,7 @@ 1.1858 ins_cost(50); 1.1859 format %{ "store $mem, $src\t# store float @ storeF_reg" %} 1.1860 ins_encode(store_F_reg_enc(mem, src)); 1.1861 - ins_pipe( fpu_mem_reg ); 1.1862 + ins_pipe( fpu_storeF ); 1.1863 %} 1.1864 1.1865 1.1866 @@ -9775,7 +9770,7 @@ 1.1867 } 1.1868 } 1.1869 %} 1.1870 - ins_pipe( ialu_mem_imm ); 1.1871 + ins_pipe( ialu_storeI ); 1.1872 %} 1.1873 1.1874 instruct storeF_imm0( memory mem, immF0 zero) %{ 1.1875 @@ -9814,7 +9809,7 @@ 1.1876 } 1.1877 } 1.1878 %} 1.1879 - ins_pipe( ialu_mem_imm ); 1.1880 + ins_pipe( ialu_storeI ); 1.1881 %} 1.1882 1.1883 // Load Double 1.1884 @@ -9824,7 +9819,7 @@ 1.1885 ins_cost(150); 1.1886 format %{ "loadD $dst, $mem #@loadD" %} 1.1887 ins_encode(load_D_enc(dst, mem)); 1.1888 - ins_pipe( fpu_reg_mem ); 1.1889 + ins_pipe( ialu_loadI ); 1.1890 %} 1.1891 1.1892 // Load Double - UNaligned 1.1893 @@ -9834,7 +9829,7 @@ 1.1894 // FIXME: Jin: Need more effective ldl/ldr 1.1895 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %} 1.1896 ins_encode(load_D_enc(dst, mem)); 1.1897 - ins_pipe( fpu_reg_mem ); 1.1898 + ins_pipe( ialu_loadI ); 1.1899 %} 1.1900 1.1901 instruct storeD_reg( memory mem, regD src) %{ 1.1902 @@ -9843,7 +9838,7 @@ 1.1903 ins_cost(50); 1.1904 format %{ "store $mem, $src\t# store float @ storeD_reg" %} 1.1905 ins_encode(store_D_reg_enc(mem, src)); 1.1906 - ins_pipe( fpu_mem_reg ); 1.1907 + ins_pipe( fpu_storeF ); 1.1908 %} 1.1909 1.1910 instruct storeD_imm0( memory mem, immD0 zero) %{ 1.1911 @@ -9885,7 +9880,7 @@ 1.1912 } 1.1913 } 1.1914 %} 1.1915 - ins_pipe( ialu_mem_imm ); 1.1916 + ins_pipe( ialu_storeI ); 1.1917 %} 1.1918 1.1919 instruct cmpFastLock( FlagsReg cr, mRegP object, mRegP box, mRegI tmp, mRegP scr) %{ 1.1920 @@ -9922,7 +9917,7 @@ 1.1921 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 1.1922 // opcode(0xC6); 1.1923 ins_encode(store_B_immI_enc(mem, src)); 1.1924 - ins_pipe( ialu_mem_reg ); 1.1925 + ins_pipe( ialu_storeI ); 1.1926 %} 1.1927 1.1928 // Die now 1.1929 @@ -9939,7 +9934,7 @@ 1.1930 __ stop("in ShoudNotReachHere"); 1.1931 1.1932 %} 1.1933 - ins_pipe(pipe_jmp); 1.1934 + ins_pipe( pipe_jump ); 1.1935 %} 1.1936 1.1937 1.1938 @@ -10003,7 +9998,7 @@ 1.1939 } 1.1940 __ nop(); 1.1941 %} 1.1942 - ins_pipe( pipe_jcc ); 1.1943 + ins_pipe( pipe_jump ); 1.1944 ins_pc_relative(1); 1.1945 %} 1.1946 1.1947 @@ -10065,7 +10060,7 @@ 1.1948 } 1.1949 __ nop(); 1.1950 %} 1.1951 - ins_pipe( pipe_jcc ); 1.1952 + ins_pipe( pipe_jump ); 1.1953 ins_pc_relative(1); 1.1954 %} 1.1955 1.1956 @@ -10081,7 +10076,7 @@ 1.1957 size(6); 1.1958 opcode(0x0F, 0x80); 1.1959 ins_encode( Jcc( cop, labl) ); 1.1960 - ins_pipe( pipe_jcc ); 1.1961 + ins_pipe( pipe_jump ); 1.1962 ins_pc_relative(1); 1.1963 %} 1.1964 1.1965 @@ -10093,7 +10088,7 @@ 1.1966 format %{ "J$cop,u $labl\t# Loop end" %} 1.1967 opcode(0x0F, 0x80); 1.1968 ins_encode( Jcc( cop, labl) ); 1.1969 - ins_pipe( pipe_jcc ); 1.1970 + ins_pipe( pipe_jump ); 1.1971 ins_pc_relative(1); 1.1972 %} 1.1973 */ 1.1974 @@ -10128,7 +10123,7 @@ 1.1975 __ nop(); 1.1976 %} 1.1977 1.1978 - ins_pipe( pipe_jcc ); 1.1979 + ins_pipe( pipe_jump ); 1.1980 ins_pc_relative(1); 1.1981 %} 1.1982 1.1983 @@ -10187,7 +10182,7 @@ 1.1984 } 1.1985 %} 1.1986 1.1987 - ins_pipe( pipe_cmpxchg ); 1.1988 + ins_pipe( long_memory_op ); 1.1989 %} 1.1990 1.1991 // Conditional-store of a long value. 1.1992 @@ -10216,7 +10211,7 @@ 1.1993 __ cmpxchg(newval, addr, oldval); 1.1994 } 1.1995 %} 1.1996 - ins_pipe(pipe_cmpxchg); 1.1997 + ins_pipe( long_memory_op ); 1.1998 %} 1.1999 1.2000 1.2001 @@ -10239,7 +10234,7 @@ 1.2002 __ cmpxchg32(newval, addr, oldval); 1.2003 __ move(res, AT); 1.2004 %} 1.2005 - ins_pipe( pipe_cmpxchg ); 1.2006 + ins_pipe( long_memory_op ); 1.2007 %} 1.2008 1.2009 //FIXME: 1.2010 @@ -10259,7 +10254,7 @@ 1.2011 __ cmpxchg(newval, addr, oldval); 1.2012 __ move(res, AT); 1.2013 %} 1.2014 - ins_pipe( pipe_cmpxchg ); 1.2015 + ins_pipe( long_memory_op ); 1.2016 %} 1.2017 1.2018 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{ 1.2019 @@ -10283,7 +10278,7 @@ 1.2020 __ cmpxchg32(newval, addr, oldval); 1.2021 __ move(res, AT); 1.2022 %} 1.2023 - ins_pipe( pipe_cmpxchg ); 1.2024 + ins_pipe( long_memory_op ); 1.2025 %} 1.2026 1.2027 //----------Max and Min-------------------------------------------------------- 1.2028 @@ -10397,7 +10392,7 @@ 1.2029 #endif 1.2030 %} 1.2031 1.2032 - ins_pipe( ialu_mem_imm ); 1.2033 + ins_pipe( ialu_storeI ); 1.2034 %} 1.2035 1.2036 //----------PEEPHOLE RULES-----------------------------------------------------
