Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
Merge
Mon, 08 Sep 2014 23:01:01 +0000
- author
- kvn
- date
- Mon, 08 Sep 2014 23:01:01 +0000
- changeset 7133
- 2219e830b668
- parent 7131
- d35872270666
- parent 7132
- b384ba33c9a0
- child 7134
- d8847542f83a
- child 7135
- d635fd1ac81c
Merge
1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Tue Sep 09 00:05:25 2014 +0200 1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Mon Sep 08 23:01:01 2014 +0000 1.3 @@ -298,6 +298,7 @@ 1.4 LWZ_OPCODE = (32u << OPCODE_SHIFT), 1.5 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 1.6 LWZU_OPCODE = (33u << OPCODE_SHIFT), 1.7 + LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 1.8 1.9 LHA_OPCODE = (42u << OPCODE_SHIFT), 1.10 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 1.11 @@ -306,6 +307,7 @@ 1.12 LHZ_OPCODE = (40u << OPCODE_SHIFT), 1.13 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 1.14 LHZU_OPCODE = (41u << OPCODE_SHIFT), 1.15 + LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 1.16 1.17 LBZ_OPCODE = (34u << OPCODE_SHIFT), 1.18 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 1.19 @@ -1364,11 +1366,17 @@ 1.20 inline void lwax( Register d, Register s1, Register s2); 1.21 inline void lwa( Register d, int si16, Register s1); 1.22 1.23 + // 4 bytes reversed 1.24 + inline void lwbrx( Register d, Register s1, Register s2); 1.25 + 1.26 // 2 bytes 1.27 inline void lhzx( Register d, Register s1, Register s2); 1.28 inline void lhz( Register d, int si16, Register s1); 1.29 inline void lhzu( Register d, int si16, Register s1); 1.30 1.31 + // 2 bytes reversed 1.32 + inline void lhbrx( Register d, Register s1, Register s2); 1.33 + 1.34 // 2 bytes 1.35 inline void lhax( Register d, Register s1, Register s2); 1.36 inline void lha( Register d, int si16, Register s1); 1.37 @@ -1858,10 +1866,12 @@ 1.38 inline void lwz( Register d, int si16); 1.39 inline void lwax( Register d, Register s2); 1.40 inline void lwa( Register d, int si16); 1.41 + inline void lwbrx(Register d, Register s2); 1.42 inline void lhzx( Register d, Register s2); 1.43 inline void lhz( Register d, int si16); 1.44 inline void lhax( Register d, Register s2); 1.45 inline void lha( Register d, int si16); 1.46 + inline void lhbrx(Register d, Register s2); 1.47 inline void lbzx( Register d, Register s2); 1.48 inline void lbz( Register d, int si16); 1.49 inline void ldx( Register d, Register s2);
2.1 --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp Tue Sep 09 00:05:25 2014 +0200 2.2 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp Mon Sep 08 23:01:01 2014 +0000 2.3 @@ -263,10 +263,14 @@ 2.4 inline void Assembler::lwax( Register d, Register s1, Register s2) { emit_int32(LWAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} 2.5 inline void Assembler::lwa( Register d, int si16, Register s1) { emit_int32(LWA_OPCODE | rt(d) | ds(si16) | ra0mem(s1));} 2.6 2.7 +inline void Assembler::lwbrx( Register d, Register s1, Register s2) { emit_int32(LWBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} 2.8 + 2.9 inline void Assembler::lhzx( Register d, Register s1, Register s2) { emit_int32(LHZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} 2.10 inline void Assembler::lhz( Register d, int si16, Register s1) { emit_int32(LHZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} 2.11 inline void Assembler::lhzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} 2.12 2.13 +inline void Assembler::lhbrx( Register d, Register s1, Register s2) { emit_int32(LHBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} 2.14 + 2.15 inline void Assembler::lhax( Register d, Register s1, Register s2) { emit_int32(LHAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} 2.16 inline void Assembler::lha( Register d, int si16, Register s1) { emit_int32(LHA_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} 2.17 inline void Assembler::lhau( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHAU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} 2.18 @@ -736,10 +740,12 @@ 2.19 inline void Assembler::lwz( Register d, int si16 ) { emit_int32( LWZ_OPCODE | rt(d) | d1(si16));} 2.20 inline void Assembler::lwax( Register d, Register s2) { emit_int32( LWAX_OPCODE | rt(d) | rb(s2));} 2.21 inline void Assembler::lwa( Register d, int si16 ) { emit_int32( LWA_OPCODE | rt(d) | ds(si16));} 2.22 +inline void Assembler::lwbrx(Register d, Register s2) { emit_int32( LWBRX_OPCODE| rt(d) | rb(s2));} 2.23 inline void Assembler::lhzx( Register d, Register s2) { emit_int32( LHZX_OPCODE | rt(d) | rb(s2));} 2.24 inline void Assembler::lhz( Register d, int si16 ) { emit_int32( LHZ_OPCODE | rt(d) | d1(si16));} 2.25 inline void Assembler::lhax( Register d, Register s2) { emit_int32( LHAX_OPCODE | rt(d) | rb(s2));} 2.26 inline void Assembler::lha( Register d, int si16 ) { emit_int32( LHA_OPCODE | rt(d) | d1(si16));} 2.27 +inline void Assembler::lhbrx(Register d, Register s2) { emit_int32( LHBRX_OPCODE| rt(d) | rb(s2));} 2.28 inline void Assembler::lbzx( Register d, Register s2) { emit_int32( LBZX_OPCODE | rt(d) | rb(s2));} 2.29 inline void Assembler::lbz( Register d, int si16 ) { emit_int32( LBZ_OPCODE | rt(d) | d1(si16));} 2.30 inline void Assembler::ld( Register d, int si16 ) { emit_int32( LD_OPCODE | rt(d) | ds(si16));}
3.1 --- a/src/cpu/ppc/vm/interp_masm_ppc_64.cpp Tue Sep 09 00:05:25 2014 +0200 3.2 +++ b/src/cpu/ppc/vm/interp_masm_ppc_64.cpp Mon Sep 08 23:01:01 2014 +0000 3.3 @@ -119,9 +119,15 @@ 3.4 // Call the Interpreter::remove_activation_preserving_args_entry() 3.5 // func to get the address of the same-named entrypoint in the 3.6 // generated interpreter code. 3.7 +#if defined(ABI_ELFv2) 3.8 + call_c(CAST_FROM_FN_PTR(address, 3.9 + Interpreter::remove_activation_preserving_args_entry), 3.10 + relocInfo::none); 3.11 +#else 3.12 call_c(CAST_FROM_FN_PTR(FunctionDescriptor*, 3.13 Interpreter::remove_activation_preserving_args_entry), 3.14 relocInfo::none); 3.15 +#endif 3.16 3.17 // Jump to Interpreter::_remove_activation_preserving_args_entry. 3.18 mtctr(R3_RET); 3.19 @@ -331,29 +337,40 @@ 3.20 void InterpreterMacroAssembler::get_2_byte_integer_at_bcp(int bcp_offset, 3.21 Register Rdst, 3.22 signedOrNot is_signed) { 3.23 +#if defined(VM_LITTLE_ENDIAN) 3.24 + if (bcp_offset) { 3.25 + load_const_optimized(Rdst, bcp_offset); 3.26 + lhbrx(Rdst, R14_bcp, Rdst); 3.27 + } else { 3.28 + lhbrx(Rdst, R14_bcp); 3.29 + } 3.30 + if (is_signed == Signed) { 3.31 + extsh(Rdst, Rdst); 3.32 + } 3.33 +#else 3.34 // Read Java big endian format. 3.35 if (is_signed == Signed) { 3.36 lha(Rdst, bcp_offset, R14_bcp); 3.37 } else { 3.38 lhz(Rdst, bcp_offset, R14_bcp); 3.39 } 3.40 -#if 0 3.41 - assert(Rtmp != Rdst, "need separate temp register"); 3.42 - Register Rfirst = Rtmp; 3.43 - lbz(Rfirst, bcp_offset, R14_bcp); // first byte 3.44 - lbz(Rdst, bcp_offset+1, R14_bcp); // second byte 3.45 - 3.46 - // Rdst = ((Rfirst<<8) & 0xFF00) | (Rdst &~ 0xFF00) 3.47 - rldimi(/*RA=*/Rdst, /*RS=*/Rfirst, /*sh=*/8, /*mb=*/48); 3.48 - if (is_signed == Signed) { 3.49 - extsh(Rdst, Rdst); 3.50 - } 3.51 #endif 3.52 } 3.53 3.54 void InterpreterMacroAssembler::get_4_byte_integer_at_bcp(int bcp_offset, 3.55 Register Rdst, 3.56 signedOrNot is_signed) { 3.57 +#if defined(VM_LITTLE_ENDIAN) 3.58 + if (bcp_offset) { 3.59 + load_const_optimized(Rdst, bcp_offset); 3.60 + lwbrx(Rdst, R14_bcp, Rdst); 3.61 + } else { 3.62 + lwbrx(Rdst, R14_bcp); 3.63 + } 3.64 + if (is_signed == Signed) { 3.65 + extsw(Rdst, Rdst); 3.66 + } 3.67 +#else 3.68 // Read Java big endian format. 3.69 if (bcp_offset & 3) { // Offset unaligned? 3.70 load_const_optimized(Rdst, bcp_offset); 3.71 @@ -369,19 +386,27 @@ 3.72 lwz(Rdst, bcp_offset, R14_bcp); 3.73 } 3.74 } 3.75 +#endif 3.76 } 3.77 3.78 + 3.79 // Load the constant pool cache index from the bytecode stream. 3.80 // 3.81 // Kills / writes: 3.82 // - Rdst, Rscratch 3.83 void InterpreterMacroAssembler::get_cache_index_at_bcp(Register Rdst, int bcp_offset, size_t index_size) { 3.84 assert(bcp_offset > 0, "bcp is still pointing to start of bytecode"); 3.85 + // Cache index is always in the native format, courtesy of Rewriter. 3.86 if (index_size == sizeof(u2)) { 3.87 - get_2_byte_integer_at_bcp(bcp_offset, Rdst, Unsigned); 3.88 + lhz(Rdst, bcp_offset, R14_bcp); 3.89 } else if (index_size == sizeof(u4)) { 3.90 assert(EnableInvokeDynamic, "giant index used only for JSR 292"); 3.91 - get_4_byte_integer_at_bcp(bcp_offset, Rdst, Signed); 3.92 + if (bcp_offset & 3) { 3.93 + load_const_optimized(Rdst, bcp_offset); 3.94 + lwax(Rdst, R14_bcp, Rdst); 3.95 + } else { 3.96 + lwa(Rdst, bcp_offset, R14_bcp); 3.97 + } 3.98 assert(ConstantPool::decode_invokedynamic_index(~123) == 123, "else change next line"); 3.99 nand(Rdst, Rdst, Rdst); // convert to plain index 3.100 } else if (index_size == sizeof(u1)) { 3.101 @@ -398,6 +423,29 @@ 3.102 add(cache, R27_constPoolCache, cache); 3.103 } 3.104 3.105 +// Load 4-byte signed or unsigned integer in Java format (that is, big-endian format) 3.106 +// from (Rsrc)+offset. 3.107 +void InterpreterMacroAssembler::get_u4(Register Rdst, Register Rsrc, int offset, 3.108 + signedOrNot is_signed) { 3.109 +#if defined(VM_LITTLE_ENDIAN) 3.110 + if (offset) { 3.111 + load_const_optimized(Rdst, offset); 3.112 + lwbrx(Rdst, Rdst, Rsrc); 3.113 + } else { 3.114 + lwbrx(Rdst, Rsrc); 3.115 + } 3.116 + if (is_signed == Signed) { 3.117 + extsw(Rdst, Rdst); 3.118 + } 3.119 +#else 3.120 + if (is_signed == Signed) { 3.121 + lwa(Rdst, offset, Rsrc); 3.122 + } else { 3.123 + lwz(Rdst, offset, Rsrc); 3.124 + } 3.125 +#endif 3.126 +} 3.127 + 3.128 // Load object from cpool->resolved_references(index). 3.129 void InterpreterMacroAssembler::load_resolved_reference_at_index(Register result, Register index) { 3.130 assert_different_registers(result, index);
4.1 --- a/src/cpu/ppc/vm/interp_masm_ppc_64.hpp Tue Sep 09 00:05:25 2014 +0200 4.2 +++ b/src/cpu/ppc/vm/interp_masm_ppc_64.hpp Mon Sep 08 23:01:01 2014 +0000 4.3 @@ -130,6 +130,7 @@ 4.4 4.5 void get_cache_and_index_at_bcp(Register cache, int bcp_offset, size_t index_size = sizeof(u2)); 4.6 4.7 + void get_u4(Register Rdst, Register Rsrc, int offset, signedOrNot is_signed); 4.8 4.9 // common code 4.10
5.1 --- a/src/cpu/ppc/vm/templateInterpreter_ppc.cpp Tue Sep 09 00:05:25 2014 +0200 5.2 +++ b/src/cpu/ppc/vm/templateInterpreter_ppc.cpp Mon Sep 08 23:01:01 2014 +0000 5.3 @@ -175,8 +175,12 @@ 5.4 const Register size = R12_scratch2; 5.5 __ get_cache_and_index_at_bcp(cache, 1, index_size); 5.6 5.7 - // Big Endian (get least significant byte of 64 bit value): 5.8 + // Get least significant byte of 64 bit value: 5.9 +#if defined(VM_LITTLE_ENDIAN) 5.10 + __ lbz(size, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset()), cache); 5.11 +#else 5.12 __ lbz(size, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset()) + 7, cache); 5.13 +#endif 5.14 __ sldi(size, size, Interpreter::logStackElementSize); 5.15 __ add(R15_esp, R15_esp, size); 5.16 __ dispatch_next(state, step); 5.17 @@ -857,7 +861,9 @@ 5.18 // Our signature handlers copy required arguments to the C stack 5.19 // (outgoing C args), R3_ARG1 to R10_ARG8, and FARG1 to FARG13. 5.20 __ mr(R3_ARG1, R18_locals); 5.21 +#if !defined(ABI_ELFv2) 5.22 __ ld(signature_handler_fd, 0, signature_handler_fd); 5.23 +#endif 5.24 5.25 __ call_stub(signature_handler_fd); 5.26 5.27 @@ -1019,8 +1025,13 @@ 5.28 // native result across the call. No oop is present. 5.29 5.30 __ mr(R3_ARG1, R16_thread); 5.31 +#if defined(ABI_ELFv2) 5.32 + __ call_c(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), 5.33 + relocInfo::none); 5.34 +#else 5.35 __ call_c(CAST_FROM_FN_PTR(FunctionDescriptor*, JavaThread::check_special_condition_for_native_trans), 5.36 relocInfo::none); 5.37 +#endif 5.38 5.39 __ bind(sync_check_done); 5.40
6.1 --- a/src/cpu/ppc/vm/templateTable_ppc_64.cpp Tue Sep 09 00:05:25 2014 +0200 6.2 +++ b/src/cpu/ppc/vm/templateTable_ppc_64.cpp Mon Sep 08 23:01:01 2014 +0000 6.3 @@ -188,8 +188,12 @@ 6.4 assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range"); 6.5 assert(load_bc_into_bc_reg, "we use bc_reg as temp"); 6.6 __ get_cache_and_index_at_bcp(Rtemp /* dst = cache */, 1); 6.7 - // Big Endian: ((*(cache+indices))>>((1+byte_no)*8))&0xFF 6.8 + // ((*(cache+indices))>>((1+byte_no)*8))&0xFF: 6.9 +#if defined(VM_LITTLE_ENDIAN) 6.10 + __ lbz(Rnew_bc, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset()) + 1 + byte_no, Rtemp); 6.11 +#else 6.12 __ lbz(Rnew_bc, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset()) + 7 - (1 + byte_no), Rtemp); 6.13 +#endif 6.14 __ cmpwi(CCR0, Rnew_bc, 0); 6.15 __ li(Rnew_bc, (unsigned int)(unsigned char)new_bc); 6.16 __ beq(CCR0, L_patch_done); 6.17 @@ -1838,8 +1842,8 @@ 6.18 __ clrrdi(Rdef_offset_addr, Rdef_offset_addr, log2_long((jlong)BytesPerInt)); 6.19 6.20 // Load lo & hi. 6.21 - __ lwz(Rlow_byte, BytesPerInt, Rdef_offset_addr); 6.22 - __ lwz(Rhigh_byte, BytesPerInt * 2, Rdef_offset_addr); 6.23 + __ get_u4(Rlow_byte, Rdef_offset_addr, BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.24 + __ get_u4(Rhigh_byte, Rdef_offset_addr, 2 *BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.25 6.26 // Check for default case (=index outside [low,high]). 6.27 __ cmpw(CCR0, R17_tos, Rlow_byte); 6.28 @@ -1853,12 +1857,17 @@ 6.29 __ profile_switch_case(Rindex, Rhigh_byte /* scratch */, Rscratch1, Rscratch2); 6.30 __ sldi(Rindex, Rindex, LogBytesPerInt); 6.31 __ addi(Rindex, Rindex, 3 * BytesPerInt); 6.32 +#if defined(VM_LITTLE_ENDIAN) 6.33 + __ lwbrx(Roffset, Rdef_offset_addr, Rindex); 6.34 + __ extsw(Roffset, Roffset); 6.35 +#else 6.36 __ lwax(Roffset, Rdef_offset_addr, Rindex); 6.37 +#endif 6.38 __ b(Ldispatch); 6.39 6.40 __ bind(Ldefault_case); 6.41 __ profile_switch_default(Rhigh_byte, Rscratch1); 6.42 - __ lwa(Roffset, 0, Rdef_offset_addr); 6.43 + __ get_u4(Roffset, Rdef_offset_addr, 0, InterpreterMacroAssembler::Signed); 6.44 6.45 __ bind(Ldispatch); 6.46 6.47 @@ -1874,12 +1883,11 @@ 6.48 // Table switch using linear search through cases. 6.49 // Bytecode stream format: 6.50 // Bytecode (1) | 4-byte padding | default offset (4) | count (4) | value/offset pair1 (8) | value/offset pair2 (8) | ... 6.51 -// Note: Everything is big-endian format here. So on little endian machines, we have to revers offset and count and cmp value. 6.52 +// Note: Everything is big-endian format here. 6.53 void TemplateTable::fast_linearswitch() { 6.54 transition(itos, vtos); 6.55 6.56 - Label Lloop_entry, Lsearch_loop, Lfound, Lcontinue_execution, Ldefault_case; 6.57 - 6.58 + Label Lloop_entry, Lsearch_loop, Lcontinue_execution, Ldefault_case; 6.59 Register Rcount = R3_ARG1, 6.60 Rcurrent_pair = R4_ARG2, 6.61 Rdef_offset_addr = R5_ARG3, // Is going to contain address of default offset. 6.62 @@ -1893,47 +1901,40 @@ 6.63 __ clrrdi(Rdef_offset_addr, Rdef_offset_addr, log2_long((jlong)BytesPerInt)); 6.64 6.65 // Setup loop counter and limit. 6.66 - __ lwz(Rcount, BytesPerInt, Rdef_offset_addr); // Load count. 6.67 + __ get_u4(Rcount, Rdef_offset_addr, BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.68 __ addi(Rcurrent_pair, Rdef_offset_addr, 2 * BytesPerInt); // Rcurrent_pair now points to first pair. 6.69 6.70 - // Set up search loop. 6.71 + __ mtctr(Rcount); 6.72 __ cmpwi(CCR0, Rcount, 0); 6.73 - __ beq(CCR0, Ldefault_case); 6.74 - 6.75 - __ mtctr(Rcount); 6.76 - 6.77 - // linear table search 6.78 - __ bind(Lsearch_loop); 6.79 - 6.80 - __ lwz(Rvalue, 0, Rcurrent_pair); 6.81 - __ lwa(Roffset, 1 * BytesPerInt, Rcurrent_pair); 6.82 - 6.83 - __ cmpw(CCR0, Rvalue, Rcmp_value); 6.84 - __ beq(CCR0, Lfound); 6.85 - 6.86 - __ addi(Rcurrent_pair, Rcurrent_pair, 2 * BytesPerInt); 6.87 - __ bdnz(Lsearch_loop); 6.88 - 6.89 - // default case 6.90 + __ bne(CCR0, Lloop_entry); 6.91 + 6.92 + // Default case 6.93 __ bind(Ldefault_case); 6.94 - 6.95 - __ lwa(Roffset, 0, Rdef_offset_addr); 6.96 + __ get_u4(Roffset, Rdef_offset_addr, 0, InterpreterMacroAssembler::Signed); 6.97 if (ProfileInterpreter) { 6.98 __ profile_switch_default(Rdef_offset_addr, Rcount/* scratch */); 6.99 - __ b(Lcontinue_execution); 6.100 } 6.101 - 6.102 - // Entry found, skip Roffset bytecodes and continue. 6.103 - __ bind(Lfound); 6.104 + __ b(Lcontinue_execution); 6.105 + 6.106 + // Next iteration 6.107 + __ bind(Lsearch_loop); 6.108 + __ bdz(Ldefault_case); 6.109 + __ addi(Rcurrent_pair, Rcurrent_pair, 2 * BytesPerInt); 6.110 + __ bind(Lloop_entry); 6.111 + __ get_u4(Rvalue, Rcurrent_pair, 0, InterpreterMacroAssembler::Unsigned); 6.112 + __ cmpw(CCR0, Rvalue, Rcmp_value); 6.113 + __ bne(CCR0, Lsearch_loop); 6.114 + 6.115 + // Found, load offset. 6.116 + __ get_u4(Roffset, Rcurrent_pair, BytesPerInt, InterpreterMacroAssembler::Signed); 6.117 + // Calculate case index and profile 6.118 + __ mfctr(Rcurrent_pair); 6.119 if (ProfileInterpreter) { 6.120 - // Calc the num of the pair we hit. Careful, Rcurrent_pair points 2 ints 6.121 - // beyond the actual current pair due to the auto update load above! 6.122 - __ sub(Rcurrent_pair, Rcurrent_pair, Rdef_offset_addr); 6.123 - __ addi(Rcurrent_pair, Rcurrent_pair, - 2 * BytesPerInt); 6.124 - __ srdi(Rcurrent_pair, Rcurrent_pair, LogBytesPerInt + 1); 6.125 + __ sub(Rcurrent_pair, Rcount, Rcurrent_pair); 6.126 __ profile_switch_case(Rcurrent_pair, Rcount /*scratch*/, Rdef_offset_addr/*scratch*/, Rscratch); 6.127 - __ bind(Lcontinue_execution); 6.128 } 6.129 + 6.130 + __ bind(Lcontinue_execution); 6.131 __ add(R14_bcp, Roffset, R14_bcp); 6.132 __ dispatch_next(vtos); 6.133 } 6.134 @@ -1989,7 +1990,7 @@ 6.135 6.136 // initialize i & j 6.137 __ li(Ri,0); 6.138 - __ lwz(Rj, -BytesPerInt, Rarray); 6.139 + __ get_u4(Rj, Rarray, -BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.140 6.141 // and start. 6.142 Label entry; 6.143 @@ -2006,7 +2007,11 @@ 6.144 // i = h; 6.145 // } 6.146 __ sldi(Rscratch, Rh, log_entry_size); 6.147 +#if defined(VM_LITTLE_ENDIAN) 6.148 + __ lwbrx(Rscratch, Rscratch, Rarray); 6.149 +#else 6.150 __ lwzx(Rscratch, Rscratch, Rarray); 6.151 +#endif 6.152 6.153 // if (key < current value) 6.154 // Rh = Rj 6.155 @@ -2038,20 +2043,20 @@ 6.156 // Ri = value offset 6.157 __ sldi(Ri, Ri, log_entry_size); 6.158 __ add(Ri, Ri, Rarray); 6.159 - __ lwz(Rscratch, 0, Ri); 6.160 + __ get_u4(Rscratch, Ri, 0, InterpreterMacroAssembler::Unsigned); 6.161 6.162 Label not_found; 6.163 // Ri = offset offset 6.164 __ cmpw(CCR0, Rkey, Rscratch); 6.165 __ beq(CCR0, not_found); 6.166 // entry not found -> j = default offset 6.167 - __ lwz(Rj, -2 * BytesPerInt, Rarray); 6.168 + __ get_u4(Rj, Rarray, -2 * BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.169 __ b(default_case); 6.170 6.171 __ bind(not_found); 6.172 // entry found -> j = offset 6.173 __ profile_switch_case(Rh, Rj, Rscratch, Rkey); 6.174 - __ lwz(Rj, BytesPerInt, Ri); 6.175 + __ get_u4(Rj, Ri, BytesPerInt, InterpreterMacroAssembler::Unsigned); 6.176 6.177 if (ProfileInterpreter) { 6.178 __ b(continue_execution); 6.179 @@ -2146,8 +2151,11 @@ 6.180 6.181 assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range"); 6.182 // We are resolved if the indices offset contains the current bytecode. 6.183 - // Big Endian: 6.184 +#if defined(VM_LITTLE_ENDIAN) 6.185 + __ lbz(Rscratch, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset()) + byte_no + 1, Rcache); 6.186 +#else 6.187 __ lbz(Rscratch, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset()) + 7 - (byte_no + 1), Rcache); 6.188 +#endif 6.189 // Acquire by cmp-br-isync (see below). 6.190 __ cmpdi(CCR0, Rscratch, (int)bytecode()); 6.191 __ beq(CCR0, Lresolved);
