Matching for baseIndexOffset8 is OK.

Wed, 17 Aug 2016 15:26:28 +0800

author
fujie
date
Wed, 17 Aug 2016 15:26:28 +0800
changeset 68
13c1934c50bb
parent 67
c17a7a85055f
child 69
75f42d5c9847

Matching for baseIndexOffset8 is OK.

* Before Opt.
06c SLL S0, A2 @ convI2L_reg
070 salL S0, S0, #2 @ salL_Reg_imm
074 dadd S0, A1, S0 #@addP_reg_reg
078 lw S1, [S0 + #16 (8-bit)] @ indOffset8 #@loadI

* After Opt.
06c salL S0, A2, #2 @ salL_convI2L_Reg_imm
070 lw S1, [A1 + S0 + #16 (8-bit)] @ baseIndexOffset8 #@loadI

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Tue Aug 16 15:31:40 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Aug 17 15:26:28 2016 +0800
     1.3 @@ -3999,7 +3999,7 @@
     1.4  operand indOffset8(mRegP reg, immL8 off)
     1.5  %{
     1.6    constraint(ALLOC_IN_RC(p_reg));
     1.7 -  op_cost(10);
     1.8 +  op_cost(20);
     1.9    match(AddP reg off);
    1.10  
    1.11    format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
    1.12 @@ -4012,7 +4012,7 @@
    1.13  %}
    1.14  
    1.15  // [base + index + offset] 
    1.16 -operand baseIndexOffset8(mRegP base, mRegP index, immL8 off)
    1.17 +operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
    1.18  %{
    1.19    constraint(ALLOC_IN_RC(p_reg));
    1.20    op_cost(5);
    1.21 @@ -4048,7 +4048,7 @@
    1.22    constraint(ALLOC_IN_RC(p_reg));
    1.23    match(AddP addr index);
    1.24  
    1.25 -  op_cost(10);
    1.26 +  op_cost(20);
    1.27    format %{"[$addr + $index] @ indIndex" %}
    1.28    interface(MEMORY_INTER) %{
    1.29      base($addr);
    1.30 @@ -8836,6 +8836,25 @@
    1.31    ins_pipe( ialu_regL_regL );
    1.32  %}
    1.33  
    1.34 +instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
    1.35 +  match(Set dst (LShiftL (ConvI2L src) shift));
    1.36 +  ins_cost(100);
    1.37 +  format %{ "salL    $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
    1.38 +  ins_encode %{
    1.39 +    Register src_reg = as_Register($src$$reg);
    1.40 +    Register dst_reg = as_Register($dst$$reg);
    1.41 +    int      shamt = $shift$$constant;
    1.42 +
    1.43 +    if (__ is_simm(shamt, 5)) {
    1.44 +        __ dsll(dst_reg, src_reg, shamt);
    1.45 +    } else {
    1.46 +       __ move(AT, shamt);
    1.47 +       __ dsllv(dst_reg, src_reg, AT);
    1.48 +    }
    1.49 +  %}
    1.50 +  ins_pipe( ialu_regL_regL );
    1.51 +%}
    1.52 +
    1.53  // Shift Right Long 
    1.54  instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
    1.55    //predicate(UseNewLongLShift);

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