Tue, 23 Aug 2016 15:23:48 +0800
Add slrL_Reg_immI_0_31 and slrL_Reg_immI_32_63 in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Tue Aug 23 14:22:12 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Tue Aug 23 15:23:48 2016 +0800 1.3 @@ -3343,7 +3343,7 @@ 1.4 interface(CONST_INTER); 1.5 %} 1.6 1.7 -operand immI_1_31() %{ 1.8 +operand immI_0_31() %{ 1.9 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 1.10 match(ConI); 1.11 1.12 @@ -9214,15 +9214,41 @@ 1.13 Register creg = T9; 1.14 Register src_reg = as_Register($src$$reg); 1.15 Register dst_reg = as_Register($dst$$reg); 1.16 - Label normal, done, notZero; 1.17 1.18 __ move(creg, $shift$$Register); 1.19 __ andi(creg, creg, 0x3f); 1.20 - __ dsrlv(dst_reg, src_reg, creg); 1.21 + __ dsrlv(dst_reg, src_reg, creg); 1.22 %} 1.23 ins_pipe( ialu_regL_regL ); 1.24 %} 1.25 1.26 +instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{ 1.27 + match(Set dst (URShiftL src shift)); 1.28 + ins_cost(80); 1.29 + format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %} 1.30 + ins_encode %{ 1.31 + Register src_reg = as_Register($src$$reg); 1.32 + Register dst_reg = as_Register($dst$$reg); 1.33 + int shamt = $shift$$constant; 1.34 + 1.35 + __ dsrl(dst_reg, src_reg, shamt); 1.36 + %} 1.37 + ins_pipe( ialu_regL_regL ); 1.38 +%} 1.39 + 1.40 +instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{ 1.41 + match(Set dst (URShiftL src shift)); 1.42 + ins_cost(80); 1.43 + format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %} 1.44 + ins_encode %{ 1.45 + Register src_reg = as_Register($src$$reg); 1.46 + Register dst_reg = as_Register($dst$$reg); 1.47 + int shamt = $shift$$constant; 1.48 + 1.49 + __ dsrl32(dst_reg, src_reg, shamt - 32); 1.50 + %} 1.51 + ins_pipe( ialu_regL_regL ); 1.52 +%} 1.53 1.54 // Xor Instructions 1.55 // Xor Register with Register