# HG changeset patch # User aoqi # Date 1527161210 -28800 # Node ID fd13a567f1795e60859271a86150aeca7f5bcc70 # Parent 2a33b32dd03cd8d2412cc4a188c5e13a5c7a6baa #7046 C2 supports long branch Contributed-by: fujie diff -r 2a33b32dd03c -r fd13a567f179 src/cpu/mips/vm/assembler_mips.cpp --- a/src/cpu/mips/vm/assembler_mips.cpp Thu May 24 19:24:53 2018 +0800 +++ b/src/cpu/mips/vm/assembler_mips.cpp Thu May 24 19:26:50 2018 +0800 @@ -237,7 +237,10 @@ switch(opcode(inst)) { case j_op: case jal_op: - assert(false, "should not use j/jal here"); + case lui_op: + case ori_op: + case daddiu_op: + ShouldNotReachHere(); break; default: assert(is_simm16(v), "must be simm16"); diff -r 2a33b32dd03c -r fd13a567f179 src/cpu/mips/vm/macroAssembler_mips.cpp --- a/src/cpu/mips/vm/macroAssembler_mips.cpp Thu May 24 19:24:53 2018 +0800 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp Thu May 24 19:26:50 2018 +0800 @@ -95,6 +95,7 @@ void MacroAssembler::pd_patch_instruction(address branch, address target) { jint& stub_inst = *(jint*) branch; + jint *pc = (jint *)branch; /* * move(AT, RA); // dadd @@ -106,8 +107,7 @@ move(RA, AT); jr(T9); */ - if(special(stub_inst) == dadd_op) { - jint *pc = (jint *)branch; + if((opcode(stub_inst) == special_op) && (special(stub_inst) == dadd_op)) { assert(opcode(pc[3]) == lui_op && opcode(pc[4]) == ori_op @@ -135,6 +135,14 @@ __ nop(); } return; + } else if (special(pc[4]) == jr_op + && opcode(pc[4]) == special_op + && (((opcode(pc[0]) == lui_op) || opcode(pc[0]) == daddiu_op) || (opcode(pc[0]) == ori_op))) { + + CodeBuffer cb(branch, 4 * 4); + MacroAssembler masm(&cb); + masm.patchable_set48(T9, (long)(target)); + return; } #ifndef PRODUCT @@ -332,6 +340,50 @@ } } +void MacroAssembler::beq_long(Register rs, Register rt, Label& L) { + Label not_taken; + + bne(rs, rt, not_taken); + nop(); + + jmp_far(L); + + bind(not_taken); +} + +void MacroAssembler::bne_long(Register rs, Register rt, Label& L) { + Label not_taken; + + beq(rs, rt, not_taken); + nop(); + + jmp_far(L); + + bind(not_taken); +} + +void MacroAssembler::bc1t_long(Label& L) { + Label not_taken; + + bc1f(not_taken); + nop(); + + jmp_far(L); + + bind(not_taken); +} + +void MacroAssembler::bc1f_long(Label& L) { + Label not_taken; + + bc1t(not_taken); + nop(); + + jmp_far(L); + + bind(not_taken); +} + void MacroAssembler::b_far(Label& L) { if (L.is_bound()) { b_far(target(L)); @@ -747,6 +799,26 @@ } } +void MacroAssembler::jmp_far(Label& L) { + if (L.is_bound()) { + address entry = target(L); + assert(entry != NULL, "jmp most probably wrong"); + InstructionMark im(this); + + relocate(relocInfo::internal_word_type); + patchable_set48(T9, (long)entry); + } else { + InstructionMark im(this); + L.add_patch_at(code(), locator()); + + relocate(relocInfo::internal_word_type); + patchable_set48(T9, (long)pc()); + } + + jr(T9); + nop(); +} + void MacroAssembler::call(address entry) { // c/c++ code assume T9 is entry point, so we just always move entry to t9 // maybe there is some more graceful method to handle this. FIXME diff -r 2a33b32dd03c -r fd13a567f179 src/cpu/mips/vm/macroAssembler_mips.hpp --- a/src/cpu/mips/vm/macroAssembler_mips.hpp Thu May 24 19:24:53 2018 +0800 +++ b/src/cpu/mips/vm/macroAssembler_mips.hpp Thu May 24 19:26:50 2018 +0800 @@ -511,6 +511,7 @@ // Jumps void jmp(address entry); void jmp(address entry, relocInfo::relocType rtype); + void jmp_far(Label& L); // always long jumps /* branches may exceed 16-bit offset */ void b_far(address entry); @@ -522,6 +523,12 @@ void beq_far (Register rs, Register rt, address entry); void beq_far (Register rs, Register rt, Label& L); + // For C2 to support long branches + void beq_long (Register rs, Register rt, Label& L); + void bne_long (Register rs, Register rt, Label& L); + void bc1t_long (Label& L); + void bc1f_long (Label& L); + void patchable_call(address target); void general_call(address target); diff -r 2a33b32dd03c -r fd13a567f179 src/cpu/mips/vm/mips_64.ad --- a/src/cpu/mips/vm/mips_64.ad Thu May 24 19:24:53 2018 +0800 +++ b/src/cpu/mips/vm/mips_64.ad Thu May 24 19:26:50 2018 +0800 @@ -654,7 +654,8 @@ bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { int offs = offset - br_size + 4; // To be conservative on MIPS - return Assembler::is_simm16((offs + 4) >> 2) && Assembler::is_simm16((offs - 4) >> 2); + const int safety_zone = 3 * BytesPerInstWord; + return Assembler::is_simm16((offs<0 ? offs-safety_zone : offs+safety_zone) >> 2); } @@ -1562,7 +1563,7 @@ // Materialize the constant table base. address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); - __ relocate(relocInfo::internal_pc_type); + __ relocate(relocInfo::internal_word_type); __ patchable_set48(Rtoc, (long)baseaddr); } } @@ -6698,17 +6699,12 @@ format %{ "JMP $labl #@jmpDir_long" %} ins_encode %{ - Label &L = *($labl$$label); - if(&L) - __ b(L); - else - __ b(int(0)); - __ nop(); - __ nop(); - %} - - ins_pipe( pipe_jump ); - ins_pc_relative(1); + Label* L = $labl$$label; + __ jmp_far(*L); + %} + + ins_pipe( pipe_jump ); + //ins_pc_relative(1); %} // Jump Direct Conditional - Label defines a relative address from Jcc+1 @@ -6721,55 +6717,35 @@ ins_encode %{ Register op1 = $src1$$Register; Register op2 = $src2$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cop$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; case 0x03: //above __ slt(AT, op2, op1); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x04: //above_equal __ slt(AT, op1, op2); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ slt(AT, op1, op2); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x06: //below_equal __ slt(AT, op2, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pipe( pipe_jump ); ins_pc_relative(1); @@ -6784,57 +6760,37 @@ ins_encode %{ Register op1 = $src1$$Register; Register op2 = AT; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cop$$cmpcode; __ move(op2, $src2$$constant); switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; case 0x03: //above __ slt(AT, op2, op1); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x04: //above_equal __ slt(AT, op1, op2); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ slt(AT, op1, op2); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x06: //below_equal __ slt(AT, op2, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pipe( pipe_jump ); ins_pc_relative(1); @@ -6850,25 +6806,17 @@ format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags_long" %} ins_encode %{ - Label &L = *($labl$$label); + Label* L = $labl$$label; switch($cop$$cmpcode) { case 0x01: //equal - if (&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x02: //not equal - if (&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pipe( pipe_jump ); @@ -6886,27 +6834,19 @@ ins_encode %{ Register op1 = $op1$$Register; Register op2 = R0; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -6924,28 +6864,20 @@ ins_encode %{ Register op1 = $op1$$Register; Register op2 = R0; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -6964,55 +6896,35 @@ ins_encode %{ Register op1 = $op1$$Register; Register op2 = $op2$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; case 0x03: //above __ sltu(AT, op2, op1); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //above_equal __ sltu(AT, op1, op2); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ sltu(AT, op1, op2); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //below_equal __ sltu(AT, op2, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7029,27 +6941,19 @@ ins_encode %{ Register op1 = $op1$$Register; Register op2 = R0; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} //TODO: pipe_branchP or create pipe_branchN LEE ins_pc_relative(1); @@ -7066,55 +6970,35 @@ ins_encode %{ Register op1_reg = $op1$$Register; Register op2_reg = $op2$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1_reg, op2_reg, L); - else - __ beq(op1_reg, op2_reg, (int)0); + __ beq_long(op1_reg, op2_reg, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1_reg, op2_reg, L); - else - __ bne(op1_reg, op2_reg, (int)0); + __ bne_long(op1_reg, op2_reg, *L); break; case 0x03: //above __ sltu(AT, op2_reg, op1_reg); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //above_equal __ sltu(AT, op1_reg, op2_reg); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ sltu(AT, op1_reg, op2_reg); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //below_equal __ sltu(AT, op2_reg, op1_reg); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); ins_pipe( pipe_alu_branch ); @@ -7128,55 +7012,35 @@ ins_encode %{ Register op1 = $src1$$Register; Register op2 = $src2$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; case 0x03: //above __ sltu(AT, op2, op1); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x04: //above_equal __ sltu(AT, op1, op2); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ sltu(AT, op1, op2); - if(&L) - __ bne(AT, R0, L); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *L); break; case 0x06: //below_equal __ sltu(AT, op2, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7192,56 +7056,36 @@ ins_encode %{ Register op1 = $src1$$Register; int val = $src2$$constant; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; __ move(AT, val); switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, AT, L); - else - __ beq(op1, AT, (int)0); + __ beq_long(op1, AT, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, AT, L); - else - __ bne(op1, AT, (int)0); + __ bne_long(op1, AT, *L); break; case 0x03: //above __ sltu(AT, AT, op1); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //above_equal __ sltu(AT, op1, AT); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ sltu(AT, op1, AT); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //below_equal __ sltu(AT, AT, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7256,55 +7100,35 @@ ins_encode %{ Register op1 = $src1$$Register; Register op2 = $src2$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, op2, L); - else - __ beq(op1, op2, (int)0); + __ beq_long(op1, op2, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, op2, L); - else - __ bne(op1, op2, (int)0); + __ bne_long(op1, op2, *L); break; case 0x03: //above __ slt(AT, op2, op1); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //above_equal __ slt(AT, op1, op2); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ slt(AT, op1, op2); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //below_equal __ slt(AT, op2, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); - break; + __ beq_long(AT, R0, *L); + break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7319,58 +7143,41 @@ ins_encode %{ Register op1 = $src1$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, R0, L); - else - __ beq(op1, R0, (int)0); + __ beq_long(op1, R0, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, R0, L); - else - __ bne(op1, R0, (int)0); + __ bne_long(op1, R0, *L); break; case 0x03: //greater - if(&L) - __ bgtz(op1, L); - else - __ bgtz(op1, (int)0); + __ slt(AT, R0, op1); + __ bne_long(R0, AT, *L); break; case 0x04: //greater_equal - if(&L) - __ bgez(op1, L); - else - __ bgez(op1, (int)0); + __ slt(AT, op1, R0); + __ beq_long(AT, R0, *L); break; case 0x05: //less - if(&L) - __ bltz(op1, L); - else - __ bltz(op1, (int)0); + __ slt(AT, op1, R0); + __ bne_long(R0, AT, *L); break; case 0x06: //less_equal - if(&L) - __ blez(op1, L); - else - __ blez(op1, (int)0); - break; + __ slt(AT, R0, op1); + __ beq_long(AT, R0, *L); + break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); ins_pipe( pipe_alu_branch ); %} - instruct branchConI_reg_imm_long(cmpOp cmp, mRegI src1, immI src2, label labl) %{ match( If cmp (CmpI src1 src2) ); effect(USE labl); @@ -7380,56 +7187,36 @@ ins_encode %{ Register op1 = $src1$$Register; int val = $src2$$constant; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; __ move(AT, val); switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, AT, L); - else - __ beq(op1, AT, (int)0); + __ beq_long(op1, AT, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, AT, L); - else - __ bne(op1, AT, (int)0); + __ bne_long(op1, AT, *L); break; case 0x03: //greater __ slt(AT, AT, op1); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //greater_equal __ slt(AT, op1, AT); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //less __ slt(AT, op1, AT); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //less_equal __ slt(AT, AT, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7443,49 +7230,32 @@ ins_encode %{ Register op1 = $src1$$Register; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&L) - __ beq(op1, R0, L); - else - __ beq(op1, R0, (int)0); + __ beq_long(op1, R0, *L); break; case 0x02: //not_equal - if (&L) - __ bne(op1, R0, L); - else - __ bne(op1, R0, (int)0); + __ bne_long(op1, R0, *L); break; case 0x03: //above - if(&L) - __ bne(R0, op1, L); - else - __ bne(R0, op1, (int)0); + __ bne_long(R0, op1, *L); break; case 0x04: //above_equal - if(&L) - __ beq(R0, R0, L); - else - __ beq(R0, R0, (int)0); + __ beq_long(R0, R0, *L); break; case 0x05: //below return; break; case 0x06: //below_equal - if(&L) - __ beq(op1, R0, L); - else - __ beq(op1, R0, (int)0); + __ beq_long(op1, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); - %} + %} ins_pc_relative(1); ins_pipe( pipe_alu_branch ); @@ -7501,59 +7271,39 @@ ins_encode %{ Register op1 = $src1$$Register; int val = $src2$$constant; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal __ move(AT, val); - if (&L) - __ beq(op1, AT, L); - else - __ beq(op1, AT, (int)0); + __ beq_long(op1, AT, *L); break; case 0x02: //not_equal __ move(AT, val); - if (&L) - __ bne(op1, AT, L); - else - __ bne(op1, AT, (int)0); + __ bne_long(op1, AT, *L); break; case 0x03: //above __ move(AT, val); __ sltu(AT, AT, op1); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x04: //above_equal __ sltiu(AT, op1, val); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; case 0x05: //below __ sltiu(AT, op1, val); - if(&L) - __ bne(R0, AT, L); - else - __ bne(R0, AT, (int)0); + __ bne_long(R0, AT, *L); break; case 0x06: //below_equal __ move(AT, val); __ sltu(AT, AT, op1); - if(&L) - __ beq(AT, R0, L); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7571,70 +7321,41 @@ Register opr1_reg = as_Register($src1$$reg); Register opr2_reg = as_Register($src2$$reg); - Label &target = *($labl$$label); + Label* target = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&target) - __ beq(opr1_reg, opr2_reg, target); - else - __ beq(opr1_reg, opr2_reg, (int)0); - __ delayed()->nop(); + __ beq_long(opr1_reg, opr2_reg, *target); break; case 0x02: //not_equal - if(&target) - __ bne(opr1_reg, opr2_reg, target); - else - __ bne(opr1_reg, opr2_reg, (int)0); - __ delayed()->nop(); + __ bne_long(opr1_reg, opr2_reg, *target); break; case 0x03: //greater __ slt(AT, opr2_reg, opr1_reg); - if(&target) - __ bne(AT, R0, target); - else - __ bne(AT, R0, (int)0); - __ delayed()->nop(); + __ bne_long(AT, R0, *target); break; case 0x04: //greater_equal __ slt(AT, opr1_reg, opr2_reg); - if(&target) - __ beq(AT, R0, target); - else - __ beq(AT, R0, (int)0); - __ delayed()->nop(); - + __ beq_long(AT, R0, *target); break; case 0x05: //less __ slt(AT, opr1_reg, opr2_reg); - if(&target) - __ bne(AT, R0, target); - else - __ bne(AT, R0, (int)0); - __ delayed()->nop(); - + __ bne_long(AT, R0, *target); break; case 0x06: //less_equal __ slt(AT, opr2_reg, opr1_reg); - - if(&target) - __ beq(AT, R0, target); - else - __ beq(AT, R0, (int)0); - __ delayed()->nop(); - + __ beq_long(AT, R0, *target); break; default: Unimplemented(); } - __ nop(); %} @@ -7642,7 +7363,6 @@ ins_pipe( pipe_alu_branch ); %} - instruct branchConL_regL_immL0_long(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{ match( If cmp (CmpL src1 zero) ); effect(USE labl); @@ -7651,58 +7371,43 @@ ins_encode %{ Register opr1_reg = as_Register($src1$$reg); - Label &target = *($labl$$label); + Register opr2_reg = R0; + + Label* target = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal - if (&target) - __ beq(opr1_reg, R0, target); - else - __ beq(opr1_reg, R0, int(0)); + __ beq_long(opr1_reg, opr2_reg, *target); break; case 0x02: //not_equal - if(&target) - __ bne(opr1_reg, R0, target); - else - __ bne(opr1_reg, R0, (int)0); + __ bne_long(opr1_reg, opr2_reg, *target); break; case 0x03: //greater - if(&target) - __ bgtz(opr1_reg, target); - else - __ bgtz(opr1_reg, (int)0); - break; + __ slt(AT, opr2_reg, opr1_reg); + __ bne_long(AT, R0, *target); + break; case 0x04: //greater_equal - if(&target) - __ bgez(opr1_reg, target); - else - __ bgez(opr1_reg, (int)0); + __ slt(AT, opr1_reg, opr2_reg); + __ beq_long(AT, R0, *target); break; case 0x05: //less - __ slt(AT, opr1_reg, R0); - if(&target) - __ bne(AT, R0, target); - else - __ bne(AT, R0, (int)0); + __ slt(AT, opr1_reg, opr2_reg); + __ bne_long(AT, R0, *target); break; case 0x06: //less_equal - if (&target) - __ blez(opr1_reg, target); - else - __ blez(opr1_reg, int(0)); + __ slt(AT, opr2_reg, opr1_reg); + __ beq_long(AT, R0, *target); break; default: - Unimplemented(); - } - __ delayed()->nop(); - __ nop(); + Unimplemented(); + } %} @@ -7720,63 +7425,43 @@ Register opr1_reg = as_Register($src1$$reg); Register opr2_reg = AT; - Label &target = *($labl$$label); + Label* target = $labl$$label; int flag = $cmp$$cmpcode; __ set64(opr2_reg, $src2$$constant); switch(flag) { case 0x01: //equal - if (&target) - __ beq(opr1_reg, opr2_reg, target); - else - __ beq(opr1_reg, opr2_reg, (int)0); + __ beq_long(opr1_reg, opr2_reg, *target); break; case 0x02: //not_equal - if(&target) - __ bne(opr1_reg, opr2_reg, target); - else - __ bne(opr1_reg, opr2_reg, (int)0); + __ bne_long(opr1_reg, opr2_reg, *target); break; case 0x03: //greater __ slt(AT, opr2_reg, opr1_reg); - if(&target) - __ bne(AT, R0, target); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *target); break; case 0x04: //greater_equal __ slt(AT, opr1_reg, opr2_reg); - if(&target) - __ beq(AT, R0, target); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *target); break; case 0x05: //less __ slt(AT, opr1_reg, opr2_reg); - if(&target) - __ bne(AT, R0, target); - else - __ bne(AT, R0, (int)0); + __ bne_long(AT, R0, *target); break; case 0x06: //less_equal __ slt(AT, opr2_reg, opr1_reg); - if(&target) - __ beq(AT, R0, target); - else - __ beq(AT, R0, (int)0); + __ beq_long(AT, R0, *target); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} @@ -7794,57 +7479,37 @@ ins_encode %{ FloatRegister reg_op1 = $src1$$FloatRegister; FloatRegister reg_op2 = $src2$$FloatRegister; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal __ c_eq_s(reg_op1, reg_op2); - if (&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; case 0x02: //not_equal __ c_eq_s(reg_op1, reg_op2); - if (&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x03: //greater __ c_ule_s(reg_op1, reg_op2); - if(&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x04: //greater_equal __ c_ult_s(reg_op1, reg_op2); - if(&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x05: //less __ c_ult_s(reg_op1, reg_op2); - if(&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; case 0x06: //less_equal __ c_ule_s(reg_op1, reg_op2); - if(&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7859,58 +7524,38 @@ ins_encode %{ FloatRegister reg_op1 = $src1$$FloatRegister; FloatRegister reg_op2 = $src2$$FloatRegister; - Label &L = *($labl$$label); + Label* L = $labl$$label; int flag = $cmp$$cmpcode; switch(flag) { case 0x01: //equal __ c_eq_d(reg_op1, reg_op2); - if (&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; case 0x02: //not_equal //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs. __ c_eq_d(reg_op1, reg_op2); - if (&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x03: //greater __ c_ule_d(reg_op1, reg_op2); - if(&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x04: //greater_equal __ c_ult_d(reg_op1, reg_op2); - if(&L) - __ bc1f(L); - else - __ bc1f((int)0); + __ bc1f_long(*L); break; case 0x05: //less __ c_ult_d(reg_op1, reg_op2); - if(&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; case 0x06: //less_equal __ c_ule_d(reg_op1, reg_op2); - if(&L) - __ bc1t(L); - else - __ bc1t((int)0); + __ bc1t_long(*L); break; default: Unimplemented(); } - __ nop(); - __ nop(); %} ins_pc_relative(1); @@ -7934,7 +7579,7 @@ if(&L) __ b(L); else - __ b(int(0)); + __ b(int(0)); __ nop(); %} diff -r 2a33b32dd03c -r fd13a567f179 src/cpu/mips/vm/relocInfo_mips.cpp --- a/src/cpu/mips/vm/relocInfo_mips.cpp Thu May 24 19:24:53 2018 +0800 +++ b/src/cpu/mips/vm/relocInfo_mips.cpp Thu May 24 19:26:50 2018 +0800 @@ -120,7 +120,6 @@ address Relocation::pd_get_address_from_code() { - tty->print_cr("%s: %d", __func__, __LINE__); //aoqi_test NativeMovConstReg* ni = nativeMovConstReg_at(addr()); return (address)ni->data(); } diff -r 2a33b32dd03c -r fd13a567f179 src/share/vm/opto/output.cpp --- a/src/share/vm/opto/output.cpp Thu May 24 19:24:53 2018 +0800 +++ b/src/share/vm/opto/output.cpp Thu May 24 19:26:50 2018 +0800 @@ -554,10 +554,6 @@ DEBUG_ONLY( jmp_target[i] = bnum; ); DEBUG_ONLY( jmp_rule[i] = mach->rule(); ); } else { -#ifdef MIPS64 - env()->record_method_not_compilable("Branch out of range for MIPS"); - return; -#endif // The jump distance is not short, try again during next iteration. has_short_branch_candidate = true; } @@ -1169,9 +1165,6 @@ // Pre-compute the length of blocks and replace // long branches with short if machine supports it. shorten_branches(blk_starts, code_req, locs_req, stub_req); -#ifdef MIPS64 - if (failing()) return NULL; // Branch out of range for MIPS -#endif // nmethod and CodeBuffer count stubs & constants as part of method's code. // class HandlerImpl is platform-specific and defined in the *.ad files.