# HG changeset patch
# User aoqi
# Date 1465694818 -28800
# Node ID c6d15c517c0004659f372ef715fef1e199ddf0fd
# Parent  9427473af9a292c74435eb6be284e4de67321dc5
[Interpreter] Fixed unaligned load in MacroAssembler::biased_locking_enter.
If tmp_reg = lock_reg, ld_ptr(swap_reg, saved_mark_addr) in line 844 may cause unaligned
load and cause slow case of monitorenter. This is because both saved_mark_addr
and tmp_reg use the same register lock_reg.

diff -r 9427473af9a2 -r c6d15c517c00 src/cpu/mips/vm/assembler_mips.cpp
--- a/src/cpu/mips/vm/assembler_mips.cpp	Thu Jun 02 17:52:46 2016 +0800
+++ b/src/cpu/mips/vm/assembler_mips.cpp	Sun Jun 12 09:26:58 2016 +0800
@@ -654,15 +654,12 @@
                                          Label* slow_case,
                                          BiasedLockingCounters* counters) {
   assert(UseBiasedLocking, "why call this otherwise?");
-  //assert(swap_reg == eax, "swap_reg must be eax for cmpxchg");
-  assert_different_registers(lock_reg, obj_reg, swap_reg);
   bool need_tmp_reg = false;
   if (tmp_reg == noreg) {
     need_tmp_reg = true;
-    tmp_reg = lock_reg;
-  } else {
-    assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
+    tmp_reg = T9;
   }
+  assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, AT);
   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
   Address saved_mark_addr(lock_reg, 0);