diff -r 000000000000 -r f90c822e73f8 src/cpu/zero/vm/icache_zero.hpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/zero/vm/icache_zero.hpp	Wed Apr 27 01:25:04 2016 +0800
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2007, 2009 Red Hat, Inc.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP
+#define CPU_ZERO_VM_ICACHE_ZERO_HPP
+
+// Interface for updating the instruction cache.  Whenever the VM
+// modifies code, part of the processor instruction cache potentially
+// has to be flushed.  This implementation is empty: Zero never deals
+// with code, and LLVM handles cache flushing for Shark.
+
+class ICache : public AbstractICache {
+ public:
+  static void initialize() {}
+  static void invalidate_word(address addr) {}
+  static void invalidate_range(address start, int nbytes) {}
+};
+
+#endif // CPU_ZERO_VM_ICACHE_ZERO_HPP