aoqi@0: /* aoqi@0: * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@0: #ifndef CPU_X86_VM_VM_VERSION_X86_HPP aoqi@0: #define CPU_X86_VM_VM_VERSION_X86_HPP aoqi@0: aoqi@0: #include "runtime/globals_extension.hpp" aoqi@0: #include "runtime/vm_version.hpp" aoqi@0: aoqi@0: class VM_Version : public Abstract_VM_Version { aoqi@0: public: aoqi@0: // cpuid result register layouts. These are all unions of a uint32_t aoqi@0: // (in case anyone wants access to the register as a whole) and a bitfield. aoqi@0: aoqi@0: union StdCpuid1Eax { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t stepping : 4, aoqi@0: model : 4, aoqi@0: family : 4, aoqi@0: proc_type : 2, aoqi@0: : 2, aoqi@0: ext_model : 4, aoqi@0: ext_family : 8, aoqi@0: : 4; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union StdCpuid1Ebx { // example, unused aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t brand_id : 8, aoqi@0: clflush_size : 8, aoqi@0: threads_per_cpu : 8, aoqi@0: apic_id : 8; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union StdCpuid1Ecx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t sse3 : 1, aoqi@0: clmul : 1, aoqi@0: : 1, aoqi@0: monitor : 1, aoqi@0: : 1, aoqi@0: vmx : 1, aoqi@0: : 1, aoqi@0: est : 1, aoqi@0: : 1, aoqi@0: ssse3 : 1, aoqi@0: cid : 1, aoqi@0: : 2, aoqi@0: cmpxchg16: 1, aoqi@0: : 4, aoqi@0: dca : 1, aoqi@0: sse4_1 : 1, aoqi@0: sse4_2 : 1, aoqi@0: : 2, aoqi@0: popcnt : 1, aoqi@0: : 1, aoqi@0: aes : 1, aoqi@0: : 1, aoqi@0: osxsave : 1, aoqi@0: avx : 1, aoqi@0: : 3; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union StdCpuid1Edx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t : 4, aoqi@0: tsc : 1, aoqi@0: : 3, aoqi@0: cmpxchg8 : 1, aoqi@0: : 6, aoqi@0: cmov : 1, aoqi@0: : 3, aoqi@0: clflush : 1, aoqi@0: : 3, aoqi@0: mmx : 1, aoqi@0: fxsr : 1, aoqi@0: sse : 1, aoqi@0: sse2 : 1, aoqi@0: : 1, aoqi@0: ht : 1, aoqi@0: : 3; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union DcpCpuid4Eax { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t cache_type : 5, aoqi@0: : 21, aoqi@0: cores_per_cpu : 6; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union DcpCpuid4Ebx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t L1_line_size : 12, aoqi@0: partitions : 10, aoqi@0: associativity : 10; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union TplCpuidBEbx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t logical_cpus : 16, aoqi@0: : 16; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union ExtCpuid1Ecx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t LahfSahf : 1, aoqi@0: CmpLegacy : 1, aoqi@0: : 3, aoqi@0: lzcnt_intel : 1, aoqi@0: lzcnt : 1, aoqi@0: sse4a : 1, aoqi@0: misalignsse : 1, aoqi@0: prefetchw : 1, aoqi@0: : 22; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union ExtCpuid1Edx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t : 22, aoqi@0: mmx_amd : 1, aoqi@0: mmx : 1, aoqi@0: fxsr : 1, aoqi@0: : 4, aoqi@0: long_mode : 1, aoqi@0: tdnow2 : 1, aoqi@0: tdnow : 1; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union ExtCpuid5Ex { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t L1_line_size : 8, aoqi@0: L1_tag_lines : 8, aoqi@0: L1_assoc : 8, aoqi@0: L1_size : 8; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union ExtCpuid7Edx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t : 8, aoqi@0: tsc_invariance : 1, aoqi@0: : 23; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union ExtCpuid8Ecx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t cores_per_cpu : 8, aoqi@0: : 24; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union SefCpuid7Eax { aoqi@0: uint32_t value; aoqi@0: }; aoqi@0: aoqi@0: union SefCpuid7Ebx { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t fsgsbase : 1, aoqi@0: : 2, aoqi@0: bmi1 : 1, aoqi@0: : 1, aoqi@0: avx2 : 1, aoqi@0: : 2, aoqi@0: bmi2 : 1, aoqi@0: erms : 1, aoqi@0: : 1, aoqi@0: rtm : 1, aoqi@0: : 20; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: union XemXcr0Eax { aoqi@0: uint32_t value; aoqi@0: struct { aoqi@0: uint32_t x87 : 1, aoqi@0: sse : 1, aoqi@0: ymm : 1, aoqi@0: : 29; aoqi@0: } bits; aoqi@0: }; aoqi@0: aoqi@0: protected: aoqi@0: static int _cpu; aoqi@0: static int _model; aoqi@0: static int _stepping; aoqi@0: static int _cpuFeatures; // features returned by the "cpuid" instruction aoqi@0: // 0 if this instruction is not available aoqi@0: static const char* _features_str; aoqi@0: aoqi@0: static address _cpuinfo_segv_addr; // address of instruction which causes SEGV aoqi@0: static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV aoqi@0: aoqi@0: enum { aoqi@0: CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) aoqi@0: CPU_CMOV = (1 << 1), aoqi@0: CPU_FXSR = (1 << 2), aoqi@0: CPU_HT = (1 << 3), aoqi@0: CPU_MMX = (1 << 4), aoqi@0: CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions aoqi@0: // may not necessarily support other 3dnow instructions aoqi@0: CPU_SSE = (1 << 6), aoqi@0: CPU_SSE2 = (1 << 7), aoqi@0: CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) aoqi@0: CPU_SSSE3 = (1 << 9), aoqi@0: CPU_SSE4A = (1 << 10), aoqi@0: CPU_SSE4_1 = (1 << 11), aoqi@0: CPU_SSE4_2 = (1 << 12), aoqi@0: CPU_POPCNT = (1 << 13), aoqi@0: CPU_LZCNT = (1 << 14), aoqi@0: CPU_TSC = (1 << 15), aoqi@0: CPU_TSCINV = (1 << 16), aoqi@0: CPU_AVX = (1 << 17), aoqi@0: CPU_AVX2 = (1 << 18), aoqi@0: CPU_AES = (1 << 19), aoqi@0: CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions aoqi@0: CPU_CLMUL = (1 << 21), // carryless multiply for CRC aoqi@0: CPU_BMI1 = (1 << 22), aoqi@0: CPU_BMI2 = (1 << 23), aoqi@0: CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions aoqi@0: } cpuFeatureFlags; aoqi@0: aoqi@0: enum { aoqi@0: // AMD aoqi@0: CPU_FAMILY_AMD_11H = 0x11, aoqi@0: // Intel aoqi@0: CPU_FAMILY_INTEL_CORE = 6, aoqi@0: CPU_MODEL_NEHALEM = 0x1e, aoqi@0: CPU_MODEL_NEHALEM_EP = 0x1a, aoqi@0: CPU_MODEL_NEHALEM_EX = 0x2e, aoqi@0: CPU_MODEL_WESTMERE = 0x25, aoqi@0: CPU_MODEL_WESTMERE_EP = 0x2c, aoqi@0: CPU_MODEL_WESTMERE_EX = 0x2f, aoqi@0: CPU_MODEL_SANDYBRIDGE = 0x2a, aoqi@0: CPU_MODEL_SANDYBRIDGE_EP = 0x2d, aoqi@0: CPU_MODEL_IVYBRIDGE_EP = 0x3a aoqi@0: } cpuExtendedFamily; aoqi@0: aoqi@0: // cpuid information block. All info derived from executing cpuid with aoqi@0: // various function numbers is stored here. Intel and AMD info is aoqi@0: // merged in this block: accessor methods disentangle it. aoqi@0: // aoqi@0: // The info block is laid out in subblocks of 4 dwords corresponding to aoqi@0: // eax, ebx, ecx and edx, whether or not they contain anything useful. aoqi@0: struct CpuidInfo { aoqi@0: // cpuid function 0 aoqi@0: uint32_t std_max_function; aoqi@0: uint32_t std_vendor_name_0; aoqi@0: uint32_t std_vendor_name_1; aoqi@0: uint32_t std_vendor_name_2; aoqi@0: aoqi@0: // cpuid function 1 aoqi@0: StdCpuid1Eax std_cpuid1_eax; aoqi@0: StdCpuid1Ebx std_cpuid1_ebx; aoqi@0: StdCpuid1Ecx std_cpuid1_ecx; aoqi@0: StdCpuid1Edx std_cpuid1_edx; aoqi@0: aoqi@0: // cpuid function 4 (deterministic cache parameters) aoqi@0: DcpCpuid4Eax dcp_cpuid4_eax; aoqi@0: DcpCpuid4Ebx dcp_cpuid4_ebx; aoqi@0: uint32_t dcp_cpuid4_ecx; // unused currently aoqi@0: uint32_t dcp_cpuid4_edx; // unused currently aoqi@0: aoqi@0: // cpuid function 7 (structured extended features) aoqi@0: SefCpuid7Eax sef_cpuid7_eax; aoqi@0: SefCpuid7Ebx sef_cpuid7_ebx; aoqi@0: uint32_t sef_cpuid7_ecx; // unused currently aoqi@0: uint32_t sef_cpuid7_edx; // unused currently aoqi@0: aoqi@0: // cpuid function 0xB (processor topology) aoqi@0: // ecx = 0 aoqi@0: uint32_t tpl_cpuidB0_eax; aoqi@0: TplCpuidBEbx tpl_cpuidB0_ebx; aoqi@0: uint32_t tpl_cpuidB0_ecx; // unused currently aoqi@0: uint32_t tpl_cpuidB0_edx; // unused currently aoqi@0: aoqi@0: // ecx = 1 aoqi@0: uint32_t tpl_cpuidB1_eax; aoqi@0: TplCpuidBEbx tpl_cpuidB1_ebx; aoqi@0: uint32_t tpl_cpuidB1_ecx; // unused currently aoqi@0: uint32_t tpl_cpuidB1_edx; // unused currently aoqi@0: aoqi@0: // ecx = 2 aoqi@0: uint32_t tpl_cpuidB2_eax; aoqi@0: TplCpuidBEbx tpl_cpuidB2_ebx; aoqi@0: uint32_t tpl_cpuidB2_ecx; // unused currently aoqi@0: uint32_t tpl_cpuidB2_edx; // unused currently aoqi@0: aoqi@0: // cpuid function 0x80000000 // example, unused aoqi@0: uint32_t ext_max_function; aoqi@0: uint32_t ext_vendor_name_0; aoqi@0: uint32_t ext_vendor_name_1; aoqi@0: uint32_t ext_vendor_name_2; aoqi@0: aoqi@0: // cpuid function 0x80000001 aoqi@0: uint32_t ext_cpuid1_eax; // reserved aoqi@0: uint32_t ext_cpuid1_ebx; // reserved aoqi@0: ExtCpuid1Ecx ext_cpuid1_ecx; aoqi@0: ExtCpuid1Edx ext_cpuid1_edx; aoqi@0: aoqi@0: // cpuid functions 0x80000002 thru 0x80000004: example, unused aoqi@0: uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; aoqi@0: uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; aoqi@0: uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; aoqi@0: aoqi@0: // cpuid function 0x80000005 // AMD L1, Intel reserved aoqi@0: uint32_t ext_cpuid5_eax; // unused currently aoqi@0: uint32_t ext_cpuid5_ebx; // reserved aoqi@0: ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) aoqi@0: ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) aoqi@0: aoqi@0: // cpuid function 0x80000007 aoqi@0: uint32_t ext_cpuid7_eax; // reserved aoqi@0: uint32_t ext_cpuid7_ebx; // reserved aoqi@0: uint32_t ext_cpuid7_ecx; // reserved aoqi@0: ExtCpuid7Edx ext_cpuid7_edx; // tscinv aoqi@0: aoqi@0: // cpuid function 0x80000008 aoqi@0: uint32_t ext_cpuid8_eax; // unused currently aoqi@0: uint32_t ext_cpuid8_ebx; // reserved aoqi@0: ExtCpuid8Ecx ext_cpuid8_ecx; aoqi@0: uint32_t ext_cpuid8_edx; // reserved aoqi@0: aoqi@0: // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) aoqi@0: XemXcr0Eax xem_xcr0_eax; aoqi@0: uint32_t xem_xcr0_edx; // reserved aoqi@0: aoqi@0: // Space to save ymm registers after signal handle aoqi@0: int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 aoqi@0: }; aoqi@0: aoqi@0: // The actual cpuid info block aoqi@0: static CpuidInfo _cpuid_info; aoqi@0: aoqi@0: // Extractors and predicates aoqi@0: static uint32_t extended_cpu_family() { aoqi@0: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; aoqi@0: result += _cpuid_info.std_cpuid1_eax.bits.ext_family; aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static uint32_t extended_cpu_model() { aoqi@0: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; aoqi@0: result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static uint32_t cpu_stepping() { aoqi@0: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static uint logical_processor_count() { aoqi@0: uint result = threads_per_core(); aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static uint32_t feature_flags() { aoqi@0: uint32_t result = 0; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) aoqi@0: result |= CPU_CX8; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) aoqi@0: result |= CPU_CMOV; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && aoqi@0: _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) aoqi@0: result |= CPU_FXSR; aoqi@0: // HT flag is set for multi-core processors also. aoqi@0: if (threads_per_core() > 1) aoqi@0: result |= CPU_HT; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && aoqi@0: _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) aoqi@0: result |= CPU_MMX; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) aoqi@0: result |= CPU_SSE; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) aoqi@0: result |= CPU_SSE2; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) aoqi@0: result |= CPU_SSE3; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) aoqi@0: result |= CPU_SSSE3; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) aoqi@0: result |= CPU_SSE4_1; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) aoqi@0: result |= CPU_SSE4_2; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) aoqi@0: result |= CPU_POPCNT; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && aoqi@0: _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && aoqi@0: _cpuid_info.xem_xcr0_eax.bits.sse != 0 && aoqi@0: _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { aoqi@0: result |= CPU_AVX; aoqi@0: if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) aoqi@0: result |= CPU_AVX2; aoqi@0: } aoqi@0: if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) aoqi@0: result |= CPU_BMI1; aoqi@0: if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) aoqi@0: result |= CPU_TSC; aoqi@0: if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) aoqi@0: result |= CPU_TSCINV; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) aoqi@0: result |= CPU_AES; aoqi@0: if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) aoqi@0: result |= CPU_ERMS; aoqi@0: if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) aoqi@0: result |= CPU_CLMUL; aoqi@0: if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) aoqi@0: result |= CPU_RTM; aoqi@0: aoqi@0: // AMD features. aoqi@0: if (is_amd()) { aoqi@0: if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || aoqi@0: (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) aoqi@0: result |= CPU_3DNOW_PREFETCH; aoqi@0: if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) aoqi@0: result |= CPU_LZCNT; aoqi@0: if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) aoqi@0: result |= CPU_SSE4A; aoqi@0: } aoqi@0: // Intel features. aoqi@0: if(is_intel()) { aoqi@0: if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) aoqi@0: result |= CPU_BMI2; aoqi@0: if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) aoqi@0: result |= CPU_LZCNT; aoqi@0: } aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static bool os_supports_avx_vectors() { aoqi@0: if (!supports_avx()) { aoqi@0: return false; aoqi@0: } aoqi@0: // Verify that OS save/restore all bits of AVX registers aoqi@0: // during signal processing. aoqi@0: int nreg = 2 LP64_ONLY(+2); aoqi@0: for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register aoqi@0: if (_cpuid_info.ymm_save[i] != ymm_test_value()) { aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: static void get_processor_features(); aoqi@0: aoqi@0: public: aoqi@0: // Offsets for cpuid asm stub aoqi@0: static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } aoqi@0: static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } aoqi@0: static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } aoqi@0: static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } aoqi@0: static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } aoqi@0: static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } aoqi@0: static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } aoqi@0: static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } aoqi@0: static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } aoqi@0: static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } aoqi@0: static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } aoqi@0: static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } aoqi@0: static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } aoqi@0: aoqi@0: // The value used to check ymm register after signal handle aoqi@0: static int ymm_test_value() { return 0xCAFEBABE; } aoqi@0: aoqi@0: static void get_cpu_info_wrapper(); aoqi@0: static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } aoqi@0: static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } aoqi@0: static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } aoqi@0: static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } aoqi@0: aoqi@0: static void clean_cpuFeatures() { _cpuFeatures = 0; } aoqi@0: static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } aoqi@0: aoqi@0: aoqi@0: // Initialization aoqi@0: static void initialize(); aoqi@0: aoqi@0: // Override Abstract_VM_Version implementation aoqi@0: static bool use_biased_locking(); aoqi@0: aoqi@0: // Asserts aoqi@0: static void assert_is_initialized() { aoqi@0: assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); aoqi@0: } aoqi@0: aoqi@0: // aoqi@0: // Processor family: aoqi@0: // 3 - 386 aoqi@0: // 4 - 486 aoqi@0: // 5 - Pentium aoqi@0: // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, aoqi@0: // Pentium M, Core Solo, Core Duo, Core2 Duo aoqi@0: // family 6 model: 9, 13, 14, 15 aoqi@0: // 0x0f - Pentium 4, Opteron aoqi@0: // aoqi@0: // Note: The cpu family should be used to select between aoqi@0: // instruction sequences which are valid on all Intel aoqi@0: // processors. Use the feature test functions below to aoqi@0: // determine whether a particular instruction is supported. aoqi@0: // aoqi@0: static int cpu_family() { return _cpu;} aoqi@0: static bool is_P6() { return cpu_family() >= 6; } aoqi@0: static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' aoqi@0: static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' aoqi@0: aoqi@0: static bool supports_processor_topology() { aoqi@0: return (_cpuid_info.std_max_function >= 0xB) && aoqi@0: // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. aoqi@0: // Some cpus have max cpuid >= 0xB but do not support processor topology. aoqi@0: (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); aoqi@0: } aoqi@0: aoqi@0: static uint cores_per_cpu() { aoqi@0: uint result = 1; aoqi@0: if (is_intel()) { aoqi@0: if (supports_processor_topology()) { aoqi@0: result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / aoqi@0: _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; aoqi@0: } else { aoqi@0: result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); aoqi@0: } aoqi@0: } else if (is_amd()) { aoqi@0: result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); aoqi@0: } aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static uint threads_per_core() { aoqi@0: uint result = 1; aoqi@0: if (is_intel() && supports_processor_topology()) { aoqi@0: result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; aoqi@0: } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { aoqi@0: result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / aoqi@0: cores_per_cpu(); aoqi@0: } aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: static intx prefetch_data_size() { aoqi@0: intx result = 0; aoqi@0: if (is_intel()) { aoqi@0: result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); aoqi@0: } else if (is_amd()) { aoqi@0: result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; aoqi@0: } aoqi@0: if (result < 32) // not defined ? aoqi@0: result = 32; // 32 bytes by default on x86 and other x64 aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: // aoqi@0: // Feature identification aoqi@0: // aoqi@0: static bool supports_cpuid() { return _cpuFeatures != 0; } aoqi@0: static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } aoqi@0: static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } aoqi@0: static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } aoqi@0: static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } aoqi@0: static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } aoqi@0: static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } aoqi@0: static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } aoqi@0: static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } aoqi@0: static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } aoqi@0: static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } aoqi@0: static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } aoqi@0: static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } aoqi@0: static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } aoqi@0: static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } aoqi@0: static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } aoqi@0: static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } aoqi@0: static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } aoqi@0: static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } aoqi@0: static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } aoqi@0: static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } aoqi@0: static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } aoqi@0: // Intel features aoqi@0: static bool is_intel_family_core() { return is_intel() && aoqi@0: extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } aoqi@0: aoqi@0: static bool is_intel_tsc_synched_at_init() { aoqi@0: if (is_intel_family_core()) { aoqi@0: uint32_t ext_model = extended_cpu_model(); aoqi@0: if (ext_model == CPU_MODEL_NEHALEM_EP || aoqi@0: ext_model == CPU_MODEL_WESTMERE_EP || aoqi@0: ext_model == CPU_MODEL_SANDYBRIDGE_EP || aoqi@0: ext_model == CPU_MODEL_IVYBRIDGE_EP) { aoqi@0: // <= 2-socket invariant tsc support. EX versions are usually used aoqi@0: // in > 2-socket systems and likely don't synchronize tscs at aoqi@0: // initialization. aoqi@0: // Code that uses tsc values must be prepared for them to arbitrarily aoqi@0: // jump forward or backward. aoqi@0: return true; aoqi@0: } aoqi@0: } aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: // AMD features aoqi@0: static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } aoqi@0: static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } aoqi@0: static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } aoqi@0: static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } aoqi@0: aoqi@0: static bool is_amd_Barcelona() { return is_amd() && aoqi@0: extended_cpu_family() == CPU_FAMILY_AMD_11H; } aoqi@0: aoqi@0: // Intel and AMD newer cores support fast timestamps well aoqi@0: static bool supports_tscinv_bit() { aoqi@0: return (_cpuFeatures & CPU_TSCINV) != 0; aoqi@0: } aoqi@0: static bool supports_tscinv() { aoqi@0: return supports_tscinv_bit() && aoqi@0: ( (is_amd() && !is_amd_Barcelona()) || aoqi@0: is_intel_tsc_synched_at_init() ); aoqi@0: } aoqi@0: aoqi@0: // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). aoqi@0: static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && aoqi@0: supports_sse3() && _model != 0x1C; } aoqi@0: aoqi@0: static bool supports_compare_and_exchange() { return true; } aoqi@0: aoqi@0: static const char* cpu_features() { return _features_str; } aoqi@0: aoqi@0: static intx allocate_prefetch_distance() { aoqi@0: // This method should be called before allocate_prefetch_style(). aoqi@0: // aoqi@0: // Hardware prefetching (distance/size in bytes): aoqi@0: // Pentium 3 - 64 / 32 aoqi@0: // Pentium 4 - 256 / 128 aoqi@0: // Athlon - 64 / 32 ???? aoqi@0: // Opteron - 128 / 64 only when 2 sequential cache lines accessed aoqi@0: // Core - 128 / 64 aoqi@0: // aoqi@0: // Software prefetching (distance in bytes / instruction with best score): aoqi@0: // Pentium 3 - 128 / prefetchnta aoqi@0: // Pentium 4 - 512 / prefetchnta aoqi@0: // Athlon - 128 / prefetchnta aoqi@0: // Opteron - 256 / prefetchnta aoqi@0: // Core - 256 / prefetchnta aoqi@0: // It will be used only when AllocatePrefetchStyle > 0 aoqi@0: aoqi@0: intx count = AllocatePrefetchDistance; aoqi@0: if (count < 0) { // default ? aoqi@0: if (is_amd()) { // AMD aoqi@0: if (supports_sse2()) aoqi@0: count = 256; // Opteron aoqi@0: else aoqi@0: count = 128; // Athlon aoqi@0: } else { // Intel aoqi@0: if (supports_sse2()) aoqi@0: if (cpu_family() == 6) { aoqi@0: count = 256; // Pentium M, Core, Core2 aoqi@0: } else { aoqi@0: count = 512; // Pentium 4 aoqi@0: } aoqi@0: else aoqi@0: count = 128; // Pentium 3 (and all other old CPUs) aoqi@0: } aoqi@0: } aoqi@0: return count; aoqi@0: } aoqi@0: static intx allocate_prefetch_style() { aoqi@0: assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); aoqi@0: // Return 0 if AllocatePrefetchDistance was not defined. aoqi@0: return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; aoqi@0: } aoqi@0: aoqi@0: // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from aoqi@0: // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. aoqi@0: // Tested intervals from 128 to 2048 in increments of 64 == one cache line. aoqi@0: // 256 bytes (4 dcache lines) was the nearest runner-up to 576. aoqi@0: aoqi@0: // gc copy/scan is disabled if prefetchw isn't supported, because aoqi@0: // Prefetch::write emits an inlined prefetchw on Linux. aoqi@0: // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. aoqi@0: // The used prefetcht0 instruction works for both amd64 and em64t. aoqi@0: static intx prefetch_copy_interval_in_bytes() { aoqi@0: intx interval = PrefetchCopyIntervalInBytes; aoqi@0: return interval >= 0 ? interval : 576; aoqi@0: } aoqi@0: static intx prefetch_scan_interval_in_bytes() { aoqi@0: intx interval = PrefetchScanIntervalInBytes; aoqi@0: return interval >= 0 ? interval : 576; aoqi@0: } aoqi@0: static intx prefetch_fields_ahead() { aoqi@0: intx count = PrefetchFieldsAhead; aoqi@0: return count >= 0 ? count : 1; aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: #endif // CPU_X86_VM_VM_VERSION_X86_HPP