aoqi@0: /* aoqi@0: * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@0: #include "precompiled.hpp" aoqi@0: #include "asm/macroAssembler.hpp" aoqi@0: #include "asm/macroAssembler.inline.hpp" aoqi@0: #include "code/debugInfoRec.hpp" aoqi@0: #include "code/icBuffer.hpp" aoqi@0: #include "code/vtableStubs.hpp" aoqi@0: #include "interpreter/interpreter.hpp" aoqi@0: #include "oops/compiledICHolder.hpp" aoqi@0: #include "prims/jvmtiRedefineClassesTrace.hpp" aoqi@0: #include "runtime/sharedRuntime.hpp" aoqi@0: #include "runtime/vframeArray.hpp" aoqi@0: #include "vmreg_x86.inline.hpp" aoqi@0: #ifdef COMPILER1 aoqi@0: #include "c1/c1_Runtime1.hpp" aoqi@0: #endif aoqi@0: #ifdef COMPILER2 aoqi@0: #include "opto/runtime.hpp" aoqi@0: #endif aoqi@0: aoqi@0: #define __ masm-> aoqi@0: aoqi@0: const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; aoqi@0: aoqi@0: class SimpleRuntimeFrame { aoqi@0: aoqi@0: public: aoqi@0: aoqi@0: // Most of the runtime stubs have this simple frame layout. aoqi@0: // This class exists to make the layout shared in one place. aoqi@0: // Offsets are for compiler stack slots, which are jints. aoqi@0: enum layout { aoqi@0: // The frame sender code expects that rbp will be in the "natural" place and aoqi@0: // will override any oopMap setting for it. We must therefore force the layout aoqi@0: // so that it agrees with the frame sender code. aoqi@0: rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, aoqi@0: rbp_off2, aoqi@0: return_off, return_off2, aoqi@0: framesize aoqi@0: }; aoqi@0: }; aoqi@0: aoqi@0: class RegisterSaver { aoqi@0: // Capture info about frame layout. Layout offsets are in jint aoqi@0: // units because compiler frame slots are jints. aoqi@0: #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off aoqi@0: enum layout { aoqi@0: fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area aoqi@0: xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area aoqi@0: DEF_XMM_OFFS(0), aoqi@0: DEF_XMM_OFFS(1), aoqi@0: DEF_XMM_OFFS(2), aoqi@0: DEF_XMM_OFFS(3), aoqi@0: DEF_XMM_OFFS(4), aoqi@0: DEF_XMM_OFFS(5), aoqi@0: DEF_XMM_OFFS(6), aoqi@0: DEF_XMM_OFFS(7), aoqi@0: DEF_XMM_OFFS(8), aoqi@0: DEF_XMM_OFFS(9), aoqi@0: DEF_XMM_OFFS(10), aoqi@0: DEF_XMM_OFFS(11), aoqi@0: DEF_XMM_OFFS(12), aoqi@0: DEF_XMM_OFFS(13), aoqi@0: DEF_XMM_OFFS(14), aoqi@0: DEF_XMM_OFFS(15), aoqi@0: fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), aoqi@0: fpu_stateH_end, aoqi@0: r15_off, r15H_off, aoqi@0: r14_off, r14H_off, aoqi@0: r13_off, r13H_off, aoqi@0: r12_off, r12H_off, aoqi@0: r11_off, r11H_off, aoqi@0: r10_off, r10H_off, aoqi@0: r9_off, r9H_off, aoqi@0: r8_off, r8H_off, aoqi@0: rdi_off, rdiH_off, aoqi@0: rsi_off, rsiH_off, aoqi@0: ignore_off, ignoreH_off, // extra copy of rbp aoqi@0: rsp_off, rspH_off, aoqi@0: rbx_off, rbxH_off, aoqi@0: rdx_off, rdxH_off, aoqi@0: rcx_off, rcxH_off, aoqi@0: rax_off, raxH_off, aoqi@0: // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state aoqi@0: align_off, alignH_off, aoqi@0: flags_off, flagsH_off, aoqi@0: // The frame sender code expects that rbp will be in the "natural" place and aoqi@0: // will override any oopMap setting for it. We must therefore force the layout aoqi@0: // so that it agrees with the frame sender code. aoqi@0: rbp_off, rbpH_off, // copy of rbp we will restore aoqi@0: return_off, returnH_off, // slot for return address aoqi@0: reg_save_size // size in compiler stack slots aoqi@0: }; aoqi@0: aoqi@0: public: aoqi@0: static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false); aoqi@0: static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); aoqi@0: aoqi@0: // Offsets into the register save area aoqi@0: // Used by deoptimization when it is managing result register aoqi@0: // values on its own aoqi@0: aoqi@0: static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; } aoqi@0: static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; } aoqi@0: static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; } aoqi@0: static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; } aoqi@0: static int return_offset_in_bytes(void) { return BytesPerInt * return_off; } aoqi@0: aoqi@0: // During deoptimization only the result registers need to be restored, aoqi@0: // all the other values have already been extracted. aoqi@0: static void restore_result_registers(MacroAssembler* masm); aoqi@0: }; aoqi@0: aoqi@0: OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { aoqi@0: int vect_words = 0; aoqi@0: #ifdef COMPILER2 aoqi@0: if (save_vectors) { aoqi@0: assert(UseAVX > 0, "256bit vectors are supported only with AVX"); aoqi@0: assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); aoqi@0: // Save upper half of YMM registes aoqi@0: vect_words = 16 * 16 / wordSize; aoqi@0: additional_frame_words += vect_words; aoqi@0: } aoqi@0: #else aoqi@0: assert(!save_vectors, "vectors are generated only by C2"); aoqi@0: #endif aoqi@0: aoqi@0: // Always make the frame size 16-byte aligned aoqi@0: int frame_size_in_bytes = round_to(additional_frame_words*wordSize + aoqi@0: reg_save_size*BytesPerInt, 16); aoqi@0: // OopMap frame size is in compiler stack slots (jint's) not bytes or words aoqi@0: int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; aoqi@0: // The caller will allocate additional_frame_words aoqi@0: int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; aoqi@0: // CodeBlob frame size is in words. aoqi@0: int frame_size_in_words = frame_size_in_bytes / wordSize; aoqi@0: *total_frame_words = frame_size_in_words; aoqi@0: aoqi@0: // Save registers, fpu state, and flags. aoqi@0: // We assume caller has already pushed the return address onto the aoqi@0: // stack, so rsp is 8-byte aligned here. aoqi@0: // We push rpb twice in this sequence because we want the real rbp aoqi@0: // to be under the return like a normal enter. aoqi@0: aoqi@0: __ enter(); // rsp becomes 16-byte aligned here aoqi@0: __ push_CPU_state(); // Push a multiple of 16 bytes aoqi@0: aoqi@0: if (vect_words > 0) { aoqi@0: assert(vect_words*wordSize == 256, ""); aoqi@0: __ subptr(rsp, 256); // Save upper half of YMM registes aoqi@0: __ vextractf128h(Address(rsp, 0),xmm0); aoqi@0: __ vextractf128h(Address(rsp, 16),xmm1); aoqi@0: __ vextractf128h(Address(rsp, 32),xmm2); aoqi@0: __ vextractf128h(Address(rsp, 48),xmm3); aoqi@0: __ vextractf128h(Address(rsp, 64),xmm4); aoqi@0: __ vextractf128h(Address(rsp, 80),xmm5); aoqi@0: __ vextractf128h(Address(rsp, 96),xmm6); aoqi@0: __ vextractf128h(Address(rsp,112),xmm7); aoqi@0: __ vextractf128h(Address(rsp,128),xmm8); aoqi@0: __ vextractf128h(Address(rsp,144),xmm9); aoqi@0: __ vextractf128h(Address(rsp,160),xmm10); aoqi@0: __ vextractf128h(Address(rsp,176),xmm11); aoqi@0: __ vextractf128h(Address(rsp,192),xmm12); aoqi@0: __ vextractf128h(Address(rsp,208),xmm13); aoqi@0: __ vextractf128h(Address(rsp,224),xmm14); aoqi@0: __ vextractf128h(Address(rsp,240),xmm15); aoqi@0: } aoqi@0: if (frame::arg_reg_save_area_bytes != 0) { aoqi@0: // Allocate argument register save area aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); aoqi@0: } aoqi@0: aoqi@0: // Set an oopmap for the call site. This oopmap will map all aoqi@0: // oop-registers and debug-info registers as callee-saved. This aoqi@0: // will allow deoptimization at this safepoint to find all possible aoqi@0: // debug-info recordings, as well as let GC find all oops. aoqi@0: aoqi@0: OopMapSet *oop_maps = new OopMapSet(); aoqi@0: OopMap* map = new OopMap(frame_size_in_slots, 0); aoqi@0: aoqi@0: #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots) aoqi@0: aoqi@0: map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg()); aoqi@0: // rbp location is known implicitly by the frame sender code, needs no oopmap aoqi@0: // and the location where rbp was saved by is ignored aoqi@0: map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg()); aoqi@0: aoqi@0: // %%% These should all be a waste but we'll keep things as they were for now aoqi@0: if (true) { aoqi@0: map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next()); aoqi@0: // rbp location is known implicitly by the frame sender code, needs no oopmap aoqi@0: map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next()); aoqi@0: map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next()); aoqi@0: } aoqi@0: aoqi@0: return map; aoqi@0: } aoqi@0: aoqi@0: void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { aoqi@0: if (frame::arg_reg_save_area_bytes != 0) { aoqi@0: // Pop arg register save area aoqi@0: __ addptr(rsp, frame::arg_reg_save_area_bytes); aoqi@0: } aoqi@0: #ifdef COMPILER2 aoqi@0: if (restore_vectors) { aoqi@0: // Restore upper half of YMM registes. aoqi@0: assert(UseAVX > 0, "256bit vectors are supported only with AVX"); aoqi@0: assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); aoqi@0: __ vinsertf128h(xmm0, Address(rsp, 0)); aoqi@0: __ vinsertf128h(xmm1, Address(rsp, 16)); aoqi@0: __ vinsertf128h(xmm2, Address(rsp, 32)); aoqi@0: __ vinsertf128h(xmm3, Address(rsp, 48)); aoqi@0: __ vinsertf128h(xmm4, Address(rsp, 64)); aoqi@0: __ vinsertf128h(xmm5, Address(rsp, 80)); aoqi@0: __ vinsertf128h(xmm6, Address(rsp, 96)); aoqi@0: __ vinsertf128h(xmm7, Address(rsp,112)); aoqi@0: __ vinsertf128h(xmm8, Address(rsp,128)); aoqi@0: __ vinsertf128h(xmm9, Address(rsp,144)); aoqi@0: __ vinsertf128h(xmm10, Address(rsp,160)); aoqi@0: __ vinsertf128h(xmm11, Address(rsp,176)); aoqi@0: __ vinsertf128h(xmm12, Address(rsp,192)); aoqi@0: __ vinsertf128h(xmm13, Address(rsp,208)); aoqi@0: __ vinsertf128h(xmm14, Address(rsp,224)); aoqi@0: __ vinsertf128h(xmm15, Address(rsp,240)); aoqi@0: __ addptr(rsp, 256); aoqi@0: } aoqi@0: #else aoqi@0: assert(!restore_vectors, "vectors are generated only by C2"); aoqi@0: #endif aoqi@0: // Recover CPU state aoqi@0: __ pop_CPU_state(); aoqi@0: // Get the rbp described implicitly by the calling convention (no oopMap) aoqi@0: __ pop(rbp); aoqi@0: } aoqi@0: aoqi@0: void RegisterSaver::restore_result_registers(MacroAssembler* masm) { aoqi@0: aoqi@0: // Just restore result register. Only used by deoptimization. By aoqi@0: // now any callee save register that needs to be restored to a c2 aoqi@0: // caller of the deoptee has been extracted into the vframeArray aoqi@0: // and will be stuffed into the c2i adapter we create for later aoqi@0: // restoration so only result registers need to be restored here. aoqi@0: aoqi@0: // Restore fp result register aoqi@0: __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes())); aoqi@0: // Restore integer result register aoqi@0: __ movptr(rax, Address(rsp, rax_offset_in_bytes())); aoqi@0: __ movptr(rdx, Address(rsp, rdx_offset_in_bytes())); aoqi@0: aoqi@0: // Pop all of the register save are off the stack except the return address aoqi@0: __ addptr(rsp, return_offset_in_bytes()); aoqi@0: } aoqi@0: aoqi@0: // Is vector's size (in bytes) bigger than a size saved by default? aoqi@0: // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. aoqi@0: bool SharedRuntime::is_wide_vector(int size) { aoqi@0: return size > 16; aoqi@0: } aoqi@0: aoqi@0: // The java_calling_convention describes stack locations as ideal slots on aoqi@0: // a frame with no abi restrictions. Since we must observe abi restrictions aoqi@0: // (like the placement of the register window) the slots must be biased by aoqi@0: // the following value. aoqi@0: static int reg2offset_in(VMReg r) { aoqi@0: // Account for saved rbp and return address aoqi@0: // This should really be in_preserve_stack_slots aoqi@0: return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; aoqi@0: } aoqi@0: aoqi@0: static int reg2offset_out(VMReg r) { aoqi@0: return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; aoqi@0: } aoqi@0: aoqi@0: // --------------------------------------------------------------------------- aoqi@0: // Read the array of BasicTypes from a signature, and compute where the aoqi@0: // arguments should go. Values in the VMRegPair regs array refer to 4-byte aoqi@0: // quantities. Values less than VMRegImpl::stack0 are registers, those above aoqi@0: // refer to 4-byte stack slots. All stack slots are based off of the stack pointer aoqi@0: // as framesizes are fixed. aoqi@0: // VMRegImpl::stack0 refers to the first slot 0(sp). aoqi@0: // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register aoqi@0: // up to RegisterImpl::number_of_registers) are the 64-bit aoqi@0: // integer registers. aoqi@0: aoqi@0: // Note: the INPUTS in sig_bt are in units of Java argument words, which are aoqi@0: // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit aoqi@0: // units regardless of build. Of course for i486 there is no 64 bit build aoqi@0: aoqi@0: // The Java calling convention is a "shifted" version of the C ABI. aoqi@0: // By skipping the first C ABI register we can call non-static jni methods aoqi@0: // with small numbers of arguments without having to shuffle the arguments aoqi@0: // at all. Since we control the java ABI we ought to at least get some aoqi@0: // advantage out of it. aoqi@0: aoqi@0: int SharedRuntime::java_calling_convention(const BasicType *sig_bt, aoqi@0: VMRegPair *regs, aoqi@0: int total_args_passed, aoqi@0: int is_outgoing) { aoqi@0: aoqi@0: // Create the mapping between argument positions and aoqi@0: // registers. aoqi@0: static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { aoqi@0: j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5 aoqi@0: }; aoqi@0: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = { aoqi@0: j_farg0, j_farg1, j_farg2, j_farg3, aoqi@0: j_farg4, j_farg5, j_farg6, j_farg7 aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: uint int_args = 0; aoqi@0: uint fp_args = 0; aoqi@0: uint stk_args = 0; // inc by 2 each time aoqi@0: aoqi@0: for (int i = 0; i < total_args_passed; i++) { aoqi@0: switch (sig_bt[i]) { aoqi@0: case T_BOOLEAN: aoqi@0: case T_CHAR: aoqi@0: case T_BYTE: aoqi@0: case T_SHORT: aoqi@0: case T_INT: aoqi@0: if (int_args < Argument::n_int_register_parameters_j) { aoqi@0: regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); aoqi@0: } else { aoqi@0: regs[i].set1(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_VOID: aoqi@0: // halves of T_LONG or T_DOUBLE aoqi@0: assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); aoqi@0: regs[i].set_bad(); aoqi@0: break; aoqi@0: case T_LONG: aoqi@0: assert(sig_bt[i + 1] == T_VOID, "expecting half"); aoqi@0: // fall through aoqi@0: case T_OBJECT: aoqi@0: case T_ARRAY: aoqi@0: case T_ADDRESS: aoqi@0: if (int_args < Argument::n_int_register_parameters_j) { aoqi@0: regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); aoqi@0: } else { aoqi@0: regs[i].set2(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_FLOAT: aoqi@0: if (fp_args < Argument::n_float_register_parameters_j) { aoqi@0: regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); aoqi@0: } else { aoqi@0: regs[i].set1(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_DOUBLE: aoqi@0: assert(sig_bt[i + 1] == T_VOID, "expecting half"); aoqi@0: if (fp_args < Argument::n_float_register_parameters_j) { aoqi@0: regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); aoqi@0: } else { aoqi@0: regs[i].set2(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: default: aoqi@0: ShouldNotReachHere(); aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: return round_to(stk_args, 2); aoqi@0: } aoqi@0: aoqi@0: // Patch the callers callsite with entry to compiled code if it exists. aoqi@0: static void patch_callers_callsite(MacroAssembler *masm) { aoqi@0: Label L; aoqi@0: __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: aoqi@0: // Save the current stack pointer aoqi@0: __ mov(r13, rsp); aoqi@0: // Schedule the branch target address early. aoqi@0: // Call into the VM to patch the caller, then jump to compiled callee aoqi@0: // rax isn't live so capture return address while we easily can aoqi@0: __ movptr(rax, Address(rsp, 0)); aoqi@0: aoqi@0: // align stack so push_CPU_state doesn't fault aoqi@0: __ andptr(rsp, -(StackAlignmentInBytes)); aoqi@0: __ push_CPU_state(); aoqi@0: aoqi@0: // VM needs caller's callsite aoqi@0: // VM needs target method aoqi@0: // This needs to be a long call since we will relocate this adapter to aoqi@0: // the codeBuffer and it may not reach aoqi@0: aoqi@0: // Allocate argument register save area aoqi@0: if (frame::arg_reg_save_area_bytes != 0) { aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); aoqi@0: } aoqi@0: __ mov(c_rarg0, rbx); aoqi@0: __ mov(c_rarg1, rax); aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); aoqi@0: aoqi@0: // De-allocate argument register save area aoqi@0: if (frame::arg_reg_save_area_bytes != 0) { aoqi@0: __ addptr(rsp, frame::arg_reg_save_area_bytes); aoqi@0: } aoqi@0: aoqi@0: __ pop_CPU_state(); aoqi@0: // restore sp aoqi@0: __ mov(rsp, r13); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: static void gen_c2i_adapter(MacroAssembler *masm, aoqi@0: int total_args_passed, aoqi@0: int comp_args_on_stack, aoqi@0: const BasicType *sig_bt, aoqi@0: const VMRegPair *regs, aoqi@0: Label& skip_fixup) { aoqi@0: // Before we get into the guts of the C2I adapter, see if we should be here aoqi@0: // at all. We've come from compiled code and are attempting to jump to the aoqi@0: // interpreter, which means the caller made a static call to get here aoqi@0: // (vcalls always get a compiled target if there is one). Check for a aoqi@0: // compiled target. If there is one, we need to patch the caller's call. aoqi@0: patch_callers_callsite(masm); aoqi@0: aoqi@0: __ bind(skip_fixup); aoqi@0: aoqi@0: // Since all args are passed on the stack, total_args_passed * aoqi@0: // Interpreter::stackElementSize is the space we need. Plus 1 because aoqi@0: // we also account for the return address location since aoqi@0: // we store it first rather than hold it in rax across all the shuffling aoqi@0: aoqi@0: int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize; aoqi@0: aoqi@0: // stack is aligned, keep it that way aoqi@0: extraspace = round_to(extraspace, 2*wordSize); aoqi@0: aoqi@0: // Get return address aoqi@0: __ pop(rax); aoqi@0: aoqi@0: // set senderSP value aoqi@0: __ mov(r13, rsp); aoqi@0: aoqi@0: __ subptr(rsp, extraspace); aoqi@0: aoqi@0: // Store the return address in the expected location aoqi@0: __ movptr(Address(rsp, 0), rax); aoqi@0: aoqi@0: // Now write the args into the outgoing interpreter space aoqi@0: for (int i = 0; i < total_args_passed; i++) { aoqi@0: if (sig_bt[i] == T_VOID) { aoqi@0: assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); aoqi@0: continue; aoqi@0: } aoqi@0: aoqi@0: // offset to start parameters aoqi@0: int st_off = (total_args_passed - i) * Interpreter::stackElementSize; aoqi@0: int next_off = st_off - Interpreter::stackElementSize; aoqi@0: aoqi@0: // Say 4 args: aoqi@0: // i st_off aoqi@0: // 0 32 T_LONG aoqi@0: // 1 24 T_VOID aoqi@0: // 2 16 T_OBJECT aoqi@0: // 3 8 T_BOOL aoqi@0: // - 0 return address aoqi@0: // aoqi@0: // However to make thing extra confusing. Because we can fit a long/double in aoqi@0: // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter aoqi@0: // leaves one slot empty and only stores to a single slot. In this case the aoqi@0: // slot that is occupied is the T_VOID slot. See I said it was confusing. aoqi@0: aoqi@0: VMReg r_1 = regs[i].first(); aoqi@0: VMReg r_2 = regs[i].second(); aoqi@0: if (!r_1->is_valid()) { aoqi@0: assert(!r_2->is_valid(), ""); aoqi@0: continue; aoqi@0: } aoqi@0: if (r_1->is_stack()) { aoqi@0: // memory to memory use rax aoqi@0: int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; aoqi@0: if (!r_2->is_valid()) { aoqi@0: // sign extend?? aoqi@0: __ movl(rax, Address(rsp, ld_off)); aoqi@0: __ movptr(Address(rsp, st_off), rax); aoqi@0: aoqi@0: } else { aoqi@0: aoqi@0: __ movq(rax, Address(rsp, ld_off)); aoqi@0: aoqi@0: // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG aoqi@0: // T_DOUBLE and T_LONG use two slots in the interpreter aoqi@0: if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { aoqi@0: // ld_off == LSW, ld_off+wordSize == MSW aoqi@0: // st_off == MSW, next_off == LSW aoqi@0: __ movq(Address(rsp, next_off), rax); aoqi@0: #ifdef ASSERT aoqi@0: // Overwrite the unused slot with known junk aoqi@0: __ mov64(rax, CONST64(0xdeadffffdeadaaaa)); aoqi@0: __ movptr(Address(rsp, st_off), rax); aoqi@0: #endif /* ASSERT */ aoqi@0: } else { aoqi@0: __ movq(Address(rsp, st_off), rax); aoqi@0: } aoqi@0: } aoqi@0: } else if (r_1->is_Register()) { aoqi@0: Register r = r_1->as_Register(); aoqi@0: if (!r_2->is_valid()) { aoqi@0: // must be only an int (or less ) so move only 32bits to slot aoqi@0: // why not sign extend?? aoqi@0: __ movl(Address(rsp, st_off), r); aoqi@0: } else { aoqi@0: // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG aoqi@0: // T_DOUBLE and T_LONG use two slots in the interpreter aoqi@0: if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { aoqi@0: // long/double in gpr aoqi@0: #ifdef ASSERT aoqi@0: // Overwrite the unused slot with known junk aoqi@0: __ mov64(rax, CONST64(0xdeadffffdeadaaab)); aoqi@0: __ movptr(Address(rsp, st_off), rax); aoqi@0: #endif /* ASSERT */ aoqi@0: __ movq(Address(rsp, next_off), r); aoqi@0: } else { aoqi@0: __ movptr(Address(rsp, st_off), r); aoqi@0: } aoqi@0: } aoqi@0: } else { aoqi@0: assert(r_1->is_XMMRegister(), ""); aoqi@0: if (!r_2->is_valid()) { aoqi@0: // only a float use just part of the slot aoqi@0: __ movflt(Address(rsp, st_off), r_1->as_XMMRegister()); aoqi@0: } else { aoqi@0: #ifdef ASSERT aoqi@0: // Overwrite the unused slot with known junk aoqi@0: __ mov64(rax, CONST64(0xdeadffffdeadaaac)); aoqi@0: __ movptr(Address(rsp, st_off), rax); aoqi@0: #endif /* ASSERT */ aoqi@0: __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Schedule the branch target address early. aoqi@0: __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset()))); aoqi@0: __ jmp(rcx); aoqi@0: } aoqi@0: aoqi@0: static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, aoqi@0: address code_start, address code_end, aoqi@0: Label& L_ok) { aoqi@0: Label L_fail; aoqi@0: __ lea(temp_reg, ExternalAddress(code_start)); aoqi@0: __ cmpptr(pc_reg, temp_reg); aoqi@0: __ jcc(Assembler::belowEqual, L_fail); aoqi@0: __ lea(temp_reg, ExternalAddress(code_end)); aoqi@0: __ cmpptr(pc_reg, temp_reg); aoqi@0: __ jcc(Assembler::below, L_ok); aoqi@0: __ bind(L_fail); aoqi@0: } aoqi@0: aoqi@0: static void gen_i2c_adapter(MacroAssembler *masm, aoqi@0: int total_args_passed, aoqi@0: int comp_args_on_stack, aoqi@0: const BasicType *sig_bt, aoqi@0: const VMRegPair *regs) { aoqi@0: aoqi@0: // Note: r13 contains the senderSP on entry. We must preserve it since aoqi@0: // we may do a i2c -> c2i transition if we lose a race where compiled aoqi@0: // code goes non-entrant while we get args ready. aoqi@0: // In addition we use r13 to locate all the interpreter args as aoqi@0: // we must align the stack to 16 bytes on an i2c entry else we aoqi@0: // lose alignment we expect in all compiled code and register aoqi@0: // save code can segv when fxsave instructions find improperly aoqi@0: // aligned stack pointer. aoqi@0: aoqi@0: // Adapters can be frameless because they do not require the caller aoqi@0: // to perform additional cleanup work, such as correcting the stack pointer. aoqi@0: // An i2c adapter is frameless because the *caller* frame, which is interpreted, aoqi@0: // routinely repairs its own stack pointer (from interpreter_frame_last_sp), aoqi@0: // even if a callee has modified the stack pointer. aoqi@0: // A c2i adapter is frameless because the *callee* frame, which is interpreted, aoqi@0: // routinely repairs its caller's stack pointer (from sender_sp, which is set aoqi@0: // up via the senderSP register). aoqi@0: // In other words, if *either* the caller or callee is interpreted, we can aoqi@0: // get the stack pointer repaired after a call. aoqi@0: // This is why c2i and i2c adapters cannot be indefinitely composed. aoqi@0: // In particular, if a c2i adapter were to somehow call an i2c adapter, aoqi@0: // both caller and callee would be compiled methods, and neither would aoqi@0: // clean up the stack pointer changes performed by the two adapters. aoqi@0: // If this happens, control eventually transfers back to the compiled aoqi@0: // caller, but with an uncorrected stack, causing delayed havoc. aoqi@0: aoqi@0: // Pick up the return address aoqi@0: __ movptr(rax, Address(rsp, 0)); aoqi@0: aoqi@0: if (VerifyAdapterCalls && aoqi@0: (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { aoqi@0: // So, let's test for cascading c2i/i2c adapters right now. aoqi@0: // assert(Interpreter::contains($return_addr) || aoqi@0: // StubRoutines::contains($return_addr), aoqi@0: // "i2c adapter must return to an interpreter frame"); aoqi@0: __ block_comment("verify_i2c { "); aoqi@0: Label L_ok; aoqi@0: if (Interpreter::code() != NULL) aoqi@0: range_check(masm, rax, r11, aoqi@0: Interpreter::code()->code_start(), Interpreter::code()->code_end(), aoqi@0: L_ok); aoqi@0: if (StubRoutines::code1() != NULL) aoqi@0: range_check(masm, rax, r11, aoqi@0: StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), aoqi@0: L_ok); aoqi@0: if (StubRoutines::code2() != NULL) aoqi@0: range_check(masm, rax, r11, aoqi@0: StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), aoqi@0: L_ok); aoqi@0: const char* msg = "i2c adapter must return to an interpreter frame"; aoqi@0: __ block_comment(msg); aoqi@0: __ stop(msg); aoqi@0: __ bind(L_ok); aoqi@0: __ block_comment("} verify_i2ce "); aoqi@0: } aoqi@0: aoqi@0: // Must preserve original SP for loading incoming arguments because aoqi@0: // we need to align the outgoing SP for compiled code. aoqi@0: __ movptr(r11, rsp); aoqi@0: aoqi@0: // Cut-out for having no stack args. Since up to 2 int/oop args are passed aoqi@0: // in registers, we will occasionally have no stack args. aoqi@0: int comp_words_on_stack = 0; aoqi@0: if (comp_args_on_stack) { aoqi@0: // Sig words on the stack are greater-than VMRegImpl::stack0. Those in aoqi@0: // registers are below. By subtracting stack0, we either get a negative aoqi@0: // number (all values in registers) or the maximum stack slot accessed. aoqi@0: aoqi@0: // Convert 4-byte c2 stack slots to words. aoqi@0: comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; aoqi@0: // Round up to miminum stack alignment, in wordSize aoqi@0: comp_words_on_stack = round_to(comp_words_on_stack, 2); aoqi@0: __ subptr(rsp, comp_words_on_stack * wordSize); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Ensure compiled code always sees stack at proper alignment aoqi@0: __ andptr(rsp, -16); aoqi@0: aoqi@0: // push the return address and misalign the stack that youngest frame always sees aoqi@0: // as far as the placement of the call instruction aoqi@0: __ push(rax); aoqi@0: aoqi@0: // Put saved SP in another register aoqi@0: const Register saved_sp = rax; aoqi@0: __ movptr(saved_sp, r11); aoqi@0: aoqi@0: // Will jump to the compiled code just as if compiled code was doing it. aoqi@0: // Pre-load the register-jump target early, to schedule it better. aoqi@0: __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset()))); aoqi@0: aoqi@0: // Now generate the shuffle code. Pick up all register args and move the aoqi@0: // rest through the floating point stack top. aoqi@0: for (int i = 0; i < total_args_passed; i++) { aoqi@0: if (sig_bt[i] == T_VOID) { aoqi@0: // Longs and doubles are passed in native word order, but misaligned aoqi@0: // in the 32-bit build. aoqi@0: assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); aoqi@0: continue; aoqi@0: } aoqi@0: aoqi@0: // Pick up 0, 1 or 2 words from SP+offset. aoqi@0: aoqi@0: assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), aoqi@0: "scrambled load targets?"); aoqi@0: // Load in argument order going down. aoqi@0: int ld_off = (total_args_passed - i)*Interpreter::stackElementSize; aoqi@0: // Point to interpreter value (vs. tag) aoqi@0: int next_off = ld_off - Interpreter::stackElementSize; aoqi@0: // aoqi@0: // aoqi@0: // aoqi@0: VMReg r_1 = regs[i].first(); aoqi@0: VMReg r_2 = regs[i].second(); aoqi@0: if (!r_1->is_valid()) { aoqi@0: assert(!r_2->is_valid(), ""); aoqi@0: continue; aoqi@0: } aoqi@0: if (r_1->is_stack()) { aoqi@0: // Convert stack slot to an SP offset (+ wordSize to account for return address ) aoqi@0: int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize; aoqi@0: aoqi@0: // We can use r13 as a temp here because compiled code doesn't need r13 as an input aoqi@0: // and if we end up going thru a c2i because of a miss a reasonable value of r13 aoqi@0: // will be generated. aoqi@0: if (!r_2->is_valid()) { aoqi@0: // sign extend??? aoqi@0: __ movl(r13, Address(saved_sp, ld_off)); aoqi@0: __ movptr(Address(rsp, st_off), r13); aoqi@0: } else { aoqi@0: // aoqi@0: // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE aoqi@0: // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case aoqi@0: // So we must adjust where to pick up the data to match the interpreter. aoqi@0: // aoqi@0: // Interpreter local[n] == MSW, local[n+1] == LSW however locals aoqi@0: // are accessed as negative so LSW is at LOW address aoqi@0: aoqi@0: // ld_off is MSW so get LSW aoqi@0: const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? aoqi@0: next_off : ld_off; aoqi@0: __ movq(r13, Address(saved_sp, offset)); aoqi@0: // st_off is LSW (i.e. reg.first()) aoqi@0: __ movq(Address(rsp, st_off), r13); aoqi@0: } aoqi@0: } else if (r_1->is_Register()) { // Register argument aoqi@0: Register r = r_1->as_Register(); aoqi@0: assert(r != rax, "must be different"); aoqi@0: if (r_2->is_valid()) { aoqi@0: // aoqi@0: // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE aoqi@0: // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case aoqi@0: // So we must adjust where to pick up the data to match the interpreter. aoqi@0: aoqi@0: const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? aoqi@0: next_off : ld_off; aoqi@0: aoqi@0: // this can be a misaligned move aoqi@0: __ movq(r, Address(saved_sp, offset)); aoqi@0: } else { aoqi@0: // sign extend and use a full word? aoqi@0: __ movl(r, Address(saved_sp, ld_off)); aoqi@0: } aoqi@0: } else { aoqi@0: if (!r_2->is_valid()) { aoqi@0: __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off)); aoqi@0: } else { aoqi@0: __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // 6243940 We might end up in handle_wrong_method if aoqi@0: // the callee is deoptimized as we race thru here. If that aoqi@0: // happens we don't want to take a safepoint because the aoqi@0: // caller frame will look interpreted and arguments are now aoqi@0: // "compiled" so it is much better to make this transition aoqi@0: // invisible to the stack walking code. Unfortunately if aoqi@0: // we try and find the callee by normal means a safepoint aoqi@0: // is possible. So we stash the desired callee in the thread aoqi@0: // and the vm will find there should this case occur. aoqi@0: aoqi@0: __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx); aoqi@0: aoqi@0: // put Method* where a c2i would expect should we end up there aoqi@0: // only needed becaus eof c2 resolve stubs return Method* as a result in aoqi@0: // rax aoqi@0: __ mov(rax, rbx); aoqi@0: __ jmp(r11); aoqi@0: } aoqi@0: aoqi@0: // --------------------------------------------------------------- aoqi@0: AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, aoqi@0: int total_args_passed, aoqi@0: int comp_args_on_stack, aoqi@0: const BasicType *sig_bt, aoqi@0: const VMRegPair *regs, aoqi@0: AdapterFingerPrint* fingerprint) { aoqi@0: address i2c_entry = __ pc(); aoqi@0: aoqi@0: gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); aoqi@0: aoqi@0: // ------------------------------------------------------------------------- aoqi@0: // Generate a C2I adapter. On entry we know rbx holds the Method* during calls aoqi@0: // to the interpreter. The args start out packed in the compiled layout. They aoqi@0: // need to be unpacked into the interpreter layout. This will almost always aoqi@0: // require some stack space. We grow the current (compiled) stack, then repack aoqi@0: // the args. We finally end in a jump to the generic interpreter entry point. aoqi@0: // On exit from the interpreter, the interpreter will restore our SP (lest the aoqi@0: // compiled code, which relys solely on SP and not RBP, get sick). aoqi@0: aoqi@0: address c2i_unverified_entry = __ pc(); aoqi@0: Label skip_fixup; aoqi@0: Label ok; aoqi@0: aoqi@0: Register holder = rax; aoqi@0: Register receiver = j_rarg0; aoqi@0: Register temp = rbx; aoqi@0: aoqi@0: { aoqi@0: __ load_klass(temp, receiver); aoqi@0: __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset())); aoqi@0: __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset())); aoqi@0: __ jcc(Assembler::equal, ok); aoqi@0: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); aoqi@0: aoqi@0: __ bind(ok); aoqi@0: // Method might have been compiled since the call site was patched to aoqi@0: // interpreted if that is the case treat it as a miss so we can get aoqi@0: // the call site corrected. aoqi@0: __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, skip_fixup); aoqi@0: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); aoqi@0: } aoqi@0: aoqi@0: address c2i_entry = __ pc(); aoqi@0: aoqi@0: gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); aoqi@0: aoqi@0: __ flush(); aoqi@0: return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); aoqi@0: } aoqi@0: aoqi@0: int SharedRuntime::c_calling_convention(const BasicType *sig_bt, aoqi@0: VMRegPair *regs, aoqi@0: VMRegPair *regs2, aoqi@0: int total_args_passed) { aoqi@0: assert(regs2 == NULL, "not needed on x86"); aoqi@0: // We return the amount of VMRegImpl stack slots we need to reserve for all aoqi@0: // the arguments NOT counting out_preserve_stack_slots. aoqi@0: aoqi@0: // NOTE: These arrays will have to change when c1 is ported aoqi@0: #ifdef _WIN64 aoqi@0: static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { aoqi@0: c_rarg0, c_rarg1, c_rarg2, c_rarg3 aoqi@0: }; aoqi@0: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { aoqi@0: c_farg0, c_farg1, c_farg2, c_farg3 aoqi@0: }; aoqi@0: #else aoqi@0: static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { aoqi@0: c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5 aoqi@0: }; aoqi@0: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { aoqi@0: c_farg0, c_farg1, c_farg2, c_farg3, aoqi@0: c_farg4, c_farg5, c_farg6, c_farg7 aoqi@0: }; aoqi@0: #endif // _WIN64 aoqi@0: aoqi@0: aoqi@0: uint int_args = 0; aoqi@0: uint fp_args = 0; aoqi@0: uint stk_args = 0; // inc by 2 each time aoqi@0: aoqi@0: for (int i = 0; i < total_args_passed; i++) { aoqi@0: switch (sig_bt[i]) { aoqi@0: case T_BOOLEAN: aoqi@0: case T_CHAR: aoqi@0: case T_BYTE: aoqi@0: case T_SHORT: aoqi@0: case T_INT: aoqi@0: if (int_args < Argument::n_int_register_parameters_c) { aoqi@0: regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); aoqi@0: #ifdef _WIN64 aoqi@0: fp_args++; aoqi@0: // Allocate slots for callee to stuff register args the stack. aoqi@0: stk_args += 2; aoqi@0: #endif aoqi@0: } else { aoqi@0: regs[i].set1(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_LONG: aoqi@0: assert(sig_bt[i + 1] == T_VOID, "expecting half"); aoqi@0: // fall through aoqi@0: case T_OBJECT: aoqi@0: case T_ARRAY: aoqi@0: case T_ADDRESS: aoqi@0: case T_METADATA: aoqi@0: if (int_args < Argument::n_int_register_parameters_c) { aoqi@0: regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); aoqi@0: #ifdef _WIN64 aoqi@0: fp_args++; aoqi@0: stk_args += 2; aoqi@0: #endif aoqi@0: } else { aoqi@0: regs[i].set2(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_FLOAT: aoqi@0: if (fp_args < Argument::n_float_register_parameters_c) { aoqi@0: regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); aoqi@0: #ifdef _WIN64 aoqi@0: int_args++; aoqi@0: // Allocate slots for callee to stuff register args the stack. aoqi@0: stk_args += 2; aoqi@0: #endif aoqi@0: } else { aoqi@0: regs[i].set1(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_DOUBLE: aoqi@0: assert(sig_bt[i + 1] == T_VOID, "expecting half"); aoqi@0: if (fp_args < Argument::n_float_register_parameters_c) { aoqi@0: regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); aoqi@0: #ifdef _WIN64 aoqi@0: int_args++; aoqi@0: // Allocate slots for callee to stuff register args the stack. aoqi@0: stk_args += 2; aoqi@0: #endif aoqi@0: } else { aoqi@0: regs[i].set2(VMRegImpl::stack2reg(stk_args)); aoqi@0: stk_args += 2; aoqi@0: } aoqi@0: break; aoqi@0: case T_VOID: // Halves of longs and doubles aoqi@0: assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); aoqi@0: regs[i].set_bad(); aoqi@0: break; aoqi@0: default: aoqi@0: ShouldNotReachHere(); aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: #ifdef _WIN64 aoqi@0: // windows abi requires that we always allocate enough stack space aoqi@0: // for 4 64bit registers to be stored down. aoqi@0: if (stk_args < 8) { aoqi@0: stk_args = 8; aoqi@0: } aoqi@0: #endif // _WIN64 aoqi@0: aoqi@0: return stk_args; aoqi@0: } aoqi@0: aoqi@0: // On 64 bit we will store integer like items to the stack as aoqi@0: // 64 bits items (sparc abi) even though java would only store aoqi@0: // 32bits for a parameter. On 32bit it will simply be 32 bits aoqi@0: // So this routine will do 32->32 on 32bit and 32->64 on 64bit aoqi@0: static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { aoqi@0: if (src.first()->is_stack()) { aoqi@0: if (dst.first()->is_stack()) { aoqi@0: // stack to stack aoqi@0: __ movslq(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); aoqi@0: } else { aoqi@0: // stack to reg aoqi@0: __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); aoqi@0: } aoqi@0: } else if (dst.first()->is_stack()) { aoqi@0: // reg to stack aoqi@0: // Do we really have to sign extend??? aoqi@0: // __ movslq(src.first()->as_Register(), src.first()->as_Register()); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); aoqi@0: } else { aoqi@0: // Do we really have to sign extend??? aoqi@0: // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); aoqi@0: if (dst.first() != src.first()) { aoqi@0: __ movq(dst.first()->as_Register(), src.first()->as_Register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { aoqi@0: if (src.first()->is_stack()) { aoqi@0: if (dst.first()->is_stack()) { aoqi@0: // stack to stack aoqi@0: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); aoqi@0: } else { aoqi@0: // stack to reg aoqi@0: __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); aoqi@0: } aoqi@0: } else if (dst.first()->is_stack()) { aoqi@0: // reg to stack aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); aoqi@0: } else { aoqi@0: if (dst.first() != src.first()) { aoqi@0: __ movq(dst.first()->as_Register(), src.first()->as_Register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // An oop arg. Must pass a handle not the oop itself aoqi@0: static void object_move(MacroAssembler* masm, aoqi@0: OopMap* map, aoqi@0: int oop_handle_offset, aoqi@0: int framesize_in_slots, aoqi@0: VMRegPair src, aoqi@0: VMRegPair dst, aoqi@0: bool is_receiver, aoqi@0: int* receiver_offset) { aoqi@0: aoqi@0: // must pass a handle. First figure out the location we use as a handle aoqi@0: aoqi@0: Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); aoqi@0: aoqi@0: // See if oop is NULL if it is we need no handle aoqi@0: aoqi@0: if (src.first()->is_stack()) { aoqi@0: aoqi@0: // Oop is already on the stack as an argument aoqi@0: int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); aoqi@0: map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); aoqi@0: if (is_receiver) { aoqi@0: *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; aoqi@0: } aoqi@0: aoqi@0: __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); aoqi@0: __ lea(rHandle, Address(rbp, reg2offset_in(src.first()))); aoqi@0: // conditionally move a NULL aoqi@0: __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); aoqi@0: } else { aoqi@0: aoqi@0: // Oop is in an a register we must store it to the space we reserve aoqi@0: // on the stack for oop_handles and pass a handle if oop is non-NULL aoqi@0: aoqi@0: const Register rOop = src.first()->as_Register(); aoqi@0: int oop_slot; aoqi@0: if (rOop == j_rarg0) aoqi@0: oop_slot = 0; aoqi@0: else if (rOop == j_rarg1) aoqi@0: oop_slot = 1; aoqi@0: else if (rOop == j_rarg2) aoqi@0: oop_slot = 2; aoqi@0: else if (rOop == j_rarg3) aoqi@0: oop_slot = 3; aoqi@0: else if (rOop == j_rarg4) aoqi@0: oop_slot = 4; aoqi@0: else { aoqi@0: assert(rOop == j_rarg5, "wrong register"); aoqi@0: oop_slot = 5; aoqi@0: } aoqi@0: aoqi@0: oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; aoqi@0: int offset = oop_slot*VMRegImpl::stack_slot_size; aoqi@0: aoqi@0: map->set_oop(VMRegImpl::stack2reg(oop_slot)); aoqi@0: // Store oop in handle area, may be NULL aoqi@0: __ movptr(Address(rsp, offset), rOop); aoqi@0: if (is_receiver) { aoqi@0: *receiver_offset = offset; aoqi@0: } aoqi@0: aoqi@0: __ cmpptr(rOop, (int32_t)NULL_WORD); aoqi@0: __ lea(rHandle, Address(rsp, offset)); aoqi@0: // conditionally move a NULL from the handle area where it was just stored aoqi@0: __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); aoqi@0: } aoqi@0: aoqi@0: // If arg is on the stack then place it otherwise it is already in correct reg. aoqi@0: if (dst.first()->is_stack()) { aoqi@0: __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // A float arg may have to do float reg int reg conversion aoqi@0: static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { aoqi@0: assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); aoqi@0: aoqi@0: // The calling conventions assures us that each VMregpair is either aoqi@0: // all really one physical register or adjacent stack slots. aoqi@0: // This greatly simplifies the cases here compared to sparc. aoqi@0: aoqi@0: if (src.first()->is_stack()) { aoqi@0: if (dst.first()->is_stack()) { aoqi@0: __ movl(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); aoqi@0: } else { aoqi@0: // stack to reg aoqi@0: assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); aoqi@0: __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); aoqi@0: } aoqi@0: } else if (dst.first()->is_stack()) { aoqi@0: // reg to stack aoqi@0: assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); aoqi@0: __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); aoqi@0: } else { aoqi@0: // reg to reg aoqi@0: // In theory these overlap but the ordering is such that this is likely a nop aoqi@0: if ( src.first() != dst.first()) { aoqi@0: __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // A long move aoqi@0: static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { aoqi@0: aoqi@0: // The calling conventions assures us that each VMregpair is either aoqi@0: // all really one physical register or adjacent stack slots. aoqi@0: // This greatly simplifies the cases here compared to sparc. aoqi@0: aoqi@0: if (src.is_single_phys_reg() ) { aoqi@0: if (dst.is_single_phys_reg()) { aoqi@0: if (dst.first() != src.first()) { aoqi@0: __ mov(dst.first()->as_Register(), src.first()->as_Register()); aoqi@0: } aoqi@0: } else { aoqi@0: assert(dst.is_single_reg(), "not a stack pair"); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); aoqi@0: } aoqi@0: } else if (dst.is_single_phys_reg()) { aoqi@0: assert(src.is_single_reg(), "not a stack pair"); aoqi@0: __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); aoqi@0: } else { aoqi@0: assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); aoqi@0: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // A double move aoqi@0: static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { aoqi@0: aoqi@0: // The calling conventions assures us that each VMregpair is either aoqi@0: // all really one physical register or adjacent stack slots. aoqi@0: // This greatly simplifies the cases here compared to sparc. aoqi@0: aoqi@0: if (src.is_single_phys_reg() ) { aoqi@0: if (dst.is_single_phys_reg()) { aoqi@0: // In theory these overlap but the ordering is such that this is likely a nop aoqi@0: if ( src.first() != dst.first()) { aoqi@0: __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); aoqi@0: } aoqi@0: } else { aoqi@0: assert(dst.is_single_reg(), "not a stack pair"); aoqi@0: __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); aoqi@0: } aoqi@0: } else if (dst.is_single_phys_reg()) { aoqi@0: assert(src.is_single_reg(), "not a stack pair"); aoqi@0: __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); aoqi@0: } else { aoqi@0: assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); aoqi@0: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { aoqi@0: // We always ignore the frame_slots arg and just use the space just below frame pointer aoqi@0: // which by this time is free to use aoqi@0: switch (ret_type) { aoqi@0: case T_FLOAT: aoqi@0: __ movflt(Address(rbp, -wordSize), xmm0); aoqi@0: break; aoqi@0: case T_DOUBLE: aoqi@0: __ movdbl(Address(rbp, -wordSize), xmm0); aoqi@0: break; aoqi@0: case T_VOID: break; aoqi@0: default: { aoqi@0: __ movptr(Address(rbp, -wordSize), rax); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { aoqi@0: // We always ignore the frame_slots arg and just use the space just below frame pointer aoqi@0: // which by this time is free to use aoqi@0: switch (ret_type) { aoqi@0: case T_FLOAT: aoqi@0: __ movflt(xmm0, Address(rbp, -wordSize)); aoqi@0: break; aoqi@0: case T_DOUBLE: aoqi@0: __ movdbl(xmm0, Address(rbp, -wordSize)); aoqi@0: break; aoqi@0: case T_VOID: break; aoqi@0: default: { aoqi@0: __ movptr(rax, Address(rbp, -wordSize)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { aoqi@0: for ( int i = first_arg ; i < arg_count ; i++ ) { aoqi@0: if (args[i].first()->is_Register()) { aoqi@0: __ push(args[i].first()->as_Register()); aoqi@0: } else if (args[i].first()->is_XMMRegister()) { aoqi@0: __ subptr(rsp, 2*wordSize); aoqi@0: __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { aoqi@0: for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { aoqi@0: if (args[i].first()->is_Register()) { aoqi@0: __ pop(args[i].first()->as_Register()); aoqi@0: } else if (args[i].first()->is_XMMRegister()) { aoqi@0: __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0)); aoqi@0: __ addptr(rsp, 2*wordSize); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: static void save_or_restore_arguments(MacroAssembler* masm, aoqi@0: const int stack_slots, aoqi@0: const int total_in_args, aoqi@0: const int arg_save_area, aoqi@0: OopMap* map, aoqi@0: VMRegPair* in_regs, aoqi@0: BasicType* in_sig_bt) { aoqi@0: // if map is non-NULL then the code should store the values, aoqi@0: // otherwise it should load them. aoqi@0: int slot = arg_save_area; aoqi@0: // Save down double word first aoqi@0: for ( int i = 0; i < total_in_args; i++) { aoqi@0: if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) { aoqi@0: int offset = slot * VMRegImpl::stack_slot_size; aoqi@0: slot += VMRegImpl::slots_per_word; aoqi@0: assert(slot <= stack_slots, "overflow"); aoqi@0: if (map != NULL) { aoqi@0: __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); aoqi@0: } else { aoqi@0: __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); aoqi@0: } aoqi@0: } aoqi@0: if (in_regs[i].first()->is_Register() && aoqi@0: (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { aoqi@0: int offset = slot * VMRegImpl::stack_slot_size; aoqi@0: if (map != NULL) { aoqi@0: __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); aoqi@0: if (in_sig_bt[i] == T_ARRAY) { aoqi@0: map->set_oop(VMRegImpl::stack2reg(slot));; aoqi@0: } aoqi@0: } else { aoqi@0: __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); aoqi@0: } aoqi@0: slot += VMRegImpl::slots_per_word; aoqi@0: } aoqi@0: } aoqi@0: // Save or restore single word registers aoqi@0: for ( int i = 0; i < total_in_args; i++) { aoqi@0: if (in_regs[i].first()->is_Register()) { aoqi@0: int offset = slot * VMRegImpl::stack_slot_size; aoqi@0: slot++; aoqi@0: assert(slot <= stack_slots, "overflow"); aoqi@0: aoqi@0: // Value is in an input register pass we must flush it to the stack aoqi@0: const Register reg = in_regs[i].first()->as_Register(); aoqi@0: switch (in_sig_bt[i]) { aoqi@0: case T_BOOLEAN: aoqi@0: case T_CHAR: aoqi@0: case T_BYTE: aoqi@0: case T_SHORT: aoqi@0: case T_INT: aoqi@0: if (map != NULL) { aoqi@0: __ movl(Address(rsp, offset), reg); aoqi@0: } else { aoqi@0: __ movl(reg, Address(rsp, offset)); aoqi@0: } aoqi@0: break; aoqi@0: case T_ARRAY: aoqi@0: case T_LONG: aoqi@0: // handled above aoqi@0: break; aoqi@0: case T_OBJECT: aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: } else if (in_regs[i].first()->is_XMMRegister()) { aoqi@0: if (in_sig_bt[i] == T_FLOAT) { aoqi@0: int offset = slot * VMRegImpl::stack_slot_size; aoqi@0: slot++; aoqi@0: assert(slot <= stack_slots, "overflow"); aoqi@0: if (map != NULL) { aoqi@0: __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); aoqi@0: } else { aoqi@0: __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); aoqi@0: } aoqi@0: } aoqi@0: } else if (in_regs[i].first()->is_stack()) { aoqi@0: if (in_sig_bt[i] == T_ARRAY && map != NULL) { aoqi@0: int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); aoqi@0: map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Check GC_locker::needs_gc and enter the runtime if it's true. This aoqi@0: // keeps a new JNI critical region from starting until a GC has been aoqi@0: // forced. Save down any oops in registers and describe them in an aoqi@0: // OopMap. aoqi@0: static void check_needs_gc_for_critical_native(MacroAssembler* masm, aoqi@0: int stack_slots, aoqi@0: int total_c_args, aoqi@0: int total_in_args, aoqi@0: int arg_save_area, aoqi@0: OopMapSet* oop_maps, aoqi@0: VMRegPair* in_regs, aoqi@0: BasicType* in_sig_bt) { aoqi@0: __ block_comment("check GC_locker::needs_gc"); aoqi@0: Label cont; aoqi@0: __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false); aoqi@0: __ jcc(Assembler::equal, cont); aoqi@0: aoqi@0: // Save down any incoming oops and call into the runtime to halt for a GC aoqi@0: aoqi@0: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); aoqi@0: save_or_restore_arguments(masm, stack_slots, total_in_args, aoqi@0: arg_save_area, map, in_regs, in_sig_bt); aoqi@0: aoqi@0: address the_pc = __ pc(); aoqi@0: oop_maps->add_gc_map( __ offset(), map); aoqi@0: __ set_last_Java_frame(rsp, noreg, the_pc); aoqi@0: aoqi@0: __ block_comment("block_for_jni_critical"); aoqi@0: __ movptr(c_rarg0, r15_thread); aoqi@0: __ mov(r12, rsp); // remember sp aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows aoqi@0: __ andptr(rsp, -16); // align stack as required by ABI aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical))); aoqi@0: __ mov(rsp, r12); // restore sp aoqi@0: __ reinit_heapbase(); aoqi@0: aoqi@0: __ reset_last_Java_frame(false, true); aoqi@0: aoqi@0: save_or_restore_arguments(masm, stack_slots, total_in_args, aoqi@0: arg_save_area, NULL, in_regs, in_sig_bt); aoqi@0: aoqi@0: __ bind(cont); aoqi@0: #ifdef ASSERT aoqi@0: if (StressCriticalJNINatives) { aoqi@0: // Stress register saving aoqi@0: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); aoqi@0: save_or_restore_arguments(masm, stack_slots, total_in_args, aoqi@0: arg_save_area, map, in_regs, in_sig_bt); aoqi@0: // Destroy argument registers aoqi@0: for (int i = 0; i < total_in_args - 1; i++) { aoqi@0: if (in_regs[i].first()->is_Register()) { aoqi@0: const Register reg = in_regs[i].first()->as_Register(); aoqi@0: __ xorptr(reg, reg); aoqi@0: } else if (in_regs[i].first()->is_XMMRegister()) { aoqi@0: __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister()); aoqi@0: } else if (in_regs[i].first()->is_FloatRegister()) { aoqi@0: ShouldNotReachHere(); aoqi@0: } else if (in_regs[i].first()->is_stack()) { aoqi@0: // Nothing to do aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) { aoqi@0: i++; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: save_or_restore_arguments(masm, stack_slots, total_in_args, aoqi@0: arg_save_area, NULL, in_regs, in_sig_bt); aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: // Unpack an array argument into a pointer to the body and the length aoqi@0: // if the array is non-null, otherwise pass 0 for both. aoqi@0: static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { aoqi@0: Register tmp_reg = rax; aoqi@0: assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg, aoqi@0: "possible collision"); aoqi@0: assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg, aoqi@0: "possible collision"); aoqi@0: aoqi@0: __ block_comment("unpack_array_argument {"); aoqi@0: aoqi@0: // Pass the length, ptr pair aoqi@0: Label is_null, done; aoqi@0: VMRegPair tmp; aoqi@0: tmp.set_ptr(tmp_reg->as_VMReg()); aoqi@0: if (reg.first()->is_stack()) { aoqi@0: // Load the arg up from the stack aoqi@0: move_ptr(masm, reg, tmp); aoqi@0: reg = tmp; aoqi@0: } aoqi@0: __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); aoqi@0: __ jccb(Assembler::equal, is_null); aoqi@0: __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type))); aoqi@0: move_ptr(masm, tmp, body_arg); aoqi@0: // load the length relative to the body. aoqi@0: __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() - aoqi@0: arrayOopDesc::base_offset_in_bytes(in_elem_type))); aoqi@0: move32_64(masm, tmp, length_arg); aoqi@0: __ jmpb(done); aoqi@0: __ bind(is_null); aoqi@0: // Pass zeros aoqi@0: __ xorptr(tmp_reg, tmp_reg); aoqi@0: move_ptr(masm, tmp, body_arg); aoqi@0: move32_64(masm, tmp, length_arg); aoqi@0: __ bind(done); aoqi@0: aoqi@0: __ block_comment("} unpack_array_argument"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Different signatures may require very different orders for the move aoqi@0: // to avoid clobbering other arguments. There's no simple way to aoqi@0: // order them safely. Compute a safe order for issuing stores and aoqi@0: // break any cycles in those stores. This code is fairly general but aoqi@0: // it's not necessary on the other platforms so we keep it in the aoqi@0: // platform dependent code instead of moving it into a shared file. aoqi@0: // (See bugs 7013347 & 7145024.) aoqi@0: // Note that this code is specific to LP64. aoqi@0: class ComputeMoveOrder: public StackObj { aoqi@0: class MoveOperation: public ResourceObj { aoqi@0: friend class ComputeMoveOrder; aoqi@0: private: aoqi@0: VMRegPair _src; aoqi@0: VMRegPair _dst; aoqi@0: int _src_index; aoqi@0: int _dst_index; aoqi@0: bool _processed; aoqi@0: MoveOperation* _next; aoqi@0: MoveOperation* _prev; aoqi@0: aoqi@0: static int get_id(VMRegPair r) { aoqi@0: return r.first()->value(); aoqi@0: } aoqi@0: aoqi@0: public: aoqi@0: MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): aoqi@0: _src(src) aoqi@0: , _src_index(src_index) aoqi@0: , _dst(dst) aoqi@0: , _dst_index(dst_index) aoqi@0: , _next(NULL) aoqi@0: , _prev(NULL) aoqi@0: , _processed(false) { aoqi@0: } aoqi@0: aoqi@0: VMRegPair src() const { return _src; } aoqi@0: int src_id() const { return get_id(src()); } aoqi@0: int src_index() const { return _src_index; } aoqi@0: VMRegPair dst() const { return _dst; } aoqi@0: void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; } aoqi@0: int dst_index() const { return _dst_index; } aoqi@0: int dst_id() const { return get_id(dst()); } aoqi@0: MoveOperation* next() const { return _next; } aoqi@0: MoveOperation* prev() const { return _prev; } aoqi@0: void set_processed() { _processed = true; } aoqi@0: bool is_processed() const { return _processed; } aoqi@0: aoqi@0: // insert aoqi@0: void break_cycle(VMRegPair temp_register) { aoqi@0: // create a new store following the last store aoqi@0: // to move from the temp_register to the original aoqi@0: MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst()); aoqi@0: aoqi@0: // break the cycle of links and insert new_store at the end aoqi@0: // break the reverse link. aoqi@0: MoveOperation* p = prev(); aoqi@0: assert(p->next() == this, "must be"); aoqi@0: _prev = NULL; aoqi@0: p->_next = new_store; aoqi@0: new_store->_prev = p; aoqi@0: aoqi@0: // change the original store to save it's value in the temp. aoqi@0: set_dst(-1, temp_register); aoqi@0: } aoqi@0: aoqi@0: void link(GrowableArray& killer) { aoqi@0: // link this store in front the store that it depends on aoqi@0: MoveOperation* n = killer.at_grow(src_id(), NULL); aoqi@0: if (n != NULL) { aoqi@0: assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet"); aoqi@0: _next = n; aoqi@0: n->_prev = this; aoqi@0: } aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: private: aoqi@0: GrowableArray edges; aoqi@0: aoqi@0: public: aoqi@0: ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, aoqi@0: BasicType* in_sig_bt, GrowableArray& arg_order, VMRegPair tmp_vmreg) { aoqi@0: // Move operations where the dest is the stack can all be aoqi@0: // scheduled first since they can't interfere with the other moves. aoqi@0: for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { aoqi@0: if (in_sig_bt[i] == T_ARRAY) { aoqi@0: c_arg--; aoqi@0: if (out_regs[c_arg].first()->is_stack() && aoqi@0: out_regs[c_arg + 1].first()->is_stack()) { aoqi@0: arg_order.push(i); aoqi@0: arg_order.push(c_arg); aoqi@0: } else { aoqi@0: if (out_regs[c_arg].first()->is_stack() || aoqi@0: in_regs[i].first() == out_regs[c_arg].first()) { aoqi@0: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]); aoqi@0: } else { aoqi@0: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); aoqi@0: } aoqi@0: } aoqi@0: } else if (in_sig_bt[i] == T_VOID) { aoqi@0: arg_order.push(i); aoqi@0: arg_order.push(c_arg); aoqi@0: } else { aoqi@0: if (out_regs[c_arg].first()->is_stack() || aoqi@0: in_regs[i].first() == out_regs[c_arg].first()) { aoqi@0: arg_order.push(i); aoqi@0: arg_order.push(c_arg); aoqi@0: } else { aoqi@0: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: // Break any cycles in the register moves and emit the in the aoqi@0: // proper order. aoqi@0: GrowableArray* stores = get_store_order(tmp_vmreg); aoqi@0: for (int i = 0; i < stores->length(); i++) { aoqi@0: arg_order.push(stores->at(i)->src_index()); aoqi@0: arg_order.push(stores->at(i)->dst_index()); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Collected all the move operations aoqi@0: void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { aoqi@0: if (src.first() == dst.first()) return; aoqi@0: edges.append(new MoveOperation(src_index, src, dst_index, dst)); aoqi@0: } aoqi@0: aoqi@0: // Walk the edges breaking cycles between moves. The result list aoqi@0: // can be walked in order to produce the proper set of loads aoqi@0: GrowableArray* get_store_order(VMRegPair temp_register) { aoqi@0: // Record which moves kill which values aoqi@0: GrowableArray killer; aoqi@0: for (int i = 0; i < edges.length(); i++) { aoqi@0: MoveOperation* s = edges.at(i); aoqi@0: assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer"); aoqi@0: killer.at_put_grow(s->dst_id(), s, NULL); aoqi@0: } aoqi@0: assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL, aoqi@0: "make sure temp isn't in the registers that are killed"); aoqi@0: aoqi@0: // create links between loads and stores aoqi@0: for (int i = 0; i < edges.length(); i++) { aoqi@0: edges.at(i)->link(killer); aoqi@0: } aoqi@0: aoqi@0: // at this point, all the move operations are chained together aoqi@0: // in a doubly linked list. Processing it backwards finds aoqi@0: // the beginning of the chain, forwards finds the end. If there's aoqi@0: // a cycle it can be broken at any point, so pick an edge and walk aoqi@0: // backward until the list ends or we end where we started. aoqi@0: GrowableArray* stores = new GrowableArray(); aoqi@0: for (int e = 0; e < edges.length(); e++) { aoqi@0: MoveOperation* s = edges.at(e); aoqi@0: if (!s->is_processed()) { aoqi@0: MoveOperation* start = s; aoqi@0: // search for the beginning of the chain or cycle aoqi@0: while (start->prev() != NULL && start->prev() != s) { aoqi@0: start = start->prev(); aoqi@0: } aoqi@0: if (start->prev() == s) { aoqi@0: start->break_cycle(temp_register); aoqi@0: } aoqi@0: // walk the chain forward inserting to store list aoqi@0: while (start != NULL) { aoqi@0: stores->append(start); aoqi@0: start->set_processed(); aoqi@0: start = start->next(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: return stores; aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: static void verify_oop_args(MacroAssembler* masm, aoqi@0: methodHandle method, aoqi@0: const BasicType* sig_bt, aoqi@0: const VMRegPair* regs) { aoqi@0: Register temp_reg = rbx; // not part of any compiled calling seq aoqi@0: if (VerifyOops) { aoqi@0: for (int i = 0; i < method->size_of_parameters(); i++) { aoqi@0: if (sig_bt[i] == T_OBJECT || aoqi@0: sig_bt[i] == T_ARRAY) { aoqi@0: VMReg r = regs[i].first(); aoqi@0: assert(r->is_valid(), "bad oop arg"); aoqi@0: if (r->is_stack()) { aoqi@0: __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); aoqi@0: __ verify_oop(temp_reg); aoqi@0: } else { aoqi@0: __ verify_oop(r->as_Register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: static void gen_special_dispatch(MacroAssembler* masm, aoqi@0: methodHandle method, aoqi@0: const BasicType* sig_bt, aoqi@0: const VMRegPair* regs) { aoqi@0: verify_oop_args(masm, method, sig_bt, regs); aoqi@0: vmIntrinsics::ID iid = method->intrinsic_id(); aoqi@0: aoqi@0: // Now write the args into the outgoing interpreter space aoqi@0: bool has_receiver = false; aoqi@0: Register receiver_reg = noreg; aoqi@0: int member_arg_pos = -1; aoqi@0: Register member_reg = noreg; aoqi@0: int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); aoqi@0: if (ref_kind != 0) { aoqi@0: member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument aoqi@0: member_reg = rbx; // known to be free at this point aoqi@0: has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); aoqi@0: } else if (iid == vmIntrinsics::_invokeBasic) { aoqi@0: has_receiver = true; aoqi@0: } else { aoqi@0: fatal(err_msg_res("unexpected intrinsic id %d", iid)); aoqi@0: } aoqi@0: aoqi@0: if (member_reg != noreg) { aoqi@0: // Load the member_arg into register, if necessary. aoqi@0: SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); aoqi@0: VMReg r = regs[member_arg_pos].first(); aoqi@0: if (r->is_stack()) { aoqi@0: __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); aoqi@0: } else { aoqi@0: // no data motion is needed aoqi@0: member_reg = r->as_Register(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (has_receiver) { aoqi@0: // Make sure the receiver is loaded into a register. aoqi@0: assert(method->size_of_parameters() > 0, "oob"); aoqi@0: assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); aoqi@0: VMReg r = regs[0].first(); aoqi@0: assert(r->is_valid(), "bad receiver arg"); aoqi@0: if (r->is_stack()) { aoqi@0: // Porting note: This assumes that compiled calling conventions always aoqi@0: // pass the receiver oop in a register. If this is not true on some aoqi@0: // platform, pick a temp and load the receiver from stack. aoqi@0: fatal("receiver always in a register"); aoqi@0: receiver_reg = j_rarg0; // known to be free at this point aoqi@0: __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); aoqi@0: } else { aoqi@0: // no data motion is needed aoqi@0: receiver_reg = r->as_Register(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Figure out which address we are really jumping to: aoqi@0: MethodHandles::generate_method_handle_dispatch(masm, iid, aoqi@0: receiver_reg, member_reg, /*for_compiler_entry:*/ true); aoqi@0: } aoqi@0: aoqi@0: // --------------------------------------------------------------------------- aoqi@0: // Generate a native wrapper for a given method. The method takes arguments aoqi@0: // in the Java compiled code convention, marshals them to the native aoqi@0: // convention (handlizes oops, etc), transitions to native, makes the call, aoqi@0: // returns to java state (possibly blocking), unhandlizes any result and aoqi@0: // returns. aoqi@0: // aoqi@0: // Critical native functions are a shorthand for the use of aoqi@0: // GetPrimtiveArrayCritical and disallow the use of any other JNI aoqi@0: // functions. The wrapper is expected to unpack the arguments before aoqi@0: // passing them to the callee and perform checks before and after the aoqi@0: // native call to ensure that they GC_locker aoqi@0: // lock_critical/unlock_critical semantics are followed. Some other aoqi@0: // parts of JNI setup are skipped like the tear down of the JNI handle aoqi@0: // block and the check for pending exceptions it's impossible for them aoqi@0: // to be thrown. aoqi@0: // aoqi@0: // They are roughly structured like this: aoqi@0: // if (GC_locker::needs_gc()) aoqi@0: // SharedRuntime::block_for_jni_critical(); aoqi@0: // tranistion to thread_in_native aoqi@0: // unpack arrray arguments and call native entry point aoqi@0: // check for safepoint in progress aoqi@0: // check if any thread suspend flags are set aoqi@0: // call into JVM and possible unlock the JNI critical aoqi@0: // if a GC was suppressed while in the critical native. aoqi@0: // transition back to thread_in_Java aoqi@0: // return to caller aoqi@0: // aoqi@0: nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, aoqi@0: methodHandle method, aoqi@0: int compile_id, aoqi@0: BasicType* in_sig_bt, aoqi@0: VMRegPair* in_regs, aoqi@0: BasicType ret_type) { aoqi@0: if (method->is_method_handle_intrinsic()) { aoqi@0: vmIntrinsics::ID iid = method->intrinsic_id(); aoqi@0: intptr_t start = (intptr_t)__ pc(); aoqi@0: int vep_offset = ((intptr_t)__ pc()) - start; aoqi@0: gen_special_dispatch(masm, aoqi@0: method, aoqi@0: in_sig_bt, aoqi@0: in_regs); aoqi@0: int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period aoqi@0: __ flush(); aoqi@0: int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually aoqi@0: return nmethod::new_native_nmethod(method, aoqi@0: compile_id, aoqi@0: masm->code(), aoqi@0: vep_offset, aoqi@0: frame_complete, aoqi@0: stack_slots / VMRegImpl::slots_per_word, aoqi@0: in_ByteSize(-1), aoqi@0: in_ByteSize(-1), aoqi@0: (OopMapSet*)NULL); aoqi@0: } aoqi@0: bool is_critical_native = true; aoqi@0: address native_func = method->critical_native_function(); aoqi@0: if (native_func == NULL) { aoqi@0: native_func = method->native_function(); aoqi@0: is_critical_native = false; aoqi@0: } aoqi@0: assert(native_func != NULL, "must have function"); aoqi@0: aoqi@0: // An OopMap for lock (and class if static) aoqi@0: OopMapSet *oop_maps = new OopMapSet(); aoqi@0: intptr_t start = (intptr_t)__ pc(); aoqi@0: aoqi@0: // We have received a description of where all the java arg are located aoqi@0: // on entry to the wrapper. We need to convert these args to where aoqi@0: // the jni function will expect them. To figure out where they go aoqi@0: // we convert the java signature to a C signature by inserting aoqi@0: // the hidden arguments as arg[0] and possibly arg[1] (static method) aoqi@0: aoqi@0: const int total_in_args = method->size_of_parameters(); aoqi@0: int total_c_args = total_in_args; aoqi@0: if (!is_critical_native) { aoqi@0: total_c_args += 1; aoqi@0: if (method->is_static()) { aoqi@0: total_c_args++; aoqi@0: } aoqi@0: } else { aoqi@0: for (int i = 0; i < total_in_args; i++) { aoqi@0: if (in_sig_bt[i] == T_ARRAY) { aoqi@0: total_c_args++; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); aoqi@0: VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); aoqi@0: BasicType* in_elem_bt = NULL; aoqi@0: aoqi@0: int argc = 0; aoqi@0: if (!is_critical_native) { aoqi@0: out_sig_bt[argc++] = T_ADDRESS; aoqi@0: if (method->is_static()) { aoqi@0: out_sig_bt[argc++] = T_OBJECT; aoqi@0: } aoqi@0: aoqi@0: for (int i = 0; i < total_in_args ; i++ ) { aoqi@0: out_sig_bt[argc++] = in_sig_bt[i]; aoqi@0: } aoqi@0: } else { aoqi@0: Thread* THREAD = Thread::current(); aoqi@0: in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); aoqi@0: SignatureStream ss(method->signature()); aoqi@0: for (int i = 0; i < total_in_args ; i++ ) { aoqi@0: if (in_sig_bt[i] == T_ARRAY) { aoqi@0: // Arrays are passed as int, elem* pair aoqi@0: out_sig_bt[argc++] = T_INT; aoqi@0: out_sig_bt[argc++] = T_ADDRESS; aoqi@0: Symbol* atype = ss.as_symbol(CHECK_NULL); aoqi@0: const char* at = atype->as_C_string(); aoqi@0: if (strlen(at) == 2) { aoqi@0: assert(at[0] == '[', "must be"); aoqi@0: switch (at[1]) { aoqi@0: case 'B': in_elem_bt[i] = T_BYTE; break; aoqi@0: case 'C': in_elem_bt[i] = T_CHAR; break; aoqi@0: case 'D': in_elem_bt[i] = T_DOUBLE; break; aoqi@0: case 'F': in_elem_bt[i] = T_FLOAT; break; aoqi@0: case 'I': in_elem_bt[i] = T_INT; break; aoqi@0: case 'J': in_elem_bt[i] = T_LONG; break; aoqi@0: case 'S': in_elem_bt[i] = T_SHORT; break; aoqi@0: case 'Z': in_elem_bt[i] = T_BOOLEAN; break; aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: } aoqi@0: } else { aoqi@0: out_sig_bt[argc++] = in_sig_bt[i]; aoqi@0: in_elem_bt[i] = T_VOID; aoqi@0: } aoqi@0: if (in_sig_bt[i] != T_VOID) { aoqi@0: assert(in_sig_bt[i] == ss.type(), "must match"); aoqi@0: ss.next(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Now figure out where the args must be stored and how much stack space aoqi@0: // they require. aoqi@0: int out_arg_slots; aoqi@0: out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); aoqi@0: aoqi@0: // Compute framesize for the wrapper. We need to handlize all oops in aoqi@0: // incoming registers aoqi@0: aoqi@0: // Calculate the total number of stack slots we will need. aoqi@0: aoqi@0: // First count the abi requirement plus all of the outgoing args aoqi@0: int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; aoqi@0: aoqi@0: // Now the space for the inbound oop handle area aoqi@0: int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers aoqi@0: if (is_critical_native) { aoqi@0: // Critical natives may have to call out so they need a save area aoqi@0: // for register arguments. aoqi@0: int double_slots = 0; aoqi@0: int single_slots = 0; aoqi@0: for ( int i = 0; i < total_in_args; i++) { aoqi@0: if (in_regs[i].first()->is_Register()) { aoqi@0: const Register reg = in_regs[i].first()->as_Register(); aoqi@0: switch (in_sig_bt[i]) { aoqi@0: case T_BOOLEAN: aoqi@0: case T_BYTE: aoqi@0: case T_SHORT: aoqi@0: case T_CHAR: aoqi@0: case T_INT: single_slots++; break; aoqi@0: case T_ARRAY: // specific to LP64 (7145024) aoqi@0: case T_LONG: double_slots++; break; aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: } else if (in_regs[i].first()->is_XMMRegister()) { aoqi@0: switch (in_sig_bt[i]) { aoqi@0: case T_FLOAT: single_slots++; break; aoqi@0: case T_DOUBLE: double_slots++; break; aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: } else if (in_regs[i].first()->is_FloatRegister()) { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: } aoqi@0: total_save_slots = double_slots * 2 + single_slots; aoqi@0: // align the save area aoqi@0: if (double_slots != 0) { aoqi@0: stack_slots = round_to(stack_slots, 2); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int oop_handle_offset = stack_slots; aoqi@0: stack_slots += total_save_slots; aoqi@0: aoqi@0: // Now any space we need for handlizing a klass if static method aoqi@0: aoqi@0: int klass_slot_offset = 0; aoqi@0: int klass_offset = -1; aoqi@0: int lock_slot_offset = 0; aoqi@0: bool is_static = false; aoqi@0: aoqi@0: if (method->is_static()) { aoqi@0: klass_slot_offset = stack_slots; aoqi@0: stack_slots += VMRegImpl::slots_per_word; aoqi@0: klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; aoqi@0: is_static = true; aoqi@0: } aoqi@0: aoqi@0: // Plus a lock if needed aoqi@0: aoqi@0: if (method->is_synchronized()) { aoqi@0: lock_slot_offset = stack_slots; aoqi@0: stack_slots += VMRegImpl::slots_per_word; aoqi@0: } aoqi@0: aoqi@0: // Now a place (+2) to save return values or temp during shuffling aoqi@0: // + 4 for return address (which we own) and saved rbp aoqi@0: stack_slots += 6; aoqi@0: aoqi@0: // Ok The space we have allocated will look like: aoqi@0: // aoqi@0: // aoqi@0: // FP-> | | aoqi@0: // |---------------------| aoqi@0: // | 2 slots for moves | aoqi@0: // |---------------------| aoqi@0: // | lock box (if sync) | aoqi@0: // |---------------------| <- lock_slot_offset aoqi@0: // | klass (if static) | aoqi@0: // |---------------------| <- klass_slot_offset aoqi@0: // | oopHandle area | aoqi@0: // |---------------------| <- oop_handle_offset (6 java arg registers) aoqi@0: // | outbound memory | aoqi@0: // | based arguments | aoqi@0: // | | aoqi@0: // |---------------------| aoqi@0: // | | aoqi@0: // SP-> | out_preserved_slots | aoqi@0: // aoqi@0: // aoqi@0: aoqi@0: aoqi@0: // Now compute actual number of stack words we need rounding to make aoqi@0: // stack properly aligned. aoqi@0: stack_slots = round_to(stack_slots, StackAlignmentInSlots); aoqi@0: aoqi@0: int stack_size = stack_slots * VMRegImpl::stack_slot_size; aoqi@0: aoqi@0: // First thing make an ic check to see if we should even be here aoqi@0: aoqi@0: // We are free to use all registers as temps without saving them and aoqi@0: // restoring them except rbp. rbp is the only callee save register aoqi@0: // as far as the interpreter and the compiler(s) are concerned. aoqi@0: aoqi@0: aoqi@0: const Register ic_reg = rax; aoqi@0: const Register receiver = j_rarg0; aoqi@0: aoqi@0: Label hit; aoqi@0: Label exception_pending; aoqi@0: aoqi@0: assert_different_registers(ic_reg, receiver, rscratch1); aoqi@0: __ verify_oop(receiver); aoqi@0: __ load_klass(rscratch1, receiver); aoqi@0: __ cmpq(ic_reg, rscratch1); aoqi@0: __ jcc(Assembler::equal, hit); aoqi@0: aoqi@0: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); aoqi@0: aoqi@0: // Verified entry point must be aligned aoqi@0: __ align(8); aoqi@0: aoqi@0: __ bind(hit); aoqi@0: aoqi@0: int vep_offset = ((intptr_t)__ pc()) - start; aoqi@0: aoqi@0: // The instruction at the verified entry point must be 5 bytes or longer aoqi@0: // because it can be patched on the fly by make_non_entrant. The stack bang aoqi@0: // instruction fits that requirement. aoqi@0: aoqi@0: // Generate stack overflow check aoqi@0: aoqi@0: if (UseStackBanging) { aoqi@0: __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); aoqi@0: } else { aoqi@0: // need a 5 byte instruction to allow MT safe patching to non-entrant aoqi@0: __ fat_nop(); aoqi@0: } aoqi@0: aoqi@0: // Generate a new frame for the wrapper. aoqi@0: __ enter(); aoqi@0: // -2 because return address is already present and so is saved rbp aoqi@0: __ subptr(rsp, stack_size - 2*wordSize); aoqi@0: aoqi@0: // Frame is now completed as far as size and linkage. aoqi@0: int frame_complete = ((intptr_t)__ pc()) - start; aoqi@0: aoqi@0: if (UseRTMLocking) { aoqi@0: // Abort RTM transaction before calling JNI aoqi@0: // because critical section will be large and will be aoqi@0: // aborted anyway. Also nmethod could be deoptimized. aoqi@0: __ xabort(0); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: { aoqi@0: Label L; aoqi@0: __ mov(rax, rsp); aoqi@0: __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI) aoqi@0: __ cmpptr(rax, rsp); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: __ stop("improperly aligned stack"); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: #endif /* ASSERT */ aoqi@0: aoqi@0: aoqi@0: // We use r14 as the oop handle for the receiver/klass aoqi@0: // It is callee save so it survives the call to native aoqi@0: aoqi@0: const Register oop_handle_reg = r14; aoqi@0: aoqi@0: if (is_critical_native) { aoqi@0: check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, aoqi@0: oop_handle_offset, oop_maps, in_regs, in_sig_bt); aoqi@0: } aoqi@0: aoqi@0: // aoqi@0: // We immediately shuffle the arguments so that any vm call we have to aoqi@0: // make from here on out (sync slow path, jvmti, etc.) we will have aoqi@0: // captured the oops from our caller and have a valid oopMap for aoqi@0: // them. aoqi@0: aoqi@0: // ----------------- aoqi@0: // The Grand Shuffle aoqi@0: aoqi@0: // The Java calling convention is either equal (linux) or denser (win64) than the aoqi@0: // c calling convention. However the because of the jni_env argument the c calling aoqi@0: // convention always has at least one more (and two for static) arguments than Java. aoqi@0: // Therefore if we move the args from java -> c backwards then we will never have aoqi@0: // a register->register conflict and we don't have to build a dependency graph aoqi@0: // and figure out how to break any cycles. aoqi@0: // aoqi@0: aoqi@0: // Record esp-based slot for receiver on stack for non-static methods aoqi@0: int receiver_offset = -1; aoqi@0: aoqi@0: // This is a trick. We double the stack slots so we can claim aoqi@0: // the oops in the caller's frame. Since we are sure to have aoqi@0: // more args than the caller doubling is enough to make aoqi@0: // sure we can capture all the incoming oop args from the aoqi@0: // caller. aoqi@0: // aoqi@0: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); aoqi@0: aoqi@0: // Mark location of rbp (someday) aoqi@0: // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp)); aoqi@0: aoqi@0: // Use eax, ebx as temporaries during any memory-memory moves we have to do aoqi@0: // All inbound args are referenced based on rbp and all outbound args via rsp. aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: bool reg_destroyed[RegisterImpl::number_of_registers]; aoqi@0: bool freg_destroyed[XMMRegisterImpl::number_of_registers]; aoqi@0: for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { aoqi@0: reg_destroyed[r] = false; aoqi@0: } aoqi@0: for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) { aoqi@0: freg_destroyed[f] = false; aoqi@0: } aoqi@0: aoqi@0: #endif /* ASSERT */ aoqi@0: aoqi@0: // This may iterate in two different directions depending on the aoqi@0: // kind of native it is. The reason is that for regular JNI natives aoqi@0: // the incoming and outgoing registers are offset upwards and for aoqi@0: // critical natives they are offset down. aoqi@0: GrowableArray arg_order(2 * total_in_args); aoqi@0: VMRegPair tmp_vmreg; aoqi@0: tmp_vmreg.set1(rbx->as_VMReg()); aoqi@0: aoqi@0: if (!is_critical_native) { aoqi@0: for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { aoqi@0: arg_order.push(i); aoqi@0: arg_order.push(c_arg); aoqi@0: } aoqi@0: } else { aoqi@0: // Compute a valid move order, using tmp_vmreg to break any cycles aoqi@0: ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); aoqi@0: } aoqi@0: aoqi@0: int temploc = -1; aoqi@0: for (int ai = 0; ai < arg_order.length(); ai += 2) { aoqi@0: int i = arg_order.at(ai); aoqi@0: int c_arg = arg_order.at(ai + 1); aoqi@0: __ block_comment(err_msg("move %d -> %d", i, c_arg)); aoqi@0: if (c_arg == -1) { aoqi@0: assert(is_critical_native, "should only be required for critical natives"); aoqi@0: // This arg needs to be moved to a temporary aoqi@0: __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); aoqi@0: in_regs[i] = tmp_vmreg; aoqi@0: temploc = i; aoqi@0: continue; aoqi@0: } else if (i == -1) { aoqi@0: assert(is_critical_native, "should only be required for critical natives"); aoqi@0: // Read from the temporary location aoqi@0: assert(temploc != -1, "must be valid"); aoqi@0: i = temploc; aoqi@0: temploc = -1; aoqi@0: } aoqi@0: #ifdef ASSERT aoqi@0: if (in_regs[i].first()->is_Register()) { aoqi@0: assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); aoqi@0: } else if (in_regs[i].first()->is_XMMRegister()) { aoqi@0: assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!"); aoqi@0: } aoqi@0: if (out_regs[c_arg].first()->is_Register()) { aoqi@0: reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; aoqi@0: } else if (out_regs[c_arg].first()->is_XMMRegister()) { aoqi@0: freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; aoqi@0: } aoqi@0: #endif /* ASSERT */ aoqi@0: switch (in_sig_bt[i]) { aoqi@0: case T_ARRAY: aoqi@0: if (is_critical_native) { aoqi@0: unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); aoqi@0: c_arg++; aoqi@0: #ifdef ASSERT aoqi@0: if (out_regs[c_arg].first()->is_Register()) { aoqi@0: reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; aoqi@0: } else if (out_regs[c_arg].first()->is_XMMRegister()) { aoqi@0: freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; aoqi@0: } aoqi@0: #endif aoqi@0: break; aoqi@0: } aoqi@0: case T_OBJECT: aoqi@0: assert(!is_critical_native, "no oop arguments"); aoqi@0: object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], aoqi@0: ((i == 0) && (!is_static)), aoqi@0: &receiver_offset); aoqi@0: break; aoqi@0: case T_VOID: aoqi@0: break; aoqi@0: aoqi@0: case T_FLOAT: aoqi@0: float_move(masm, in_regs[i], out_regs[c_arg]); aoqi@0: break; aoqi@0: aoqi@0: case T_DOUBLE: aoqi@0: assert( i + 1 < total_in_args && aoqi@0: in_sig_bt[i + 1] == T_VOID && aoqi@0: out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); aoqi@0: double_move(masm, in_regs[i], out_regs[c_arg]); aoqi@0: break; aoqi@0: aoqi@0: case T_LONG : aoqi@0: long_move(masm, in_regs[i], out_regs[c_arg]); aoqi@0: break; aoqi@0: aoqi@0: case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); aoqi@0: aoqi@0: default: aoqi@0: move32_64(masm, in_regs[i], out_regs[c_arg]); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int c_arg; aoqi@0: aoqi@0: // Pre-load a static method's oop into r14. Used both by locking code and aoqi@0: // the normal JNI call code. aoqi@0: if (!is_critical_native) { aoqi@0: // point c_arg at the first arg that is already loaded in case we aoqi@0: // need to spill before we call out aoqi@0: c_arg = total_c_args - total_in_args; aoqi@0: aoqi@0: if (method->is_static()) { aoqi@0: aoqi@0: // load oop into a register aoqi@0: __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror())); aoqi@0: aoqi@0: // Now handlize the static class mirror it's known not-null. aoqi@0: __ movptr(Address(rsp, klass_offset), oop_handle_reg); aoqi@0: map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); aoqi@0: aoqi@0: // Now get the handle aoqi@0: __ lea(oop_handle_reg, Address(rsp, klass_offset)); aoqi@0: // store the klass handle as second argument aoqi@0: __ movptr(c_rarg1, oop_handle_reg); aoqi@0: // and protect the arg if we must spill aoqi@0: c_arg--; aoqi@0: } aoqi@0: } else { aoqi@0: // For JNI critical methods we need to save all registers in save_args. aoqi@0: c_arg = 0; aoqi@0: } aoqi@0: aoqi@0: // Change state to native (we save the return address in the thread, since it might not aoqi@0: // be pushed on the stack when we do a a stack traversal). It is enough that the pc() aoqi@0: // points into the right code segment. It does not have to be the correct return pc. aoqi@0: // We use the same pc/oopMap repeatedly when we call out aoqi@0: aoqi@0: intptr_t the_pc = (intptr_t) __ pc(); aoqi@0: oop_maps->add_gc_map(the_pc - start, map); aoqi@0: aoqi@0: __ set_last_Java_frame(rsp, noreg, (address)the_pc); aoqi@0: aoqi@0: aoqi@0: // We have all of the arguments setup at this point. We must not touch any register aoqi@0: // argument registers at this point (what if we save/restore them there are no oop? aoqi@0: aoqi@0: { aoqi@0: SkipIfEqual skip(masm, &DTraceMethodProbes, false); aoqi@0: // protect the args we've loaded aoqi@0: save_args(masm, total_c_args, c_arg, out_regs); aoqi@0: __ mov_metadata(c_rarg1, method()); aoqi@0: __ call_VM_leaf( aoqi@0: CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), aoqi@0: r15_thread, c_rarg1); aoqi@0: restore_args(masm, total_c_args, c_arg, out_regs); aoqi@0: } aoqi@0: aoqi@0: // RedefineClasses() tracing support for obsolete method entry aoqi@0: if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { aoqi@0: // protect the args we've loaded aoqi@0: save_args(masm, total_c_args, c_arg, out_regs); aoqi@0: __ mov_metadata(c_rarg1, method()); aoqi@0: __ call_VM_leaf( aoqi@0: CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), aoqi@0: r15_thread, c_rarg1); aoqi@0: restore_args(masm, total_c_args, c_arg, out_regs); aoqi@0: } aoqi@0: aoqi@0: // Lock a synchronized method aoqi@0: aoqi@0: // Register definitions used by locking and unlocking aoqi@0: aoqi@0: const Register swap_reg = rax; // Must use rax for cmpxchg instruction aoqi@0: const Register obj_reg = rbx; // Will contain the oop aoqi@0: const Register lock_reg = r13; // Address of compiler lock object (BasicLock) aoqi@0: const Register old_hdr = r13; // value of old header at unlock time aoqi@0: aoqi@0: Label slow_path_lock; aoqi@0: Label lock_done; aoqi@0: aoqi@0: if (method->is_synchronized()) { aoqi@0: assert(!is_critical_native, "unhandled"); aoqi@0: aoqi@0: aoqi@0: const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); aoqi@0: aoqi@0: // Get the handle (the 2nd argument) aoqi@0: __ mov(oop_handle_reg, c_rarg1); aoqi@0: aoqi@0: // Get address of the box aoqi@0: aoqi@0: __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); aoqi@0: aoqi@0: // Load the oop from the handle aoqi@0: __ movptr(obj_reg, Address(oop_handle_reg, 0)); aoqi@0: aoqi@0: if (UseBiasedLocking) { aoqi@0: __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock); aoqi@0: } aoqi@0: aoqi@0: // Load immediate 1 into swap_reg %rax aoqi@0: __ movl(swap_reg, 1); aoqi@0: aoqi@0: // Load (object->mark() | 1) into swap_reg %rax aoqi@0: __ orptr(swap_reg, Address(obj_reg, 0)); aoqi@0: aoqi@0: // Save (object->mark() | 1) into BasicLock's displaced header aoqi@0: __ movptr(Address(lock_reg, mark_word_offset), swap_reg); aoqi@0: aoqi@0: if (os::is_MP()) { aoqi@0: __ lock(); aoqi@0: } aoqi@0: aoqi@0: // src -> dest iff dest == rax else rax <- dest aoqi@0: __ cmpxchgptr(lock_reg, Address(obj_reg, 0)); aoqi@0: __ jcc(Assembler::equal, lock_done); aoqi@0: aoqi@0: // Hmm should this move to the slow path code area??? aoqi@0: aoqi@0: // Test if the oopMark is an obvious stack pointer, i.e., aoqi@0: // 1) (mark & 3) == 0, and aoqi@0: // 2) rsp <= mark < mark + os::pagesize() aoqi@0: // These 3 tests can be done by evaluating the following aoqi@0: // expression: ((mark - rsp) & (3 - os::vm_page_size())), aoqi@0: // assuming both stack pointer and pagesize have their aoqi@0: // least significant 2 bits clear. aoqi@0: // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg aoqi@0: aoqi@0: __ subptr(swap_reg, rsp); aoqi@0: __ andptr(swap_reg, 3 - os::vm_page_size()); aoqi@0: aoqi@0: // Save the test result, for recursive case, the result is zero aoqi@0: __ movptr(Address(lock_reg, mark_word_offset), swap_reg); aoqi@0: __ jcc(Assembler::notEqual, slow_path_lock); aoqi@0: aoqi@0: // Slow path will re-enter here aoqi@0: aoqi@0: __ bind(lock_done); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Finally just about ready to make the JNI call aoqi@0: aoqi@0: aoqi@0: // get JNIEnv* which is first argument to native aoqi@0: if (!is_critical_native) { aoqi@0: __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset()))); aoqi@0: } aoqi@0: aoqi@0: // Now set thread in native aoqi@0: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native); aoqi@0: aoqi@0: __ call(RuntimeAddress(native_func)); aoqi@0: aoqi@0: // Verify or restore cpu control state after JNI call aoqi@0: __ restore_cpu_control_state_after_jni(); aoqi@0: aoqi@0: // Unpack native results. aoqi@0: switch (ret_type) { aoqi@0: case T_BOOLEAN: __ c2bool(rax); break; aoqi@0: case T_CHAR : __ movzwl(rax, rax); break; aoqi@0: case T_BYTE : __ sign_extend_byte (rax); break; aoqi@0: case T_SHORT : __ sign_extend_short(rax); break; aoqi@0: case T_INT : /* nothing to do */ break; aoqi@0: case T_DOUBLE : aoqi@0: case T_FLOAT : aoqi@0: // Result is in xmm0 we'll save as needed aoqi@0: break; aoqi@0: case T_ARRAY: // Really a handle aoqi@0: case T_OBJECT: // Really a handle aoqi@0: break; // can't de-handlize until after safepoint check aoqi@0: case T_VOID: break; aoqi@0: case T_LONG: break; aoqi@0: default : ShouldNotReachHere(); aoqi@0: } aoqi@0: aoqi@0: // Switch thread to "native transition" state before reading the synchronization state. aoqi@0: // This additional state is necessary because reading and testing the synchronization aoqi@0: // state is not atomic w.r.t. GC, as this scenario demonstrates: aoqi@0: // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. aoqi@0: // VM thread changes sync state to synchronizing and suspends threads for GC. aoqi@0: // Thread A is resumed to finish this native method, but doesn't block here since it aoqi@0: // didn't see any synchronization is progress, and escapes. aoqi@0: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans); aoqi@0: aoqi@0: if(os::is_MP()) { aoqi@0: if (UseMembar) { aoqi@0: // Force this write out before the read below aoqi@0: __ membar(Assembler::Membar_mask_bits( aoqi@0: Assembler::LoadLoad | Assembler::LoadStore | aoqi@0: Assembler::StoreLoad | Assembler::StoreStore)); aoqi@0: } else { aoqi@0: // Write serialization page so VM thread can do a pseudo remote membar. aoqi@0: // We use the current thread pointer to calculate a thread specific aoqi@0: // offset to write to within the page. This minimizes bus traffic aoqi@0: // due to cache line collision. aoqi@0: __ serialize_memory(r15_thread, rcx); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: Label after_transition; aoqi@0: aoqi@0: // check for safepoint operation in progress and/or pending suspend requests aoqi@0: { aoqi@0: Label Continue; aoqi@0: aoqi@0: __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()), aoqi@0: SafepointSynchronize::_not_synchronized); aoqi@0: aoqi@0: Label L; aoqi@0: __ jcc(Assembler::notEqual, L); aoqi@0: __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0); aoqi@0: __ jcc(Assembler::equal, Continue); aoqi@0: __ bind(L); aoqi@0: aoqi@0: // Don't use call_VM as it will see a possible pending exception and forward it aoqi@0: // and never return here preventing us from clearing _last_native_pc down below. aoqi@0: // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are aoqi@0: // preserved and correspond to the bcp/locals pointers. So we do a runtime call aoqi@0: // by hand. aoqi@0: // aoqi@0: save_native_result(masm, ret_type, stack_slots); aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ mov(r12, rsp); // remember sp aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows aoqi@0: __ andptr(rsp, -16); // align stack as required by ABI aoqi@0: if (!is_critical_native) { aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); aoqi@0: } else { aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); aoqi@0: } aoqi@0: __ mov(rsp, r12); // restore sp aoqi@0: __ reinit_heapbase(); aoqi@0: // Restore any method result value aoqi@0: restore_native_result(masm, ret_type, stack_slots); aoqi@0: aoqi@0: if (is_critical_native) { aoqi@0: // The call above performed the transition to thread_in_Java so aoqi@0: // skip the transition logic below. aoqi@0: __ jmpb(after_transition); aoqi@0: } aoqi@0: aoqi@0: __ bind(Continue); aoqi@0: } aoqi@0: aoqi@0: // change thread state aoqi@0: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java); aoqi@0: __ bind(after_transition); aoqi@0: aoqi@0: Label reguard; aoqi@0: Label reguard_done; aoqi@0: __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled); aoqi@0: __ jcc(Assembler::equal, reguard); aoqi@0: __ bind(reguard_done); aoqi@0: aoqi@0: // native result if any is live aoqi@0: aoqi@0: // Unlock aoqi@0: Label unlock_done; aoqi@0: Label slow_path_unlock; aoqi@0: if (method->is_synchronized()) { aoqi@0: aoqi@0: // Get locked oop from the handle we passed to jni aoqi@0: __ movptr(obj_reg, Address(oop_handle_reg, 0)); aoqi@0: aoqi@0: Label done; aoqi@0: aoqi@0: if (UseBiasedLocking) { aoqi@0: __ biased_locking_exit(obj_reg, old_hdr, done); aoqi@0: } aoqi@0: aoqi@0: // Simple recursive lock? aoqi@0: aoqi@0: __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, done); aoqi@0: aoqi@0: // Must save rax if if it is live now because cmpxchg must use it aoqi@0: if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { aoqi@0: save_native_result(masm, ret_type, stack_slots); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // get address of the stack lock aoqi@0: __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); aoqi@0: // get old displaced header aoqi@0: __ movptr(old_hdr, Address(rax, 0)); aoqi@0: aoqi@0: // Atomic swap old header if oop still contains the stack lock aoqi@0: if (os::is_MP()) { aoqi@0: __ lock(); aoqi@0: } aoqi@0: __ cmpxchgptr(old_hdr, Address(obj_reg, 0)); aoqi@0: __ jcc(Assembler::notEqual, slow_path_unlock); aoqi@0: aoqi@0: // slow path re-enters here aoqi@0: __ bind(unlock_done); aoqi@0: if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { aoqi@0: restore_native_result(masm, ret_type, stack_slots); aoqi@0: } aoqi@0: aoqi@0: __ bind(done); aoqi@0: aoqi@0: } aoqi@0: { aoqi@0: SkipIfEqual skip(masm, &DTraceMethodProbes, false); aoqi@0: save_native_result(masm, ret_type, stack_slots); aoqi@0: __ mov_metadata(c_rarg1, method()); aoqi@0: __ call_VM_leaf( aoqi@0: CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), aoqi@0: r15_thread, c_rarg1); aoqi@0: restore_native_result(masm, ret_type, stack_slots); aoqi@0: } aoqi@0: aoqi@0: __ reset_last_Java_frame(false, true); aoqi@0: aoqi@0: // Unpack oop result aoqi@0: if (ret_type == T_OBJECT || ret_type == T_ARRAY) { aoqi@0: Label L; aoqi@0: __ testptr(rax, rax); aoqi@0: __ jcc(Assembler::zero, L); aoqi@0: __ movptr(rax, Address(rax, 0)); aoqi@0: __ bind(L); aoqi@0: __ verify_oop(rax); aoqi@0: } aoqi@0: aoqi@0: if (!is_critical_native) { aoqi@0: // reset handle block aoqi@0: __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset())); aoqi@0: __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD); aoqi@0: } aoqi@0: aoqi@0: // pop our frame aoqi@0: aoqi@0: __ leave(); aoqi@0: aoqi@0: if (!is_critical_native) { aoqi@0: // Any exception pending? aoqi@0: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::notEqual, exception_pending); aoqi@0: } aoqi@0: aoqi@0: // Return aoqi@0: aoqi@0: __ ret(0); aoqi@0: aoqi@0: // Unexpected paths are out of line and go here aoqi@0: aoqi@0: if (!is_critical_native) { aoqi@0: // forward the exception aoqi@0: __ bind(exception_pending); aoqi@0: aoqi@0: // and forward the exception aoqi@0: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); aoqi@0: } aoqi@0: aoqi@0: // Slow path locking & unlocking aoqi@0: if (method->is_synchronized()) { aoqi@0: aoqi@0: // BEGIN Slow path lock aoqi@0: __ bind(slow_path_lock); aoqi@0: aoqi@0: // has last_Java_frame setup. No exceptions so do vanilla call not call_VM aoqi@0: // args are (oop obj, BasicLock* lock, JavaThread* thread) aoqi@0: aoqi@0: // protect the args we've loaded aoqi@0: save_args(masm, total_c_args, c_arg, out_regs); aoqi@0: aoqi@0: __ mov(c_rarg0, obj_reg); aoqi@0: __ mov(c_rarg1, lock_reg); aoqi@0: __ mov(c_rarg2, r15_thread); aoqi@0: aoqi@0: // Not a leaf but we have last_Java_frame setup as we want aoqi@0: __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); aoqi@0: restore_args(masm, total_c_args, c_arg, out_regs); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: { Label L; aoqi@0: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: __ stop("no pending exception allowed on exit from monitorenter"); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: #endif aoqi@0: __ jmp(lock_done); aoqi@0: aoqi@0: // END Slow path lock aoqi@0: aoqi@0: // BEGIN Slow path unlock aoqi@0: __ bind(slow_path_unlock); aoqi@0: aoqi@0: // If we haven't already saved the native result we must save it now as xmm registers aoqi@0: // are still exposed. aoqi@0: aoqi@0: if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { aoqi@0: save_native_result(masm, ret_type, stack_slots); aoqi@0: } aoqi@0: aoqi@0: __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); aoqi@0: aoqi@0: __ mov(c_rarg0, obj_reg); aoqi@0: __ mov(r12, rsp); // remember sp aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows aoqi@0: __ andptr(rsp, -16); // align stack as required by ABI aoqi@0: aoqi@0: // Save pending exception around call to VM (which contains an EXCEPTION_MARK) aoqi@0: // NOTE that obj_reg == rbx currently aoqi@0: __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset()))); aoqi@0: __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); aoqi@0: aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C))); aoqi@0: __ mov(rsp, r12); // restore sp aoqi@0: __ reinit_heapbase(); aoqi@0: #ifdef ASSERT aoqi@0: { aoqi@0: Label L; aoqi@0: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: #endif /* ASSERT */ aoqi@0: aoqi@0: __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx); aoqi@0: aoqi@0: if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { aoqi@0: restore_native_result(masm, ret_type, stack_slots); aoqi@0: } aoqi@0: __ jmp(unlock_done); aoqi@0: aoqi@0: // END Slow path unlock aoqi@0: aoqi@0: } // synchronized aoqi@0: aoqi@0: // SLOW PATH Reguard the stack if needed aoqi@0: aoqi@0: __ bind(reguard); aoqi@0: save_native_result(masm, ret_type, stack_slots); aoqi@0: __ mov(r12, rsp); // remember sp aoqi@0: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows aoqi@0: __ andptr(rsp, -16); // align stack as required by ABI aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages))); aoqi@0: __ mov(rsp, r12); // restore sp aoqi@0: __ reinit_heapbase(); aoqi@0: restore_native_result(masm, ret_type, stack_slots); aoqi@0: // and continue aoqi@0: __ jmp(reguard_done); aoqi@0: aoqi@0: aoqi@0: aoqi@0: __ flush(); aoqi@0: aoqi@0: nmethod *nm = nmethod::new_native_nmethod(method, aoqi@0: compile_id, aoqi@0: masm->code(), aoqi@0: vep_offset, aoqi@0: frame_complete, aoqi@0: stack_slots / VMRegImpl::slots_per_word, aoqi@0: (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), aoqi@0: in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), aoqi@0: oop_maps); aoqi@0: aoqi@0: if (is_critical_native) { aoqi@0: nm->set_lazy_critical_native(true); aoqi@0: } aoqi@0: aoqi@0: return nm; aoqi@0: aoqi@0: } aoqi@0: aoqi@0: #ifdef HAVE_DTRACE_H aoqi@0: // --------------------------------------------------------------------------- aoqi@0: // Generate a dtrace nmethod for a given signature. The method takes arguments aoqi@0: // in the Java compiled code convention, marshals them to the native aoqi@0: // abi and then leaves nops at the position you would expect to call a native aoqi@0: // function. When the probe is enabled the nops are replaced with a trap aoqi@0: // instruction that dtrace inserts and the trace will cause a notification aoqi@0: // to dtrace. aoqi@0: // aoqi@0: // The probes are only able to take primitive types and java/lang/String as aoqi@0: // arguments. No other java types are allowed. Strings are converted to utf8 aoqi@0: // strings so that from dtrace point of view java strings are converted to C aoqi@0: // strings. There is an arbitrary fixed limit on the total space that a method aoqi@0: // can use for converting the strings. (256 chars per string in the signature). aoqi@0: // So any java string larger then this is truncated. aoqi@0: aoqi@0: static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; aoqi@0: static bool offsets_initialized = false; aoqi@0: aoqi@0: aoqi@0: nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm, aoqi@0: methodHandle method) { aoqi@0: aoqi@0: aoqi@0: // generate_dtrace_nmethod is guarded by a mutex so we are sure to aoqi@0: // be single threaded in this method. aoqi@0: assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); aoqi@0: aoqi@0: if (!offsets_initialized) { aoqi@0: fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize; aoqi@0: fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize; aoqi@0: fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize; aoqi@0: fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize; aoqi@0: fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize; aoqi@0: fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize; aoqi@0: aoqi@0: fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize; aoqi@0: fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize; aoqi@0: fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize; aoqi@0: fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize; aoqi@0: fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize; aoqi@0: fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize; aoqi@0: fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize; aoqi@0: fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize; aoqi@0: aoqi@0: offsets_initialized = true; aoqi@0: } aoqi@0: // Fill in the signature array, for the calling-convention call. aoqi@0: int total_args_passed = method->size_of_parameters(); aoqi@0: aoqi@0: BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); aoqi@0: VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); aoqi@0: aoqi@0: // The signature we are going to use for the trap that dtrace will see aoqi@0: // java/lang/String is converted. We drop "this" and any other object aoqi@0: // is converted to NULL. (A one-slot java/lang/Long object reference aoqi@0: // is converted to a two-slot long, which is why we double the allocation). aoqi@0: BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); aoqi@0: VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); aoqi@0: aoqi@0: int i=0; aoqi@0: int total_strings = 0; aoqi@0: int first_arg_to_pass = 0; aoqi@0: int total_c_args = 0; aoqi@0: aoqi@0: // Skip the receiver as dtrace doesn't want to see it aoqi@0: if( !method->is_static() ) { aoqi@0: in_sig_bt[i++] = T_OBJECT; aoqi@0: first_arg_to_pass = 1; aoqi@0: } aoqi@0: aoqi@0: // We need to convert the java args to where a native (non-jni) function aoqi@0: // would expect them. To figure out where they go we convert the java aoqi@0: // signature to a C signature. aoqi@0: aoqi@0: SignatureStream ss(method->signature()); aoqi@0: for ( ; !ss.at_return_type(); ss.next()) { aoqi@0: BasicType bt = ss.type(); aoqi@0: in_sig_bt[i++] = bt; // Collect remaining bits of signature aoqi@0: out_sig_bt[total_c_args++] = bt; aoqi@0: if( bt == T_OBJECT) { aoqi@0: Symbol* s = ss.as_symbol_or_null(); // symbol is created aoqi@0: if (s == vmSymbols::java_lang_String()) { aoqi@0: total_strings++; aoqi@0: out_sig_bt[total_c_args-1] = T_ADDRESS; aoqi@0: } else if (s == vmSymbols::java_lang_Boolean() || aoqi@0: s == vmSymbols::java_lang_Character() || aoqi@0: s == vmSymbols::java_lang_Byte() || aoqi@0: s == vmSymbols::java_lang_Short() || aoqi@0: s == vmSymbols::java_lang_Integer() || aoqi@0: s == vmSymbols::java_lang_Float()) { aoqi@0: out_sig_bt[total_c_args-1] = T_INT; aoqi@0: } else if (s == vmSymbols::java_lang_Long() || aoqi@0: s == vmSymbols::java_lang_Double()) { aoqi@0: out_sig_bt[total_c_args-1] = T_LONG; aoqi@0: out_sig_bt[total_c_args++] = T_VOID; aoqi@0: } aoqi@0: } else if ( bt == T_LONG || bt == T_DOUBLE ) { aoqi@0: in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots aoqi@0: // We convert double to long aoqi@0: out_sig_bt[total_c_args-1] = T_LONG; aoqi@0: out_sig_bt[total_c_args++] = T_VOID; aoqi@0: } else if ( bt == T_FLOAT) { aoqi@0: // We convert float to int aoqi@0: out_sig_bt[total_c_args-1] = T_INT; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: assert(i==total_args_passed, "validly parsed signature"); aoqi@0: aoqi@0: // Now get the compiled-Java layout as input arguments aoqi@0: int comp_args_on_stack; aoqi@0: comp_args_on_stack = SharedRuntime::java_calling_convention( aoqi@0: in_sig_bt, in_regs, total_args_passed, false); aoqi@0: aoqi@0: // Now figure out where the args must be stored and how much stack space aoqi@0: // they require (neglecting out_preserve_stack_slots but space for storing aoqi@0: // the 1st six register arguments). It's weird see int_stk_helper. aoqi@0: aoqi@0: int out_arg_slots; aoqi@0: out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); aoqi@0: aoqi@0: // Calculate the total number of stack slots we will need. aoqi@0: aoqi@0: // First count the abi requirement plus all of the outgoing args aoqi@0: int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; aoqi@0: aoqi@0: // Now space for the string(s) we must convert aoqi@0: int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1); aoqi@0: for (i = 0; i < total_strings ; i++) { aoqi@0: string_locs[i] = stack_slots; aoqi@0: stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size; aoqi@0: } aoqi@0: aoqi@0: // Plus the temps we might need to juggle register args aoqi@0: // regs take two slots each aoqi@0: stack_slots += (Argument::n_int_register_parameters_c + aoqi@0: Argument::n_float_register_parameters_c) * 2; aoqi@0: aoqi@0: aoqi@0: // + 4 for return address (which we own) and saved rbp, aoqi@0: aoqi@0: stack_slots += 4; aoqi@0: aoqi@0: // Ok The space we have allocated will look like: aoqi@0: // aoqi@0: // aoqi@0: // FP-> | | aoqi@0: // |---------------------| aoqi@0: // | string[n] | aoqi@0: // |---------------------| <- string_locs[n] aoqi@0: // | string[n-1] | aoqi@0: // |---------------------| <- string_locs[n-1] aoqi@0: // | ... | aoqi@0: // | ... | aoqi@0: // |---------------------| <- string_locs[1] aoqi@0: // | string[0] | aoqi@0: // |---------------------| <- string_locs[0] aoqi@0: // | outbound memory | aoqi@0: // | based arguments | aoqi@0: // | | aoqi@0: // |---------------------| aoqi@0: // | | aoqi@0: // SP-> | out_preserved_slots | aoqi@0: // aoqi@0: // aoqi@0: aoqi@0: // Now compute actual number of stack words we need rounding to make aoqi@0: // stack properly aligned. aoqi@0: stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); aoqi@0: aoqi@0: int stack_size = stack_slots * VMRegImpl::stack_slot_size; aoqi@0: aoqi@0: intptr_t start = (intptr_t)__ pc(); aoqi@0: aoqi@0: // First thing make an ic check to see if we should even be here aoqi@0: aoqi@0: // We are free to use all registers as temps without saving them and aoqi@0: // restoring them except rbp. rbp, is the only callee save register aoqi@0: // as far as the interpreter and the compiler(s) are concerned. aoqi@0: aoqi@0: const Register ic_reg = rax; aoqi@0: const Register receiver = rcx; aoqi@0: Label hit; aoqi@0: Label exception_pending; aoqi@0: aoqi@0: aoqi@0: __ verify_oop(receiver); aoqi@0: __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes())); aoqi@0: __ jcc(Assembler::equal, hit); aoqi@0: aoqi@0: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); aoqi@0: aoqi@0: // verified entry must be aligned for code patching. aoqi@0: // and the first 5 bytes must be in the same cache line aoqi@0: // if we align at 8 then we will be sure 5 bytes are in the same line aoqi@0: __ align(8); aoqi@0: aoqi@0: __ bind(hit); aoqi@0: aoqi@0: int vep_offset = ((intptr_t)__ pc()) - start; aoqi@0: aoqi@0: aoqi@0: // The instruction at the verified entry point must be 5 bytes or longer aoqi@0: // because it can be patched on the fly by make_non_entrant. The stack bang aoqi@0: // instruction fits that requirement. aoqi@0: aoqi@0: // Generate stack overflow check aoqi@0: aoqi@0: if (UseStackBanging) { aoqi@0: if (stack_size <= StackShadowPages*os::vm_page_size()) { aoqi@0: __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); aoqi@0: } else { aoqi@0: __ movl(rax, stack_size); aoqi@0: __ bang_stack_size(rax, rbx); aoqi@0: } aoqi@0: } else { aoqi@0: // need a 5 byte instruction to allow MT safe patching to non-entrant aoqi@0: __ fat_nop(); aoqi@0: } aoqi@0: aoqi@0: assert(((uintptr_t)__ pc() - start - vep_offset) >= 5, aoqi@0: "valid size for make_non_entrant"); aoqi@0: aoqi@0: // Generate a new frame for the wrapper. aoqi@0: __ enter(); aoqi@0: aoqi@0: // -4 because return address is already present and so is saved rbp, aoqi@0: if (stack_size - 2*wordSize != 0) { aoqi@0: __ subq(rsp, stack_size - 2*wordSize); aoqi@0: } aoqi@0: aoqi@0: // Frame is now completed as far a size and linkage. aoqi@0: aoqi@0: int frame_complete = ((intptr_t)__ pc()) - start; aoqi@0: aoqi@0: int c_arg, j_arg; aoqi@0: aoqi@0: // State of input register args aoqi@0: aoqi@0: bool live[ConcreteRegisterImpl::number_of_registers]; aoqi@0: aoqi@0: live[j_rarg0->as_VMReg()->value()] = false; aoqi@0: live[j_rarg1->as_VMReg()->value()] = false; aoqi@0: live[j_rarg2->as_VMReg()->value()] = false; aoqi@0: live[j_rarg3->as_VMReg()->value()] = false; aoqi@0: live[j_rarg4->as_VMReg()->value()] = false; aoqi@0: live[j_rarg5->as_VMReg()->value()] = false; aoqi@0: aoqi@0: live[j_farg0->as_VMReg()->value()] = false; aoqi@0: live[j_farg1->as_VMReg()->value()] = false; aoqi@0: live[j_farg2->as_VMReg()->value()] = false; aoqi@0: live[j_farg3->as_VMReg()->value()] = false; aoqi@0: live[j_farg4->as_VMReg()->value()] = false; aoqi@0: live[j_farg5->as_VMReg()->value()] = false; aoqi@0: live[j_farg6->as_VMReg()->value()] = false; aoqi@0: live[j_farg7->as_VMReg()->value()] = false; aoqi@0: aoqi@0: aoqi@0: bool rax_is_zero = false; aoqi@0: aoqi@0: // All args (except strings) destined for the stack are moved first aoqi@0: for (j_arg = first_arg_to_pass, c_arg = 0 ; aoqi@0: j_arg < total_args_passed ; j_arg++, c_arg++ ) { aoqi@0: VMRegPair src = in_regs[j_arg]; aoqi@0: VMRegPair dst = out_regs[c_arg]; aoqi@0: aoqi@0: // Get the real reg value or a dummy (rsp) aoqi@0: aoqi@0: int src_reg = src.first()->is_reg() ? aoqi@0: src.first()->value() : aoqi@0: rsp->as_VMReg()->value(); aoqi@0: aoqi@0: bool useless = in_sig_bt[j_arg] == T_ARRAY || aoqi@0: (in_sig_bt[j_arg] == T_OBJECT && aoqi@0: out_sig_bt[c_arg] != T_INT && aoqi@0: out_sig_bt[c_arg] != T_ADDRESS && aoqi@0: out_sig_bt[c_arg] != T_LONG); aoqi@0: aoqi@0: live[src_reg] = !useless; aoqi@0: aoqi@0: if (dst.first()->is_stack()) { aoqi@0: aoqi@0: // Even though a string arg in a register is still live after this loop aoqi@0: // after the string conversion loop (next) it will be dead so we take aoqi@0: // advantage of that now for simpler code to manage live. aoqi@0: aoqi@0: live[src_reg] = false; aoqi@0: switch (in_sig_bt[j_arg]) { aoqi@0: aoqi@0: case T_ARRAY: aoqi@0: case T_OBJECT: aoqi@0: { aoqi@0: Address stack_dst(rsp, reg2offset_out(dst.first())); aoqi@0: aoqi@0: if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { aoqi@0: // need to unbox a one-word value aoqi@0: Register in_reg = rax; aoqi@0: if ( src.first()->is_reg() ) { aoqi@0: in_reg = src.first()->as_Register(); aoqi@0: } else { aoqi@0: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); aoqi@0: rax_is_zero = false; aoqi@0: } aoqi@0: Label skipUnbox; aoqi@0: __ movptr(Address(rsp, reg2offset_out(dst.first())), aoqi@0: (int32_t)NULL_WORD); aoqi@0: __ testq(in_reg, in_reg); aoqi@0: __ jcc(Assembler::zero, skipUnbox); aoqi@0: aoqi@0: BasicType bt = out_sig_bt[c_arg]; aoqi@0: int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); aoqi@0: Address src1(in_reg, box_offset); aoqi@0: if ( bt == T_LONG ) { aoqi@0: __ movq(in_reg, src1); aoqi@0: __ movq(stack_dst, in_reg); aoqi@0: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); aoqi@0: ++c_arg; // skip over T_VOID to keep the loop indices in sync aoqi@0: } else { aoqi@0: __ movl(in_reg, src1); aoqi@0: __ movl(stack_dst, in_reg); aoqi@0: } aoqi@0: aoqi@0: __ bind(skipUnbox); aoqi@0: } else if (out_sig_bt[c_arg] != T_ADDRESS) { aoqi@0: // Convert the arg to NULL aoqi@0: if (!rax_is_zero) { aoqi@0: __ xorq(rax, rax); aoqi@0: rax_is_zero = true; aoqi@0: } aoqi@0: __ movq(stack_dst, rax); aoqi@0: } aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case T_VOID: aoqi@0: break; aoqi@0: aoqi@0: case T_FLOAT: aoqi@0: // This does the right thing since we know it is destined for the aoqi@0: // stack aoqi@0: float_move(masm, src, dst); aoqi@0: break; aoqi@0: aoqi@0: case T_DOUBLE: aoqi@0: // This does the right thing since we know it is destined for the aoqi@0: // stack aoqi@0: double_move(masm, src, dst); aoqi@0: break; aoqi@0: aoqi@0: case T_LONG : aoqi@0: long_move(masm, src, dst); aoqi@0: break; aoqi@0: aoqi@0: case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); aoqi@0: aoqi@0: default: aoqi@0: move32_64(masm, src, dst); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: } aoqi@0: aoqi@0: // If we have any strings we must store any register based arg to the stack aoqi@0: // This includes any still live xmm registers too. aoqi@0: aoqi@0: int sid = 0; aoqi@0: aoqi@0: if (total_strings > 0 ) { aoqi@0: for (j_arg = first_arg_to_pass, c_arg = 0 ; aoqi@0: j_arg < total_args_passed ; j_arg++, c_arg++ ) { aoqi@0: VMRegPair src = in_regs[j_arg]; aoqi@0: VMRegPair dst = out_regs[c_arg]; aoqi@0: aoqi@0: if (src.first()->is_reg()) { aoqi@0: Address src_tmp(rbp, fp_offset[src.first()->value()]); aoqi@0: aoqi@0: // string oops were left untouched by the previous loop even if the aoqi@0: // eventual (converted) arg is destined for the stack so park them aoqi@0: // away now (except for first) aoqi@0: aoqi@0: if (out_sig_bt[c_arg] == T_ADDRESS) { aoqi@0: Address utf8_addr = Address( aoqi@0: rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); aoqi@0: if (sid != 1) { aoqi@0: // The first string arg won't be killed until after the utf8 aoqi@0: // conversion aoqi@0: __ movq(utf8_addr, src.first()->as_Register()); aoqi@0: } aoqi@0: } else if (dst.first()->is_reg()) { aoqi@0: if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) { aoqi@0: aoqi@0: // Convert the xmm register to an int and store it in the reserved aoqi@0: // location for the eventual c register arg aoqi@0: XMMRegister f = src.first()->as_XMMRegister(); aoqi@0: if (in_sig_bt[j_arg] == T_FLOAT) { aoqi@0: __ movflt(src_tmp, f); aoqi@0: } else { aoqi@0: __ movdbl(src_tmp, f); aoqi@0: } aoqi@0: } else { aoqi@0: // If the arg is an oop type we don't support don't bother to store aoqi@0: // it remember string was handled above. aoqi@0: bool useless = in_sig_bt[j_arg] == T_ARRAY || aoqi@0: (in_sig_bt[j_arg] == T_OBJECT && aoqi@0: out_sig_bt[c_arg] != T_INT && aoqi@0: out_sig_bt[c_arg] != T_LONG); aoqi@0: aoqi@0: if (!useless) { aoqi@0: __ movq(src_tmp, src.first()->as_Register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { aoqi@0: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); aoqi@0: ++c_arg; // skip over T_VOID to keep the loop indices in sync aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Now that the volatile registers are safe, convert all the strings aoqi@0: sid = 0; aoqi@0: aoqi@0: for (j_arg = first_arg_to_pass, c_arg = 0 ; aoqi@0: j_arg < total_args_passed ; j_arg++, c_arg++ ) { aoqi@0: if (out_sig_bt[c_arg] == T_ADDRESS) { aoqi@0: // It's a string aoqi@0: Address utf8_addr = Address( aoqi@0: rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); aoqi@0: // The first string we find might still be in the original java arg aoqi@0: // register aoqi@0: aoqi@0: VMReg src = in_regs[j_arg].first(); aoqi@0: aoqi@0: // We will need to eventually save the final argument to the trap aoqi@0: // in the von-volatile location dedicated to src. This is the offset aoqi@0: // from fp we will use. aoqi@0: int src_off = src->is_reg() ? aoqi@0: fp_offset[src->value()] : reg2offset_in(src); aoqi@0: aoqi@0: // This is where the argument will eventually reside aoqi@0: VMRegPair dst = out_regs[c_arg]; aoqi@0: aoqi@0: if (src->is_reg()) { aoqi@0: if (sid == 1) { aoqi@0: __ movq(c_rarg0, src->as_Register()); aoqi@0: } else { aoqi@0: __ movq(c_rarg0, utf8_addr); aoqi@0: } aoqi@0: } else { aoqi@0: // arg is still in the original location aoqi@0: __ movq(c_rarg0, Address(rbp, reg2offset_in(src))); aoqi@0: } aoqi@0: Label done, convert; aoqi@0: aoqi@0: // see if the oop is NULL aoqi@0: __ testq(c_rarg0, c_rarg0); aoqi@0: __ jcc(Assembler::notEqual, convert); aoqi@0: aoqi@0: if (dst.first()->is_reg()) { aoqi@0: // Save the ptr to utf string in the origina src loc or the tmp aoqi@0: // dedicated to it aoqi@0: __ movq(Address(rbp, src_off), c_rarg0); aoqi@0: } else { aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0); aoqi@0: } aoqi@0: __ jmp(done); aoqi@0: aoqi@0: __ bind(convert); aoqi@0: aoqi@0: __ lea(c_rarg1, utf8_addr); aoqi@0: if (dst.first()->is_reg()) { aoqi@0: __ movq(Address(rbp, src_off), c_rarg1); aoqi@0: } else { aoqi@0: __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1); aoqi@0: } aoqi@0: // And do the conversion aoqi@0: __ call(RuntimeAddress( aoqi@0: CAST_FROM_FN_PTR(address, SharedRuntime::get_utf))); aoqi@0: aoqi@0: __ bind(done); aoqi@0: } aoqi@0: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { aoqi@0: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); aoqi@0: ++c_arg; // skip over T_VOID to keep the loop indices in sync aoqi@0: } aoqi@0: } aoqi@0: // The get_utf call killed all the c_arg registers aoqi@0: live[c_rarg0->as_VMReg()->value()] = false; aoqi@0: live[c_rarg1->as_VMReg()->value()] = false; aoqi@0: live[c_rarg2->as_VMReg()->value()] = false; aoqi@0: live[c_rarg3->as_VMReg()->value()] = false; aoqi@0: live[c_rarg4->as_VMReg()->value()] = false; aoqi@0: live[c_rarg5->as_VMReg()->value()] = false; aoqi@0: aoqi@0: live[c_farg0->as_VMReg()->value()] = false; aoqi@0: live[c_farg1->as_VMReg()->value()] = false; aoqi@0: live[c_farg2->as_VMReg()->value()] = false; aoqi@0: live[c_farg3->as_VMReg()->value()] = false; aoqi@0: live[c_farg4->as_VMReg()->value()] = false; aoqi@0: live[c_farg5->as_VMReg()->value()] = false; aoqi@0: live[c_farg6->as_VMReg()->value()] = false; aoqi@0: live[c_farg7->as_VMReg()->value()] = false; aoqi@0: } aoqi@0: aoqi@0: // Now we can finally move the register args to their desired locations aoqi@0: aoqi@0: rax_is_zero = false; aoqi@0: aoqi@0: for (j_arg = first_arg_to_pass, c_arg = 0 ; aoqi@0: j_arg < total_args_passed ; j_arg++, c_arg++ ) { aoqi@0: aoqi@0: VMRegPair src = in_regs[j_arg]; aoqi@0: VMRegPair dst = out_regs[c_arg]; aoqi@0: aoqi@0: // Only need to look for args destined for the interger registers (since we aoqi@0: // convert float/double args to look like int/long outbound) aoqi@0: if (dst.first()->is_reg()) { aoqi@0: Register r = dst.first()->as_Register(); aoqi@0: aoqi@0: // Check if the java arg is unsupported and thereofre useless aoqi@0: bool useless = in_sig_bt[j_arg] == T_ARRAY || aoqi@0: (in_sig_bt[j_arg] == T_OBJECT && aoqi@0: out_sig_bt[c_arg] != T_INT && aoqi@0: out_sig_bt[c_arg] != T_ADDRESS && aoqi@0: out_sig_bt[c_arg] != T_LONG); aoqi@0: aoqi@0: aoqi@0: // If we're going to kill an existing arg save it first aoqi@0: if (live[dst.first()->value()]) { aoqi@0: // you can't kill yourself aoqi@0: if (src.first() != dst.first()) { aoqi@0: __ movq(Address(rbp, fp_offset[dst.first()->value()]), r); aoqi@0: } aoqi@0: } aoqi@0: if (src.first()->is_reg()) { aoqi@0: if (live[src.first()->value()] ) { aoqi@0: if (in_sig_bt[j_arg] == T_FLOAT) { aoqi@0: __ movdl(r, src.first()->as_XMMRegister()); aoqi@0: } else if (in_sig_bt[j_arg] == T_DOUBLE) { aoqi@0: __ movdq(r, src.first()->as_XMMRegister()); aoqi@0: } else if (r != src.first()->as_Register()) { aoqi@0: if (!useless) { aoqi@0: __ movq(r, src.first()->as_Register()); aoqi@0: } aoqi@0: } aoqi@0: } else { aoqi@0: // If the arg is an oop type we don't support don't bother to store aoqi@0: // it aoqi@0: if (!useless) { aoqi@0: if (in_sig_bt[j_arg] == T_DOUBLE || aoqi@0: in_sig_bt[j_arg] == T_LONG || aoqi@0: in_sig_bt[j_arg] == T_OBJECT ) { aoqi@0: __ movq(r, Address(rbp, fp_offset[src.first()->value()])); aoqi@0: } else { aoqi@0: __ movl(r, Address(rbp, fp_offset[src.first()->value()])); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: live[src.first()->value()] = false; aoqi@0: } else if (!useless) { aoqi@0: // full sized move even for int should be ok aoqi@0: __ movq(r, Address(rbp, reg2offset_in(src.first()))); aoqi@0: } aoqi@0: aoqi@0: // At this point r has the original java arg in the final location aoqi@0: // (assuming it wasn't useless). If the java arg was an oop aoqi@0: // we have a bit more to do aoqi@0: aoqi@0: if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) { aoqi@0: if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { aoqi@0: // need to unbox a one-word value aoqi@0: Label skip; aoqi@0: __ testq(r, r); aoqi@0: __ jcc(Assembler::equal, skip); aoqi@0: BasicType bt = out_sig_bt[c_arg]; aoqi@0: int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); aoqi@0: Address src1(r, box_offset); aoqi@0: if ( bt == T_LONG ) { aoqi@0: __ movq(r, src1); aoqi@0: } else { aoqi@0: __ movl(r, src1); aoqi@0: } aoqi@0: __ bind(skip); aoqi@0: aoqi@0: } else if (out_sig_bt[c_arg] != T_ADDRESS) { aoqi@0: // Convert the arg to NULL aoqi@0: __ xorq(r, r); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // dst can longer be holding an input value aoqi@0: live[dst.first()->value()] = false; aoqi@0: } aoqi@0: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { aoqi@0: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); aoqi@0: ++c_arg; // skip over T_VOID to keep the loop indices in sync aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Ok now we are done. Need to place the nop that dtrace wants in order to aoqi@0: // patch in the trap aoqi@0: int patch_offset = ((intptr_t)__ pc()) - start; aoqi@0: aoqi@0: __ nop(); aoqi@0: aoqi@0: aoqi@0: // Return aoqi@0: aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ flush(); aoqi@0: aoqi@0: nmethod *nm = nmethod::new_dtrace_nmethod( aoqi@0: method, masm->code(), vep_offset, patch_offset, frame_complete, aoqi@0: stack_slots / VMRegImpl::slots_per_word); aoqi@0: return nm; aoqi@0: aoqi@0: } aoqi@0: aoqi@0: #endif // HAVE_DTRACE_H aoqi@0: aoqi@0: // this function returns the adjust size (in number of words) to a c2i adapter aoqi@0: // activation for use during deoptimization aoqi@0: int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) { aoqi@0: return (callee_locals - callee_parameters) * Interpreter::stackElementWords; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: uint SharedRuntime::out_preserve_stack_slots() { aoqi@0: return 0; aoqi@0: } aoqi@0: aoqi@0: //------------------------------generate_deopt_blob---------------------------- aoqi@0: void SharedRuntime::generate_deopt_blob() { aoqi@0: // Allocate space for the code aoqi@0: ResourceMark rm; aoqi@0: // Setup code generation tools aoqi@0: CodeBuffer buffer("deopt_blob", 2048, 1024); aoqi@0: MacroAssembler* masm = new MacroAssembler(&buffer); aoqi@0: int frame_size_in_words; aoqi@0: OopMap* map = NULL; aoqi@0: OopMapSet *oop_maps = new OopMapSet(); aoqi@0: aoqi@0: // ------------- aoqi@0: // This code enters when returning to a de-optimized nmethod. A return aoqi@0: // address has been pushed on the the stack, and return values are in aoqi@0: // registers. aoqi@0: // If we are doing a normal deopt then we were called from the patched aoqi@0: // nmethod from the point we returned to the nmethod. So the return aoqi@0: // address on the stack is wrong by NativeCall::instruction_size aoqi@0: // We will adjust the value so it looks like we have the original return aoqi@0: // address on the stack (like when we eagerly deoptimized). aoqi@0: // In the case of an exception pending when deoptimizing, we enter aoqi@0: // with a return address on the stack that points after the call we patched aoqi@0: // into the exception handler. We have the following register state from, aoqi@0: // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). aoqi@0: // rax: exception oop aoqi@0: // rbx: exception handler aoqi@0: // rdx: throwing pc aoqi@0: // So in this case we simply jam rdx into the useless return address and aoqi@0: // the stack looks just like we want. aoqi@0: // aoqi@0: // At this point we need to de-opt. We save the argument return aoqi@0: // registers. We call the first C routine, fetch_unroll_info(). This aoqi@0: // routine captures the return values and returns a structure which aoqi@0: // describes the current frame size and the sizes of all replacement frames. aoqi@0: // The current frame is compiled code and may contain many inlined aoqi@0: // functions, each with their own JVM state. We pop the current frame, then aoqi@0: // push all the new frames. Then we call the C routine unpack_frames() to aoqi@0: // populate these frames. Finally unpack_frames() returns us the new target aoqi@0: // address. Notice that callee-save registers are BLOWN here; they have aoqi@0: // already been captured in the vframeArray at the time the return PC was aoqi@0: // patched. aoqi@0: address start = __ pc(); aoqi@0: Label cont; aoqi@0: aoqi@0: // Prolog for non exception case! aoqi@0: aoqi@0: // Save everything in sight. aoqi@0: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); aoqi@0: aoqi@0: // Normal deoptimization. Save exec mode for unpack_frames. aoqi@0: __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved aoqi@0: __ jmp(cont); aoqi@0: aoqi@0: int reexecute_offset = __ pc() - start; aoqi@0: aoqi@0: // Reexecute case aoqi@0: // return address is the pc describes what bci to do re-execute at aoqi@0: aoqi@0: // No need to update map as each call to save_live_registers will produce identical oopmap aoqi@0: (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); aoqi@0: aoqi@0: __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved aoqi@0: __ jmp(cont); aoqi@0: aoqi@0: int exception_offset = __ pc() - start; aoqi@0: aoqi@0: // Prolog for exception case aoqi@0: aoqi@0: // all registers are dead at this entry point, except for rax, and aoqi@0: // rdx which contain the exception oop and exception pc aoqi@0: // respectively. Set them in TLS and fall thru to the aoqi@0: // unpack_with_exception_in_tls entry point. aoqi@0: aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax); aoqi@0: aoqi@0: int exception_in_tls_offset = __ pc() - start; aoqi@0: aoqi@0: // new implementation because exception oop is now passed in JavaThread aoqi@0: aoqi@0: // Prolog for exception case aoqi@0: // All registers must be preserved because they might be used by LinearScan aoqi@0: // Exceptiop oop and throwing PC are passed in JavaThread aoqi@0: // tos: stack at point of call to method that threw the exception (i.e. only aoqi@0: // args are on the stack, no return address) aoqi@0: aoqi@0: // make room on stack for the return address aoqi@0: // It will be patched later with the throwing pc. The correct value is not aoqi@0: // available now because loading it from memory would destroy registers. aoqi@0: __ push(0); aoqi@0: aoqi@0: // Save everything in sight. aoqi@0: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); aoqi@0: aoqi@0: // Now it is safe to overwrite any register aoqi@0: aoqi@0: // Deopt during an exception. Save exec mode for unpack_frames. aoqi@0: __ movl(r14, Deoptimization::Unpack_exception); // callee-saved aoqi@0: aoqi@0: // load throwing pc from JavaThread and patch it as the return address aoqi@0: // of the current frame. Then clear the field in JavaThread aoqi@0: aoqi@0: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); aoqi@0: __ movptr(Address(rbp, wordSize), rdx); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // verify that there is really an exception oop in JavaThread aoqi@0: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); aoqi@0: __ verify_oop(rax); aoqi@0: aoqi@0: // verify that there is no pending exception aoqi@0: Label no_pending_exception; aoqi@0: __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); aoqi@0: __ testptr(rax, rax); aoqi@0: __ jcc(Assembler::zero, no_pending_exception); aoqi@0: __ stop("must not have pending exception here"); aoqi@0: __ bind(no_pending_exception); aoqi@0: #endif aoqi@0: aoqi@0: __ bind(cont); aoqi@0: aoqi@0: // Call C code. Need thread and this frame, but NOT official VM entry aoqi@0: // crud. We cannot block on this call, no GC can happen. aoqi@0: // aoqi@0: // UnrollBlock* fetch_unroll_info(JavaThread* thread) aoqi@0: aoqi@0: // fetch_unroll_info needs to call last_java_frame(). aoqi@0: aoqi@0: __ set_last_Java_frame(noreg, noreg, NULL); aoqi@0: #ifdef ASSERT aoqi@0: { Label L; aoqi@0: __ cmpptr(Address(r15_thread, aoqi@0: JavaThread::last_Java_fp_offset()), aoqi@0: (int32_t)0); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: #endif // ASSERT aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); aoqi@0: aoqi@0: // Need to have an oopmap that tells fetch_unroll_info where to aoqi@0: // find any register it might need. aoqi@0: oop_maps->add_gc_map(__ pc() - start, map); aoqi@0: aoqi@0: __ reset_last_Java_frame(false, false); aoqi@0: aoqi@0: // Load UnrollBlock* into rdi aoqi@0: __ mov(rdi, rax); aoqi@0: aoqi@0: Label noException; aoqi@0: __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending? aoqi@0: __ jcc(Assembler::notEqual, noException); aoqi@0: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); aoqi@0: // QQQ this is useless it was NULL above aoqi@0: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); aoqi@0: aoqi@0: __ verify_oop(rax); aoqi@0: aoqi@0: // Overwrite the result registers with the exception results. aoqi@0: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); aoqi@0: // I think this is useless aoqi@0: __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx); aoqi@0: aoqi@0: __ bind(noException); aoqi@0: aoqi@0: // Only register save data is on the stack. aoqi@0: // Now restore the result registers. Everything else is either dead aoqi@0: // or captured in the vframeArray. aoqi@0: RegisterSaver::restore_result_registers(masm); aoqi@0: aoqi@0: // All of the register save area has been popped of the stack. Only the aoqi@0: // return address remains. aoqi@0: aoqi@0: // Pop all the frames we must move/replace. aoqi@0: // aoqi@0: // Frame picture (youngest to oldest) aoqi@0: // 1: self-frame (no frame link) aoqi@0: // 2: deopting frame (no frame link) aoqi@0: // 3: caller of deopting frame (could be compiled/interpreted). aoqi@0: // aoqi@0: // Note: by leaving the return address of self-frame on the stack aoqi@0: // and using the size of frame 2 to adjust the stack aoqi@0: // when we are done the return to frame 3 will still be on the stack. aoqi@0: aoqi@0: // Pop deoptimized frame aoqi@0: __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); aoqi@0: __ addptr(rsp, rcx); aoqi@0: aoqi@0: // rsp should be pointing at the return address to the caller (3) aoqi@0: aoqi@0: // Pick up the initial fp we should save aoqi@0: // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) aoqi@0: __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // Compilers generate code that bang the stack by as much as the aoqi@0: // interpreter would need. So this stack banging should never aoqi@0: // trigger a fault. Verify that it does not on non product builds. aoqi@0: if (UseStackBanging) { aoqi@0: __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); aoqi@0: __ bang_stack_size(rbx, rcx); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // Load address of array of frame pcs into rcx aoqi@0: __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); aoqi@0: aoqi@0: // Trash the old pc aoqi@0: __ addptr(rsp, wordSize); aoqi@0: aoqi@0: // Load address of array of frame sizes into rsi aoqi@0: __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); aoqi@0: aoqi@0: // Load counter into rdx aoqi@0: __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); aoqi@0: aoqi@0: // Now adjust the caller's stack to make up for the extra locals aoqi@0: // but record the original sp so that we can save it in the skeletal interpreter aoqi@0: // frame and the stack walking of interpreter_sender will get the unextended sp aoqi@0: // value and not the "real" sp value. aoqi@0: aoqi@0: const Register sender_sp = r8; aoqi@0: aoqi@0: __ mov(sender_sp, rsp); aoqi@0: __ movl(rbx, Address(rdi, aoqi@0: Deoptimization::UnrollBlock:: aoqi@0: caller_adjustment_offset_in_bytes())); aoqi@0: __ subptr(rsp, rbx); aoqi@0: aoqi@0: // Push interpreter frames in a loop aoqi@0: Label loop; aoqi@0: __ bind(loop); aoqi@0: __ movptr(rbx, Address(rsi, 0)); // Load frame size aoqi@0: #ifdef CC_INTERP aoqi@0: __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and aoqi@0: #ifdef ASSERT aoqi@0: __ push(0xDEADDEAD); // Make a recognizable pattern aoqi@0: __ push(0xDEADDEAD); aoqi@0: #else /* ASSERT */ aoqi@0: __ subptr(rsp, 2*wordSize); // skip the "static long no_param" aoqi@0: #endif /* ASSERT */ aoqi@0: #else aoqi@0: __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand aoqi@0: #endif // CC_INTERP aoqi@0: __ pushptr(Address(rcx, 0)); // Save return address aoqi@0: __ enter(); // Save old & set new ebp aoqi@0: __ subptr(rsp, rbx); // Prolog aoqi@0: #ifdef CC_INTERP aoqi@0: __ movptr(Address(rbp, aoqi@0: -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), aoqi@0: sender_sp); // Make it walkable aoqi@0: #else /* CC_INTERP */ aoqi@0: // This value is corrected by layout_activation_impl aoqi@0: __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); aoqi@0: __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable aoqi@0: #endif /* CC_INTERP */ aoqi@0: __ mov(sender_sp, rsp); // Pass sender_sp to next frame aoqi@0: __ addptr(rsi, wordSize); // Bump array pointer (sizes) aoqi@0: __ addptr(rcx, wordSize); // Bump array pointer (pcs) aoqi@0: __ decrementl(rdx); // Decrement counter aoqi@0: __ jcc(Assembler::notZero, loop); aoqi@0: __ pushptr(Address(rcx, 0)); // Save final return address aoqi@0: aoqi@0: // Re-push self-frame aoqi@0: __ enter(); // Save old & set new ebp aoqi@0: aoqi@0: // Allocate a full sized register save area. aoqi@0: // Return address and rbp are in place, so we allocate two less words. aoqi@0: __ subptr(rsp, (frame_size_in_words - 2) * wordSize); aoqi@0: aoqi@0: // Restore frame locals after moving the frame aoqi@0: __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0); aoqi@0: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); aoqi@0: aoqi@0: // Call C code. Need thread but NOT official VM entry aoqi@0: // crud. We cannot block on this call, no GC can happen. Call should aoqi@0: // restore return values to their stack-slots with the new SP. aoqi@0: // aoqi@0: // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) aoqi@0: aoqi@0: // Use rbp because the frames look interpreted now aoqi@0: // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. aoqi@0: // Don't need the precise return PC here, just precise enough to point into this code blob. aoqi@0: address the_pc = __ pc(); aoqi@0: __ set_last_Java_frame(noreg, rbp, the_pc); aoqi@0: aoqi@0: __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ movl(c_rarg1, r14); // second arg: exec_mode aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); aoqi@0: // Revert SP alignment after call since we're going to do some SP relative addressing below aoqi@0: __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset())); aoqi@0: aoqi@0: // Set an oopmap for the call site aoqi@0: // Use the same PC we used for the last java frame aoqi@0: oop_maps->add_gc_map(the_pc - start, aoqi@0: new OopMap( frame_size_in_words, 0 )); aoqi@0: aoqi@0: // Clear fp AND pc aoqi@0: __ reset_last_Java_frame(true, true); aoqi@0: aoqi@0: // Collect return values aoqi@0: __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes())); aoqi@0: __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes())); aoqi@0: // I think this is useless (throwing pc?) aoqi@0: __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes())); aoqi@0: aoqi@0: // Pop self-frame. aoqi@0: __ leave(); // Epilog aoqi@0: aoqi@0: // Jump to interpreter aoqi@0: __ ret(0); aoqi@0: aoqi@0: // Make sure all code is generated aoqi@0: masm->flush(); aoqi@0: aoqi@0: _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); aoqi@0: _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); aoqi@0: } aoqi@0: aoqi@0: #ifdef COMPILER2 aoqi@0: //------------------------------generate_uncommon_trap_blob-------------------- aoqi@0: void SharedRuntime::generate_uncommon_trap_blob() { aoqi@0: // Allocate space for the code aoqi@0: ResourceMark rm; aoqi@0: // Setup code generation tools aoqi@0: CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); aoqi@0: MacroAssembler* masm = new MacroAssembler(&buffer); aoqi@0: aoqi@0: assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); aoqi@0: aoqi@0: address start = __ pc(); aoqi@0: aoqi@0: if (UseRTMLocking) { aoqi@0: // Abort RTM transaction before possible nmethod deoptimization. aoqi@0: __ xabort(0); aoqi@0: } aoqi@0: aoqi@0: // Push self-frame. We get here with a return address on the aoqi@0: // stack, so rsp is 8-byte aligned until we allocate our frame. aoqi@0: __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog! aoqi@0: aoqi@0: // No callee saved registers. rbp is assumed implicitly saved aoqi@0: __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); aoqi@0: aoqi@0: // compiler left unloaded_class_index in j_rarg0 move to where the aoqi@0: // runtime expects it. aoqi@0: __ movl(c_rarg1, j_rarg0); aoqi@0: aoqi@0: __ set_last_Java_frame(noreg, noreg, NULL); aoqi@0: aoqi@0: // Call C code. Need thread but NOT official VM entry aoqi@0: // crud. We cannot block on this call, no GC can happen. Call should aoqi@0: // capture callee-saved registers as well as return values. aoqi@0: // Thread is in rdi already. aoqi@0: // aoqi@0: // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); aoqi@0: aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); aoqi@0: aoqi@0: // Set an oopmap for the call site aoqi@0: OopMapSet* oop_maps = new OopMapSet(); aoqi@0: OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); aoqi@0: aoqi@0: // location of rbp is known implicitly by the frame sender code aoqi@0: aoqi@0: oop_maps->add_gc_map(__ pc() - start, map); aoqi@0: aoqi@0: __ reset_last_Java_frame(false, false); aoqi@0: aoqi@0: // Load UnrollBlock* into rdi aoqi@0: __ mov(rdi, rax); aoqi@0: aoqi@0: // Pop all the frames we must move/replace. aoqi@0: // aoqi@0: // Frame picture (youngest to oldest) aoqi@0: // 1: self-frame (no frame link) aoqi@0: // 2: deopting frame (no frame link) aoqi@0: // 3: caller of deopting frame (could be compiled/interpreted). aoqi@0: aoqi@0: // Pop self-frame. We have no frame, and must rely only on rax and rsp. aoqi@0: __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog! aoqi@0: aoqi@0: // Pop deoptimized frame (int) aoqi@0: __ movl(rcx, Address(rdi, aoqi@0: Deoptimization::UnrollBlock:: aoqi@0: size_of_deoptimized_frame_offset_in_bytes())); aoqi@0: __ addptr(rsp, rcx); aoqi@0: aoqi@0: // rsp should be pointing at the return address to the caller (3) aoqi@0: aoqi@0: // Pick up the initial fp we should save aoqi@0: // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) aoqi@0: __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // Compilers generate code that bang the stack by as much as the aoqi@0: // interpreter would need. So this stack banging should never aoqi@0: // trigger a fault. Verify that it does not on non product builds. aoqi@0: if (UseStackBanging) { aoqi@0: __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); aoqi@0: __ bang_stack_size(rbx, rcx); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // Load address of array of frame pcs into rcx (address*) aoqi@0: __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); aoqi@0: aoqi@0: // Trash the return pc aoqi@0: __ addptr(rsp, wordSize); aoqi@0: aoqi@0: // Load address of array of frame sizes into rsi (intptr_t*) aoqi@0: __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes())); aoqi@0: aoqi@0: // Counter aoqi@0: __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int) aoqi@0: aoqi@0: // Now adjust the caller's stack to make up for the extra locals but aoqi@0: // record the original sp so that we can save it in the skeletal aoqi@0: // interpreter frame and the stack walking of interpreter_sender aoqi@0: // will get the unextended sp value and not the "real" sp value. aoqi@0: aoqi@0: const Register sender_sp = r8; aoqi@0: aoqi@0: __ mov(sender_sp, rsp); aoqi@0: __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int) aoqi@0: __ subptr(rsp, rbx); aoqi@0: aoqi@0: // Push interpreter frames in a loop aoqi@0: Label loop; aoqi@0: __ bind(loop); aoqi@0: __ movptr(rbx, Address(rsi, 0)); // Load frame size aoqi@0: __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand aoqi@0: __ pushptr(Address(rcx, 0)); // Save return address aoqi@0: __ enter(); // Save old & set new rbp aoqi@0: __ subptr(rsp, rbx); // Prolog aoqi@0: #ifdef CC_INTERP aoqi@0: __ movptr(Address(rbp, aoqi@0: -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), aoqi@0: sender_sp); // Make it walkable aoqi@0: #else // CC_INTERP aoqi@0: __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), aoqi@0: sender_sp); // Make it walkable aoqi@0: // This value is corrected by layout_activation_impl aoqi@0: __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); aoqi@0: #endif // CC_INTERP aoqi@0: __ mov(sender_sp, rsp); // Pass sender_sp to next frame aoqi@0: __ addptr(rsi, wordSize); // Bump array pointer (sizes) aoqi@0: __ addptr(rcx, wordSize); // Bump array pointer (pcs) aoqi@0: __ decrementl(rdx); // Decrement counter aoqi@0: __ jcc(Assembler::notZero, loop); aoqi@0: __ pushptr(Address(rcx, 0)); // Save final return address aoqi@0: aoqi@0: // Re-push self-frame aoqi@0: __ enter(); // Save old & set new rbp aoqi@0: __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt); aoqi@0: // Prolog aoqi@0: aoqi@0: // Use rbp because the frames look interpreted now aoqi@0: // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. aoqi@0: // Don't need the precise return PC here, just precise enough to point into this code blob. aoqi@0: address the_pc = __ pc(); aoqi@0: __ set_last_Java_frame(noreg, rbp, the_pc); aoqi@0: aoqi@0: // Call C code. Need thread but NOT official VM entry aoqi@0: // crud. We cannot block on this call, no GC can happen. Call should aoqi@0: // restore return values to their stack-slots with the new SP. aoqi@0: // Thread is in rdi already. aoqi@0: // aoqi@0: // BasicType unpack_frames(JavaThread* thread, int exec_mode); aoqi@0: aoqi@0: __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap); aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); aoqi@0: aoqi@0: // Set an oopmap for the call site aoqi@0: // Use the same PC we used for the last java frame aoqi@0: oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); aoqi@0: aoqi@0: // Clear fp AND pc aoqi@0: __ reset_last_Java_frame(true, true); aoqi@0: aoqi@0: // Pop self-frame. aoqi@0: __ leave(); // Epilog aoqi@0: aoqi@0: // Jump to interpreter aoqi@0: __ ret(0); aoqi@0: aoqi@0: // Make sure all code is generated aoqi@0: masm->flush(); aoqi@0: aoqi@0: _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, aoqi@0: SimpleRuntimeFrame::framesize >> 1); aoqi@0: } aoqi@0: #endif // COMPILER2 aoqi@0: aoqi@0: aoqi@0: //------------------------------generate_handler_blob------ aoqi@0: // aoqi@0: // Generate a special Compile2Runtime blob that saves all registers, aoqi@0: // and setup oopmap. aoqi@0: // aoqi@0: SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { aoqi@0: assert(StubRoutines::forward_exception_entry() != NULL, aoqi@0: "must be generated before"); aoqi@0: aoqi@0: ResourceMark rm; aoqi@0: OopMapSet *oop_maps = new OopMapSet(); aoqi@0: OopMap* map; aoqi@0: aoqi@0: // Allocate space for the code. Setup code generation tools. aoqi@0: CodeBuffer buffer("handler_blob", 2048, 1024); aoqi@0: MacroAssembler* masm = new MacroAssembler(&buffer); aoqi@0: aoqi@0: address start = __ pc(); aoqi@0: address call_pc = NULL; aoqi@0: int frame_size_in_words; aoqi@0: bool cause_return = (poll_type == POLL_AT_RETURN); aoqi@0: bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP); aoqi@0: aoqi@0: if (UseRTMLocking) { aoqi@0: // Abort RTM transaction before calling runtime aoqi@0: // because critical section will be large and will be aoqi@0: // aborted anyway. Also nmethod could be deoptimized. aoqi@0: __ xabort(0); aoqi@0: } aoqi@0: aoqi@0: // Make room for return address (or push it again) aoqi@0: if (!cause_return) { aoqi@0: __ push(rbx); aoqi@0: } aoqi@0: aoqi@0: // Save registers, fpu state, and flags aoqi@0: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors); aoqi@0: aoqi@0: // The following is basically a call_VM. However, we need the precise aoqi@0: // address of the call in order to generate an oopmap. Hence, we do all the aoqi@0: // work outselves. aoqi@0: aoqi@0: __ set_last_Java_frame(noreg, noreg, NULL); aoqi@0: aoqi@0: // The return address must always be correct so that frame constructor never aoqi@0: // sees an invalid pc. aoqi@0: aoqi@0: if (!cause_return) { aoqi@0: // overwrite the dummy value we pushed on entry aoqi@0: __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset())); aoqi@0: __ movptr(Address(rbp, wordSize), c_rarg0); aoqi@0: } aoqi@0: aoqi@0: // Do the call aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ call(RuntimeAddress(call_ptr)); aoqi@0: aoqi@0: // Set an oopmap for the call site. This oopmap will map all aoqi@0: // oop-registers and debug-info registers as callee-saved. This aoqi@0: // will allow deoptimization at this safepoint to find all possible aoqi@0: // debug-info recordings, as well as let GC find all oops. aoqi@0: aoqi@0: oop_maps->add_gc_map( __ pc() - start, map); aoqi@0: aoqi@0: Label noException; aoqi@0: aoqi@0: __ reset_last_Java_frame(false, false); aoqi@0: aoqi@0: __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, noException); aoqi@0: aoqi@0: // Exception pending aoqi@0: aoqi@0: RegisterSaver::restore_live_registers(masm, save_vectors); aoqi@0: aoqi@0: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); aoqi@0: aoqi@0: // No exception case aoqi@0: __ bind(noException); aoqi@0: aoqi@0: // Normal exit, restore registers and exit. aoqi@0: RegisterSaver::restore_live_registers(masm, save_vectors); aoqi@0: aoqi@0: __ ret(0); aoqi@0: aoqi@0: // Make sure all code is generated aoqi@0: masm->flush(); aoqi@0: aoqi@0: // Fill-out other meta info aoqi@0: return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); aoqi@0: } aoqi@0: aoqi@0: // aoqi@0: // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss aoqi@0: // aoqi@0: // Generate a stub that calls into vm to find out the proper destination aoqi@0: // of a java call. All the argument registers are live at this point aoqi@0: // but since this is generic code we don't know what they are and the caller aoqi@0: // must do any gc of the args. aoqi@0: // aoqi@0: RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { aoqi@0: assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); aoqi@0: aoqi@0: // allocate space for the code aoqi@0: ResourceMark rm; aoqi@0: aoqi@0: CodeBuffer buffer(name, 1000, 512); aoqi@0: MacroAssembler* masm = new MacroAssembler(&buffer); aoqi@0: aoqi@0: int frame_size_in_words; aoqi@0: aoqi@0: OopMapSet *oop_maps = new OopMapSet(); aoqi@0: OopMap* map = NULL; aoqi@0: aoqi@0: int start = __ offset(); aoqi@0: aoqi@0: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); aoqi@0: aoqi@0: int frame_complete = __ offset(); aoqi@0: aoqi@0: __ set_last_Java_frame(noreg, noreg, NULL); aoqi@0: aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: aoqi@0: __ call(RuntimeAddress(destination)); aoqi@0: aoqi@0: aoqi@0: // Set an oopmap for the call site. aoqi@0: // We need this not only for callee-saved registers, but also for volatile aoqi@0: // registers that the compiler might be keeping live across a safepoint. aoqi@0: aoqi@0: oop_maps->add_gc_map( __ offset() - start, map); aoqi@0: aoqi@0: // rax contains the address we are going to jump to assuming no exception got installed aoqi@0: aoqi@0: // clear last_Java_sp aoqi@0: __ reset_last_Java_frame(false, false); aoqi@0: // check for pending exceptions aoqi@0: Label pending; aoqi@0: __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::notEqual, pending); aoqi@0: aoqi@0: // get the returned Method* aoqi@0: __ get_vm_result_2(rbx, r15_thread); aoqi@0: __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx); aoqi@0: aoqi@0: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); aoqi@0: aoqi@0: RegisterSaver::restore_live_registers(masm); aoqi@0: aoqi@0: // We are back the the original state on entry and ready to go. aoqi@0: aoqi@0: __ jmp(rax); aoqi@0: aoqi@0: // Pending exception after the safepoint aoqi@0: aoqi@0: __ bind(pending); aoqi@0: aoqi@0: RegisterSaver::restore_live_registers(masm); aoqi@0: aoqi@0: // exception pending => remove activation and forward to exception handler aoqi@0: aoqi@0: __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD); aoqi@0: aoqi@0: __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); aoqi@0: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); aoqi@0: aoqi@0: // ------------- aoqi@0: // make sure all code is generated aoqi@0: masm->flush(); aoqi@0: aoqi@0: // return the blob aoqi@0: // frame_size_words or bytes?? aoqi@0: return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef COMPILER2 aoqi@0: // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame aoqi@0: // aoqi@0: //------------------------------generate_exception_blob--------------------------- aoqi@0: // creates exception blob at the end aoqi@0: // Using exception blob, this code is jumped from a compiled method. aoqi@0: // (see emit_exception_handler in x86_64.ad file) aoqi@0: // aoqi@0: // Given an exception pc at a call we call into the runtime for the aoqi@0: // handler in this method. This handler might merely restore state aoqi@0: // (i.e. callee save registers) unwind the frame and jump to the aoqi@0: // exception handler for the nmethod if there is no Java level handler aoqi@0: // for the nmethod. aoqi@0: // aoqi@0: // This code is entered with a jmp. aoqi@0: // aoqi@0: // Arguments: aoqi@0: // rax: exception oop aoqi@0: // rdx: exception pc aoqi@0: // aoqi@0: // Results: aoqi@0: // rax: exception oop aoqi@0: // rdx: exception pc in caller or ??? aoqi@0: // destination: exception handler of caller aoqi@0: // aoqi@0: // Note: the exception pc MUST be at a call (precise debug information) aoqi@0: // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved. aoqi@0: // aoqi@0: aoqi@0: void OptoRuntime::generate_exception_blob() { aoqi@0: assert(!OptoRuntime::is_callee_saved_register(RDX_num), ""); aoqi@0: assert(!OptoRuntime::is_callee_saved_register(RAX_num), ""); aoqi@0: assert(!OptoRuntime::is_callee_saved_register(RCX_num), ""); aoqi@0: aoqi@0: assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); aoqi@0: aoqi@0: // Allocate space for the code aoqi@0: ResourceMark rm; aoqi@0: // Setup code generation tools aoqi@0: CodeBuffer buffer("exception_blob", 2048, 1024); aoqi@0: MacroAssembler* masm = new MacroAssembler(&buffer); aoqi@0: aoqi@0: aoqi@0: address start = __ pc(); aoqi@0: aoqi@0: // Exception pc is 'return address' for stack walker aoqi@0: __ push(rdx); aoqi@0: __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog aoqi@0: aoqi@0: // Save callee-saved registers. See x86_64.ad. aoqi@0: aoqi@0: // rbp is an implicitly saved callee saved register (i.e. the calling aoqi@0: // convention will save restore it in prolog/epilog) Other than that aoqi@0: // there are no callee save registers now that adapter frames are gone. aoqi@0: aoqi@0: __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); aoqi@0: aoqi@0: // Store exception in Thread object. We cannot pass any arguments to the aoqi@0: // handle_exception call, since we do not want to make any assumption aoqi@0: // about the size of the frame where the exception happened in. aoqi@0: // c_rarg0 is either rdi (Linux) or rcx (Windows). aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); aoqi@0: aoqi@0: // This call does all the hard work. It checks if an exception handler aoqi@0: // exists in the method. aoqi@0: // If so, it returns the handler address. aoqi@0: // If not, it prepares for stack-unwinding, restoring the callee-save aoqi@0: // registers of the frame being removed. aoqi@0: // aoqi@0: // address OptoRuntime::handle_exception_C(JavaThread* thread) aoqi@0: aoqi@0: // At a method handle call, the stack may not be properly aligned aoqi@0: // when returning with an exception. aoqi@0: address the_pc = __ pc(); aoqi@0: __ set_last_Java_frame(noreg, noreg, the_pc); aoqi@0: __ mov(c_rarg0, r15_thread); aoqi@0: __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); aoqi@0: aoqi@0: // Set an oopmap for the call site. This oopmap will only be used if we aoqi@0: // are unwinding the stack. Hence, all locations will be dead. aoqi@0: // Callee-saved registers will be the same as the frame above (i.e., aoqi@0: // handle_exception_stub), since they were restored when we got the aoqi@0: // exception. aoqi@0: aoqi@0: OopMapSet* oop_maps = new OopMapSet(); aoqi@0: aoqi@0: oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); aoqi@0: aoqi@0: __ reset_last_Java_frame(false, true); aoqi@0: aoqi@0: // Restore callee-saved registers aoqi@0: aoqi@0: // rbp is an implicitly saved callee saved register (i.e. the calling aoqi@0: // convention will save restore it in prolog/epilog) Other than that aoqi@0: // there are no callee save registers no that adapter frames are gone. aoqi@0: aoqi@0: __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt)); aoqi@0: aoqi@0: __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog aoqi@0: __ pop(rdx); // No need for exception pc anymore aoqi@0: aoqi@0: // rax: exception handler aoqi@0: aoqi@0: // Restore SP from BP if the exception PC is a MethodHandle call site. aoqi@0: __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0); aoqi@0: __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save); aoqi@0: aoqi@0: // We have a handler in rax (could be deopt blob). aoqi@0: __ mov(r8, rax); aoqi@0: aoqi@0: // Get the exception oop aoqi@0: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); aoqi@0: // Get the exception pc in case we are deoptimized aoqi@0: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); aoqi@0: #ifdef ASSERT aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD); aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD); aoqi@0: #endif aoqi@0: // Clear the exception oop so GC no longer processes it as a root. aoqi@0: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD); aoqi@0: aoqi@0: // rax: exception oop aoqi@0: // r8: exception handler aoqi@0: // rdx: exception pc aoqi@0: // Jump to handler aoqi@0: aoqi@0: __ jmp(r8); aoqi@0: aoqi@0: // Make sure all code is generated aoqi@0: masm->flush(); aoqi@0: aoqi@0: // Set exception blob aoqi@0: _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); aoqi@0: } aoqi@0: #endif // COMPILER2