aoqi@0: /* aoqi@0: * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@0: #ifndef CPU_X86_VM_NATIVEINST_X86_HPP aoqi@0: #define CPU_X86_VM_NATIVEINST_X86_HPP aoqi@0: aoqi@0: #include "asm/assembler.hpp" aoqi@0: #include "memory/allocation.hpp" aoqi@0: #include "runtime/icache.hpp" aoqi@0: #include "runtime/os.hpp" aoqi@0: #include "utilities/top.hpp" aoqi@0: aoqi@0: // We have interfaces for the following instructions: aoqi@0: // - NativeInstruction aoqi@0: // - - NativeCall aoqi@0: // - - NativeMovConstReg aoqi@0: // - - NativeMovConstRegPatching aoqi@0: // - - NativeMovRegMem aoqi@0: // - - NativeMovRegMemPatching aoqi@0: // - - NativeJump aoqi@0: // - - NativeIllegalOpCode aoqi@0: // - - NativeGeneralJump aoqi@0: // - - NativeReturn aoqi@0: // - - NativeReturnX (return with argument) aoqi@0: // - - NativePushConst aoqi@0: // - - NativeTstRegMem aoqi@0: aoqi@0: // The base class for different kinds of native instruction abstractions. aoqi@0: // Provides the primitive operations to manipulate code relative to this. aoqi@0: aoqi@0: class NativeInstruction VALUE_OBJ_CLASS_SPEC { aoqi@0: friend class Relocation; aoqi@0: aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: nop_instruction_code = 0x90, aoqi@0: nop_instruction_size = 1 aoqi@0: }; aoqi@0: aoqi@0: bool is_nop() { return ubyte_at(0) == nop_instruction_code; } aoqi@0: bool is_dtrace_trap(); aoqi@0: inline bool is_call(); aoqi@0: inline bool is_illegal(); aoqi@0: inline bool is_return(); aoqi@0: inline bool is_jump(); aoqi@0: inline bool is_cond_jump(); aoqi@0: inline bool is_safepoint_poll(); aoqi@0: inline bool is_mov_literal64(); aoqi@0: aoqi@0: protected: aoqi@0: address addr_at(int offset) const { return address(this) + offset; } aoqi@0: aoqi@0: s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } aoqi@0: u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } aoqi@0: aoqi@0: jint int_at(int offset) const { return *(jint*) addr_at(offset); } aoqi@0: aoqi@0: intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } aoqi@0: aoqi@0: oop oop_at (int offset) const { return *(oop*) addr_at(offset); } aoqi@0: aoqi@0: aoqi@0: void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } aoqi@0: void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } aoqi@0: void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } aoqi@0: void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } aoqi@0: aoqi@0: // This doesn't really do anything on Intel, but it is the place where aoqi@0: // cache invalidation belongs, generically: aoqi@0: void wrote(int offset); aoqi@0: aoqi@0: public: aoqi@0: aoqi@0: // unit test stuff aoqi@0: static void test() {} // override for testing aoqi@0: aoqi@0: inline friend NativeInstruction* nativeInstruction_at(address address); aoqi@0: }; aoqi@0: aoqi@0: inline NativeInstruction* nativeInstruction_at(address address) { aoqi@0: NativeInstruction* inst = (NativeInstruction*)address; aoqi@0: #ifdef ASSERT aoqi@0: //inst->verify(); aoqi@0: #endif aoqi@0: return inst; aoqi@0: } aoqi@0: aoqi@0: inline NativeCall* nativeCall_at(address address); aoqi@0: // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off aoqi@0: // instructions (used to manipulate inline caches, primitive & dll calls, etc.). aoqi@0: aoqi@0: class NativeCall: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0xE8, aoqi@0: instruction_size = 5, aoqi@0: instruction_offset = 0, aoqi@0: displacement_offset = 1, aoqi@0: return_address_offset = 5 aoqi@0: }; aoqi@0: aoqi@0: enum { cache_line_size = BytesPerWord }; // conservative estimate! aoqi@0: aoqi@0: address instruction_address() const { return addr_at(instruction_offset); } aoqi@0: address next_instruction_address() const { return addr_at(return_address_offset); } aoqi@0: int displacement() const { return (jint) int_at(displacement_offset); } aoqi@0: address displacement_address() const { return addr_at(displacement_offset); } aoqi@0: address return_address() const { return addr_at(return_address_offset); } aoqi@0: address destination() const; aoqi@0: void set_destination(address dest) { aoqi@0: #ifdef AMD64 aoqi@0: assert((labs((intptr_t) dest - (intptr_t) return_address()) & aoqi@0: 0xFFFFFFFF00000000) == 0, aoqi@0: "must be 32bit offset"); aoqi@0: #endif // AMD64 aoqi@0: set_int_at(displacement_offset, dest - return_address()); aoqi@0: } aoqi@0: void set_destination_mt_safe(address dest); aoqi@0: aoqi@0: void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } aoqi@0: void verify(); aoqi@0: void print(); aoqi@0: aoqi@0: // Creation aoqi@0: inline friend NativeCall* nativeCall_at(address address); aoqi@0: inline friend NativeCall* nativeCall_before(address return_address); aoqi@0: aoqi@0: static bool is_call_at(address instr) { aoqi@0: return ((*instr) & 0xFF) == NativeCall::instruction_code; aoqi@0: } aoqi@0: aoqi@0: static bool is_call_before(address return_address) { aoqi@0: return is_call_at(return_address - NativeCall::return_address_offset); aoqi@0: } aoqi@0: aoqi@0: static bool is_call_to(address instr, address target) { aoqi@0: return nativeInstruction_at(instr)->is_call() && aoqi@0: nativeCall_at(instr)->destination() == target; aoqi@0: } aoqi@0: aoqi@0: // MT-safe patching of a call instruction. aoqi@0: static void insert(address code_pos, address entry); aoqi@0: aoqi@0: static void replace_mt_safe(address instr_addr, address code_buffer); aoqi@0: }; aoqi@0: aoqi@0: inline NativeCall* nativeCall_at(address address) { aoqi@0: NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: call->verify(); aoqi@0: #endif aoqi@0: return call; aoqi@0: } aoqi@0: aoqi@0: inline NativeCall* nativeCall_before(address return_address) { aoqi@0: NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); aoqi@0: #ifdef ASSERT aoqi@0: call->verify(); aoqi@0: #endif aoqi@0: return call; aoqi@0: } aoqi@0: aoqi@0: // An interface for accessing/manipulating native mov reg, imm32 instructions. aoqi@0: // (used to manipulate inlined 32bit data dll calls, etc.) aoqi@0: class NativeMovConstReg: public NativeInstruction { aoqi@0: #ifdef AMD64 aoqi@0: static const bool has_rex = true; aoqi@0: static const int rex_size = 1; aoqi@0: #else aoqi@0: static const bool has_rex = false; aoqi@0: static const int rex_size = 0; aoqi@0: #endif // AMD64 aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0xB8, aoqi@0: instruction_size = 1 + rex_size + wordSize, aoqi@0: instruction_offset = 0, aoqi@0: data_offset = 1 + rex_size, aoqi@0: next_instruction_offset = instruction_size, aoqi@0: register_mask = 0x07 aoqi@0: }; aoqi@0: aoqi@0: address instruction_address() const { return addr_at(instruction_offset); } aoqi@0: address next_instruction_address() const { return addr_at(next_instruction_offset); } aoqi@0: intptr_t data() const { return ptr_at(data_offset); } aoqi@0: void set_data(intptr_t x) { set_ptr_at(data_offset, x); } aoqi@0: aoqi@0: void verify(); aoqi@0: void print(); aoqi@0: aoqi@0: // unit test stuff aoqi@0: static void test() {} aoqi@0: aoqi@0: // Creation aoqi@0: inline friend NativeMovConstReg* nativeMovConstReg_at(address address); aoqi@0: inline friend NativeMovConstReg* nativeMovConstReg_before(address address); aoqi@0: }; aoqi@0: aoqi@0: inline NativeMovConstReg* nativeMovConstReg_at(address address) { aoqi@0: NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: aoqi@0: inline NativeMovConstReg* nativeMovConstReg_before(address address) { aoqi@0: NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: aoqi@0: class NativeMovConstRegPatching: public NativeMovConstReg { aoqi@0: private: aoqi@0: friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { aoqi@0: NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: // An interface for accessing/manipulating native moves of the form: aoqi@0: // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) aoqi@0: // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg aoqi@0: // mov[s/z]x[w/b/q] [reg + offset], reg aoqi@0: // fld_s [reg+offset] aoqi@0: // fld_d [reg+offset] aoqi@0: // fstp_s [reg + offset] aoqi@0: // fstp_d [reg + offset] aoqi@0: // mov_literal64 scratch, ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) aoqi@0: // aoqi@0: // Warning: These routines must be able to handle any instruction sequences aoqi@0: // that are generated as a result of the load/store byte,word,long aoqi@0: // macros. For example: The load_unsigned_byte instruction generates aoqi@0: // an xor reg,reg inst prior to generating the movb instruction. This aoqi@0: // class must skip the xor instruction. aoqi@0: aoqi@0: class NativeMovRegMem: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_prefix_wide_lo = Assembler::REX, aoqi@0: instruction_prefix_wide_hi = Assembler::REX_WRXB, aoqi@0: instruction_code_xor = 0x33, aoqi@0: instruction_extended_prefix = 0x0F, aoqi@0: instruction_code_mem2reg_movslq = 0x63, aoqi@0: instruction_code_mem2reg_movzxb = 0xB6, aoqi@0: instruction_code_mem2reg_movsxb = 0xBE, aoqi@0: instruction_code_mem2reg_movzxw = 0xB7, aoqi@0: instruction_code_mem2reg_movsxw = 0xBF, aoqi@0: instruction_operandsize_prefix = 0x66, aoqi@0: instruction_code_reg2mem = 0x89, aoqi@0: instruction_code_mem2reg = 0x8b, aoqi@0: instruction_code_reg2memb = 0x88, aoqi@0: instruction_code_mem2regb = 0x8a, aoqi@0: instruction_code_float_s = 0xd9, aoqi@0: instruction_code_float_d = 0xdd, aoqi@0: instruction_code_long_volatile = 0xdf, aoqi@0: instruction_code_xmm_ss_prefix = 0xf3, aoqi@0: instruction_code_xmm_sd_prefix = 0xf2, aoqi@0: instruction_code_xmm_code = 0x0f, aoqi@0: instruction_code_xmm_load = 0x10, aoqi@0: instruction_code_xmm_store = 0x11, aoqi@0: instruction_code_xmm_lpd = 0x12, aoqi@0: aoqi@0: instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes, aoqi@0: instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes, aoqi@0: aoqi@0: instruction_size = 4, aoqi@0: instruction_offset = 0, aoqi@0: data_offset = 2, aoqi@0: next_instruction_offset = 4 aoqi@0: }; aoqi@0: aoqi@0: // helper aoqi@0: int instruction_start() const; aoqi@0: aoqi@0: address instruction_address() const; aoqi@0: aoqi@0: address next_instruction_address() const; aoqi@0: aoqi@0: int offset() const; aoqi@0: aoqi@0: void set_offset(int x); aoqi@0: aoqi@0: void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } aoqi@0: aoqi@0: void verify(); aoqi@0: void print (); aoqi@0: aoqi@0: // unit test stuff aoqi@0: static void test() {} aoqi@0: aoqi@0: private: aoqi@0: inline friend NativeMovRegMem* nativeMovRegMem_at (address address); aoqi@0: }; aoqi@0: aoqi@0: inline NativeMovRegMem* nativeMovRegMem_at (address address) { aoqi@0: NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: aoqi@0: class NativeMovRegMemPatching: public NativeMovRegMem { aoqi@0: private: aoqi@0: friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { aoqi@0: NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: aoqi@0: // An interface for accessing/manipulating native leal instruction of form: aoqi@0: // leal reg, [reg + offset] aoqi@0: aoqi@0: class NativeLoadAddress: public NativeMovRegMem { aoqi@0: #ifdef AMD64 aoqi@0: static const bool has_rex = true; aoqi@0: static const int rex_size = 1; aoqi@0: #else aoqi@0: static const bool has_rex = false; aoqi@0: static const int rex_size = 0; aoqi@0: #endif // AMD64 aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_prefix_wide = Assembler::REX_W, aoqi@0: instruction_prefix_wide_extended = Assembler::REX_WB, aoqi@0: lea_instruction_code = 0x8D, aoqi@0: mov64_instruction_code = 0xB8 aoqi@0: }; aoqi@0: aoqi@0: void verify(); aoqi@0: void print (); aoqi@0: aoqi@0: // unit test stuff aoqi@0: static void test() {} aoqi@0: aoqi@0: private: aoqi@0: friend NativeLoadAddress* nativeLoadAddress_at (address address) { aoqi@0: NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: test->verify(); aoqi@0: #endif aoqi@0: return test; aoqi@0: } aoqi@0: }; aoqi@0: aoqi@0: // jump rel32off aoqi@0: aoqi@0: class NativeJump: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0xe9, aoqi@0: instruction_size = 5, aoqi@0: instruction_offset = 0, aoqi@0: data_offset = 1, aoqi@0: next_instruction_offset = 5 aoqi@0: }; aoqi@0: aoqi@0: address instruction_address() const { return addr_at(instruction_offset); } aoqi@0: address next_instruction_address() const { return addr_at(next_instruction_offset); } aoqi@0: address jump_destination() const { aoqi@0: address dest = (int_at(data_offset)+next_instruction_address()); aoqi@0: // 32bit used to encode unresolved jmp as jmp -1 aoqi@0: // 64bit can't produce this so it used jump to self. aoqi@0: // Now 32bit and 64bit use jump to self as the unresolved address aoqi@0: // which the inline cache code (and relocs) know about aoqi@0: aoqi@0: // return -1 if jump to self aoqi@0: dest = (dest == (address) this) ? (address) -1 : dest; aoqi@0: return dest; aoqi@0: } aoqi@0: aoqi@0: void set_jump_destination(address dest) { aoqi@0: intptr_t val = dest - next_instruction_address(); aoqi@0: if (dest == (address) -1) { aoqi@0: val = -5; // jump to self aoqi@0: } aoqi@0: #ifdef AMD64 aoqi@0: assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1"); aoqi@0: #endif // AMD64 aoqi@0: set_int_at(data_offset, (jint)val); aoqi@0: } aoqi@0: aoqi@0: // Creation aoqi@0: inline friend NativeJump* nativeJump_at(address address); aoqi@0: aoqi@0: void verify(); aoqi@0: aoqi@0: // Unit testing stuff aoqi@0: static void test() {} aoqi@0: aoqi@0: // Insertion of native jump instruction aoqi@0: static void insert(address code_pos, address entry); aoqi@0: // MT-safe insertion of native jump at verified method entry aoqi@0: static void check_verified_entry_alignment(address entry, address verified_entry); aoqi@0: static void patch_verified_entry(address entry, address verified_entry, address dest); aoqi@0: }; aoqi@0: aoqi@0: inline NativeJump* nativeJump_at(address address) { aoqi@0: NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); aoqi@0: #ifdef ASSERT aoqi@0: jump->verify(); aoqi@0: #endif aoqi@0: return jump; aoqi@0: } aoqi@0: aoqi@0: // Handles all kinds of jump on Intel. Long/far, conditional/unconditional aoqi@0: class NativeGeneralJump: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: // Constants does not apply, since the lengths and offsets depends on the actual jump aoqi@0: // used aoqi@0: // Instruction codes: aoqi@0: // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) aoqi@0: // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) aoqi@0: unconditional_long_jump = 0xe9, aoqi@0: unconditional_short_jump = 0xeb, aoqi@0: instruction_size = 5 aoqi@0: }; aoqi@0: aoqi@0: address instruction_address() const { return addr_at(0); } aoqi@0: address jump_destination() const; aoqi@0: aoqi@0: // Creation aoqi@0: inline friend NativeGeneralJump* nativeGeneralJump_at(address address); aoqi@0: aoqi@0: // Insertion of native general jump instruction aoqi@0: static void insert_unconditional(address code_pos, address entry); aoqi@0: static void replace_mt_safe(address instr_addr, address code_buffer); aoqi@0: aoqi@0: void verify(); aoqi@0: }; aoqi@0: aoqi@0: inline NativeGeneralJump* nativeGeneralJump_at(address address) { aoqi@0: NativeGeneralJump* jump = (NativeGeneralJump*)(address); aoqi@0: debug_only(jump->verify();) aoqi@0: return jump; aoqi@0: } aoqi@0: aoqi@0: class NativePopReg : public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0x58, aoqi@0: instruction_size = 1, aoqi@0: instruction_offset = 0, aoqi@0: data_offset = 1, aoqi@0: next_instruction_offset = 1 aoqi@0: }; aoqi@0: aoqi@0: // Insert a pop instruction aoqi@0: static void insert(address code_pos, Register reg); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: class NativeIllegalInstruction: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B aoqi@0: instruction_size = 2, aoqi@0: instruction_offset = 0, aoqi@0: next_instruction_offset = 2 aoqi@0: }; aoqi@0: aoqi@0: // Insert illegal opcode as specific address aoqi@0: static void insert(address code_pos); aoqi@0: }; aoqi@0: aoqi@0: // return instruction that does not pop values of the stack aoqi@0: class NativeReturn: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0xC3, aoqi@0: instruction_size = 1, aoqi@0: instruction_offset = 0, aoqi@0: next_instruction_offset = 1 aoqi@0: }; aoqi@0: }; aoqi@0: aoqi@0: // return instruction that does pop values of the stack aoqi@0: class NativeReturnX: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_code = 0xC2, aoqi@0: instruction_size = 2, aoqi@0: instruction_offset = 0, aoqi@0: next_instruction_offset = 2 aoqi@0: }; aoqi@0: }; aoqi@0: aoqi@0: // Simple test vs memory aoqi@0: class NativeTstRegMem: public NativeInstruction { aoqi@0: public: aoqi@0: enum Intel_specific_constants { aoqi@0: instruction_rex_prefix_mask = 0xF0, aoqi@0: instruction_rex_prefix = Assembler::REX, aoqi@0: instruction_code_memXregl = 0x85, aoqi@0: modrm_mask = 0x38, // select reg from the ModRM byte aoqi@0: modrm_reg = 0x00 // rax aoqi@0: }; aoqi@0: }; aoqi@0: aoqi@0: inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } aoqi@0: inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } aoqi@0: inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || aoqi@0: ubyte_at(0) == NativeReturnX::instruction_code; } aoqi@0: inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || aoqi@0: ubyte_at(0) == 0xEB; /* short jump */ } aoqi@0: inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || aoqi@0: (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } aoqi@0: inline bool NativeInstruction::is_safepoint_poll() { aoqi@0: #ifdef AMD64 aoqi@0: if (Assembler::is_polling_page_far()) { aoqi@0: // two cases, depending on the choice of the base register in the address. aoqi@0: if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix && aoqi@0: ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl && aoqi@0: (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) || aoqi@0: ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && aoqi@0: (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) { aoqi@0: return true; aoqi@0: } else { aoqi@0: return false; aoqi@0: } aoqi@0: } else { aoqi@0: if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && aoqi@0: ubyte_at(1) == 0x05) { // 00 rax 101 aoqi@0: address fault = addr_at(6) + int_at(2); aoqi@0: return os::is_poll_address(fault); aoqi@0: } else { aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: #else aoqi@0: return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg || aoqi@0: ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && aoqi@0: (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ aoqi@0: (os::is_poll_address((address)int_at(2))); aoqi@0: #endif // AMD64 aoqi@0: } aoqi@0: aoqi@0: inline bool NativeInstruction::is_mov_literal64() { aoqi@0: #ifdef AMD64 aoqi@0: return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && aoqi@0: (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); aoqi@0: #else aoqi@0: return false; aoqi@0: #endif // AMD64 aoqi@0: } aoqi@0: aoqi@0: #endif // CPU_X86_VM_NATIVEINST_X86_HPP