aoqi@0: /*
aoqi@0:  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
aoqi@0:  *
aoqi@0:  */
aoqi@0: 
aoqi@0: #include "precompiled.hpp"
aoqi@0: #include "asm/macroAssembler.inline.hpp"
aoqi@0: #include "memory/resourceArea.hpp"
aoqi@0: #include "runtime/java.hpp"
aoqi@0: #include "runtime/stubCodeGenerator.hpp"
aoqi@0: #include "vm_version_sparc.hpp"
aoqi@0: #ifdef TARGET_OS_FAMILY_linux
aoqi@0: # include "os_linux.inline.hpp"
aoqi@0: #endif
aoqi@0: #ifdef TARGET_OS_FAMILY_solaris
aoqi@0: # include "os_solaris.inline.hpp"
aoqi@0: #endif
aoqi@0: 
aoqi@0: int VM_Version::_features = VM_Version::unknown_m;
aoqi@0: const char* VM_Version::_features_str = "";
aoqi@0: 
aoqi@0: void VM_Version::initialize() {
aoqi@0:   _features = determine_features();
aoqi@0:   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
aoqi@0:   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
aoqi@0:   PrefetchFieldsAhead         = prefetch_fields_ahead();
aoqi@0: 
aoqi@0:   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
aoqi@0:   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
aoqi@0:   if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
aoqi@0: 
aoqi@0:   // Allocation prefetch settings
aoqi@0:   intx cache_line_size = prefetch_data_size();
aoqi@0:   if( cache_line_size > AllocatePrefetchStepSize )
aoqi@0:     AllocatePrefetchStepSize = cache_line_size;
aoqi@0: 
aoqi@0:   assert(AllocatePrefetchLines > 0, "invalid value");
aoqi@0:   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
aoqi@0:     AllocatePrefetchLines = 3;
aoqi@0:   assert(AllocateInstancePrefetchLines > 0, "invalid value");
aoqi@0:   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
aoqi@0:     AllocateInstancePrefetchLines = 1;
aoqi@0: 
aoqi@0:   AllocatePrefetchDistance = allocate_prefetch_distance();
aoqi@0:   AllocatePrefetchStyle    = allocate_prefetch_style();
aoqi@0: 
aoqi@0:   assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
aoqi@0:          (AllocatePrefetchDistance > 0), "invalid value");
aoqi@0:   if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
aoqi@0:       (AllocatePrefetchDistance <= 0)) {
aoqi@0:     AllocatePrefetchDistance = AllocatePrefetchStepSize;
aoqi@0:   }
aoqi@0: 
aoqi@0:   if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
aoqi@0:     warning("BIS instructions are not available on this CPU");
aoqi@0:     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
aoqi@0:   }
aoqi@0: 
aoqi@0:   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
aoqi@0: 
aoqi@0:   assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
aoqi@0:   if (ArraycopySrcPrefetchDistance >= 4096)
aoqi@0:     ArraycopySrcPrefetchDistance = 4064;
aoqi@0:   assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
aoqi@0:   if (ArraycopyDstPrefetchDistance >= 4096)
aoqi@0:     ArraycopyDstPrefetchDistance = 4064;
aoqi@0: 
aoqi@0:   UseSSE = 0; // Only on x86 and x64
aoqi@0: 
aoqi@0:   _supports_cx8 = has_v9();
aoqi@0:   _supports_atomic_getset4 = true; // swap instruction
aoqi@0: 
aoqi@0:   // There are Fujitsu Sparc64 CPUs which support blk_init as well so
aoqi@0:   // we have to take this check out of the 'is_niagara()' block below.
aoqi@0:   if (has_blk_init()) {
aoqi@0:     // When using CMS or G1, we cannot use memset() in BOT updates
aoqi@0:     // because the sun4v/CMT version in libc_psr uses BIS which
aoqi@0:     // exposes "phantom zeros" to concurrent readers. See 6948537.
aoqi@0:     if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
aoqi@0:       FLAG_SET_DEFAULT(UseMemSetInBOT, false);
aoqi@0:     }
aoqi@0:     // Issue a stern warning if the user has explicitly set
aoqi@0:     // UseMemSetInBOT (it is known to cause issues), but allow
aoqi@0:     // use for experimentation and debugging.
aoqi@0:     if (UseConcMarkSweepGC || UseG1GC) {
aoqi@0:       if (UseMemSetInBOT) {
aoqi@0:         assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
aoqi@0:         warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
aoqi@0:                 " on sun4v; please understand that you are using at your own risk!");
aoqi@0:       }
aoqi@0:     }
aoqi@0:   }
aoqi@0: 
aoqi@0:   if (is_niagara()) {
aoqi@0:     // Indirect branch is the same cost as direct
aoqi@0:     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
aoqi@0:       FLAG_SET_DEFAULT(UseInlineCaches, false);
aoqi@0:     }
aoqi@0:     // Align loops on a single instruction boundary.
aoqi@0:     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
aoqi@0:       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
aoqi@0:     }
aoqi@0: #ifdef _LP64
aoqi@0:     // 32-bit oops don't make sense for the 64-bit VM on sparc
aoqi@0:     // since the 32-bit VM has the same registers and smaller objects.
aoqi@0:     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
aoqi@0:     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
aoqi@0: #endif // _LP64
aoqi@0: #ifdef COMPILER2
aoqi@0:     // Indirect branch is the same cost as direct
aoqi@0:     if (FLAG_IS_DEFAULT(UseJumpTables)) {
aoqi@0:       FLAG_SET_DEFAULT(UseJumpTables, true);
aoqi@0:     }
aoqi@0:     // Single-issue, so entry and loop tops are
aoqi@0:     // aligned on a single instruction boundary
aoqi@0:     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
aoqi@0:       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
aoqi@0:     }
aoqi@0:     if (is_niagara_plus()) {
aoqi@0:       if (has_blk_init() && UseTLAB &&
aoqi@0:           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
aoqi@0:         // Use BIS instruction for TLAB allocation prefetch.
aoqi@0:         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
aoqi@0:         if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
aoqi@0:           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
aoqi@0:         }
aoqi@0:         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
aoqi@0:           // Use smaller prefetch distance with BIS
aoqi@0:           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
aoqi@0:         }
aoqi@0:       }
aoqi@0:       if (is_T4()) {
aoqi@0:         // Double number of prefetched cache lines on T4
aoqi@0:         // since L2 cache line size is smaller (32 bytes).
aoqi@0:         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
aoqi@0:           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
aoqi@0:         }
aoqi@0:         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
aoqi@0:           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
aoqi@0:         }
aoqi@0:       }
aoqi@0:       if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
aoqi@0:         // Use different prefetch distance without BIS
aoqi@0:         FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
aoqi@0:       }
aoqi@0:       if (AllocatePrefetchInstr == 1) {
aoqi@0:         // Need a space at the end of TLAB for BIS since it
aoqi@0:         // will fault when accessing memory outside of heap.
aoqi@0: 
aoqi@0:         // +1 for rounding up to next cache line, +1 to be safe
aoqi@0:         int lines = AllocatePrefetchLines + 2;
aoqi@0:         int step_size = AllocatePrefetchStepSize;
aoqi@0:         int distance = AllocatePrefetchDistance;
aoqi@0:         _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
aoqi@0:       }
aoqi@0:     }
aoqi@0: #endif
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Use hardware population count instruction if available.
aoqi@0:   if (has_hardware_popc()) {
aoqi@0:     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
aoqi@0:       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
aoqi@0:     }
aoqi@0:   } else if (UsePopCountInstruction) {
aoqi@0:     warning("POPC instruction is not available on this CPU");
aoqi@0:     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
aoqi@0:   }
aoqi@0: 
aoqi@0:   // T4 and newer Sparc cpus have new compare and branch instruction.
aoqi@0:   if (has_cbcond()) {
aoqi@0:     if (FLAG_IS_DEFAULT(UseCBCond)) {
aoqi@0:       FLAG_SET_DEFAULT(UseCBCond, true);
aoqi@0:     }
aoqi@0:   } else if (UseCBCond) {
aoqi@0:     warning("CBCOND instruction is not available on this CPU");
aoqi@0:     FLAG_SET_DEFAULT(UseCBCond, false);
aoqi@0:   }
aoqi@0: 
aoqi@0:   assert(BlockZeroingLowLimit > 0, "invalid value");
aoqi@0:   if (has_block_zeroing()) {
aoqi@0:     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
aoqi@0:       FLAG_SET_DEFAULT(UseBlockZeroing, true);
aoqi@0:     }
aoqi@0:   } else if (UseBlockZeroing) {
aoqi@0:     warning("BIS zeroing instructions are not available on this CPU");
aoqi@0:     FLAG_SET_DEFAULT(UseBlockZeroing, false);
aoqi@0:   }
aoqi@0: 
aoqi@0:   assert(BlockCopyLowLimit > 0, "invalid value");
aoqi@0:   if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
aoqi@0:     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
aoqi@0:       FLAG_SET_DEFAULT(UseBlockCopy, true);
aoqi@0:     }
aoqi@0:   } else if (UseBlockCopy) {
aoqi@0:     warning("BIS instructions are not available or expensive on this CPU");
aoqi@0:     FLAG_SET_DEFAULT(UseBlockCopy, false);
aoqi@0:   }
aoqi@0: 
aoqi@0: #ifdef COMPILER2
aoqi@0:   // T4 and newer Sparc cpus have fast RDPC.
aoqi@0:   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
aoqi@0:     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Currently not supported anywhere.
aoqi@0:   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
aoqi@0: 
aoqi@0:   MaxVectorSize = 8;
aoqi@0: 
aoqi@0:   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
aoqi@0: #endif
aoqi@0: 
aoqi@0:   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
aoqi@0:   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
aoqi@0: 
aoqi@0:   char buf[512];
aoqi@0:   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
aoqi@0:                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
aoqi@0:                (has_hardware_popc() ? ", popc" : ""),
aoqi@0:                (has_vis1() ? ", vis1" : ""),
aoqi@0:                (has_vis2() ? ", vis2" : ""),
aoqi@0:                (has_vis3() ? ", vis3" : ""),
aoqi@0:                (has_blk_init() ? ", blk_init" : ""),
aoqi@0:                (has_cbcond() ? ", cbcond" : ""),
aoqi@0:                (has_aes() ? ", aes" : ""),
aoqi@0:                (is_ultra3() ? ", ultra3" : ""),
aoqi@0:                (is_sun4v() ? ", sun4v" : ""),
aoqi@0:                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
aoqi@0:                (is_sparc64() ? ", sparc64" : ""),
aoqi@0:                (!has_hardware_mul32() ? ", no-mul32" : ""),
aoqi@0:                (!has_hardware_div32() ? ", no-div32" : ""),
aoqi@0:                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
aoqi@0: 
aoqi@0:   // buf is started with ", " or is empty
aoqi@0:   _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
aoqi@0: 
aoqi@0:   // UseVIS is set to the smallest of what hardware supports and what
aoqi@0:   // the command line requires.  I.e., you cannot set UseVIS to 3 on
aoqi@0:   // older UltraSparc which do not support it.
aoqi@0:   if (UseVIS > 3) UseVIS=3;
aoqi@0:   if (UseVIS < 0) UseVIS=0;
aoqi@0:   if (!has_vis3()) // Drop to 2 if no VIS3 support
aoqi@0:     UseVIS = MIN2((intx)2,UseVIS);
aoqi@0:   if (!has_vis2()) // Drop to 1 if no VIS2 support
aoqi@0:     UseVIS = MIN2((intx)1,UseVIS);
aoqi@0:   if (!has_vis1()) // Drop to 0 if no VIS1 support
aoqi@0:     UseVIS = 0;
aoqi@0: 
aoqi@0:   // SPARC T4 and above should have support for AES instructions
aoqi@0:   if (has_aes()) {
aoqi@0:     if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
aoqi@0:       if (FLAG_IS_DEFAULT(UseAES)) {
aoqi@0:         FLAG_SET_DEFAULT(UseAES, true);
aoqi@0:       }
aoqi@0:       if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
aoqi@0:         FLAG_SET_DEFAULT(UseAESIntrinsics, true);
aoqi@0:       }
aoqi@0:       // we disable both the AES flags if either of them is disabled on the command line
aoqi@0:       if (!UseAES || !UseAESIntrinsics) {
aoqi@0:         FLAG_SET_DEFAULT(UseAES, false);
aoqi@0:         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
aoqi@0:       }
aoqi@0:     } else {
aoqi@0:         if (UseAES || UseAESIntrinsics) {
aoqi@0:           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
aoqi@0:           if (UseAES) {
aoqi@0:             FLAG_SET_DEFAULT(UseAES, false);
aoqi@0:           }
aoqi@0:           if (UseAESIntrinsics) {
aoqi@0:             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
aoqi@0:           }
aoqi@0:         }
aoqi@0:     }
aoqi@0:   } else if (UseAES || UseAESIntrinsics) {
aoqi@0:     warning("AES instructions are not available on this CPU");
aoqi@0:     if (UseAES) {
aoqi@0:       FLAG_SET_DEFAULT(UseAES, false);
aoqi@0:     }
aoqi@0:     if (UseAESIntrinsics) {
aoqi@0:       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
aoqi@0:     }
aoqi@0:   }
aoqi@0: 
aoqi@0:   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
aoqi@0:     (cache_line_size > ContendedPaddingWidth))
aoqi@0:     ContendedPaddingWidth = cache_line_size;
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:   if (PrintMiscellaneous && Verbose) {
aoqi@0:     tty->print("Allocation");
aoqi@0:     if (AllocatePrefetchStyle <= 0) {
aoqi@0:       tty->print_cr(": no prefetching");
aoqi@0:     } else {
aoqi@0:       tty->print(" prefetching: ");
aoqi@0:       if (AllocatePrefetchInstr == 0) {
aoqi@0:           tty->print("PREFETCH");
aoqi@0:       } else if (AllocatePrefetchInstr == 1) {
aoqi@0:           tty->print("BIS");
aoqi@0:       }
aoqi@0:       if (AllocatePrefetchLines > 1) {
aoqi@0:         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
aoqi@0:       } else {
aoqi@0:         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
aoqi@0:       }
aoqi@0:     }
aoqi@0:     if (PrefetchCopyIntervalInBytes > 0) {
aoqi@0:       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
aoqi@0:     }
aoqi@0:     if (PrefetchScanIntervalInBytes > 0) {
aoqi@0:       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
aoqi@0:     }
aoqi@0:     if (PrefetchFieldsAhead > 0) {
aoqi@0:       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
aoqi@0:     }
aoqi@0:     if (ContendedPaddingWidth > 0) {
aoqi@0:       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
aoqi@0:     }
aoqi@0:   }
aoqi@0: #endif // PRODUCT
aoqi@0: }
aoqi@0: 
aoqi@0: void VM_Version::print_features() {
aoqi@0:   tty->print_cr("Version:%s", cpu_features());
aoqi@0: }
aoqi@0: 
aoqi@0: int VM_Version::determine_features() {
aoqi@0:   if (UseV8InstrsOnly) {
aoqi@0:     NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
aoqi@0:     return generic_v8_m;
aoqi@0:   }
aoqi@0: 
aoqi@0:   int features = platform_features(unknown_m); // platform_features() is os_arch specific
aoqi@0: 
aoqi@0:   if (features == unknown_m) {
aoqi@0:     features = generic_v9_m;
aoqi@0:     warning("Cannot recognize SPARC version. Default to V9");
aoqi@0:   }
aoqi@0: 
aoqi@0:   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
aoqi@0:   if (UseNiagaraInstrs) { // Force code generation for Niagara
aoqi@0:     if (is_T_family(features)) {
aoqi@0:       // Happy to accomodate...
aoqi@0:     } else {
aoqi@0:       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
aoqi@0:       features |= T_family_m;
aoqi@0:     }
aoqi@0:   } else {
aoqi@0:     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
aoqi@0:       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
aoqi@0:       features &= ~(T_family_m | T1_model_m);
aoqi@0:     } else {
aoqi@0:       // Happy to accomodate...
aoqi@0:     }
aoqi@0:   }
aoqi@0: 
aoqi@0:   return features;
aoqi@0: }
aoqi@0: 
aoqi@0: static int saved_features = 0;
aoqi@0: 
aoqi@0: void VM_Version::allow_all() {
aoqi@0:   saved_features = _features;
aoqi@0:   _features      = all_features_m;
aoqi@0: }
aoqi@0: 
aoqi@0: void VM_Version::revert() {
aoqi@0:   _features = saved_features;
aoqi@0: }
aoqi@0: 
aoqi@0: unsigned int VM_Version::calc_parallel_worker_threads() {
aoqi@0:   unsigned int result;
aoqi@0:   if (is_M_series()) {
aoqi@0:     // for now, use same gc thread calculation for M-series as for niagara-plus
aoqi@0:     // in future, we may want to tweak parameters for nof_parallel_worker_thread
aoqi@0:     result = nof_parallel_worker_threads(5, 16, 8);
aoqi@0:   } else if (is_niagara_plus()) {
aoqi@0:     result = nof_parallel_worker_threads(5, 16, 8);
aoqi@0:   } else {
aoqi@0:     result = nof_parallel_worker_threads(5, 8, 8);
aoqi@0:   }
aoqi@0:   return result;
aoqi@0: }