duke@435: /*
duke@435:  * Copyright 1999-2006 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: //  On i486 the frame looks as follows:
duke@435: //
duke@435: //  +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435: //  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
duke@435: //  +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435: //
duke@435: //  The FPU registers are mapped with their offset from TOS; therefore the
duke@435: //  status of FPU stack must be updated during code emission.
duke@435: 
duke@435:  public:
duke@435:   static const int pd_c_runtime_reserved_arg_size;
duke@435: 
duke@435:   enum {
duke@435:     nof_xmm_regs = pd_nof_xmm_regs_frame_map,
duke@435:     nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
duke@435:     first_available_sp_in_frame = 0,
duke@435:     frame_pad_in_bytes = 8,
duke@435:     nof_reg_args = 2
duke@435:   };
duke@435: 
duke@435:  private:
duke@435:   static LIR_Opr      _caller_save_xmm_regs [nof_caller_save_xmm_regs];
duke@435: 
duke@435:   static XMMRegister _xmm_regs[nof_xmm_regs];
duke@435: 
duke@435:  public:
duke@435:   static LIR_Opr receiver_opr;
duke@435: 
duke@435:   static LIR_Opr rsi_opr;
duke@435:   static LIR_Opr rdi_opr;
duke@435:   static LIR_Opr rbx_opr;
duke@435:   static LIR_Opr rax_opr;
duke@435:   static LIR_Opr rdx_opr;
duke@435:   static LIR_Opr rcx_opr;
duke@435:   static LIR_Opr rsp_opr;
duke@435:   static LIR_Opr rbp_opr;
duke@435: 
duke@435:   static LIR_Opr rsi_oop_opr;
duke@435:   static LIR_Opr rdi_oop_opr;
duke@435:   static LIR_Opr rbx_oop_opr;
duke@435:   static LIR_Opr rax_oop_opr;
duke@435:   static LIR_Opr rdx_oop_opr;
duke@435:   static LIR_Opr rcx_oop_opr;
duke@435: 
duke@435:   static LIR_Opr rax_rdx_long_opr;
duke@435:   static LIR_Opr rbx_rcx_long_opr;
duke@435:   static LIR_Opr fpu0_float_opr;
duke@435:   static LIR_Opr fpu0_double_opr;
duke@435:   static LIR_Opr xmm0_float_opr;
duke@435:   static LIR_Opr xmm0_double_opr;
duke@435: 
duke@435:   static LIR_Opr as_long_opr(Register r, Register r2) {
duke@435:     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
duke@435:   }
duke@435: 
duke@435:   // VMReg name for spilled physical FPU stack slot n
duke@435:   static VMReg fpu_regname (int n);
duke@435: 
duke@435:   static XMMRegister nr2xmmreg(int rnr);
duke@435: 
duke@435:   static bool is_caller_save_register (LIR_Opr opr) { return true; }
duke@435:   static bool is_caller_save_register (Register r) { return true; }
duke@435: 
duke@435:   static LIR_Opr caller_save_xmm_reg_at(int i) {
duke@435:     assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
duke@435:     return _caller_save_xmm_regs[i];
duke@435:   }