twisti@4323: /* twisti@4323: * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. twisti@4323: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. twisti@4323: * twisti@4323: * This code is free software; you can redistribute it and/or modify it twisti@4323: * under the terms of the GNU General Public License version 2 only, as twisti@4323: * published by the Free Software Foundation. twisti@4323: * twisti@4323: * This code is distributed in the hope that it will be useful, but WITHOUT twisti@4323: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or twisti@4323: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License twisti@4323: * version 2 for more details (a copy is included in the LICENSE file that twisti@4323: * accompanied this code). twisti@4323: * twisti@4323: * You should have received a copy of the GNU General Public License version twisti@4323: * 2 along with this work; if not, write to the Free Software Foundation, twisti@4323: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. twisti@4323: * twisti@4323: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA twisti@4323: * or visit www.oracle.com if you need additional information or have any twisti@4323: * questions. twisti@4323: * twisti@4323: */ twisti@4323: twisti@4323: #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP twisti@4323: #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP twisti@4323: twisti@4323: #include "asm/assembler.hpp" twisti@4323: twisti@4323: // promises that the system will not use traps 16-31 twisti@4323: #define ST_RESERVED_FOR_USER_0 0x10 twisti@4323: twisti@4323: class BiasedLockingCounters; twisti@4323: twisti@4323: twisti@4323: // Register aliases for parts of the system: twisti@4323: twisti@4323: // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe twisti@4323: // across context switches in V8+ ABI. Of course, there are no 64 bit regs twisti@4323: // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. twisti@4323: twisti@4323: // g2-g4 are scratch registers called "application globals". Their twisti@4323: // meaning is reserved to the "compilation system"--which means us! twisti@4323: // They are are not supposed to be touched by ordinary C code, although twisti@4323: // highly-optimized C code might steal them for temps. They are safe twisti@4323: // across thread switches, and the ABI requires that they be safe twisti@4323: // across function calls. twisti@4323: // twisti@4323: // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered twisti@4323: // across func calls, and V8+ also allows g5 to be clobbered across twisti@4323: // func calls. Also, g1 and g5 can get touched while doing shared twisti@4323: // library loading. twisti@4323: // twisti@4323: // We must not touch g7 (it is the thread-self register) and g6 is twisti@4323: // reserved for certain tools. g0, of course, is always zero. twisti@4323: // twisti@4323: // (Sources: SunSoft Compilers Group, thread library engineers.) twisti@4323: twisti@4323: // %%%% The interpreter should be revisited to reduce global scratch regs. twisti@4323: twisti@4323: // This global always holds the current JavaThread pointer: twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, G2_thread , G2); twisti@4323: REGISTER_DECLARATION(Register, G6_heapbase , G6); twisti@4323: twisti@4323: // The following globals are part of the Java calling convention: twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, G5_method , G5); twisti@4323: REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); twisti@4323: REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); twisti@4323: twisti@4323: // The following globals are used for the new C1 & interpreter calling convention: twisti@4323: REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument twisti@4323: twisti@4323: // This local is used to preserve G2_thread in the interpreter and in stubs: twisti@4323: REGISTER_DECLARATION(Register, L7_thread_cache , L7); twisti@4323: twisti@4323: // These globals are used as scratch registers in the interpreter: twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch twisti@4323: REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME twisti@4323: REGISTER_DECLARATION(Register, G3_scratch , G3); twisti@4323: REGISTER_DECLARATION(Register, G4_scratch , G4); twisti@4323: twisti@4323: // These globals are used as short-lived scratch registers in the compiler: twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, Gtemp , G5); twisti@4323: twisti@4323: // JSR 292 fixed register usages: twisti@4323: REGISTER_DECLARATION(Register, G5_method_type , G5); twisti@4323: REGISTER_DECLARATION(Register, G3_method_handle , G3); twisti@4323: REGISTER_DECLARATION(Register, L7_mh_SP_save , L7); twisti@4323: twisti@4323: // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, twisti@4323: // because a single patchable "set" instruction (NativeMovConstReg, twisti@4323: // or NativeMovConstPatching for compiler1) instruction twisti@4323: // serves to set up either quantity, depending on whether the compiled twisti@4323: // call site is an inline cache or is megamorphic. See the function twisti@4323: // CompiledIC::set_to_megamorphic. twisti@4323: // twisti@4323: // If a inline cache targets an interpreted method, then the twisti@4323: // G5 register will be used twice during the call. First, twisti@4323: // the call site will be patched to load a compiledICHolder twisti@4323: // into G5. (This is an ordered pair of ic_klass, method.) twisti@4323: // The c2i adapter will first check the ic_klass, then load twisti@4323: // G5_method with the method part of the pair just before twisti@4323: // jumping into the interpreter. twisti@4323: // twisti@4323: // Note that G5_method is only the method-self for the interpreter, twisti@4323: // and is logically unrelated to G5_megamorphic_method. twisti@4323: // twisti@4323: // Invariants on G2_thread (the JavaThread pointer): twisti@4323: // - it should not be used for any other purpose anywhere twisti@4323: // - it must be re-initialized by StubRoutines::call_stub() twisti@4323: // - it must be preserved around every use of call_VM twisti@4323: twisti@4323: // We can consider using g2/g3/g4 to cache more values than the twisti@4323: // JavaThread, such as the card-marking base or perhaps pointers into twisti@4323: // Eden. It's something of a waste to use them as scratch temporaries, twisti@4323: // since they are not supposed to be volatile. (Of course, if we find twisti@4323: // that Java doesn't benefit from application globals, then we can just twisti@4323: // use them as ordinary temporaries.) twisti@4323: // twisti@4323: // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, twisti@4323: // it makes sense to use them routinely for procedure linkage, twisti@4323: // whenever the On registers are not applicable. Examples: G5_method, twisti@4323: // G5_inline_cache_klass, and a double handful of miscellaneous compiler twisti@4323: // stubs. This means that compiler stubs, etc., should be kept to a twisti@4323: // maximum of two or three G-register arguments. twisti@4323: twisti@4323: twisti@4323: // stub frames twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself twisti@4323: twisti@4323: // Interpreter frames twisti@4323: twisti@4323: #ifdef CC_INTERP twisti@4323: REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer twisti@4323: REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch twisti@4323: REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) twisti@4323: REGISTER_DECLARATION(Register, L2_scratch , L2); twisti@4323: REGISTER_DECLARATION(Register, L3_scratch , L3); twisti@4323: REGISTER_DECLARATION(Register, L4_scratch , L4); twisti@4323: REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses twisti@4323: REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses twisti@4323: REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache twisti@4323: REGISTER_DECLARATION(Register, O5_savedSP , O5); twisti@4323: REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply twisti@4323: // a copy SP, so in 64-bit it's a biased value. The bias twisti@4323: // is added and removed as needed in the frame code. twisti@4323: // Interface to signature handler twisti@4323: REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler twisti@4323: REGISTER_DECLARATION(Register, Lmethod , L6); // Method* when calling signature handler twisti@4323: twisti@4323: #else twisti@4323: REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer twisti@4323: REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode twisti@4323: REGISTER_DECLARATION(Register, Lmethod , L2); twisti@4323: REGISTER_DECLARATION(Register, Llocals , L3); twisti@4323: REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler twisti@4323: // must match Llocals in asm interpreter twisti@4323: REGISTER_DECLARATION(Register, Lmonitors , L4); twisti@4323: REGISTER_DECLARATION(Register, Lbyte_code , L5); twisti@4323: // When calling out from the interpreter we record SP so that we can remove any extra stack twisti@4323: // space allocated during adapter transitions. This register is only live from the point twisti@4323: // of the call until we return. twisti@4323: REGISTER_DECLARATION(Register, Llast_SP , L5); twisti@4323: REGISTER_DECLARATION(Register, Lscratch , L5); twisti@4323: REGISTER_DECLARATION(Register, Lscratch2 , L6); twisti@4323: REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache twisti@4323: twisti@4323: REGISTER_DECLARATION(Register, O5_savedSP , O5); twisti@4323: REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply twisti@4323: // a copy SP, so in 64-bit it's a biased value. The bias twisti@4323: // is added and removed as needed in the frame code. twisti@4323: REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables twisti@4323: REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode twisti@4323: REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data twisti@4323: #endif /* CC_INTERP */ twisti@4323: twisti@4323: // NOTE: Lscratch2 and LcpoolCache point to the same registers in twisti@4323: // the interpreter code. If Lscratch2 needs to be used for some twisti@4323: // purpose than LcpoolCache should be restore after that for twisti@4323: // the interpreter to work right twisti@4323: // (These assignments must be compatible with L7_thread_cache; see above.) twisti@4323: twisti@4323: // Since Lbcp points into the middle of the method object, twisti@4323: // it is temporarily converted into a "bcx" during GC. twisti@4323: twisti@4323: // Exception processing twisti@4323: // These registers are passed into exception handlers. twisti@4323: // All exception handlers require the exception object being thrown. twisti@4323: // In addition, an nmethod's exception handler must be passed twisti@4323: // the address of the call site within the nmethod, to allow twisti@4323: // proper selection of the applicable catch block. twisti@4323: // (Interpreter frames use their own bcp() for this purpose.) twisti@4323: // twisti@4323: // The Oissuing_pc value is not always needed. When jumping to a twisti@4323: // handler that is known to be interpreted, the Oissuing_pc value can be twisti@4323: // omitted. An actual catch block in compiled code receives (from its twisti@4323: // nmethod's exception handler) the thrown exception in the Oexception, twisti@4323: // but it doesn't need the Oissuing_pc. twisti@4323: // twisti@4323: // If an exception handler (either interpreted or compiled) twisti@4323: // discovers there is no applicable catch block, it updates twisti@4323: // the Oissuing_pc to the continuation PC of its own caller, twisti@4323: // pops back to that caller's stack frame, and executes that twisti@4323: // caller's exception handler. Obviously, this process will twisti@4323: // iterate until the control stack is popped back to a method twisti@4323: // containing an applicable catch block. A key invariant is twisti@4323: // that the Oissuing_pc value is always a value local to twisti@4323: // the method whose exception handler is currently executing. twisti@4323: // twisti@4323: // Note: The issuing PC value is __not__ a raw return address (I7 value). twisti@4323: // It is a "return pc", the address __following__ the call. twisti@4323: // Raw return addresses are converted to issuing PCs by frame::pc(), twisti@4323: // or by stubs. Issuing PCs can be used directly with PC range tables. twisti@4323: // twisti@4323: REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown twisti@4323: REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from twisti@4323: twisti@4323: twisti@4323: // These must occur after the declarations above twisti@4323: #ifndef DONT_USE_REGISTER_DEFINES twisti@4323: twisti@4323: #define Gthread AS_REGISTER(Register, Gthread) twisti@4323: #define Gmethod AS_REGISTER(Register, Gmethod) twisti@4323: #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) twisti@4323: #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) twisti@4323: #define Gargs AS_REGISTER(Register, Gargs) twisti@4323: #define Lthread_cache AS_REGISTER(Register, Lthread_cache) twisti@4323: #define Gframe_size AS_REGISTER(Register, Gframe_size) twisti@4323: #define Gtemp AS_REGISTER(Register, Gtemp) twisti@4323: twisti@4323: #ifdef CC_INTERP twisti@4323: #define Lstate AS_REGISTER(Register, Lstate) twisti@4323: #define Lesp AS_REGISTER(Register, Lesp) twisti@4323: #define L1_scratch AS_REGISTER(Register, L1_scratch) twisti@4323: #define Lmirror AS_REGISTER(Register, Lmirror) twisti@4323: #define L2_scratch AS_REGISTER(Register, L2_scratch) twisti@4323: #define L3_scratch AS_REGISTER(Register, L3_scratch) twisti@4323: #define L4_scratch AS_REGISTER(Register, L4_scratch) twisti@4323: #define Lscratch AS_REGISTER(Register, Lscratch) twisti@4323: #define Lscratch2 AS_REGISTER(Register, Lscratch2) twisti@4323: #define L7_scratch AS_REGISTER(Register, L7_scratch) twisti@4323: #define Ostate AS_REGISTER(Register, Ostate) twisti@4323: #else twisti@4323: #define Lesp AS_REGISTER(Register, Lesp) twisti@4323: #define Lbcp AS_REGISTER(Register, Lbcp) twisti@4323: #define Lmethod AS_REGISTER(Register, Lmethod) twisti@4323: #define Llocals AS_REGISTER(Register, Llocals) twisti@4323: #define Lmonitors AS_REGISTER(Register, Lmonitors) twisti@4323: #define Lbyte_code AS_REGISTER(Register, Lbyte_code) twisti@4323: #define Lscratch AS_REGISTER(Register, Lscratch) twisti@4323: #define Lscratch2 AS_REGISTER(Register, Lscratch2) twisti@4323: #define LcpoolCache AS_REGISTER(Register, LcpoolCache) twisti@4323: #endif /* ! CC_INTERP */ twisti@4323: twisti@4323: #define Lentry_args AS_REGISTER(Register, Lentry_args) twisti@4323: #define I5_savedSP AS_REGISTER(Register, I5_savedSP) twisti@4323: #define O5_savedSP AS_REGISTER(Register, O5_savedSP) twisti@4323: #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) twisti@4323: #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) twisti@4323: #define IdispatchTables AS_REGISTER(Register, IdispatchTables) twisti@4323: twisti@4323: #define Oexception AS_REGISTER(Register, Oexception) twisti@4323: #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) twisti@4323: twisti@4323: #endif twisti@4323: twisti@4323: twisti@4323: // Address is an abstraction used to represent a memory location. twisti@4323: // twisti@4323: // Note: A register location is represented via a Register, not twisti@4323: // via an address for efficiency & simplicity reasons. twisti@4323: twisti@4323: class Address VALUE_OBJ_CLASS_SPEC { twisti@4323: private: twisti@4323: Register _base; // Base register. twisti@4323: RegisterOrConstant _index_or_disp; // Index register or constant displacement. twisti@4323: RelocationHolder _rspec; twisti@4323: twisti@4323: public: twisti@4323: Address() : _base(noreg), _index_or_disp(noreg) {} twisti@4323: twisti@4323: Address(Register base, RegisterOrConstant index_or_disp) twisti@4323: : _base(base), twisti@4323: _index_or_disp(index_or_disp) { twisti@4323: } twisti@4323: twisti@4323: Address(Register base, Register index) twisti@4323: : _base(base), twisti@4323: _index_or_disp(index) { twisti@4323: } twisti@4323: twisti@4323: Address(Register base, int disp) twisti@4323: : _base(base), twisti@4323: _index_or_disp(disp) { twisti@4323: } twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@4323: Address(Register base, ByteSize disp) twisti@4323: : _base(base), twisti@4323: _index_or_disp(in_bytes(disp)) { twisti@4323: } twisti@4323: #endif twisti@4323: twisti@4323: // accessors twisti@4323: Register base() const { return _base; } twisti@4323: Register index() const { return _index_or_disp.as_register(); } twisti@4323: int disp() const { return _index_or_disp.as_constant(); } twisti@4323: twisti@4323: bool has_index() const { return _index_or_disp.is_register(); } twisti@4323: bool has_disp() const { return _index_or_disp.is_constant(); } twisti@4323: twisti@4323: bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); } twisti@4323: twisti@4323: const relocInfo::relocType rtype() { return _rspec.type(); } twisti@4323: const RelocationHolder& rspec() { return _rspec; } twisti@4323: twisti@4323: RelocationHolder rspec(int offset) const { twisti@4323: return offset == 0 ? _rspec : _rspec.plus(offset); twisti@4323: } twisti@4323: twisti@4323: inline bool is_simm13(int offset = 0); // check disp+offset for overflow twisti@4323: twisti@4323: Address plus_disp(int plusdisp) const { // bump disp by a small amount twisti@4323: assert(_index_or_disp.is_constant(), "must have a displacement"); twisti@4323: Address a(base(), disp() + plusdisp); twisti@4323: return a; twisti@4323: } twisti@4323: bool is_same_address(Address a) const { twisti@4323: // disregard _rspec twisti@4323: return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp()); twisti@4323: } twisti@4323: twisti@4323: Address after_save() const { twisti@4323: Address a = (*this); twisti@4323: a._base = a._base->after_save(); twisti@4323: return a; twisti@4323: } twisti@4323: twisti@4323: Address after_restore() const { twisti@4323: Address a = (*this); twisti@4323: a._base = a._base->after_restore(); twisti@4323: return a; twisti@4323: } twisti@4323: twisti@4323: // Convert the raw encoding form into the form expected by the twisti@4323: // constructor for Address. twisti@4323: static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); twisti@4323: twisti@4323: friend class Assembler; twisti@4323: }; twisti@4323: twisti@4323: twisti@4323: class AddressLiteral VALUE_OBJ_CLASS_SPEC { twisti@4323: private: twisti@4323: address _address; twisti@4323: RelocationHolder _rspec; twisti@4323: twisti@4323: RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { twisti@4323: switch (rtype) { twisti@4323: case relocInfo::external_word_type: twisti@4323: return external_word_Relocation::spec(addr); twisti@4323: case relocInfo::internal_word_type: twisti@4323: return internal_word_Relocation::spec(addr); twisti@4323: #ifdef _LP64 twisti@4323: case relocInfo::opt_virtual_call_type: twisti@4323: return opt_virtual_call_Relocation::spec(); twisti@4323: case relocInfo::static_call_type: twisti@4323: return static_call_Relocation::spec(); twisti@4323: case relocInfo::runtime_call_type: twisti@4323: return runtime_call_Relocation::spec(); twisti@4323: #endif twisti@4323: case relocInfo::none: twisti@4323: return RelocationHolder(); twisti@4323: default: twisti@4323: ShouldNotReachHere(); twisti@4323: return RelocationHolder(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: protected: twisti@4323: // creation twisti@4323: AddressLiteral() : _address(NULL), _rspec(NULL) {} twisti@4323: twisti@4323: public: twisti@4323: AddressLiteral(address addr, RelocationHolder const& rspec) twisti@4323: : _address(addr), twisti@4323: _rspec(rspec) {} twisti@4323: twisti@4323: // Some constructors to avoid casting at the call site. twisti@4323: AddressLiteral(jobject obj, RelocationHolder const& rspec) twisti@4323: : _address((address) obj), twisti@4323: _rspec(rspec) {} twisti@4323: twisti@4323: AddressLiteral(intptr_t value, RelocationHolder const& rspec) twisti@4323: : _address((address) value), twisti@4323: _rspec(rspec) {} twisti@4323: twisti@4323: AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: // Some constructors to avoid casting at the call site. twisti@4323: AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: // 32-bit complains about a multiple declaration for int*. twisti@4323: AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: #endif twisti@4323: twisti@4323: AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) twisti@4323: : _address((address) addr), twisti@4323: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@4323: twisti@4323: intptr_t value() const { return (intptr_t) _address; } twisti@4323: int low10() const; twisti@4323: twisti@4323: const relocInfo::relocType rtype() const { return _rspec.type(); } twisti@4323: const RelocationHolder& rspec() const { return _rspec; } twisti@4323: twisti@4323: RelocationHolder rspec(int offset) const { twisti@4323: return offset == 0 ? _rspec : _rspec.plus(offset); twisti@4323: } twisti@4323: }; twisti@4323: twisti@4323: // Convenience classes twisti@4323: class ExternalAddress: public AddressLiteral { twisti@4323: private: twisti@4323: static relocInfo::relocType reloc_for_target(address target) { twisti@4323: // Sometimes ExternalAddress is used for values which aren't twisti@4323: // exactly addresses, like the card table base. twisti@4323: // external_word_type can't be used for values in the first page twisti@4323: // so just skip the reloc in that case. twisti@4323: return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; twisti@4323: } twisti@4323: twisti@4323: public: twisti@4323: ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} twisti@4323: ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {} twisti@4323: }; twisti@4323: twisti@4323: inline Address RegisterImpl::address_in_saved_window() const { twisti@4323: return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: // Argument is an abstraction used to represent an outgoing twisti@4323: // actual argument or an incoming formal parameter, whether twisti@4323: // it resides in memory or in a register, in a manner consistent twisti@4323: // with the SPARC Application Binary Interface, or ABI. This is twisti@4323: // often referred to as the native or C calling convention. twisti@4323: twisti@4323: class Argument VALUE_OBJ_CLASS_SPEC { twisti@4323: private: twisti@4323: int _number; twisti@4323: bool _is_in; twisti@4323: twisti@4323: public: twisti@4323: #ifdef _LP64 twisti@4323: enum { twisti@4323: n_register_parameters = 6, // only 6 registers may contain integer parameters twisti@4323: n_float_register_parameters = 16 // Can have up to 16 floating registers twisti@4323: }; twisti@4323: #else twisti@4323: enum { twisti@4323: n_register_parameters = 6 // only 6 registers may contain integer parameters twisti@4323: }; twisti@4323: #endif twisti@4323: twisti@4323: // creation twisti@4323: Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} twisti@4323: twisti@4323: int number() const { return _number; } twisti@4323: bool is_in() const { return _is_in; } twisti@4323: bool is_out() const { return !is_in(); } twisti@4323: twisti@4323: Argument successor() const { return Argument(number() + 1, is_in()); } twisti@4323: Argument as_in() const { return Argument(number(), true ); } twisti@4323: Argument as_out() const { return Argument(number(), false); } twisti@4323: twisti@4323: // locating register-based arguments: twisti@4323: bool is_register() const { return _number < n_register_parameters; } twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: // locating Floating Point register-based arguments: twisti@4323: bool is_float_register() const { return _number < n_float_register_parameters; } twisti@4323: twisti@4323: FloatRegister as_float_register() const { twisti@4323: assert(is_float_register(), "must be a register argument"); twisti@4323: return as_FloatRegister(( number() *2 ) + 1); twisti@4323: } twisti@4323: FloatRegister as_double_register() const { twisti@4323: assert(is_float_register(), "must be a register argument"); twisti@4323: return as_FloatRegister(( number() *2 )); twisti@4323: } twisti@4323: #endif twisti@4323: twisti@4323: Register as_register() const { twisti@4323: assert(is_register(), "must be a register argument"); twisti@4323: return is_in() ? as_iRegister(number()) : as_oRegister(number()); twisti@4323: } twisti@4323: twisti@4323: // locating memory-based arguments twisti@4323: Address as_address() const { twisti@4323: assert(!is_register(), "must be a memory argument"); twisti@4323: return address_in_frame(); twisti@4323: } twisti@4323: twisti@4323: // When applied to a register-based argument, give the corresponding address twisti@4323: // into the 6-word area "into which callee may store register arguments" twisti@4323: // (This is a different place than the corresponding register-save area location.) twisti@4323: Address address_in_frame() const; twisti@4323: twisti@4323: // debugging twisti@4323: const char* name() const; twisti@4323: twisti@4323: friend class Assembler; twisti@4323: }; twisti@4323: twisti@4323: twisti@4323: class RegistersForDebugging : public StackObj { twisti@4323: public: twisti@4323: intptr_t i[8], l[8], o[8], g[8]; twisti@4323: float f[32]; twisti@4323: double d[32]; twisti@4323: twisti@4323: void print(outputStream* s); twisti@4323: twisti@4323: static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } twisti@4323: static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } twisti@4323: static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } twisti@4323: static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } twisti@4323: static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } twisti@4323: static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } twisti@4323: twisti@4323: // gen asm code to save regs twisti@4323: static void save_registers(MacroAssembler* a); twisti@4323: twisti@4323: // restore global registers in case C code disturbed them twisti@4323: static void restore_registers(MacroAssembler* a, Register r); twisti@4323: }; twisti@4323: twisti@4323: twisti@4323: // MacroAssembler extends Assembler by a few frequently used macros. twisti@4323: // twisti@4323: // Most of the standard SPARC synthetic ops are defined here. twisti@4323: // Instructions for which a 'better' code sequence exists depending twisti@4323: // on arguments should also go in here. twisti@4323: twisti@4323: #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) twisti@4323: #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) twisti@4323: #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) twisti@4323: #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) twisti@4323: twisti@4323: twisti@4323: class MacroAssembler : public Assembler { twisti@4323: // code patchers need various routines like inv_wdisp() twisti@4323: friend class NativeInstruction; twisti@4323: friend class NativeGeneralJump; twisti@4323: friend class Relocation; twisti@4323: friend class Label; twisti@4323: twisti@4323: protected: twisti@4323: static void print_instruction(int inst); twisti@4323: static int patched_branch(int dest_pos, int inst, int inst_pos); twisti@4323: static int branch_destination(int inst, int pos); twisti@4323: twisti@4323: // Support for VM calls twisti@4323: // This is the base routine called by the different versions of call_VM_leaf. The interpreter twisti@4323: // may customize this version by overriding it for its purposes (e.g., to save/restore twisti@4323: // additional registers when doing a VM call). twisti@4323: #ifdef CC_INTERP twisti@4323: #define VIRTUAL twisti@4323: #else twisti@4323: #define VIRTUAL virtual twisti@4323: #endif twisti@4323: twisti@4323: VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); twisti@4323: twisti@4323: // twisti@4323: // It is imperative that all calls into the VM are handled via the call_VM macros. twisti@4323: // They make sure that the stack linkage is setup correctly. call_VM's correspond twisti@4323: // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. twisti@4323: // twisti@4323: // This is the base routine called by the different versions of call_VM. The interpreter twisti@4323: // may customize this version by overriding it for its purposes (e.g., to save/restore twisti@4323: // additional registers when doing a VM call). twisti@4323: // twisti@4323: // A non-volatile java_thread_cache register should be specified so twisti@4323: // that the G2_thread value can be preserved across the call. twisti@4323: // (If java_thread_cache is noreg, then a slow get_thread call twisti@4323: // will re-initialize the G2_thread.) call_VM_base returns the register that contains the twisti@4323: // thread. twisti@4323: // twisti@4323: // If no last_java_sp is specified (noreg) than SP will be used instead. twisti@4323: twisti@4323: virtual void call_VM_base( twisti@4323: Register oop_result, // where an oop-result ends up if any; use noreg otherwise twisti@4323: Register java_thread_cache, // the thread if computed before ; use noreg otherwise twisti@4323: Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise twisti@4323: address entry_point, // the entry point twisti@4323: int number_of_arguments, // the number of arguments (w/o thread) to pop after call twisti@4323: bool check_exception=true // flag which indicates if exception should be checked twisti@4323: ); twisti@4323: twisti@4323: // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. twisti@4323: // The implementation is only non-empty for the InterpreterMacroAssembler, twisti@4323: // as only the interpreter handles and ForceEarlyReturn PopFrame requests. twisti@4323: virtual void check_and_handle_popframe(Register scratch_reg); twisti@4323: virtual void check_and_handle_earlyret(Register scratch_reg); twisti@4323: twisti@4323: public: twisti@4323: MacroAssembler(CodeBuffer* code) : Assembler(code) {} twisti@4323: twisti@4323: // Support for NULL-checks twisti@4323: // twisti@4323: // Generates code that causes a NULL OS exception if the content of reg is NULL. twisti@4323: // If the accessed location is M[reg + offset] and the offset is known, provide the twisti@4323: // offset. No explicit code generation is needed if the offset is within a certain twisti@4323: // range (0 <= offset <= page_size). twisti@4323: // twisti@4323: // %%%%%% Currently not done for SPARC twisti@4323: twisti@4323: void null_check(Register reg, int offset = -1); twisti@4323: static bool needs_explicit_null_check(intptr_t offset); twisti@4323: twisti@4323: // support for delayed instructions twisti@4323: MacroAssembler* delayed() { Assembler::delayed(); return this; } twisti@4323: twisti@4323: // branches that use right instruction for v8 vs. v9 twisti@4323: inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void br( Condition c, bool a, Predict p, Label& L ); twisti@4323: twisti@4323: inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void fb( Condition c, bool a, Predict p, Label& L ); twisti@4323: twisti@4323: // compares register with zero (32 bit) and branches (V9 and V8 instructions) twisti@4323: void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn ); twisti@4323: // Compares a pointer register with zero and branches on (not)null. twisti@4323: // Does a test & branch on 32-bit systems and a register-branch on 64-bit. twisti@4323: void br_null ( Register s1, bool a, Predict p, Label& L ); twisti@4323: void br_notnull( Register s1, bool a, Predict p, Label& L ); twisti@4323: twisti@4323: // twisti@4323: // Compare registers and branch with nop in delay slot or cbcond without delay slot. twisti@4323: // twisti@4323: // ATTENTION: use these instructions with caution because cbcond instruction twisti@4323: // has very short distance: 512 instructions (2Kbyte). twisti@4323: twisti@4323: // Compare integer (32 bit) values (icc only). twisti@4323: void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L); twisti@4323: void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L); twisti@4323: // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64). twisti@4323: void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L); twisti@4323: void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L); twisti@4323: twisti@4323: // Short branch version for compares a pointer pwith zero. twisti@4323: void br_null_short ( Register s1, Predict p, Label& L ); twisti@4323: void br_notnull_short( Register s1, Predict p, Label& L ); twisti@4323: twisti@4323: // unconditional short branch twisti@4323: void ba_short(Label& L); twisti@4323: twisti@4323: inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); twisti@4323: twisti@4323: // Branch that tests xcc in LP64 and icc in !LP64 twisti@4323: inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void brx( Condition c, bool a, Predict p, Label& L ); twisti@4323: twisti@4323: // unconditional branch twisti@4323: inline void ba( Label& L ); twisti@4323: twisti@4323: // Branch that tests fp condition codes twisti@4323: inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); twisti@4323: twisti@4323: // get PC the best way twisti@4323: inline int get_pc( Register d ); twisti@4323: twisti@4323: // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) twisti@4323: inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } twisti@4323: inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } twisti@4323: twisti@4323: inline void jmp( Register s1, Register s2 ); twisti@4323: inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); twisti@4323: twisti@4323: // Check if the call target is out of wdisp30 range (relative to the code cache) twisti@4323: static inline bool is_far_target(address d); twisti@4323: inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); twisti@4323: inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); twisti@4323: inline void callr( Register s1, Register s2 ); twisti@4323: inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); twisti@4323: twisti@4323: // Emits nothing on V8 twisti@4323: inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); twisti@4323: inline void iprefetch( Label& L); twisti@4323: twisti@4323: inline void tst( Register s ) { orcc( G0, s, G0 ); } twisti@4323: twisti@4323: #ifdef PRODUCT twisti@4323: inline void ret( bool trace = TraceJumps ) { if (trace) { twisti@4323: mov(I7, O7); // traceable register twisti@4323: JMP(O7, 2 * BytesPerInstWord); twisti@4323: } else { twisti@4323: jmpl( I7, 2 * BytesPerInstWord, G0 ); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); twisti@4323: else jmpl( O7, 2 * BytesPerInstWord, G0 ); } twisti@4323: #else twisti@4323: void ret( bool trace = TraceJumps ); twisti@4323: void retl( bool trace = TraceJumps ); twisti@4323: #endif /* PRODUCT */ twisti@4323: twisti@4323: // Required platform-specific helpers for Label::patch_instructions. twisti@4323: // They _shadow_ the declarations in AbstractAssembler, which are undefined. twisti@4323: void pd_patch_instruction(address branch, address target); twisti@4323: #ifndef PRODUCT twisti@4323: static void pd_print_patched_instruction(address branch); twisti@4323: #endif twisti@4323: twisti@4323: // sethi Macro handles optimizations and relocations twisti@4323: private: twisti@4323: void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); twisti@4323: public: twisti@4323: void sethi(const AddressLiteral& addrlit, Register d); twisti@4323: void patchable_sethi(const AddressLiteral& addrlit, Register d); twisti@4323: twisti@4323: // compute the number of instructions for a sethi/set twisti@4323: static int insts_for_sethi( address a, bool worst_case = false ); twisti@4323: static int worst_case_insts_for_set(); twisti@4323: twisti@4323: // set may be either setsw or setuw (high 32 bits may be zero or sign) twisti@4323: private: twisti@4323: void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); twisti@4323: static int insts_for_internal_set(intptr_t value); twisti@4323: public: twisti@4323: void set(const AddressLiteral& addrlit, Register d); twisti@4323: void set(intptr_t value, Register d); twisti@4323: void set(address addr, Register d, RelocationHolder const& rspec); twisti@4323: static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); } twisti@4323: twisti@4323: void patchable_set(const AddressLiteral& addrlit, Register d); twisti@4323: void patchable_set(intptr_t value, Register d); twisti@4323: void set64(jlong value, Register d, Register tmp); twisti@4323: static int insts_for_set64(jlong value); twisti@4323: twisti@4323: // sign-extend 32 to 64 twisti@4323: inline void signx( Register s, Register d ) { sra( s, G0, d); } twisti@4323: inline void signx( Register d ) { sra( d, G0, d); } twisti@4323: twisti@4323: inline void not1( Register s, Register d ) { xnor( s, G0, d ); } twisti@4323: inline void not1( Register d ) { xnor( d, G0, d ); } twisti@4323: twisti@4323: inline void neg( Register s, Register d ) { sub( G0, s, d ); } twisti@4323: inline void neg( Register d ) { sub( G0, d, d ); } twisti@4323: twisti@4323: inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } twisti@4323: inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } twisti@4323: // Functions for isolating 64 bit atomic swaps for LP64 twisti@4323: // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's twisti@4323: inline void cas_ptr( Register s1, Register s2, Register d) { twisti@4323: #ifdef _LP64 twisti@4323: casx( s1, s2, d ); twisti@4323: #else twisti@4323: cas( s1, s2, d ); twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: // Functions for isolating 64 bit shifts for LP64 twisti@4323: inline void sll_ptr( Register s1, Register s2, Register d ); twisti@4323: inline void sll_ptr( Register s1, int imm6a, Register d ); twisti@4323: inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void srl_ptr( Register s1, Register s2, Register d ); twisti@4323: inline void srl_ptr( Register s1, int imm6a, Register d ); twisti@4323: twisti@4323: // little-endian twisti@4323: inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } twisti@4323: inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } twisti@4323: twisti@4323: inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } twisti@4323: inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } twisti@4323: twisti@4323: inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } twisti@4323: inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } twisti@4323: twisti@4323: using Assembler::add; twisti@4323: inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype); twisti@4323: inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); twisti@4323: inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); twisti@4323: inline void add(const Address& a, Register d, int offset = 0); twisti@4323: twisti@4323: using Assembler::andn; twisti@4323: inline void andn( Register s1, RegisterOrConstant s2, Register d); twisti@4323: twisti@4323: inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } twisti@4323: inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } twisti@4323: twisti@4323: inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } twisti@4323: inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } twisti@4323: twisti@4323: inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } twisti@4323: inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } twisti@4323: twisti@4323: inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } twisti@4323: inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } twisti@4323: twisti@4323: inline void clr( Register d ) { or3( G0, G0, d ); } twisti@4323: twisti@4323: inline void clrb( Register s1, Register s2); twisti@4323: inline void clrh( Register s1, Register s2); twisti@4323: inline void clr( Register s1, Register s2); twisti@4323: inline void clrx( Register s1, Register s2); twisti@4323: twisti@4323: inline void clrb( Register s1, int simm13a); twisti@4323: inline void clrh( Register s1, int simm13a); twisti@4323: inline void clr( Register s1, int simm13a); twisti@4323: inline void clrx( Register s1, int simm13a); twisti@4323: twisti@4323: // copy & clear upper word twisti@4323: inline void clruw( Register s, Register d ) { srl( s, G0, d); } twisti@4323: // clear upper word twisti@4323: inline void clruwu( Register d ) { srl( d, G0, d); } twisti@4323: twisti@4323: using Assembler::ldsb; twisti@4323: using Assembler::ldsh; twisti@4323: using Assembler::ldsw; twisti@4323: using Assembler::ldub; twisti@4323: using Assembler::lduh; twisti@4323: using Assembler::lduw; twisti@4323: using Assembler::ldx; twisti@4323: using Assembler::ldd; twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@4323: inline void ld(Register s1, ByteSize simm13a, Register d); twisti@4323: #endif twisti@4323: twisti@4323: inline void ld(Register s1, Register s2, Register d); twisti@4323: inline void ld(Register s1, int simm13a, Register d); twisti@4323: twisti@4323: inline void ldsb(const Address& a, Register d, int offset = 0); twisti@4323: inline void ldsh(const Address& a, Register d, int offset = 0); twisti@4323: inline void ldsw(const Address& a, Register d, int offset = 0); twisti@4323: inline void ldub(const Address& a, Register d, int offset = 0); twisti@4323: inline void lduh(const Address& a, Register d, int offset = 0); twisti@4323: inline void lduw(const Address& a, Register d, int offset = 0); twisti@4323: inline void ldx( const Address& a, Register d, int offset = 0); twisti@4323: inline void ld( const Address& a, Register d, int offset = 0); twisti@4323: inline void ldd( const Address& a, Register d, int offset = 0); twisti@4323: twisti@4323: inline void ldub(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ldsb(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void lduh(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ldsh(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void lduw(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ldsw(Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ldx( Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ld( Register s1, RegisterOrConstant s2, Register d ); twisti@4323: inline void ldd( Register s1, RegisterOrConstant s2, Register d ); twisti@4323: twisti@4323: using Assembler::ldf; twisti@4323: inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); twisti@4323: inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); twisti@4323: twisti@4323: // membar psuedo instruction. takes into account target memory model. twisti@4323: inline void membar( Assembler::Membar_mask_bits const7a ); twisti@4323: twisti@4323: // returns if membar generates anything. twisti@4323: inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); twisti@4323: twisti@4323: // mov pseudo instructions twisti@4323: inline void mov( Register s, Register d) { twisti@4323: if ( s != d ) or3( G0, s, d); twisti@4323: else assert_not_delayed(); // Put something useful in the delay slot! twisti@4323: } twisti@4323: twisti@4323: inline void mov_or_nop( Register s, Register d) { twisti@4323: if ( s != d ) or3( G0, s, d); twisti@4323: else nop(); twisti@4323: } twisti@4323: twisti@4323: inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } twisti@4323: twisti@4323: using Assembler::prefetch; twisti@4323: inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); twisti@4323: twisti@4323: using Assembler::stb; twisti@4323: using Assembler::sth; twisti@4323: using Assembler::stw; twisti@4323: using Assembler::stx; twisti@4323: using Assembler::std; twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@4323: inline void st(Register d, Register s1, ByteSize simm13a); twisti@4323: #endif twisti@4323: twisti@4323: inline void st(Register d, Register s1, Register s2); twisti@4323: inline void st(Register d, Register s1, int simm13a); twisti@4323: twisti@4323: inline void stb(Register d, const Address& a, int offset = 0 ); twisti@4323: inline void sth(Register d, const Address& a, int offset = 0 ); twisti@4323: inline void stw(Register d, const Address& a, int offset = 0 ); twisti@4323: inline void stx(Register d, const Address& a, int offset = 0 ); twisti@4323: inline void st( Register d, const Address& a, int offset = 0 ); twisti@4323: inline void std(Register d, const Address& a, int offset = 0 ); twisti@4323: twisti@4323: inline void stb(Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: inline void sth(Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: inline void stw(Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: inline void stx(Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: inline void std(Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: inline void st( Register d, Register s1, RegisterOrConstant s2 ); twisti@4323: twisti@4323: using Assembler::stf; twisti@4323: inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); twisti@4323: inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); twisti@4323: twisti@4323: // Note: offset is added to s2. twisti@4323: using Assembler::sub; twisti@4323: inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0); twisti@4323: twisti@4323: using Assembler::swap; twisti@4323: inline void swap(Address& a, Register d, int offset = 0); twisti@4323: twisti@4323: // address pseudos: make these names unlike instruction names to avoid confusion twisti@4323: inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); twisti@4323: inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0); twisti@4323: inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0); twisti@4323: inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0); twisti@4323: inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); twisti@4323: inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); twisti@4323: inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0); twisti@4323: inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0); twisti@4323: inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); twisti@4323: twisti@4323: // ring buffer traceable jumps twisti@4323: twisti@4323: void jmp2( Register r1, Register r2, const char* file, int line ); twisti@4323: void jmp ( Register r1, int offset, const char* file, int line ); twisti@4323: twisti@4323: void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); twisti@4323: void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); twisti@4323: twisti@4323: twisti@4323: // argument pseudos: twisti@4323: twisti@4323: inline void load_argument( Argument& a, Register d ); twisti@4323: inline void store_argument( Register s, Argument& a ); twisti@4323: inline void store_ptr_argument( Register s, Argument& a ); twisti@4323: inline void store_float_argument( FloatRegister s, Argument& a ); twisti@4323: inline void store_double_argument( FloatRegister s, Argument& a ); twisti@4323: inline void store_long_argument( Register s, Argument& a ); twisti@4323: twisti@4323: // handy macros: twisti@4323: twisti@4323: inline void round_to( Register r, int modulus ) { twisti@4323: assert_not_delayed(); twisti@4323: inc( r, modulus - 1 ); twisti@4323: and3( r, -modulus, r ); twisti@4323: } twisti@4323: twisti@4323: // -------------------------------------------------- twisti@4323: twisti@4323: // Functions for isolating 64 bit loads for LP64 twisti@4323: // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's twisti@4323: // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's twisti@4323: inline void ld_ptr(Register s1, Register s2, Register d); twisti@4323: inline void ld_ptr(Register s1, int simm13a, Register d); twisti@4323: inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); twisti@4323: inline void ld_ptr(const Address& a, Register d, int offset = 0); twisti@4323: inline void st_ptr(Register d, Register s1, Register s2); twisti@4323: inline void st_ptr(Register d, Register s1, int simm13a); twisti@4323: inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); twisti@4323: inline void st_ptr(Register d, const Address& a, int offset = 0); twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@4323: inline void ld_ptr(Register s1, ByteSize simm13a, Register d); twisti@4323: inline void st_ptr(Register d, Register s1, ByteSize simm13a); twisti@4323: #endif twisti@4323: twisti@4323: // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's twisti@4323: // st_long will perform std for 32 bit VM's and stx for 64 bit VM's twisti@4323: inline void ld_long(Register s1, Register s2, Register d); twisti@4323: inline void ld_long(Register s1, int simm13a, Register d); twisti@4323: inline void ld_long(Register s1, RegisterOrConstant s2, Register d); twisti@4323: inline void ld_long(const Address& a, Register d, int offset = 0); twisti@4323: inline void st_long(Register d, Register s1, Register s2); twisti@4323: inline void st_long(Register d, Register s1, int simm13a); twisti@4323: inline void st_long(Register d, Register s1, RegisterOrConstant s2); twisti@4323: inline void st_long(Register d, const Address& a, int offset = 0); twisti@4323: twisti@4323: // Helpers for address formation. twisti@4323: // - They emit only a move if s2 is a constant zero. twisti@4323: // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result. twisti@4323: // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant. twisti@4323: RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); twisti@4323: RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); twisti@4323: RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); twisti@4323: twisti@4323: RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) { twisti@4323: if (is_simm13(src.constant_or_zero())) twisti@4323: return src; // register or short constant twisti@4323: guarantee(temp != noreg, "constant offset overflow"); twisti@4323: set(src.as_constant(), temp); twisti@4323: return temp; twisti@4323: } twisti@4323: twisti@4323: // -------------------------------------------------- twisti@4323: twisti@4323: public: twisti@4323: // traps as per trap.h (SPARC ABI?) twisti@4323: twisti@4323: void breakpoint_trap(); twisti@4323: void breakpoint_trap(Condition c, CC cc); twisti@4323: void flush_windows_trap(); twisti@4323: void clean_windows_trap(); twisti@4323: void get_psr_trap(); twisti@4323: void set_psr_trap(); twisti@4323: twisti@4323: // V8/V9 flush_windows twisti@4323: void flush_windows(); twisti@4323: twisti@4323: // Support for serializing memory accesses between threads twisti@4323: void serialize_memory(Register thread, Register tmp1, Register tmp2); twisti@4323: twisti@4323: // Stack frame creation/removal twisti@4323: void enter(); twisti@4323: void leave(); twisti@4323: twisti@4323: // V8/V9 integer multiply twisti@4323: void mult(Register s1, Register s2, Register d); twisti@4323: void mult(Register s1, int simm13a, Register d); twisti@4323: twisti@4323: // V8/V9 read and write of condition codes. twisti@4323: void read_ccr(Register d); twisti@4323: void write_ccr(Register s); twisti@4323: twisti@4323: // Manipulation of C++ bools twisti@4323: // These are idioms to flag the need for care with accessing bools but on twisti@4323: // this platform we assume byte size twisti@4323: twisti@4323: inline void stbool(Register d, const Address& a) { stb(d, a); } twisti@4323: inline void ldbool(const Address& a, Register d) { ldub(a, d); } twisti@4323: inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } twisti@4323: twisti@4323: // klass oop manipulations if compressed twisti@4323: void load_klass(Register src_oop, Register klass); twisti@4323: void store_klass(Register klass, Register dst_oop); twisti@4323: void store_klass_gap(Register s, Register dst_oop); twisti@4323: twisti@4323: // oop manipulations twisti@4323: void load_heap_oop(const Address& s, Register d); twisti@4323: void load_heap_oop(Register s1, Register s2, Register d); twisti@4323: void load_heap_oop(Register s1, int simm13a, Register d); twisti@4323: void load_heap_oop(Register s1, RegisterOrConstant s2, Register d); twisti@4323: void store_heap_oop(Register d, Register s1, Register s2); twisti@4323: void store_heap_oop(Register d, Register s1, int simm13a); twisti@4323: void store_heap_oop(Register d, const Address& a, int offset = 0); twisti@4323: twisti@4323: void encode_heap_oop(Register src, Register dst); twisti@4323: void encode_heap_oop(Register r) { twisti@4323: encode_heap_oop(r, r); twisti@4323: } twisti@4323: void decode_heap_oop(Register src, Register dst); twisti@4323: void decode_heap_oop(Register r) { twisti@4323: decode_heap_oop(r, r); twisti@4323: } twisti@4323: void encode_heap_oop_not_null(Register r); twisti@4323: void decode_heap_oop_not_null(Register r); twisti@4323: void encode_heap_oop_not_null(Register src, Register dst); twisti@4323: void decode_heap_oop_not_null(Register src, Register dst); twisti@4323: twisti@4323: void encode_klass_not_null(Register r); twisti@4323: void decode_klass_not_null(Register r); twisti@4323: void encode_klass_not_null(Register src, Register dst); twisti@4323: void decode_klass_not_null(Register src, Register dst); twisti@4323: twisti@4323: // Support for managing the JavaThread pointer (i.e.; the reference to twisti@4323: // thread-local information). twisti@4323: void get_thread(); // load G2_thread twisti@4323: void verify_thread(); // verify G2_thread contents twisti@4323: void save_thread (const Register threache); // save to cache twisti@4323: void restore_thread(const Register thread_cache); // restore from cache twisti@4323: twisti@4323: // Support for last Java frame (but use call_VM instead where possible) twisti@4323: void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); twisti@4323: void reset_last_Java_frame(void); twisti@4323: twisti@4323: // Call into the VM. twisti@4323: // Passes the thread pointer (in O0) as a prepended argument. twisti@4323: // Makes sure oop return values are visible to the GC. twisti@4323: void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); twisti@4323: twisti@4323: // these overloadings are not presently used on SPARC: twisti@4323: void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); twisti@4323: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); twisti@4323: twisti@4323: void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); twisti@4323: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); twisti@4323: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); twisti@4323: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); twisti@4323: twisti@4323: void get_vm_result (Register oop_result); twisti@4323: void get_vm_result_2(Register metadata_result); twisti@4323: twisti@4323: // vm result is currently getting hijacked to for oop preservation twisti@4323: void set_vm_result(Register oop_result); twisti@4323: twisti@4323: // Emit the CompiledIC call idiom twisti@4323: void ic_call(address entry, bool emit_delay = true); twisti@4323: twisti@4323: // if call_VM_base was called with check_exceptions=false, then call twisti@4323: // check_and_forward_exception to handle exceptions when it is safe twisti@4323: void check_and_forward_exception(Register scratch_reg); twisti@4323: twisti@4323: private: twisti@4323: // For V8 twisti@4323: void read_ccr_trap(Register ccr_save); twisti@4323: void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // For V8 debugging. Uses V8 instruction sequence and checks twisti@4323: // result with V9 insturctions rdccr and wrccr. twisti@4323: // Uses Gscatch and Gscatch2 twisti@4323: void read_ccr_v8_assert(Register ccr_save); twisti@4323: void write_ccr_v8_assert(Register ccr_save); twisti@4323: #endif // ASSERT twisti@4323: twisti@4323: public: twisti@4323: twisti@4323: // Write to card table for - register is destroyed afterwards. twisti@4323: void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); twisti@4323: twisti@4323: void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); twisti@4323: twisti@4323: #ifndef SERIALGC twisti@4323: // General G1 pre-barrier generator. twisti@4323: void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs); twisti@4323: twisti@4323: // General G1 post-barrier generator twisti@4323: void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); twisti@4323: #endif // SERIALGC twisti@4323: twisti@4323: // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack twisti@4323: void push_fTOS(); twisti@4323: twisti@4323: // pops double TOS element from CPU stack and pushes on FPU stack twisti@4323: void pop_fTOS(); twisti@4323: twisti@4323: void empty_FPU_stack(); twisti@4323: twisti@4323: void push_IU_state(); twisti@4323: void pop_IU_state(); twisti@4323: twisti@4323: void push_FPU_state(); twisti@4323: void pop_FPU_state(); twisti@4323: twisti@4323: void push_CPU_state(); twisti@4323: void pop_CPU_state(); twisti@4323: twisti@4323: // if heap base register is used - reinit it with the correct value twisti@4323: void reinit_heapbase(); twisti@4323: twisti@4323: // Debugging twisti@4323: void _verify_oop(Register reg, const char * msg, const char * file, int line); twisti@4323: void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); twisti@4323: twisti@4323: // TODO: verify_method and klass metadata (compare against vptr?) twisti@4323: void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} twisti@4323: void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} twisti@4323: twisti@4323: #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) twisti@4323: #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) twisti@4323: #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) twisti@4323: #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) twisti@4323: twisti@4323: // only if +VerifyOops twisti@4323: void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); twisti@4323: // only if +VerifyFPU twisti@4323: void stop(const char* msg); // prints msg, dumps registers and stops execution twisti@4323: void warn(const char* msg); // prints msg, but don't stop twisti@4323: void untested(const char* what = ""); twisti@4323: void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } twisti@4323: void should_not_reach_here() { stop("should not reach here"); } twisti@4323: void print_CPU_state(); twisti@4323: twisti@4323: // oops in code twisti@4323: AddressLiteral allocate_oop_address(jobject obj); // allocate_index twisti@4323: AddressLiteral constant_oop_address(jobject obj); // find_index twisti@4323: inline void set_oop (jobject obj, Register d); // uses allocate_oop_address twisti@4323: inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address twisti@4323: inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address twisti@4323: twisti@4323: // metadata in code that we have to keep track of twisti@4323: AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index twisti@4323: AddressLiteral constant_metadata_address(Metadata* obj); // find_index twisti@4323: inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address twisti@4323: inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address twisti@4323: inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address twisti@4323: twisti@4323: void set_narrow_oop( jobject obj, Register d ); twisti@4323: void set_narrow_klass( Klass* k, Register d ); twisti@4323: twisti@4323: // nop padding twisti@4323: void align(int modulus); twisti@4323: twisti@4323: // declare a safepoint twisti@4323: void safepoint(); twisti@4323: twisti@4323: // factor out part of stop into subroutine to save space twisti@4323: void stop_subroutine(); twisti@4323: // factor out part of verify_oop into subroutine to save space twisti@4323: void verify_oop_subroutine(); twisti@4323: twisti@4323: // side-door communication with signalHandler in os_solaris.cpp twisti@4323: static address _verify_oop_implicit_branch[3]; twisti@4323: twisti@4323: int total_frame_size_in_bytes(int extraWords); twisti@4323: twisti@4323: // used when extraWords known statically twisti@4323: void save_frame(int extraWords = 0); twisti@4323: void save_frame_c1(int size_in_bytes); twisti@4323: // make a frame, and simultaneously pass up one or two register value twisti@4323: // into the new register window twisti@4323: void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); twisti@4323: twisti@4323: // give no. (outgoing) params, calc # of words will need on frame twisti@4323: void calc_mem_param_words(Register Rparam_words, Register Rresult); twisti@4323: twisti@4323: // used to calculate frame size dynamically twisti@4323: // result is in bytes and must be negated for save inst twisti@4323: void calc_frame_size(Register extraWords, Register resultReg); twisti@4323: twisti@4323: // calc and also save twisti@4323: void calc_frame_size_and_save(Register extraWords, Register resultReg); twisti@4323: twisti@4323: static void debug(char* msg, RegistersForDebugging* outWindow); twisti@4323: twisti@4323: // implementations of bytecodes used by both interpreter and compiler twisti@4323: twisti@4323: void lcmp( Register Ra_hi, Register Ra_low, twisti@4323: Register Rb_hi, Register Rb_low, twisti@4323: Register Rresult); twisti@4323: twisti@4323: void lneg( Register Rhi, Register Rlow ); twisti@4323: twisti@4323: void lshl( Register Rin_high, Register Rin_low, Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, Register Rtemp ); twisti@4323: twisti@4323: void lshr( Register Rin_high, Register Rin_low, Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, Register Rtemp ); twisti@4323: twisti@4323: void lushr( Register Rin_high, Register Rin_low, Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, Register Rtemp ); twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: void lcmp( Register Ra, Register Rb, Register Rresult); twisti@4323: #endif twisti@4323: twisti@4323: // Load and store values by size and signed-ness twisti@4323: void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed); twisti@4323: void store_sized_value(Register src, Address dst, size_t size_in_bytes); twisti@4323: twisti@4323: void float_cmp( bool is_float, int unordered_result, twisti@4323: FloatRegister Fa, FloatRegister Fb, twisti@4323: Register Rresult); twisti@4323: twisti@4323: void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); twisti@4323: void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } twisti@4323: void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); twisti@4323: void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); twisti@4323: twisti@4323: void save_all_globals_into_locals(); twisti@4323: void restore_globals_from_locals(); twisti@4323: twisti@4323: void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, twisti@4323: address lock_addr=0, bool use_call_vm=false); twisti@4323: void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, twisti@4323: address lock_addr=0, bool use_call_vm=false); twisti@4323: void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; twisti@4323: twisti@4323: // These set the icc condition code to equal if the lock succeeded twisti@4323: // and notEqual if it failed and requires a slow case twisti@4323: void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, twisti@4323: Register Rscratch, twisti@4323: BiasedLockingCounters* counters = NULL, twisti@4323: bool try_bias = UseBiasedLocking); twisti@4323: void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, twisti@4323: Register Rscratch, twisti@4323: bool try_bias = UseBiasedLocking); twisti@4323: twisti@4323: // Biased locking support twisti@4323: // Upon entry, lock_reg must point to the lock record on the stack, twisti@4323: // obj_reg must contain the target object, and mark_reg must contain twisti@4323: // the target object's header. twisti@4323: // Destroys mark_reg if an attempt is made to bias an anonymously twisti@4323: // biased lock. In this case a failure will go either to the slow twisti@4323: // case or fall through with the notEqual condition code set with twisti@4323: // the expectation that the slow case in the runtime will be called. twisti@4323: // In the fall-through case where the CAS-based lock is done, twisti@4323: // mark_reg is not destroyed. twisti@4323: void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, twisti@4323: Label& done, Label* slow_case = NULL, twisti@4323: BiasedLockingCounters* counters = NULL); twisti@4323: // Upon entry, the base register of mark_addr must contain the oop. twisti@4323: // Destroys temp_reg. twisti@4323: twisti@4323: // If allow_delay_slot_filling is set to true, the next instruction twisti@4323: // emitted after this one will go in an annulled delay slot if the twisti@4323: // biased locking exit case failed. twisti@4323: void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); twisti@4323: twisti@4323: // allocation twisti@4323: void eden_allocate( twisti@4323: Register obj, // result: pointer to object after successful allocation twisti@4323: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise twisti@4323: int con_size_in_bytes, // object size in bytes if known at compile time twisti@4323: Register t1, // temp register twisti@4323: Register t2, // temp register twisti@4323: Label& slow_case // continuation point if fast allocation fails twisti@4323: ); twisti@4323: void tlab_allocate( twisti@4323: Register obj, // result: pointer to object after successful allocation twisti@4323: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise twisti@4323: int con_size_in_bytes, // object size in bytes if known at compile time twisti@4323: Register t1, // temp register twisti@4323: Label& slow_case // continuation point if fast allocation fails twisti@4323: ); twisti@4323: void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); twisti@4323: void incr_allocated_bytes(RegisterOrConstant size_in_bytes, twisti@4323: Register t1, Register t2); twisti@4323: twisti@4323: // interface method calling twisti@4323: void lookup_interface_method(Register recv_klass, twisti@4323: Register intf_klass, twisti@4323: RegisterOrConstant itable_index, twisti@4323: Register method_result, twisti@4323: Register temp_reg, Register temp2_reg, twisti@4323: Label& no_such_interface); twisti@4323: twisti@4323: // virtual method calling twisti@4323: void lookup_virtual_method(Register recv_klass, twisti@4323: RegisterOrConstant vtable_index, twisti@4323: Register method_result); twisti@4323: twisti@4323: // Test sub_klass against super_klass, with fast and slow paths. twisti@4323: twisti@4323: // The fast path produces a tri-state answer: yes / no / maybe-slow. twisti@4323: // One of the three labels can be NULL, meaning take the fall-through. twisti@4323: // If super_check_offset is -1, the value is loaded up from super_klass. twisti@4323: // No registers are killed, except temp_reg and temp2_reg. twisti@4323: // If super_check_offset is not -1, temp2_reg is not used and can be noreg. twisti@4323: void check_klass_subtype_fast_path(Register sub_klass, twisti@4323: Register super_klass, twisti@4323: Register temp_reg, twisti@4323: Register temp2_reg, twisti@4323: Label* L_success, twisti@4323: Label* L_failure, twisti@4323: Label* L_slow_path, twisti@4323: RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); twisti@4323: twisti@4323: // The rest of the type check; must be wired to a corresponding fast path. twisti@4323: // It does not repeat the fast path logic, so don't use it standalone. twisti@4323: // The temp_reg can be noreg, if no temps are available. twisti@4323: // It can also be sub_klass or super_klass, meaning it's OK to kill that one. twisti@4323: // Updates the sub's secondary super cache as necessary. twisti@4323: void check_klass_subtype_slow_path(Register sub_klass, twisti@4323: Register super_klass, twisti@4323: Register temp_reg, twisti@4323: Register temp2_reg, twisti@4323: Register temp3_reg, twisti@4323: Register temp4_reg, twisti@4323: Label* L_success, twisti@4323: Label* L_failure); twisti@4323: twisti@4323: // Simplified, combined version, good for typical uses. twisti@4323: // Falls through on failure. twisti@4323: void check_klass_subtype(Register sub_klass, twisti@4323: Register super_klass, twisti@4323: Register temp_reg, twisti@4323: Register temp2_reg, twisti@4323: Label& L_success); twisti@4323: twisti@4323: // method handles (JSR 292) twisti@4323: // offset relative to Gargs of argument at tos[arg_slot]. twisti@4323: // (arg_slot == 0 means the last argument, not the first). twisti@4323: RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, twisti@4323: Register temp_reg, twisti@4323: int extra_slot_offset = 0); twisti@4323: // Address of Gargs and argument_offset. twisti@4323: Address argument_address(RegisterOrConstant arg_slot, twisti@4323: Register temp_reg = noreg, twisti@4323: int extra_slot_offset = 0); twisti@4323: twisti@4323: // Stack overflow checking twisti@4323: twisti@4323: // Note: this clobbers G3_scratch twisti@4323: void bang_stack_with_offset(int offset) { twisti@4323: // stack grows down, caller passes positive offset twisti@4323: assert(offset > 0, "must bang with negative offset"); twisti@4323: set((-offset)+STACK_BIAS, G3_scratch); twisti@4323: st(G0, SP, G3_scratch); twisti@4323: } twisti@4323: twisti@4323: // Writes to stack successive pages until offset reached to check for twisti@4323: // stack overflow + shadow pages. Clobbers tsp and scratch registers. twisti@4323: void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); twisti@4323: twisti@4323: virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); twisti@4323: twisti@4323: void verify_tlab(); twisti@4323: twisti@4323: Condition negate_condition(Condition cond); twisti@4323: twisti@4323: // Helper functions for statistics gathering. twisti@4323: // Conditionally (non-atomically) increments passed counter address, preserving condition codes. twisti@4323: void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); twisti@4323: // Unconditional increment. twisti@4323: void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); twisti@4323: void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); twisti@4323: twisti@4323: // Compare char[] arrays aligned to 4 bytes. twisti@4323: void char_arrays_equals(Register ary1, Register ary2, twisti@4323: Register limit, Register result, twisti@4323: Register chr1, Register chr2, Label& Ldone); twisti@4323: // Use BIS for zeroing twisti@4323: void bis_zeroing(Register to, Register count, Register temp, Label& Ldone); twisti@4323: twisti@4323: #undef VIRTUAL twisti@4323: }; twisti@4323: twisti@4323: /** twisti@4323: * class SkipIfEqual: twisti@4323: * twisti@4323: * Instantiating this class will result in assembly code being output that will twisti@4323: * jump around any code emitted between the creation of the instance and it's twisti@4323: * automatic destruction at the end of a scope block, depending on the value of twisti@4323: * the flag passed to the constructor, which will be checked at run-time. twisti@4323: */ twisti@4323: class SkipIfEqual : public StackObj { twisti@4323: private: twisti@4323: MacroAssembler* _masm; twisti@4323: Label _label; twisti@4323: twisti@4323: public: twisti@4323: // 'temp' is a temp register that this object can use (and trash) twisti@4323: SkipIfEqual(MacroAssembler*, Register temp, twisti@4323: const bool* flag_addr, Assembler::Condition condition); twisti@4323: ~SkipIfEqual(); twisti@4323: }; twisti@4323: twisti@4323: #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP