aoqi@0: /* aoqi@0: * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@0: #ifndef SHARE_VM_RUNTIME_ORDERACCESS_HPP aoqi@0: #define SHARE_VM_RUNTIME_ORDERACCESS_HPP aoqi@0: aoqi@0: #include "memory/allocation.hpp" aoqi@0: aoqi@0: // Memory Access Ordering Model aoqi@0: // aoqi@0: // This interface is based on the JSR-133 Cookbook for Compiler Writers aoqi@0: // and on the IA64 memory model. It is the dynamic equivalent of the aoqi@0: // C/C++ volatile specifier. I.e., volatility restricts compile-time aoqi@0: // memory access reordering in a way similar to what we want to occur aoqi@0: // at runtime. aoqi@0: // aoqi@0: // In the following, the terms 'previous', 'subsequent', 'before', aoqi@0: // 'after', 'preceding' and 'succeeding' refer to program order. The aoqi@0: // terms 'down' and 'below' refer to forward load or store motion aoqi@0: // relative to program order, while 'up' and 'above' refer to backward aoqi@0: // motion. aoqi@0: // aoqi@0: // aoqi@0: // We define four primitive memory barrier operations. aoqi@0: // aoqi@0: // LoadLoad: Load1(s); LoadLoad; Load2 aoqi@0: // aoqi@0: // Ensures that Load1 completes (obtains the value it loads from memory) aoqi@0: // before Load2 and any subsequent load operations. Loads before Load1 aoqi@0: // may *not* float below Load2 and any subsequent load operations. aoqi@0: // aoqi@0: // StoreStore: Store1(s); StoreStore; Store2 aoqi@0: // aoqi@0: // Ensures that Store1 completes (the effect on memory of Store1 is made aoqi@0: // visible to other processors) before Store2 and any subsequent store aoqi@0: // operations. Stores before Store1 may *not* float below Store2 and any aoqi@0: // subsequent store operations. aoqi@0: // aoqi@0: // LoadStore: Load1(s); LoadStore; Store2 aoqi@0: // aoqi@0: // Ensures that Load1 completes before Store2 and any subsequent store aoqi@0: // operations. Loads before Load1 may *not* float below Store2 and any aoqi@0: // subseqeuent store operations. aoqi@0: // aoqi@0: // StoreLoad: Store1(s); StoreLoad; Load2 aoqi@0: // aoqi@0: // Ensures that Store1 completes before Load2 and any subsequent load aoqi@0: // operations. Stores before Store1 may *not* float below Load2 and any aoqi@0: // subseqeuent load operations. aoqi@0: // aoqi@0: // aoqi@0: // We define two further operations, 'release' and 'acquire'. They are aoqi@0: // mirror images of each other. aoqi@0: // aoqi@0: // Execution by a processor of release makes the effect of all memory aoqi@0: // accesses issued by it previous to the release visible to all aoqi@0: // processors *before* the release completes. The effect of subsequent aoqi@0: // memory accesses issued by it *may* be made visible *before* the aoqi@0: // release. I.e., subsequent memory accesses may float above the aoqi@0: // release, but prior ones may not float below it. aoqi@0: // aoqi@0: // Execution by a processor of acquire makes the effect of all memory aoqi@0: // accesses issued by it subsequent to the acquire visible to all aoqi@0: // processors *after* the acquire completes. The effect of prior memory aoqi@0: // accesses issued by it *may* be made visible *after* the acquire. aoqi@0: // I.e., prior memory accesses may float below the acquire, but aoqi@0: // subsequent ones may not float above it. aoqi@0: // aoqi@0: // Finally, we define a 'fence' operation, which conceptually is a aoqi@0: // release combined with an acquire. In the real world these operations aoqi@0: // require one or more machine instructions which can float above and aoqi@0: // below the release or acquire, so we usually can't just issue the aoqi@0: // release-acquire back-to-back. All machines we know of implement some aoqi@0: // sort of memory fence instruction. aoqi@0: // aoqi@0: // aoqi@0: // The standalone implementations of release and acquire need an associated aoqi@0: // dummy volatile store or load respectively. To avoid redundant operations, aoqi@0: // we can define the composite operators: 'release_store', 'store_fence' and aoqi@0: // 'load_acquire'. Here's a summary of the machine instructions corresponding aoqi@0: // to each operation. aoqi@0: // aoqi@0: // sparc RMO ia64 x86 aoqi@0: // --------------------------------------------------------------------- aoqi@0: // fence membar #LoadStore | mf lock addl 0,(sp) aoqi@0: // #StoreStore | aoqi@0: // #LoadLoad | aoqi@0: // #StoreLoad aoqi@0: // aoqi@0: // release membar #LoadStore | st.rel [sp]=r0 movl $0, aoqi@0: // #StoreStore aoqi@0: // st %g0,[] aoqi@0: // aoqi@0: // acquire ld [%sp],%g0 ld.acq =[sp] movl (sp), aoqi@0: // membar #LoadLoad | aoqi@0: // #LoadStore aoqi@0: // aoqi@0: // release_store membar #LoadStore | st.rel aoqi@0: // #StoreStore aoqi@0: // st aoqi@0: // aoqi@0: // store_fence st st lock xchg aoqi@0: // fence mf aoqi@0: // aoqi@0: // load_acquire ld ld.acq aoqi@0: // membar #LoadLoad | aoqi@0: // #LoadStore aoqi@0: // aoqi@0: // Using only release_store and load_acquire, we can implement the aoqi@0: // following ordered sequences. aoqi@0: // aoqi@0: // 1. load, load == load_acquire, load aoqi@0: // or load_acquire, load_acquire aoqi@0: // 2. load, store == load, release_store aoqi@0: // or load_acquire, store aoqi@0: // or load_acquire, release_store aoqi@0: // 3. store, store == store, release_store aoqi@0: // or release_store, release_store aoqi@0: // aoqi@0: // These require no membar instructions for sparc-TSO and no extra aoqi@0: // instructions for ia64. aoqi@0: // aoqi@0: // Ordering a load relative to preceding stores requires a store_fence, aoqi@0: // which implies a membar #StoreLoad between the store and load under aoqi@0: // sparc-TSO. A fence is required by ia64. On x86, we use locked xchg. aoqi@0: // aoqi@0: // 4. store, load == store_fence, load aoqi@0: // aoqi@0: // Use store_fence to make sure all stores done in an 'interesting' aoqi@0: // region are made visible prior to both subsequent loads and stores. aoqi@0: // aoqi@0: // Conventional usage is to issue a load_acquire for ordered loads. Use aoqi@0: // release_store for ordered stores when you care only that prior stores aoqi@0: // are visible before the release_store, but don't care exactly when the aoqi@0: // store associated with the release_store becomes visible. Use aoqi@0: // release_store_fence to update values like the thread state, where we aoqi@0: // don't want the current thread to continue until all our prior memory aoqi@0: // accesses (including the new thread state) are visible to other threads. aoqi@0: // aoqi@0: // aoqi@0: // C++ Volatility aoqi@0: // aoqi@0: // C++ guarantees ordering at operations termed 'sequence points' (defined aoqi@0: // to be volatile accesses and calls to library I/O functions). 'Side aoqi@0: // effects' (defined as volatile accesses, calls to library I/O functions aoqi@0: // and object modification) previous to a sequence point must be visible aoqi@0: // at that sequence point. See the C++ standard, section 1.9, titled aoqi@0: // "Program Execution". This means that all barrier implementations, aoqi@0: // including standalone loadload, storestore, loadstore, storeload, acquire aoqi@0: // and release must include a sequence point, usually via a volatile memory aoqi@0: // access. Other ways to guarantee a sequence point are, e.g., use of aoqi@0: // indirect calls and linux's __asm__ volatile. aoqi@0: // Note: as of 6973570, we have replaced the originally static "dummy" field aoqi@0: // (see above) by a volatile store to the stack. All of the versions of the aoqi@0: // compilers that we currently use (SunStudio, gcc and VC++) respect the aoqi@0: // semantics of volatile here. If you build HotSpot using other aoqi@0: // compilers, you may need to verify that no compiler reordering occurs aoqi@0: // across the sequence point respresented by the volatile access. aoqi@0: // aoqi@0: // aoqi@0: // os::is_MP Considered Redundant aoqi@0: // aoqi@0: // Callers of this interface do not need to test os::is_MP() before aoqi@0: // issuing an operation. The test is taken care of by the implementation aoqi@0: // of the interface (depending on the vm version and platform, the test aoqi@0: // may or may not be actually done by the implementation). aoqi@0: // aoqi@0: // aoqi@0: // A Note on Memory Ordering and Cache Coherency aoqi@0: // aoqi@0: // Cache coherency and memory ordering are orthogonal concepts, though they aoqi@0: // interact. E.g., all existing itanium machines are cache-coherent, but aoqi@0: // the hardware can freely reorder loads wrt other loads unless it sees a aoqi@0: // load-acquire instruction. All existing sparc machines are cache-coherent aoqi@0: // and, unlike itanium, TSO guarantees that the hardware orders loads wrt aoqi@0: // loads and stores, and stores wrt to each other. aoqi@0: // aoqi@0: // Consider the implementation of loadload. *If* your platform *isn't* aoqi@0: // cache-coherent, then loadload must not only prevent hardware load aoqi@0: // instruction reordering, but it must *also* ensure that subsequent aoqi@0: // loads from addresses that could be written by other processors (i.e., aoqi@0: // that are broadcast by other processors) go all the way to the first aoqi@0: // level of memory shared by those processors and the one issuing aoqi@0: // the loadload. aoqi@0: // aoqi@0: // So if we have a MP that has, say, a per-processor D$ that doesn't see aoqi@0: // writes by other processors, and has a shared E$ that does, the loadload aoqi@0: // barrier would have to make sure that either aoqi@0: // aoqi@0: // 1. cache lines in the issuing processor's D$ that contained data from aoqi@0: // addresses that could be written by other processors are invalidated, so aoqi@0: // subsequent loads from those addresses go to the E$, (it could do this aoqi@0: // by tagging such cache lines as 'shared', though how to tell the hardware aoqi@0: // to do the tagging is an interesting problem), or aoqi@0: // aoqi@0: // 2. there never are such cache lines in the issuing processor's D$, which aoqi@0: // means all references to shared data (however identified: see above) aoqi@0: // bypass the D$ (i.e., are satisfied from the E$). aoqi@0: // aoqi@0: // If your machine doesn't have an E$, substitute 'main memory' for 'E$'. aoqi@0: // aoqi@0: // Either of these alternatives is a pain, so no current machine we know of aoqi@0: // has incoherent caches. aoqi@0: // aoqi@0: // If loadload didn't have these properties, the store-release sequence for aoqi@0: // publishing a shared data structure wouldn't work, because a processor aoqi@0: // trying to read data newly published by another processor might go to aoqi@0: // its own incoherent caches to satisfy the read instead of to the newly aoqi@0: // written shared memory. aoqi@0: // aoqi@0: // aoqi@0: // NOTE WELL!! aoqi@0: // aoqi@0: // A Note on MutexLocker and Friends aoqi@0: // aoqi@0: // See mutexLocker.hpp. We assume throughout the VM that MutexLocker's aoqi@0: // and friends' constructors do a fence, a lock and an acquire *in that aoqi@0: // order*. And that their destructors do a release and unlock, in *that* aoqi@0: // order. If their implementations change such that these assumptions aoqi@0: // are violated, a whole lot of code will break. aoqi@0: aoqi@0: class OrderAccess : AllStatic { aoqi@0: public: aoqi@0: static void loadload(); aoqi@0: static void storestore(); aoqi@0: static void loadstore(); aoqi@0: static void storeload(); aoqi@0: aoqi@0: static void acquire(); aoqi@0: static void release(); aoqi@0: static void fence(); aoqi@0: aoqi@0: static jbyte load_acquire(volatile jbyte* p); aoqi@0: static jshort load_acquire(volatile jshort* p); aoqi@0: static jint load_acquire(volatile jint* p); aoqi@0: static jlong load_acquire(volatile jlong* p); aoqi@0: static jubyte load_acquire(volatile jubyte* p); aoqi@0: static jushort load_acquire(volatile jushort* p); aoqi@0: static juint load_acquire(volatile juint* p); aoqi@0: static julong load_acquire(volatile julong* p); aoqi@0: static jfloat load_acquire(volatile jfloat* p); aoqi@0: static jdouble load_acquire(volatile jdouble* p); aoqi@0: aoqi@0: static intptr_t load_ptr_acquire(volatile intptr_t* p); aoqi@0: static void* load_ptr_acquire(volatile void* p); aoqi@0: static void* load_ptr_acquire(const volatile void* p); aoqi@0: aoqi@0: static void release_store(volatile jbyte* p, jbyte v); aoqi@0: static void release_store(volatile jshort* p, jshort v); aoqi@0: static void release_store(volatile jint* p, jint v); aoqi@0: static void release_store(volatile jlong* p, jlong v); aoqi@0: static void release_store(volatile jubyte* p, jubyte v); aoqi@0: static void release_store(volatile jushort* p, jushort v); aoqi@0: static void release_store(volatile juint* p, juint v); aoqi@0: static void release_store(volatile julong* p, julong v); aoqi@0: static void release_store(volatile jfloat* p, jfloat v); aoqi@0: static void release_store(volatile jdouble* p, jdouble v); aoqi@0: aoqi@0: static void release_store_ptr(volatile intptr_t* p, intptr_t v); aoqi@0: static void release_store_ptr(volatile void* p, void* v); aoqi@0: aoqi@0: static void store_fence(jbyte* p, jbyte v); aoqi@0: static void store_fence(jshort* p, jshort v); aoqi@0: static void store_fence(jint* p, jint v); aoqi@0: static void store_fence(jlong* p, jlong v); aoqi@0: static void store_fence(jubyte* p, jubyte v); aoqi@0: static void store_fence(jushort* p, jushort v); aoqi@0: static void store_fence(juint* p, juint v); aoqi@0: static void store_fence(julong* p, julong v); aoqi@0: static void store_fence(jfloat* p, jfloat v); aoqi@0: static void store_fence(jdouble* p, jdouble v); aoqi@0: aoqi@0: static void store_ptr_fence(intptr_t* p, intptr_t v); aoqi@0: static void store_ptr_fence(void** p, void* v); aoqi@0: aoqi@0: static void release_store_fence(volatile jbyte* p, jbyte v); aoqi@0: static void release_store_fence(volatile jshort* p, jshort v); aoqi@0: static void release_store_fence(volatile jint* p, jint v); aoqi@0: static void release_store_fence(volatile jlong* p, jlong v); aoqi@0: static void release_store_fence(volatile jubyte* p, jubyte v); aoqi@0: static void release_store_fence(volatile jushort* p, jushort v); aoqi@0: static void release_store_fence(volatile juint* p, juint v); aoqi@0: static void release_store_fence(volatile julong* p, julong v); aoqi@0: static void release_store_fence(volatile jfloat* p, jfloat v); aoqi@0: static void release_store_fence(volatile jdouble* p, jdouble v); aoqi@0: aoqi@0: static void release_store_ptr_fence(volatile intptr_t* p, intptr_t v); aoqi@0: static void release_store_ptr_fence(volatile void* p, void* v); aoqi@0: aoqi@0: private: aoqi@0: // This is a helper that invokes the StubRoutines::fence_entry() aoqi@0: // routine if it exists, It should only be used by platforms that aoqi@0: // don't another way to do the inline eassembly. aoqi@0: static void StubRoutines_fence(); aoqi@0: }; aoqi@0: aoqi@0: #endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP