duke@435: /* never@3500: * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * trims@1907: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA trims@1907: * or visit www.oracle.com if you need additional information or have any trims@1907: * questions. duke@435: * duke@435: */ duke@435: stefank@2314: #include "precompiled.hpp" twisti@4318: #include "asm/macroAssembler.hpp" twisti@4318: #include "asm/macroAssembler.inline.hpp" stefank@2314: #include "code/debugInfoRec.hpp" stefank@2314: #include "code/icBuffer.hpp" stefank@2314: #include "code/vtableStubs.hpp" stefank@2314: #include "interpreter/interpreter.hpp" coleenp@4037: #include "oops/compiledICHolder.hpp" stefank@2314: #include "prims/jvmtiRedefineClassesTrace.hpp" stefank@2314: #include "runtime/sharedRuntime.hpp" stefank@2314: #include "runtime/vframeArray.hpp" stefank@2314: #include "vmreg_x86.inline.hpp" stefank@2314: #ifdef COMPILER1 stefank@2314: #include "c1/c1_Runtime1.hpp" stefank@2314: #endif stefank@2314: #ifdef COMPILER2 stefank@2314: #include "opto/runtime.hpp" stefank@2314: #endif duke@435: never@2950: #define __ masm-> duke@435: xlu@959: const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; xlu@959: duke@435: class SimpleRuntimeFrame { duke@435: duke@435: public: duke@435: duke@435: // Most of the runtime stubs have this simple frame layout. duke@435: // This class exists to make the layout shared in one place. duke@435: // Offsets are for compiler stack slots, which are jints. duke@435: enum layout { duke@435: // The frame sender code expects that rbp will be in the "natural" place and duke@435: // will override any oopMap setting for it. We must therefore force the layout duke@435: // so that it agrees with the frame sender code. duke@435: rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, duke@435: rbp_off2, duke@435: return_off, return_off2, duke@435: framesize duke@435: }; duke@435: }; duke@435: duke@435: class RegisterSaver { duke@435: // Capture info about frame layout. Layout offsets are in jint duke@435: // units because compiler frame slots are jints. duke@435: #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off duke@435: enum layout { duke@435: fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area duke@435: xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area duke@435: DEF_XMM_OFFS(0), duke@435: DEF_XMM_OFFS(1), duke@435: DEF_XMM_OFFS(2), duke@435: DEF_XMM_OFFS(3), duke@435: DEF_XMM_OFFS(4), duke@435: DEF_XMM_OFFS(5), duke@435: DEF_XMM_OFFS(6), duke@435: DEF_XMM_OFFS(7), duke@435: DEF_XMM_OFFS(8), duke@435: DEF_XMM_OFFS(9), duke@435: DEF_XMM_OFFS(10), duke@435: DEF_XMM_OFFS(11), duke@435: DEF_XMM_OFFS(12), duke@435: DEF_XMM_OFFS(13), duke@435: DEF_XMM_OFFS(14), duke@435: DEF_XMM_OFFS(15), duke@435: fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), duke@435: fpu_stateH_end, duke@435: r15_off, r15H_off, duke@435: r14_off, r14H_off, duke@435: r13_off, r13H_off, duke@435: r12_off, r12H_off, duke@435: r11_off, r11H_off, duke@435: r10_off, r10H_off, duke@435: r9_off, r9H_off, duke@435: r8_off, r8H_off, duke@435: rdi_off, rdiH_off, duke@435: rsi_off, rsiH_off, duke@435: ignore_off, ignoreH_off, // extra copy of rbp duke@435: rsp_off, rspH_off, duke@435: rbx_off, rbxH_off, duke@435: rdx_off, rdxH_off, duke@435: rcx_off, rcxH_off, duke@435: rax_off, raxH_off, duke@435: // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state duke@435: align_off, alignH_off, duke@435: flags_off, flagsH_off, duke@435: // The frame sender code expects that rbp will be in the "natural" place and duke@435: // will override any oopMap setting for it. We must therefore force the layout duke@435: // so that it agrees with the frame sender code. duke@435: rbp_off, rbpH_off, // copy of rbp we will restore duke@435: return_off, returnH_off, // slot for return address duke@435: reg_save_size // size in compiler stack slots duke@435: }; duke@435: duke@435: public: kvn@4103: static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false); kvn@4103: static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); duke@435: duke@435: // Offsets into the register save area duke@435: // Used by deoptimization when it is managing result register duke@435: // values on its own duke@435: duke@435: static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; } never@739: static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; } duke@435: static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; } duke@435: static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; } duke@435: static int return_offset_in_bytes(void) { return BytesPerInt * return_off; } duke@435: duke@435: // During deoptimization only the result registers need to be restored, duke@435: // all the other values have already been extracted. duke@435: static void restore_result_registers(MacroAssembler* masm); duke@435: }; duke@435: kvn@4103: OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { kvn@4103: int vect_words = 0; kvn@4103: #ifdef COMPILER2 kvn@4103: if (save_vectors) { kvn@4103: assert(UseAVX > 0, "256bit vectors are supported only with AVX"); kvn@4103: assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); kvn@4103: // Save upper half of YMM registes kvn@4103: vect_words = 16 * 16 / wordSize; kvn@4103: additional_frame_words += vect_words; kvn@4103: } kvn@4103: #else kvn@4103: assert(!save_vectors, "vectors are generated only by C2"); kvn@4103: #endif duke@435: duke@435: // Always make the frame size 16-byte aligned duke@435: int frame_size_in_bytes = round_to(additional_frame_words*wordSize + duke@435: reg_save_size*BytesPerInt, 16); duke@435: // OopMap frame size is in compiler stack slots (jint's) not bytes or words duke@435: int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; duke@435: // The caller will allocate additional_frame_words duke@435: int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; duke@435: // CodeBlob frame size is in words. duke@435: int frame_size_in_words = frame_size_in_bytes / wordSize; duke@435: *total_frame_words = frame_size_in_words; duke@435: duke@435: // Save registers, fpu state, and flags. duke@435: // We assume caller has already pushed the return address onto the duke@435: // stack, so rsp is 8-byte aligned here. duke@435: // We push rpb twice in this sequence because we want the real rbp duke@435: // to be under the return like a normal enter. duke@435: duke@435: __ enter(); // rsp becomes 16-byte aligned here duke@435: __ push_CPU_state(); // Push a multiple of 16 bytes kvn@4103: kvn@4103: if (vect_words > 0) { kvn@4103: assert(vect_words*wordSize == 256, ""); kvn@4103: __ subptr(rsp, 256); // Save upper half of YMM registes kvn@4103: __ vextractf128h(Address(rsp, 0),xmm0); kvn@4103: __ vextractf128h(Address(rsp, 16),xmm1); kvn@4103: __ vextractf128h(Address(rsp, 32),xmm2); kvn@4103: __ vextractf128h(Address(rsp, 48),xmm3); kvn@4103: __ vextractf128h(Address(rsp, 64),xmm4); kvn@4103: __ vextractf128h(Address(rsp, 80),xmm5); kvn@4103: __ vextractf128h(Address(rsp, 96),xmm6); kvn@4103: __ vextractf128h(Address(rsp,112),xmm7); kvn@4103: __ vextractf128h(Address(rsp,128),xmm8); kvn@4103: __ vextractf128h(Address(rsp,144),xmm9); kvn@4103: __ vextractf128h(Address(rsp,160),xmm10); kvn@4103: __ vextractf128h(Address(rsp,176),xmm11); kvn@4103: __ vextractf128h(Address(rsp,192),xmm12); kvn@4103: __ vextractf128h(Address(rsp,208),xmm13); kvn@4103: __ vextractf128h(Address(rsp,224),xmm14); kvn@4103: __ vextractf128h(Address(rsp,240),xmm15); kvn@4103: } duke@435: if (frame::arg_reg_save_area_bytes != 0) { duke@435: // Allocate argument register save area never@739: __ subptr(rsp, frame::arg_reg_save_area_bytes); duke@435: } duke@435: duke@435: // Set an oopmap for the call site. This oopmap will map all duke@435: // oop-registers and debug-info registers as callee-saved. This duke@435: // will allow deoptimization at this safepoint to find all possible duke@435: // debug-info recordings, as well as let GC find all oops. duke@435: duke@435: OopMapSet *oop_maps = new OopMapSet(); duke@435: OopMap* map = new OopMap(frame_size_in_slots, 0); kvn@4103: kvn@4103: #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots) kvn@4103: kvn@4103: map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg()); duke@435: // rbp location is known implicitly by the frame sender code, needs no oopmap duke@435: // and the location where rbp was saved by is ignored kvn@4103: map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg()); duke@435: duke@435: // %%% These should all be a waste but we'll keep things as they were for now duke@435: if (true) { kvn@4103: map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next()); duke@435: // rbp location is known implicitly by the frame sender code, needs no oopmap kvn@4103: map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next()); kvn@4103: map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next()); duke@435: } duke@435: duke@435: return map; duke@435: } duke@435: kvn@4103: void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { duke@435: if (frame::arg_reg_save_area_bytes != 0) { duke@435: // Pop arg register save area never@739: __ addptr(rsp, frame::arg_reg_save_area_bytes); duke@435: } kvn@4103: #ifdef COMPILER2 kvn@4103: if (restore_vectors) { kvn@4103: // Restore upper half of YMM registes. kvn@4103: assert(UseAVX > 0, "256bit vectors are supported only with AVX"); kvn@4103: assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); kvn@4103: __ vinsertf128h(xmm0, Address(rsp, 0)); kvn@4103: __ vinsertf128h(xmm1, Address(rsp, 16)); kvn@4103: __ vinsertf128h(xmm2, Address(rsp, 32)); kvn@4103: __ vinsertf128h(xmm3, Address(rsp, 48)); kvn@4103: __ vinsertf128h(xmm4, Address(rsp, 64)); kvn@4103: __ vinsertf128h(xmm5, Address(rsp, 80)); kvn@4103: __ vinsertf128h(xmm6, Address(rsp, 96)); kvn@4103: __ vinsertf128h(xmm7, Address(rsp,112)); kvn@4103: __ vinsertf128h(xmm8, Address(rsp,128)); kvn@4103: __ vinsertf128h(xmm9, Address(rsp,144)); kvn@4103: __ vinsertf128h(xmm10, Address(rsp,160)); kvn@4103: __ vinsertf128h(xmm11, Address(rsp,176)); kvn@4103: __ vinsertf128h(xmm12, Address(rsp,192)); kvn@4103: __ vinsertf128h(xmm13, Address(rsp,208)); kvn@4103: __ vinsertf128h(xmm14, Address(rsp,224)); kvn@4103: __ vinsertf128h(xmm15, Address(rsp,240)); kvn@4103: __ addptr(rsp, 256); kvn@4103: } kvn@4103: #else kvn@4103: assert(!restore_vectors, "vectors are generated only by C2"); kvn@4103: #endif duke@435: // Recover CPU state duke@435: __ pop_CPU_state(); duke@435: // Get the rbp described implicitly by the calling convention (no oopMap) never@739: __ pop(rbp); duke@435: } duke@435: duke@435: void RegisterSaver::restore_result_registers(MacroAssembler* masm) { duke@435: duke@435: // Just restore result register. Only used by deoptimization. By duke@435: // now any callee save register that needs to be restored to a c2 duke@435: // caller of the deoptee has been extracted into the vframeArray duke@435: // and will be stuffed into the c2i adapter we create for later duke@435: // restoration so only result registers need to be restored here. duke@435: duke@435: // Restore fp result register duke@435: __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes())); duke@435: // Restore integer result register never@739: __ movptr(rax, Address(rsp, rax_offset_in_bytes())); never@739: __ movptr(rdx, Address(rsp, rdx_offset_in_bytes())); never@739: duke@435: // Pop all of the register save are off the stack except the return address never@739: __ addptr(rsp, return_offset_in_bytes()); duke@435: } duke@435: kvn@4103: // Is vector's size (in bytes) bigger than a size saved by default? kvn@4103: // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. kvn@4103: bool SharedRuntime::is_wide_vector(int size) { kvn@4103: return size > 16; kvn@4103: } kvn@4103: duke@435: // The java_calling_convention describes stack locations as ideal slots on duke@435: // a frame with no abi restrictions. Since we must observe abi restrictions duke@435: // (like the placement of the register window) the slots must be biased by duke@435: // the following value. duke@435: static int reg2offset_in(VMReg r) { duke@435: // Account for saved rbp and return address duke@435: // This should really be in_preserve_stack_slots duke@435: return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; duke@435: } duke@435: duke@435: static int reg2offset_out(VMReg r) { duke@435: return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; duke@435: } duke@435: duke@435: // --------------------------------------------------------------------------- duke@435: // Read the array of BasicTypes from a signature, and compute where the duke@435: // arguments should go. Values in the VMRegPair regs array refer to 4-byte duke@435: // quantities. Values less than VMRegImpl::stack0 are registers, those above duke@435: // refer to 4-byte stack slots. All stack slots are based off of the stack pointer duke@435: // as framesizes are fixed. duke@435: // VMRegImpl::stack0 refers to the first slot 0(sp). duke@435: // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register duke@435: // up to RegisterImpl::number_of_registers) are the 64-bit duke@435: // integer registers. duke@435: duke@435: // Note: the INPUTS in sig_bt are in units of Java argument words, which are duke@435: // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit duke@435: // units regardless of build. Of course for i486 there is no 64 bit build duke@435: duke@435: // The Java calling convention is a "shifted" version of the C ABI. duke@435: // By skipping the first C ABI register we can call non-static jni methods duke@435: // with small numbers of arguments without having to shuffle the arguments duke@435: // at all. Since we control the java ABI we ought to at least get some duke@435: // advantage out of it. duke@435: duke@435: int SharedRuntime::java_calling_convention(const BasicType *sig_bt, duke@435: VMRegPair *regs, duke@435: int total_args_passed, duke@435: int is_outgoing) { duke@435: duke@435: // Create the mapping between argument positions and duke@435: // registers. duke@435: static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { duke@435: j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5 duke@435: }; duke@435: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = { duke@435: j_farg0, j_farg1, j_farg2, j_farg3, duke@435: j_farg4, j_farg5, j_farg6, j_farg7 duke@435: }; duke@435: duke@435: duke@435: uint int_args = 0; duke@435: uint fp_args = 0; duke@435: uint stk_args = 0; // inc by 2 each time duke@435: duke@435: for (int i = 0; i < total_args_passed; i++) { duke@435: switch (sig_bt[i]) { duke@435: case T_BOOLEAN: duke@435: case T_CHAR: duke@435: case T_BYTE: duke@435: case T_SHORT: duke@435: case T_INT: duke@435: if (int_args < Argument::n_int_register_parameters_j) { duke@435: regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); duke@435: } else { duke@435: regs[i].set1(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_VOID: duke@435: // halves of T_LONG or T_DOUBLE duke@435: assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); duke@435: regs[i].set_bad(); duke@435: break; duke@435: case T_LONG: duke@435: assert(sig_bt[i + 1] == T_VOID, "expecting half"); duke@435: // fall through duke@435: case T_OBJECT: duke@435: case T_ARRAY: duke@435: case T_ADDRESS: duke@435: if (int_args < Argument::n_int_register_parameters_j) { duke@435: regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); duke@435: } else { duke@435: regs[i].set2(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_FLOAT: duke@435: if (fp_args < Argument::n_float_register_parameters_j) { duke@435: regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); duke@435: } else { duke@435: regs[i].set1(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_DOUBLE: duke@435: assert(sig_bt[i + 1] == T_VOID, "expecting half"); duke@435: if (fp_args < Argument::n_float_register_parameters_j) { duke@435: regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); duke@435: } else { duke@435: regs[i].set2(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: break; duke@435: } duke@435: } duke@435: duke@435: return round_to(stk_args, 2); duke@435: } duke@435: duke@435: // Patch the callers callsite with entry to compiled code if it exists. duke@435: static void patch_callers_callsite(MacroAssembler *masm) { duke@435: Label L; coleenp@4037: __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, L); duke@435: duke@435: // Save the current stack pointer never@739: __ mov(r13, rsp); duke@435: // Schedule the branch target address early. duke@435: // Call into the VM to patch the caller, then jump to compiled callee duke@435: // rax isn't live so capture return address while we easily can never@739: __ movptr(rax, Address(rsp, 0)); duke@435: duke@435: // align stack so push_CPU_state doesn't fault never@739: __ andptr(rsp, -(StackAlignmentInBytes)); duke@435: __ push_CPU_state(); duke@435: duke@435: // VM needs caller's callsite duke@435: // VM needs target method duke@435: // This needs to be a long call since we will relocate this adapter to duke@435: // the codeBuffer and it may not reach duke@435: duke@435: // Allocate argument register save area duke@435: if (frame::arg_reg_save_area_bytes != 0) { never@739: __ subptr(rsp, frame::arg_reg_save_area_bytes); duke@435: } never@739: __ mov(c_rarg0, rbx); never@739: __ mov(c_rarg1, rax); duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); duke@435: duke@435: // De-allocate argument register save area duke@435: if (frame::arg_reg_save_area_bytes != 0) { never@739: __ addptr(rsp, frame::arg_reg_save_area_bytes); duke@435: } duke@435: duke@435: __ pop_CPU_state(); duke@435: // restore sp never@739: __ mov(rsp, r13); duke@435: __ bind(L); duke@435: } duke@435: duke@435: duke@435: static void gen_c2i_adapter(MacroAssembler *masm, duke@435: int total_args_passed, duke@435: int comp_args_on_stack, duke@435: const BasicType *sig_bt, duke@435: const VMRegPair *regs, duke@435: Label& skip_fixup) { duke@435: // Before we get into the guts of the C2I adapter, see if we should be here duke@435: // at all. We've come from compiled code and are attempting to jump to the duke@435: // interpreter, which means the caller made a static call to get here duke@435: // (vcalls always get a compiled target if there is one). Check for a duke@435: // compiled target. If there is one, we need to patch the caller's call. duke@435: patch_callers_callsite(masm); duke@435: duke@435: __ bind(skip_fixup); duke@435: duke@435: // Since all args are passed on the stack, total_args_passed * duke@435: // Interpreter::stackElementSize is the space we need. Plus 1 because duke@435: // we also account for the return address location since duke@435: // we store it first rather than hold it in rax across all the shuffling duke@435: twisti@1861: int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize; duke@435: duke@435: // stack is aligned, keep it that way duke@435: extraspace = round_to(extraspace, 2*wordSize); duke@435: duke@435: // Get return address never@739: __ pop(rax); duke@435: duke@435: // set senderSP value never@739: __ mov(r13, rsp); never@739: never@739: __ subptr(rsp, extraspace); duke@435: duke@435: // Store the return address in the expected location never@739: __ movptr(Address(rsp, 0), rax); duke@435: duke@435: // Now write the args into the outgoing interpreter space duke@435: for (int i = 0; i < total_args_passed; i++) { duke@435: if (sig_bt[i] == T_VOID) { duke@435: assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); duke@435: continue; duke@435: } duke@435: duke@435: // offset to start parameters twisti@1861: int st_off = (total_args_passed - i) * Interpreter::stackElementSize; twisti@1861: int next_off = st_off - Interpreter::stackElementSize; duke@435: duke@435: // Say 4 args: duke@435: // i st_off duke@435: // 0 32 T_LONG duke@435: // 1 24 T_VOID duke@435: // 2 16 T_OBJECT duke@435: // 3 8 T_BOOL duke@435: // - 0 return address duke@435: // duke@435: // However to make thing extra confusing. Because we can fit a long/double in duke@435: // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter duke@435: // leaves one slot empty and only stores to a single slot. In this case the duke@435: // slot that is occupied is the T_VOID slot. See I said it was confusing. duke@435: duke@435: VMReg r_1 = regs[i].first(); duke@435: VMReg r_2 = regs[i].second(); duke@435: if (!r_1->is_valid()) { duke@435: assert(!r_2->is_valid(), ""); duke@435: continue; duke@435: } duke@435: if (r_1->is_stack()) { duke@435: // memory to memory use rax duke@435: int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; duke@435: if (!r_2->is_valid()) { duke@435: // sign extend?? duke@435: __ movl(rax, Address(rsp, ld_off)); never@739: __ movptr(Address(rsp, st_off), rax); duke@435: duke@435: } else { duke@435: duke@435: __ movq(rax, Address(rsp, ld_off)); duke@435: duke@435: // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG duke@435: // T_DOUBLE and T_LONG use two slots in the interpreter duke@435: if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { duke@435: // ld_off == LSW, ld_off+wordSize == MSW duke@435: // st_off == MSW, next_off == LSW duke@435: __ movq(Address(rsp, next_off), rax); duke@435: #ifdef ASSERT duke@435: // Overwrite the unused slot with known junk duke@435: __ mov64(rax, CONST64(0xdeadffffdeadaaaa)); never@739: __ movptr(Address(rsp, st_off), rax); duke@435: #endif /* ASSERT */ duke@435: } else { duke@435: __ movq(Address(rsp, st_off), rax); duke@435: } duke@435: } duke@435: } else if (r_1->is_Register()) { duke@435: Register r = r_1->as_Register(); duke@435: if (!r_2->is_valid()) { duke@435: // must be only an int (or less ) so move only 32bits to slot duke@435: // why not sign extend?? duke@435: __ movl(Address(rsp, st_off), r); duke@435: } else { duke@435: // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG duke@435: // T_DOUBLE and T_LONG use two slots in the interpreter duke@435: if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { duke@435: // long/double in gpr duke@435: #ifdef ASSERT duke@435: // Overwrite the unused slot with known junk duke@435: __ mov64(rax, CONST64(0xdeadffffdeadaaab)); never@739: __ movptr(Address(rsp, st_off), rax); duke@435: #endif /* ASSERT */ duke@435: __ movq(Address(rsp, next_off), r); duke@435: } else { never@739: __ movptr(Address(rsp, st_off), r); duke@435: } duke@435: } duke@435: } else { duke@435: assert(r_1->is_XMMRegister(), ""); duke@435: if (!r_2->is_valid()) { duke@435: // only a float use just part of the slot duke@435: __ movflt(Address(rsp, st_off), r_1->as_XMMRegister()); duke@435: } else { duke@435: #ifdef ASSERT duke@435: // Overwrite the unused slot with known junk duke@435: __ mov64(rax, CONST64(0xdeadffffdeadaaac)); never@739: __ movptr(Address(rsp, st_off), rax); duke@435: #endif /* ASSERT */ duke@435: __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister()); duke@435: } duke@435: } duke@435: } duke@435: duke@435: // Schedule the branch target address early. coleenp@4037: __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset()))); duke@435: __ jmp(rcx); duke@435: } duke@435: twisti@3969: static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, twisti@3969: address code_start, address code_end, twisti@3969: Label& L_ok) { twisti@3969: Label L_fail; twisti@3969: __ lea(temp_reg, ExternalAddress(code_start)); twisti@3969: __ cmpptr(pc_reg, temp_reg); twisti@3969: __ jcc(Assembler::belowEqual, L_fail); twisti@3969: __ lea(temp_reg, ExternalAddress(code_end)); twisti@3969: __ cmpptr(pc_reg, temp_reg); twisti@3969: __ jcc(Assembler::below, L_ok); twisti@3969: __ bind(L_fail); twisti@3969: } twisti@3969: duke@435: static void gen_i2c_adapter(MacroAssembler *masm, duke@435: int total_args_passed, duke@435: int comp_args_on_stack, duke@435: const BasicType *sig_bt, duke@435: const VMRegPair *regs) { duke@435: duke@435: // Note: r13 contains the senderSP on entry. We must preserve it since duke@435: // we may do a i2c -> c2i transition if we lose a race where compiled duke@435: // code goes non-entrant while we get args ready. duke@435: // In addition we use r13 to locate all the interpreter args as duke@435: // we must align the stack to 16 bytes on an i2c entry else we duke@435: // lose alignment we expect in all compiled code and register duke@435: // save code can segv when fxsave instructions find improperly duke@435: // aligned stack pointer. duke@435: twisti@3969: // Adapters can be frameless because they do not require the caller twisti@3969: // to perform additional cleanup work, such as correcting the stack pointer. twisti@3969: // An i2c adapter is frameless because the *caller* frame, which is interpreted, twisti@3969: // routinely repairs its own stack pointer (from interpreter_frame_last_sp), twisti@3969: // even if a callee has modified the stack pointer. twisti@3969: // A c2i adapter is frameless because the *callee* frame, which is interpreted, twisti@3969: // routinely repairs its caller's stack pointer (from sender_sp, which is set twisti@3969: // up via the senderSP register). twisti@3969: // In other words, if *either* the caller or callee is interpreted, we can twisti@3969: // get the stack pointer repaired after a call. twisti@3969: // This is why c2i and i2c adapters cannot be indefinitely composed. twisti@3969: // In particular, if a c2i adapter were to somehow call an i2c adapter, twisti@3969: // both caller and callee would be compiled methods, and neither would twisti@3969: // clean up the stack pointer changes performed by the two adapters. twisti@3969: // If this happens, control eventually transfers back to the compiled twisti@3969: // caller, but with an uncorrected stack, causing delayed havoc. twisti@3969: twisti@2552: // Pick up the return address never@739: __ movptr(rax, Address(rsp, 0)); duke@435: twisti@3969: if (VerifyAdapterCalls && twisti@3969: (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { twisti@3969: // So, let's test for cascading c2i/i2c adapters right now. twisti@3969: // assert(Interpreter::contains($return_addr) || twisti@3969: // StubRoutines::contains($return_addr), twisti@3969: // "i2c adapter must return to an interpreter frame"); twisti@3969: __ block_comment("verify_i2c { "); twisti@3969: Label L_ok; twisti@3969: if (Interpreter::code() != NULL) twisti@3969: range_check(masm, rax, r11, twisti@3969: Interpreter::code()->code_start(), Interpreter::code()->code_end(), twisti@3969: L_ok); twisti@3969: if (StubRoutines::code1() != NULL) twisti@3969: range_check(masm, rax, r11, twisti@3969: StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), twisti@3969: L_ok); twisti@3969: if (StubRoutines::code2() != NULL) twisti@3969: range_check(masm, rax, r11, twisti@3969: StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), twisti@3969: L_ok); twisti@3969: const char* msg = "i2c adapter must return to an interpreter frame"; twisti@3969: __ block_comment(msg); twisti@3969: __ stop(msg); twisti@3969: __ bind(L_ok); twisti@3969: __ block_comment("} verify_i2ce "); twisti@3969: } twisti@3969: twisti@1570: // Must preserve original SP for loading incoming arguments because twisti@1570: // we need to align the outgoing SP for compiled code. twisti@1570: __ movptr(r11, rsp); twisti@1570: duke@435: // Cut-out for having no stack args. Since up to 2 int/oop args are passed duke@435: // in registers, we will occasionally have no stack args. duke@435: int comp_words_on_stack = 0; duke@435: if (comp_args_on_stack) { duke@435: // Sig words on the stack are greater-than VMRegImpl::stack0. Those in duke@435: // registers are below. By subtracting stack0, we either get a negative duke@435: // number (all values in registers) or the maximum stack slot accessed. duke@435: duke@435: // Convert 4-byte c2 stack slots to words. duke@435: comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; duke@435: // Round up to miminum stack alignment, in wordSize duke@435: comp_words_on_stack = round_to(comp_words_on_stack, 2); never@739: __ subptr(rsp, comp_words_on_stack * wordSize); duke@435: } duke@435: duke@435: duke@435: // Ensure compiled code always sees stack at proper alignment never@739: __ andptr(rsp, -16); duke@435: duke@435: // push the return address and misalign the stack that youngest frame always sees duke@435: // as far as the placement of the call instruction never@739: __ push(rax); duke@435: twisti@1570: // Put saved SP in another register twisti@1570: const Register saved_sp = rax; twisti@1570: __ movptr(saved_sp, r11); twisti@1570: duke@435: // Will jump to the compiled code just as if compiled code was doing it. duke@435: // Pre-load the register-jump target early, to schedule it better. coleenp@4037: __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset()))); duke@435: duke@435: // Now generate the shuffle code. Pick up all register args and move the duke@435: // rest through the floating point stack top. duke@435: for (int i = 0; i < total_args_passed; i++) { duke@435: if (sig_bt[i] == T_VOID) { duke@435: // Longs and doubles are passed in native word order, but misaligned duke@435: // in the 32-bit build. duke@435: assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); duke@435: continue; duke@435: } duke@435: duke@435: // Pick up 0, 1 or 2 words from SP+offset. duke@435: duke@435: assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), duke@435: "scrambled load targets?"); duke@435: // Load in argument order going down. twisti@1861: int ld_off = (total_args_passed - i)*Interpreter::stackElementSize; duke@435: // Point to interpreter value (vs. tag) twisti@1861: int next_off = ld_off - Interpreter::stackElementSize; duke@435: // duke@435: // duke@435: // duke@435: VMReg r_1 = regs[i].first(); duke@435: VMReg r_2 = regs[i].second(); duke@435: if (!r_1->is_valid()) { duke@435: assert(!r_2->is_valid(), ""); duke@435: continue; duke@435: } duke@435: if (r_1->is_stack()) { duke@435: // Convert stack slot to an SP offset (+ wordSize to account for return address ) duke@435: int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize; twisti@1570: twisti@1570: // We can use r13 as a temp here because compiled code doesn't need r13 as an input twisti@1570: // and if we end up going thru a c2i because of a miss a reasonable value of r13 twisti@1570: // will be generated. duke@435: if (!r_2->is_valid()) { duke@435: // sign extend??? twisti@1570: __ movl(r13, Address(saved_sp, ld_off)); twisti@1570: __ movptr(Address(rsp, st_off), r13); duke@435: } else { duke@435: // duke@435: // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE duke@435: // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case duke@435: // So we must adjust where to pick up the data to match the interpreter. duke@435: // duke@435: // Interpreter local[n] == MSW, local[n+1] == LSW however locals duke@435: // are accessed as negative so LSW is at LOW address duke@435: duke@435: // ld_off is MSW so get LSW duke@435: const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? duke@435: next_off : ld_off; twisti@1570: __ movq(r13, Address(saved_sp, offset)); duke@435: // st_off is LSW (i.e. reg.first()) twisti@1570: __ movq(Address(rsp, st_off), r13); duke@435: } duke@435: } else if (r_1->is_Register()) { // Register argument duke@435: Register r = r_1->as_Register(); duke@435: assert(r != rax, "must be different"); duke@435: if (r_2->is_valid()) { duke@435: // duke@435: // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE duke@435: // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case duke@435: // So we must adjust where to pick up the data to match the interpreter. duke@435: duke@435: const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? duke@435: next_off : ld_off; duke@435: duke@435: // this can be a misaligned move twisti@1570: __ movq(r, Address(saved_sp, offset)); duke@435: } else { duke@435: // sign extend and use a full word? twisti@1570: __ movl(r, Address(saved_sp, ld_off)); duke@435: } duke@435: } else { duke@435: if (!r_2->is_valid()) { twisti@1570: __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off)); duke@435: } else { twisti@1570: __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off)); duke@435: } duke@435: } duke@435: } duke@435: duke@435: // 6243940 We might end up in handle_wrong_method if duke@435: // the callee is deoptimized as we race thru here. If that duke@435: // happens we don't want to take a safepoint because the duke@435: // caller frame will look interpreted and arguments are now duke@435: // "compiled" so it is much better to make this transition duke@435: // invisible to the stack walking code. Unfortunately if duke@435: // we try and find the callee by normal means a safepoint duke@435: // is possible. So we stash the desired callee in the thread duke@435: // and the vm will find there should this case occur. duke@435: never@739: __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx); duke@435: coleenp@4037: // put Method* where a c2i would expect should we end up there coleenp@4037: // only needed becaus eof c2 resolve stubs return Method* as a result in duke@435: // rax never@739: __ mov(rax, rbx); duke@435: __ jmp(r11); duke@435: } duke@435: duke@435: // --------------------------------------------------------------- duke@435: AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, duke@435: int total_args_passed, duke@435: int comp_args_on_stack, duke@435: const BasicType *sig_bt, never@1622: const VMRegPair *regs, never@1622: AdapterFingerPrint* fingerprint) { duke@435: address i2c_entry = __ pc(); duke@435: duke@435: gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); duke@435: duke@435: // ------------------------------------------------------------------------- coleenp@4037: // Generate a C2I adapter. On entry we know rbx holds the Method* during calls duke@435: // to the interpreter. The args start out packed in the compiled layout. They duke@435: // need to be unpacked into the interpreter layout. This will almost always duke@435: // require some stack space. We grow the current (compiled) stack, then repack duke@435: // the args. We finally end in a jump to the generic interpreter entry point. duke@435: // On exit from the interpreter, the interpreter will restore our SP (lest the duke@435: // compiled code, which relys solely on SP and not RBP, get sick). duke@435: duke@435: address c2i_unverified_entry = __ pc(); duke@435: Label skip_fixup; duke@435: Label ok; duke@435: duke@435: Register holder = rax; duke@435: Register receiver = j_rarg0; duke@435: Register temp = rbx; duke@435: duke@435: { coleenp@548: __ load_klass(temp, receiver); coleenp@4037: __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset())); coleenp@4037: __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset())); duke@435: __ jcc(Assembler::equal, ok); duke@435: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); duke@435: duke@435: __ bind(ok); duke@435: // Method might have been compiled since the call site was patched to duke@435: // interpreted if that is the case treat it as a miss so we can get duke@435: // the call site corrected. coleenp@4037: __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, skip_fixup); duke@435: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); duke@435: } duke@435: duke@435: address c2i_entry = __ pc(); duke@435: duke@435: gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); duke@435: duke@435: __ flush(); never@1622: return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); duke@435: } duke@435: duke@435: int SharedRuntime::c_calling_convention(const BasicType *sig_bt, duke@435: VMRegPair *regs, duke@435: int total_args_passed) { duke@435: // We return the amount of VMRegImpl stack slots we need to reserve for all duke@435: // the arguments NOT counting out_preserve_stack_slots. duke@435: duke@435: // NOTE: These arrays will have to change when c1 is ported duke@435: #ifdef _WIN64 duke@435: static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { duke@435: c_rarg0, c_rarg1, c_rarg2, c_rarg3 duke@435: }; duke@435: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { duke@435: c_farg0, c_farg1, c_farg2, c_farg3 duke@435: }; duke@435: #else duke@435: static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { duke@435: c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5 duke@435: }; duke@435: static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { duke@435: c_farg0, c_farg1, c_farg2, c_farg3, duke@435: c_farg4, c_farg5, c_farg6, c_farg7 duke@435: }; duke@435: #endif // _WIN64 duke@435: duke@435: duke@435: uint int_args = 0; duke@435: uint fp_args = 0; duke@435: uint stk_args = 0; // inc by 2 each time duke@435: duke@435: for (int i = 0; i < total_args_passed; i++) { duke@435: switch (sig_bt[i]) { duke@435: case T_BOOLEAN: duke@435: case T_CHAR: duke@435: case T_BYTE: duke@435: case T_SHORT: duke@435: case T_INT: duke@435: if (int_args < Argument::n_int_register_parameters_c) { duke@435: regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); duke@435: #ifdef _WIN64 duke@435: fp_args++; duke@435: // Allocate slots for callee to stuff register args the stack. duke@435: stk_args += 2; duke@435: #endif duke@435: } else { duke@435: regs[i].set1(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_LONG: duke@435: assert(sig_bt[i + 1] == T_VOID, "expecting half"); duke@435: // fall through duke@435: case T_OBJECT: duke@435: case T_ARRAY: duke@435: case T_ADDRESS: roland@4051: case T_METADATA: duke@435: if (int_args < Argument::n_int_register_parameters_c) { duke@435: regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); duke@435: #ifdef _WIN64 duke@435: fp_args++; duke@435: stk_args += 2; duke@435: #endif duke@435: } else { duke@435: regs[i].set2(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_FLOAT: duke@435: if (fp_args < Argument::n_float_register_parameters_c) { duke@435: regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); duke@435: #ifdef _WIN64 duke@435: int_args++; duke@435: // Allocate slots for callee to stuff register args the stack. duke@435: stk_args += 2; duke@435: #endif duke@435: } else { duke@435: regs[i].set1(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_DOUBLE: duke@435: assert(sig_bt[i + 1] == T_VOID, "expecting half"); duke@435: if (fp_args < Argument::n_float_register_parameters_c) { duke@435: regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); duke@435: #ifdef _WIN64 duke@435: int_args++; duke@435: // Allocate slots for callee to stuff register args the stack. duke@435: stk_args += 2; duke@435: #endif duke@435: } else { duke@435: regs[i].set2(VMRegImpl::stack2reg(stk_args)); duke@435: stk_args += 2; duke@435: } duke@435: break; duke@435: case T_VOID: // Halves of longs and doubles duke@435: assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); duke@435: regs[i].set_bad(); duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: break; duke@435: } duke@435: } duke@435: #ifdef _WIN64 duke@435: // windows abi requires that we always allocate enough stack space duke@435: // for 4 64bit registers to be stored down. duke@435: if (stk_args < 8) { duke@435: stk_args = 8; duke@435: } duke@435: #endif // _WIN64 duke@435: duke@435: return stk_args; duke@435: } duke@435: duke@435: // On 64 bit we will store integer like items to the stack as duke@435: // 64 bits items (sparc abi) even though java would only store duke@435: // 32bits for a parameter. On 32bit it will simply be 32 bits duke@435: // So this routine will do 32->32 on 32bit and 32->64 on 64bit duke@435: static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { duke@435: if (src.first()->is_stack()) { duke@435: if (dst.first()->is_stack()) { duke@435: // stack to stack duke@435: __ movslq(rax, Address(rbp, reg2offset_in(src.first()))); duke@435: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); duke@435: } else { duke@435: // stack to reg duke@435: __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); duke@435: } duke@435: } else if (dst.first()->is_stack()) { duke@435: // reg to stack duke@435: // Do we really have to sign extend??? duke@435: // __ movslq(src.first()->as_Register(), src.first()->as_Register()); duke@435: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); duke@435: } else { duke@435: // Do we really have to sign extend??? duke@435: // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); duke@435: if (dst.first() != src.first()) { duke@435: __ movq(dst.first()->as_Register(), src.first()->as_Register()); duke@435: } duke@435: } duke@435: } duke@435: never@3500: static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { never@3500: if (src.first()->is_stack()) { never@3500: if (dst.first()->is_stack()) { never@3500: // stack to stack never@3500: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); never@3500: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); never@3500: } else { never@3500: // stack to reg never@3500: __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); never@3500: } never@3500: } else if (dst.first()->is_stack()) { never@3500: // reg to stack never@3500: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); never@3500: } else { never@3500: if (dst.first() != src.first()) { never@3500: __ movq(dst.first()->as_Register(), src.first()->as_Register()); never@3500: } never@3500: } never@3500: } duke@435: duke@435: // An oop arg. Must pass a handle not the oop itself duke@435: static void object_move(MacroAssembler* masm, duke@435: OopMap* map, duke@435: int oop_handle_offset, duke@435: int framesize_in_slots, duke@435: VMRegPair src, duke@435: VMRegPair dst, duke@435: bool is_receiver, duke@435: int* receiver_offset) { duke@435: duke@435: // must pass a handle. First figure out the location we use as a handle duke@435: duke@435: Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); duke@435: duke@435: // See if oop is NULL if it is we need no handle duke@435: duke@435: if (src.first()->is_stack()) { duke@435: duke@435: // Oop is already on the stack as an argument duke@435: int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); duke@435: map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); duke@435: if (is_receiver) { duke@435: *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; duke@435: } duke@435: never@739: __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); never@739: __ lea(rHandle, Address(rbp, reg2offset_in(src.first()))); duke@435: // conditionally move a NULL never@739: __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); duke@435: } else { duke@435: duke@435: // Oop is in an a register we must store it to the space we reserve duke@435: // on the stack for oop_handles and pass a handle if oop is non-NULL duke@435: duke@435: const Register rOop = src.first()->as_Register(); duke@435: int oop_slot; duke@435: if (rOop == j_rarg0) duke@435: oop_slot = 0; duke@435: else if (rOop == j_rarg1) duke@435: oop_slot = 1; duke@435: else if (rOop == j_rarg2) duke@435: oop_slot = 2; duke@435: else if (rOop == j_rarg3) duke@435: oop_slot = 3; duke@435: else if (rOop == j_rarg4) duke@435: oop_slot = 4; duke@435: else { duke@435: assert(rOop == j_rarg5, "wrong register"); duke@435: oop_slot = 5; duke@435: } duke@435: duke@435: oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; duke@435: int offset = oop_slot*VMRegImpl::stack_slot_size; duke@435: duke@435: map->set_oop(VMRegImpl::stack2reg(oop_slot)); duke@435: // Store oop in handle area, may be NULL never@739: __ movptr(Address(rsp, offset), rOop); duke@435: if (is_receiver) { duke@435: *receiver_offset = offset; duke@435: } duke@435: never@739: __ cmpptr(rOop, (int32_t)NULL_WORD); never@739: __ lea(rHandle, Address(rsp, offset)); duke@435: // conditionally move a NULL from the handle area where it was just stored never@739: __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); duke@435: } duke@435: duke@435: // If arg is on the stack then place it otherwise it is already in correct reg. duke@435: if (dst.first()->is_stack()) { never@739: __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); duke@435: } duke@435: } duke@435: duke@435: // A float arg may have to do float reg int reg conversion duke@435: static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { duke@435: assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); duke@435: duke@435: // The calling conventions assures us that each VMregpair is either duke@435: // all really one physical register or adjacent stack slots. duke@435: // This greatly simplifies the cases here compared to sparc. duke@435: duke@435: if (src.first()->is_stack()) { duke@435: if (dst.first()->is_stack()) { duke@435: __ movl(rax, Address(rbp, reg2offset_in(src.first()))); never@739: __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); duke@435: } else { duke@435: // stack to reg duke@435: assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); duke@435: __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); duke@435: } duke@435: } else if (dst.first()->is_stack()) { duke@435: // reg to stack duke@435: assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); duke@435: __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); duke@435: } else { duke@435: // reg to reg duke@435: // In theory these overlap but the ordering is such that this is likely a nop duke@435: if ( src.first() != dst.first()) { duke@435: __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); duke@435: } duke@435: } duke@435: } duke@435: duke@435: // A long move duke@435: static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { duke@435: duke@435: // The calling conventions assures us that each VMregpair is either duke@435: // all really one physical register or adjacent stack slots. duke@435: // This greatly simplifies the cases here compared to sparc. duke@435: duke@435: if (src.is_single_phys_reg() ) { duke@435: if (dst.is_single_phys_reg()) { duke@435: if (dst.first() != src.first()) { never@739: __ mov(dst.first()->as_Register(), src.first()->as_Register()); duke@435: } duke@435: } else { duke@435: assert(dst.is_single_reg(), "not a stack pair"); duke@435: __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); duke@435: } duke@435: } else if (dst.is_single_phys_reg()) { duke@435: assert(src.is_single_reg(), "not a stack pair"); duke@435: __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); duke@435: } else { duke@435: assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); duke@435: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); duke@435: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); duke@435: } duke@435: } duke@435: duke@435: // A double move duke@435: static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { duke@435: duke@435: // The calling conventions assures us that each VMregpair is either duke@435: // all really one physical register or adjacent stack slots. duke@435: // This greatly simplifies the cases here compared to sparc. duke@435: duke@435: if (src.is_single_phys_reg() ) { duke@435: if (dst.is_single_phys_reg()) { duke@435: // In theory these overlap but the ordering is such that this is likely a nop duke@435: if ( src.first() != dst.first()) { duke@435: __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); duke@435: } duke@435: } else { duke@435: assert(dst.is_single_reg(), "not a stack pair"); duke@435: __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); duke@435: } duke@435: } else if (dst.is_single_phys_reg()) { duke@435: assert(src.is_single_reg(), "not a stack pair"); duke@435: __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); duke@435: } else { duke@435: assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); duke@435: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); duke@435: __ movq(Address(rsp, reg2offset_out(dst.first())), rax); duke@435: } duke@435: } duke@435: duke@435: duke@435: void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { duke@435: // We always ignore the frame_slots arg and just use the space just below frame pointer duke@435: // which by this time is free to use duke@435: switch (ret_type) { duke@435: case T_FLOAT: duke@435: __ movflt(Address(rbp, -wordSize), xmm0); duke@435: break; duke@435: case T_DOUBLE: duke@435: __ movdbl(Address(rbp, -wordSize), xmm0); duke@435: break; duke@435: case T_VOID: break; duke@435: default: { never@739: __ movptr(Address(rbp, -wordSize), rax); duke@435: } duke@435: } duke@435: } duke@435: duke@435: void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { duke@435: // We always ignore the frame_slots arg and just use the space just below frame pointer duke@435: // which by this time is free to use duke@435: switch (ret_type) { duke@435: case T_FLOAT: duke@435: __ movflt(xmm0, Address(rbp, -wordSize)); duke@435: break; duke@435: case T_DOUBLE: duke@435: __ movdbl(xmm0, Address(rbp, -wordSize)); duke@435: break; duke@435: case T_VOID: break; duke@435: default: { never@739: __ movptr(rax, Address(rbp, -wordSize)); duke@435: } duke@435: } duke@435: } duke@435: duke@435: static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { duke@435: for ( int i = first_arg ; i < arg_count ; i++ ) { duke@435: if (args[i].first()->is_Register()) { never@739: __ push(args[i].first()->as_Register()); duke@435: } else if (args[i].first()->is_XMMRegister()) { never@739: __ subptr(rsp, 2*wordSize); duke@435: __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister()); duke@435: } duke@435: } duke@435: } duke@435: duke@435: static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { duke@435: for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { duke@435: if (args[i].first()->is_Register()) { never@739: __ pop(args[i].first()->as_Register()); duke@435: } else if (args[i].first()->is_XMMRegister()) { duke@435: __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0)); never@739: __ addptr(rsp, 2*wordSize); duke@435: } duke@435: } duke@435: } duke@435: never@3500: never@3500: static void save_or_restore_arguments(MacroAssembler* masm, never@3500: const int stack_slots, never@3500: const int total_in_args, never@3500: const int arg_save_area, never@3500: OopMap* map, never@3500: VMRegPair* in_regs, never@3500: BasicType* in_sig_bt) { never@3500: // if map is non-NULL then the code should store the values, never@3500: // otherwise it should load them. never@3608: int slot = arg_save_area; never@3500: // Save down double word first never@3500: for ( int i = 0; i < total_in_args; i++) { never@3500: if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) { never@3500: int offset = slot * VMRegImpl::stack_slot_size; never@3608: slot += VMRegImpl::slots_per_word; never@3608: assert(slot <= stack_slots, "overflow"); never@3500: if (map != NULL) { never@3500: __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); never@3500: } else { never@3500: __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); never@3500: } never@3500: } never@3500: if (in_regs[i].first()->is_Register() && never@3500: (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { never@3500: int offset = slot * VMRegImpl::stack_slot_size; never@3500: if (map != NULL) { never@3500: __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); never@3500: if (in_sig_bt[i] == T_ARRAY) { never@3500: map->set_oop(VMRegImpl::stack2reg(slot));; never@3500: } never@3500: } else { never@3500: __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); never@3500: } never@3610: slot += VMRegImpl::slots_per_word; never@3500: } never@3500: } never@3500: // Save or restore single word registers never@3500: for ( int i = 0; i < total_in_args; i++) { never@3500: if (in_regs[i].first()->is_Register()) { never@3500: int offset = slot * VMRegImpl::stack_slot_size; never@3608: slot++; never@3608: assert(slot <= stack_slots, "overflow"); never@3500: never@3500: // Value is in an input register pass we must flush it to the stack never@3500: const Register reg = in_regs[i].first()->as_Register(); never@3500: switch (in_sig_bt[i]) { never@3500: case T_BOOLEAN: never@3500: case T_CHAR: never@3500: case T_BYTE: never@3500: case T_SHORT: never@3500: case T_INT: never@3500: if (map != NULL) { never@3500: __ movl(Address(rsp, offset), reg); never@3500: } else { never@3500: __ movl(reg, Address(rsp, offset)); never@3500: } never@3500: break; never@3500: case T_ARRAY: never@3500: case T_LONG: never@3500: // handled above never@3500: break; never@3500: case T_OBJECT: never@3500: default: ShouldNotReachHere(); never@3500: } never@3500: } else if (in_regs[i].first()->is_XMMRegister()) { never@3500: if (in_sig_bt[i] == T_FLOAT) { never@3500: int offset = slot * VMRegImpl::stack_slot_size; never@3608: slot++; never@3608: assert(slot <= stack_slots, "overflow"); never@3500: if (map != NULL) { never@3500: __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); never@3500: } else { never@3500: __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); never@3500: } never@3500: } never@3500: } else if (in_regs[i].first()->is_stack()) { never@3500: if (in_sig_bt[i] == T_ARRAY && map != NULL) { never@3500: int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); never@3500: map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); never@3500: } never@3500: } never@3500: } never@3500: } never@3500: never@3500: never@3500: // Check GC_locker::needs_gc and enter the runtime if it's true. This never@3500: // keeps a new JNI critical region from starting until a GC has been never@3500: // forced. Save down any oops in registers and describe them in an never@3500: // OopMap. never@3500: static void check_needs_gc_for_critical_native(MacroAssembler* masm, never@3500: int stack_slots, never@3500: int total_c_args, never@3500: int total_in_args, never@3500: int arg_save_area, never@3500: OopMapSet* oop_maps, never@3500: VMRegPair* in_regs, never@3500: BasicType* in_sig_bt) { never@3500: __ block_comment("check GC_locker::needs_gc"); never@3500: Label cont; never@3500: __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false); never@3500: __ jcc(Assembler::equal, cont); never@3500: never@3500: // Save down any incoming oops and call into the runtime to halt for a GC never@3500: never@3500: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); never@3500: save_or_restore_arguments(masm, stack_slots, total_in_args, never@3500: arg_save_area, map, in_regs, in_sig_bt); never@3500: never@3500: address the_pc = __ pc(); never@3500: oop_maps->add_gc_map( __ offset(), map); never@3500: __ set_last_Java_frame(rsp, noreg, the_pc); never@3500: never@3500: __ block_comment("block_for_jni_critical"); never@3500: __ movptr(c_rarg0, r15_thread); never@3500: __ mov(r12, rsp); // remember sp never@3500: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows never@3500: __ andptr(rsp, -16); // align stack as required by ABI never@3500: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical))); never@3500: __ mov(rsp, r12); // restore sp never@3500: __ reinit_heapbase(); never@3500: never@3500: __ reset_last_Java_frame(false, true); never@3500: never@3500: save_or_restore_arguments(masm, stack_slots, total_in_args, never@3500: arg_save_area, NULL, in_regs, in_sig_bt); never@3500: never@3500: __ bind(cont); never@3500: #ifdef ASSERT never@3500: if (StressCriticalJNINatives) { never@3500: // Stress register saving never@3500: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); never@3500: save_or_restore_arguments(masm, stack_slots, total_in_args, never@3500: arg_save_area, map, in_regs, in_sig_bt); never@3500: // Destroy argument registers never@3500: for (int i = 0; i < total_in_args - 1; i++) { never@3500: if (in_regs[i].first()->is_Register()) { never@3500: const Register reg = in_regs[i].first()->as_Register(); never@3500: __ xorptr(reg, reg); never@3500: } else if (in_regs[i].first()->is_XMMRegister()) { never@3500: __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister()); never@3500: } else if (in_regs[i].first()->is_FloatRegister()) { never@3500: ShouldNotReachHere(); never@3500: } else if (in_regs[i].first()->is_stack()) { never@3500: // Nothing to do never@3500: } else { never@3500: ShouldNotReachHere(); never@3500: } never@3500: if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) { never@3500: i++; never@3500: } never@3500: } never@3500: never@3500: save_or_restore_arguments(masm, stack_slots, total_in_args, never@3500: arg_save_area, NULL, in_regs, in_sig_bt); never@3500: } never@3500: #endif never@3500: } never@3500: never@3500: // Unpack an array argument into a pointer to the body and the length never@3500: // if the array is non-null, otherwise pass 0 for both. never@3500: static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { never@3500: Register tmp_reg = rax; never@3500: assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg, never@3500: "possible collision"); never@3500: assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg, never@3500: "possible collision"); never@3500: never@3500: // Pass the length, ptr pair never@3500: Label is_null, done; never@3500: VMRegPair tmp; never@3500: tmp.set_ptr(tmp_reg->as_VMReg()); never@3500: if (reg.first()->is_stack()) { never@3500: // Load the arg up from the stack never@3500: move_ptr(masm, reg, tmp); never@3500: reg = tmp; never@3500: } never@3500: __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); never@3500: __ jccb(Assembler::equal, is_null); never@3500: __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type))); never@3500: move_ptr(masm, tmp, body_arg); never@3500: // load the length relative to the body. never@3500: __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() - never@3500: arrayOopDesc::base_offset_in_bytes(in_elem_type))); never@3500: move32_64(masm, tmp, length_arg); never@3500: __ jmpb(done); never@3500: __ bind(is_null); never@3500: // Pass zeros never@3500: __ xorptr(tmp_reg, tmp_reg); never@3500: move_ptr(masm, tmp, body_arg); never@3500: move32_64(masm, tmp, length_arg); never@3500: __ bind(done); never@3500: } never@3500: never@3608: twisti@3969: // Different signatures may require very different orders for the move twisti@3969: // to avoid clobbering other arguments. There's no simple way to twisti@3969: // order them safely. Compute a safe order for issuing stores and twisti@3969: // break any cycles in those stores. This code is fairly general but twisti@3969: // it's not necessary on the other platforms so we keep it in the twisti@3969: // platform dependent code instead of moving it into a shared file. twisti@3969: // (See bugs 7013347 & 7145024.) twisti@3969: // Note that this code is specific to LP64. never@3608: class ComputeMoveOrder: public StackObj { never@3608: class MoveOperation: public ResourceObj { never@3608: friend class ComputeMoveOrder; never@3608: private: never@3608: VMRegPair _src; never@3608: VMRegPair _dst; never@3608: int _src_index; never@3608: int _dst_index; never@3608: bool _processed; never@3608: MoveOperation* _next; never@3608: MoveOperation* _prev; never@3608: never@3608: static int get_id(VMRegPair r) { never@3608: return r.first()->value(); never@3608: } never@3608: never@3608: public: never@3608: MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): never@3608: _src(src) never@3608: , _src_index(src_index) never@3608: , _dst(dst) never@3608: , _dst_index(dst_index) never@3608: , _next(NULL) never@3608: , _prev(NULL) never@3608: , _processed(false) { never@3608: } never@3608: never@3608: VMRegPair src() const { return _src; } never@3608: int src_id() const { return get_id(src()); } never@3608: int src_index() const { return _src_index; } never@3608: VMRegPair dst() const { return _dst; } never@3608: void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; } never@3608: int dst_index() const { return _dst_index; } never@3608: int dst_id() const { return get_id(dst()); } never@3608: MoveOperation* next() const { return _next; } never@3608: MoveOperation* prev() const { return _prev; } never@3608: void set_processed() { _processed = true; } never@3608: bool is_processed() const { return _processed; } never@3608: never@3608: // insert never@3608: void break_cycle(VMRegPair temp_register) { never@3608: // create a new store following the last store never@3608: // to move from the temp_register to the original never@3608: MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst()); never@3608: never@3608: // break the cycle of links and insert new_store at the end never@3608: // break the reverse link. never@3608: MoveOperation* p = prev(); never@3608: assert(p->next() == this, "must be"); never@3608: _prev = NULL; never@3608: p->_next = new_store; never@3608: new_store->_prev = p; never@3608: never@3608: // change the original store to save it's value in the temp. never@3608: set_dst(-1, temp_register); never@3608: } never@3608: never@3608: void link(GrowableArray& killer) { never@3608: // link this store in front the store that it depends on never@3608: MoveOperation* n = killer.at_grow(src_id(), NULL); never@3608: if (n != NULL) { never@3608: assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet"); never@3608: _next = n; never@3608: n->_prev = this; never@3608: } never@3608: } never@3608: }; never@3608: never@3608: private: never@3608: GrowableArray edges; never@3608: never@3608: public: never@3608: ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, never@3608: BasicType* in_sig_bt, GrowableArray& arg_order, VMRegPair tmp_vmreg) { never@3608: // Move operations where the dest is the stack can all be never@3608: // scheduled first since they can't interfere with the other moves. never@3608: for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { never@3608: if (in_sig_bt[i] == T_ARRAY) { never@3608: c_arg--; never@3608: if (out_regs[c_arg].first()->is_stack() && never@3608: out_regs[c_arg + 1].first()->is_stack()) { never@3608: arg_order.push(i); never@3608: arg_order.push(c_arg); never@3608: } else { never@3608: if (out_regs[c_arg].first()->is_stack() || never@3608: in_regs[i].first() == out_regs[c_arg].first()) { never@3608: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]); never@3608: } else { never@3608: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); never@3608: } never@3608: } never@3608: } else if (in_sig_bt[i] == T_VOID) { never@3608: arg_order.push(i); never@3608: arg_order.push(c_arg); never@3608: } else { never@3608: if (out_regs[c_arg].first()->is_stack() || never@3608: in_regs[i].first() == out_regs[c_arg].first()) { never@3608: arg_order.push(i); never@3608: arg_order.push(c_arg); never@3608: } else { never@3608: add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); never@3608: } never@3608: } never@3608: } never@3608: // Break any cycles in the register moves and emit the in the never@3608: // proper order. never@3608: GrowableArray* stores = get_store_order(tmp_vmreg); never@3608: for (int i = 0; i < stores->length(); i++) { never@3608: arg_order.push(stores->at(i)->src_index()); never@3608: arg_order.push(stores->at(i)->dst_index()); never@3608: } never@3608: } never@3608: never@3608: // Collected all the move operations never@3608: void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { never@3608: if (src.first() == dst.first()) return; never@3608: edges.append(new MoveOperation(src_index, src, dst_index, dst)); never@3608: } never@3608: never@3608: // Walk the edges breaking cycles between moves. The result list never@3608: // can be walked in order to produce the proper set of loads never@3608: GrowableArray* get_store_order(VMRegPair temp_register) { never@3608: // Record which moves kill which values never@3608: GrowableArray killer; never@3608: for (int i = 0; i < edges.length(); i++) { never@3608: MoveOperation* s = edges.at(i); never@3608: assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer"); never@3608: killer.at_put_grow(s->dst_id(), s, NULL); never@3608: } never@3608: assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL, never@3608: "make sure temp isn't in the registers that are killed"); never@3608: never@3608: // create links between loads and stores never@3608: for (int i = 0; i < edges.length(); i++) { never@3608: edges.at(i)->link(killer); never@3608: } never@3608: never@3608: // at this point, all the move operations are chained together never@3608: // in a doubly linked list. Processing it backwards finds never@3608: // the beginning of the chain, forwards finds the end. If there's never@3608: // a cycle it can be broken at any point, so pick an edge and walk never@3608: // backward until the list ends or we end where we started. never@3608: GrowableArray* stores = new GrowableArray(); never@3608: for (int e = 0; e < edges.length(); e++) { never@3608: MoveOperation* s = edges.at(e); never@3608: if (!s->is_processed()) { never@3608: MoveOperation* start = s; never@3608: // search for the beginning of the chain or cycle never@3608: while (start->prev() != NULL && start->prev() != s) { never@3608: start = start->prev(); never@3608: } never@3608: if (start->prev() == s) { never@3608: start->break_cycle(temp_register); never@3608: } never@3608: // walk the chain forward inserting to store list never@3608: while (start != NULL) { never@3608: stores->append(start); never@3608: start->set_processed(); never@3608: start = start->next(); never@3608: } never@3608: } never@3608: } never@3608: return stores; never@3608: } never@3608: }; never@3608: twisti@3969: static void verify_oop_args(MacroAssembler* masm, twisti@4101: methodHandle method, twisti@3969: const BasicType* sig_bt, twisti@3969: const VMRegPair* regs) { twisti@3969: Register temp_reg = rbx; // not part of any compiled calling seq twisti@3969: if (VerifyOops) { twisti@4101: for (int i = 0; i < method->size_of_parameters(); i++) { twisti@3969: if (sig_bt[i] == T_OBJECT || twisti@3969: sig_bt[i] == T_ARRAY) { twisti@3969: VMReg r = regs[i].first(); twisti@3969: assert(r->is_valid(), "bad oop arg"); twisti@3969: if (r->is_stack()) { twisti@3969: __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); twisti@3969: __ verify_oop(temp_reg); twisti@3969: } else { twisti@3969: __ verify_oop(r->as_Register()); twisti@3969: } twisti@3969: } twisti@3969: } twisti@3969: } twisti@3969: } twisti@3969: twisti@3969: static void gen_special_dispatch(MacroAssembler* masm, twisti@4101: methodHandle method, twisti@3969: const BasicType* sig_bt, twisti@3969: const VMRegPair* regs) { twisti@4101: verify_oop_args(masm, method, sig_bt, regs); twisti@4101: vmIntrinsics::ID iid = method->intrinsic_id(); twisti@3969: twisti@3969: // Now write the args into the outgoing interpreter space twisti@3969: bool has_receiver = false; twisti@3969: Register receiver_reg = noreg; twisti@3969: int member_arg_pos = -1; twisti@3969: Register member_reg = noreg; twisti@4101: int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); twisti@3969: if (ref_kind != 0) { twisti@4101: member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument twisti@3969: member_reg = rbx; // known to be free at this point twisti@3969: has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); twisti@4101: } else if (iid == vmIntrinsics::_invokeBasic) { twisti@3969: has_receiver = true; twisti@3969: } else { twisti@4101: fatal(err_msg_res("unexpected intrinsic id %d", iid)); twisti@3969: } twisti@3969: twisti@3969: if (member_reg != noreg) { twisti@3969: // Load the member_arg into register, if necessary. twisti@4101: SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); twisti@3969: VMReg r = regs[member_arg_pos].first(); twisti@3969: if (r->is_stack()) { twisti@3969: __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); twisti@3969: } else { twisti@3969: // no data motion is needed twisti@3969: member_reg = r->as_Register(); twisti@3969: } twisti@3969: } twisti@3969: twisti@3969: if (has_receiver) { twisti@3969: // Make sure the receiver is loaded into a register. twisti@4101: assert(method->size_of_parameters() > 0, "oob"); twisti@3969: assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); twisti@3969: VMReg r = regs[0].first(); twisti@3969: assert(r->is_valid(), "bad receiver arg"); twisti@3969: if (r->is_stack()) { twisti@3969: // Porting note: This assumes that compiled calling conventions always twisti@3969: // pass the receiver oop in a register. If this is not true on some twisti@3969: // platform, pick a temp and load the receiver from stack. twisti@4101: fatal("receiver always in a register"); twisti@3969: receiver_reg = j_rarg0; // known to be free at this point twisti@3969: __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); twisti@3969: } else { twisti@3969: // no data motion is needed twisti@3969: receiver_reg = r->as_Register(); twisti@3969: } twisti@3969: } twisti@3969: twisti@3969: // Figure out which address we are really jumping to: twisti@4101: MethodHandles::generate_method_handle_dispatch(masm, iid, twisti@3969: receiver_reg, member_reg, /*for_compiler_entry:*/ true); twisti@3969: } never@3608: duke@435: // --------------------------------------------------------------------------- duke@435: // Generate a native wrapper for a given method. The method takes arguments duke@435: // in the Java compiled code convention, marshals them to the native duke@435: // convention (handlizes oops, etc), transitions to native, makes the call, duke@435: // returns to java state (possibly blocking), unhandlizes any result and duke@435: // returns. twisti@3969: // twisti@3969: // Critical native functions are a shorthand for the use of twisti@3969: // GetPrimtiveArrayCritical and disallow the use of any other JNI twisti@3969: // functions. The wrapper is expected to unpack the arguments before twisti@3969: // passing them to the callee and perform checks before and after the twisti@3969: // native call to ensure that they GC_locker twisti@3969: // lock_critical/unlock_critical semantics are followed. Some other twisti@3969: // parts of JNI setup are skipped like the tear down of the JNI handle twisti@3969: // block and the check for pending exceptions it's impossible for them twisti@3969: // to be thrown. twisti@3969: // twisti@3969: // They are roughly structured like this: twisti@3969: // if (GC_locker::needs_gc()) twisti@3969: // SharedRuntime::block_for_jni_critical(); twisti@3969: // tranistion to thread_in_native twisti@3969: // unpack arrray arguments and call native entry point twisti@3969: // check for safepoint in progress twisti@3969: // check if any thread suspend flags are set twisti@3969: // call into JVM and possible unlock the JNI critical twisti@3969: // if a GC was suppressed while in the critical native. twisti@3969: // transition back to thread_in_Java twisti@3969: // return to caller twisti@3969: // twisti@3969: nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, duke@435: methodHandle method, twisti@2687: int compile_id, twisti@3969: BasicType* in_sig_bt, twisti@3969: VMRegPair* in_regs, duke@435: BasicType ret_type) { twisti@3969: if (method->is_method_handle_intrinsic()) { twisti@3969: vmIntrinsics::ID iid = method->intrinsic_id(); twisti@3969: intptr_t start = (intptr_t)__ pc(); twisti@3969: int vep_offset = ((intptr_t)__ pc()) - start; twisti@3969: gen_special_dispatch(masm, twisti@4101: method, twisti@3969: in_sig_bt, twisti@3969: in_regs); twisti@3969: int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period twisti@3969: __ flush(); twisti@3969: int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually twisti@3969: return nmethod::new_native_nmethod(method, twisti@3969: compile_id, twisti@3969: masm->code(), twisti@3969: vep_offset, twisti@3969: frame_complete, twisti@3969: stack_slots / VMRegImpl::slots_per_word, twisti@3969: in_ByteSize(-1), twisti@3969: in_ByteSize(-1), twisti@3969: (OopMapSet*)NULL); twisti@3969: } never@3500: bool is_critical_native = true; never@3500: address native_func = method->critical_native_function(); never@3500: if (native_func == NULL) { never@3500: native_func = method->native_function(); never@3500: is_critical_native = false; never@3500: } never@3500: assert(native_func != NULL, "must have function"); never@3500: duke@435: // An OopMap for lock (and class if static) duke@435: OopMapSet *oop_maps = new OopMapSet(); duke@435: intptr_t start = (intptr_t)__ pc(); duke@435: duke@435: // We have received a description of where all the java arg are located duke@435: // on entry to the wrapper. We need to convert these args to where duke@435: // the jni function will expect them. To figure out where they go duke@435: // we convert the java signature to a C signature by inserting duke@435: // the hidden arguments as arg[0] and possibly arg[1] (static method) duke@435: twisti@4101: const int total_in_args = method->size_of_parameters(); never@3500: int total_c_args = total_in_args; never@3500: if (!is_critical_native) { never@3500: total_c_args += 1; never@3500: if (method->is_static()) { never@3500: total_c_args++; never@3500: } never@3500: } else { never@3500: for (int i = 0; i < total_in_args; i++) { never@3500: if (in_sig_bt[i] == T_ARRAY) { never@3500: total_c_args++; never@3500: } never@3500: } duke@435: } duke@435: duke@435: BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); never@3500: VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); never@3500: BasicType* in_elem_bt = NULL; duke@435: duke@435: int argc = 0; never@3500: if (!is_critical_native) { never@3500: out_sig_bt[argc++] = T_ADDRESS; never@3500: if (method->is_static()) { never@3500: out_sig_bt[argc++] = T_OBJECT; never@3500: } never@3500: never@3500: for (int i = 0; i < total_in_args ; i++ ) { never@3500: out_sig_bt[argc++] = in_sig_bt[i]; never@3500: } never@3500: } else { never@3500: Thread* THREAD = Thread::current(); never@3500: in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); never@3500: SignatureStream ss(method->signature()); never@3500: for (int i = 0; i < total_in_args ; i++ ) { never@3500: if (in_sig_bt[i] == T_ARRAY) { never@3500: // Arrays are passed as int, elem* pair never@3500: out_sig_bt[argc++] = T_INT; never@3500: out_sig_bt[argc++] = T_ADDRESS; never@3500: Symbol* atype = ss.as_symbol(CHECK_NULL); never@3500: const char* at = atype->as_C_string(); never@3500: if (strlen(at) == 2) { never@3500: assert(at[0] == '[', "must be"); never@3500: switch (at[1]) { never@3500: case 'B': in_elem_bt[i] = T_BYTE; break; never@3500: case 'C': in_elem_bt[i] = T_CHAR; break; never@3500: case 'D': in_elem_bt[i] = T_DOUBLE; break; never@3500: case 'F': in_elem_bt[i] = T_FLOAT; break; never@3500: case 'I': in_elem_bt[i] = T_INT; break; never@3500: case 'J': in_elem_bt[i] = T_LONG; break; never@3500: case 'S': in_elem_bt[i] = T_SHORT; break; never@3500: case 'Z': in_elem_bt[i] = T_BOOLEAN; break; never@3500: default: ShouldNotReachHere(); never@3500: } never@3500: } never@3500: } else { never@3500: out_sig_bt[argc++] = in_sig_bt[i]; never@3500: in_elem_bt[i] = T_VOID; never@3500: } never@3500: if (in_sig_bt[i] != T_VOID) { never@3500: assert(in_sig_bt[i] == ss.type(), "must match"); never@3500: ss.next(); never@3500: } never@3500: } duke@435: } duke@435: duke@435: // Now figure out where the args must be stored and how much stack space duke@435: // they require. duke@435: int out_arg_slots; duke@435: out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); duke@435: duke@435: // Compute framesize for the wrapper. We need to handlize all oops in duke@435: // incoming registers duke@435: duke@435: // Calculate the total number of stack slots we will need. duke@435: duke@435: // First count the abi requirement plus all of the outgoing args duke@435: int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; duke@435: duke@435: // Now the space for the inbound oop handle area never@3500: int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers never@3500: if (is_critical_native) { never@3500: // Critical natives may have to call out so they need a save area never@3500: // for register arguments. never@3500: int double_slots = 0; never@3500: int single_slots = 0; never@3500: for ( int i = 0; i < total_in_args; i++) { never@3500: if (in_regs[i].first()->is_Register()) { never@3500: const Register reg = in_regs[i].first()->as_Register(); never@3500: switch (in_sig_bt[i]) { never@3500: case T_BOOLEAN: never@3500: case T_BYTE: never@3500: case T_SHORT: never@3500: case T_CHAR: never@3500: case T_INT: single_slots++; break; twisti@3969: case T_ARRAY: // specific to LP64 (7145024) never@3500: case T_LONG: double_slots++; break; never@3500: default: ShouldNotReachHere(); never@3500: } never@3500: } else if (in_regs[i].first()->is_XMMRegister()) { never@3500: switch (in_sig_bt[i]) { never@3500: case T_FLOAT: single_slots++; break; never@3500: case T_DOUBLE: double_slots++; break; never@3500: default: ShouldNotReachHere(); never@3500: } never@3500: } else if (in_regs[i].first()->is_FloatRegister()) { never@3500: ShouldNotReachHere(); never@3500: } never@3500: } never@3500: total_save_slots = double_slots * 2 + single_slots; never@3500: // align the save area never@3500: if (double_slots != 0) { never@3500: stack_slots = round_to(stack_slots, 2); never@3500: } never@3500: } duke@435: duke@435: int oop_handle_offset = stack_slots; never@3500: stack_slots += total_save_slots; duke@435: duke@435: // Now any space we need for handlizing a klass if static method duke@435: duke@435: int klass_slot_offset = 0; duke@435: int klass_offset = -1; duke@435: int lock_slot_offset = 0; duke@435: bool is_static = false; duke@435: duke@435: if (method->is_static()) { duke@435: klass_slot_offset = stack_slots; duke@435: stack_slots += VMRegImpl::slots_per_word; duke@435: klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; duke@435: is_static = true; duke@435: } duke@435: duke@435: // Plus a lock if needed duke@435: duke@435: if (method->is_synchronized()) { duke@435: lock_slot_offset = stack_slots; duke@435: stack_slots += VMRegImpl::slots_per_word; duke@435: } duke@435: duke@435: // Now a place (+2) to save return values or temp during shuffling duke@435: // + 4 for return address (which we own) and saved rbp duke@435: stack_slots += 6; duke@435: duke@435: // Ok The space we have allocated will look like: duke@435: // duke@435: // duke@435: // FP-> | | duke@435: // |---------------------| duke@435: // | 2 slots for moves | duke@435: // |---------------------| duke@435: // | lock box (if sync) | duke@435: // |---------------------| <- lock_slot_offset duke@435: // | klass (if static) | duke@435: // |---------------------| <- klass_slot_offset duke@435: // | oopHandle area | duke@435: // |---------------------| <- oop_handle_offset (6 java arg registers) duke@435: // | outbound memory | duke@435: // | based arguments | duke@435: // | | duke@435: // |---------------------| duke@435: // | | duke@435: // SP-> | out_preserved_slots | duke@435: // duke@435: // duke@435: duke@435: duke@435: // Now compute actual number of stack words we need rounding to make duke@435: // stack properly aligned. xlu@959: stack_slots = round_to(stack_slots, StackAlignmentInSlots); duke@435: duke@435: int stack_size = stack_slots * VMRegImpl::stack_slot_size; duke@435: duke@435: // First thing make an ic check to see if we should even be here duke@435: duke@435: // We are free to use all registers as temps without saving them and duke@435: // restoring them except rbp. rbp is the only callee save register duke@435: // as far as the interpreter and the compiler(s) are concerned. duke@435: duke@435: duke@435: const Register ic_reg = rax; duke@435: const Register receiver = j_rarg0; duke@435: never@3500: Label hit; duke@435: Label exception_pending; duke@435: never@1283: assert_different_registers(ic_reg, receiver, rscratch1); duke@435: __ verify_oop(receiver); never@1283: __ load_klass(rscratch1, receiver); never@1283: __ cmpq(ic_reg, rscratch1); never@3500: __ jcc(Assembler::equal, hit); duke@435: duke@435: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); duke@435: duke@435: // Verified entry point must be aligned duke@435: __ align(8); duke@435: never@3500: __ bind(hit); never@3500: duke@435: int vep_offset = ((intptr_t)__ pc()) - start; duke@435: duke@435: // The instruction at the verified entry point must be 5 bytes or longer duke@435: // because it can be patched on the fly by make_non_entrant. The stack bang duke@435: // instruction fits that requirement. duke@435: duke@435: // Generate stack overflow check duke@435: duke@435: if (UseStackBanging) { duke@435: __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); duke@435: } else { duke@435: // need a 5 byte instruction to allow MT safe patching to non-entrant duke@435: __ fat_nop(); duke@435: } duke@435: duke@435: // Generate a new frame for the wrapper. duke@435: __ enter(); duke@435: // -2 because return address is already present and so is saved rbp never@739: __ subptr(rsp, stack_size - 2*wordSize); duke@435: never@3500: // Frame is now completed as far as size and linkage. never@3500: int frame_complete = ((intptr_t)__ pc()) - start; duke@435: duke@435: #ifdef ASSERT duke@435: { duke@435: Label L; never@739: __ mov(rax, rsp); twisti@1040: __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI) never@739: __ cmpptr(rax, rsp); duke@435: __ jcc(Assembler::equal, L); duke@435: __ stop("improperly aligned stack"); duke@435: __ bind(L); duke@435: } duke@435: #endif /* ASSERT */ duke@435: duke@435: duke@435: // We use r14 as the oop handle for the receiver/klass duke@435: // It is callee save so it survives the call to native duke@435: duke@435: const Register oop_handle_reg = r14; duke@435: never@3500: if (is_critical_native) { never@3500: check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, never@3500: oop_handle_offset, oop_maps, in_regs, in_sig_bt); never@3500: } duke@435: duke@435: // duke@435: // We immediately shuffle the arguments so that any vm call we have to duke@435: // make from here on out (sync slow path, jvmti, etc.) we will have duke@435: // captured the oops from our caller and have a valid oopMap for duke@435: // them. duke@435: duke@435: // ----------------- duke@435: // The Grand Shuffle duke@435: duke@435: // The Java calling convention is either equal (linux) or denser (win64) than the duke@435: // c calling convention. However the because of the jni_env argument the c calling duke@435: // convention always has at least one more (and two for static) arguments than Java. duke@435: // Therefore if we move the args from java -> c backwards then we will never have duke@435: // a register->register conflict and we don't have to build a dependency graph duke@435: // and figure out how to break any cycles. duke@435: // duke@435: duke@435: // Record esp-based slot for receiver on stack for non-static methods duke@435: int receiver_offset = -1; duke@435: duke@435: // This is a trick. We double the stack slots so we can claim duke@435: // the oops in the caller's frame. Since we are sure to have duke@435: // more args than the caller doubling is enough to make duke@435: // sure we can capture all the incoming oop args from the duke@435: // caller. duke@435: // duke@435: OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); duke@435: duke@435: // Mark location of rbp (someday) duke@435: // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp)); duke@435: duke@435: // Use eax, ebx as temporaries during any memory-memory moves we have to do duke@435: // All inbound args are referenced based on rbp and all outbound args via rsp. duke@435: duke@435: duke@435: #ifdef ASSERT duke@435: bool reg_destroyed[RegisterImpl::number_of_registers]; duke@435: bool freg_destroyed[XMMRegisterImpl::number_of_registers]; duke@435: for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { duke@435: reg_destroyed[r] = false; duke@435: } duke@435: for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) { duke@435: freg_destroyed[f] = false; duke@435: } duke@435: duke@435: #endif /* ASSERT */ duke@435: never@3500: // This may iterate in two different directions depending on the never@3500: // kind of native it is. The reason is that for regular JNI natives never@3500: // the incoming and outgoing registers are offset upwards and for never@3500: // critical natives they are offset down. never@3608: GrowableArray arg_order(2 * total_in_args); never@3608: VMRegPair tmp_vmreg; never@3608: tmp_vmreg.set1(rbx->as_VMReg()); never@3608: never@3608: if (!is_critical_native) { never@3608: for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { never@3608: arg_order.push(i); never@3608: arg_order.push(c_arg); never@3608: } never@3608: } else { never@3608: // Compute a valid move order, using tmp_vmreg to break any cycles never@3608: ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); never@3500: } never@3608: never@3608: int temploc = -1; never@3608: for (int ai = 0; ai < arg_order.length(); ai += 2) { never@3608: int i = arg_order.at(ai); never@3608: int c_arg = arg_order.at(ai + 1); never@3608: __ block_comment(err_msg("move %d -> %d", i, c_arg)); never@3608: if (c_arg == -1) { never@3608: assert(is_critical_native, "should only be required for critical natives"); never@3608: // This arg needs to be moved to a temporary never@3608: __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); never@3608: in_regs[i] = tmp_vmreg; never@3608: temploc = i; never@3608: continue; never@3608: } else if (i == -1) { never@3608: assert(is_critical_native, "should only be required for critical natives"); never@3608: // Read from the temporary location never@3608: assert(temploc != -1, "must be valid"); never@3608: i = temploc; never@3608: temploc = -1; never@3608: } duke@435: #ifdef ASSERT duke@435: if (in_regs[i].first()->is_Register()) { duke@435: assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); duke@435: } else if (in_regs[i].first()->is_XMMRegister()) { duke@435: assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!"); duke@435: } duke@435: if (out_regs[c_arg].first()->is_Register()) { duke@435: reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; duke@435: } else if (out_regs[c_arg].first()->is_XMMRegister()) { duke@435: freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; duke@435: } duke@435: #endif /* ASSERT */ duke@435: switch (in_sig_bt[i]) { duke@435: case T_ARRAY: never@3500: if (is_critical_native) { never@3500: unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); never@3500: c_arg++; never@3500: #ifdef ASSERT never@3500: if (out_regs[c_arg].first()->is_Register()) { never@3500: reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; never@3500: } else if (out_regs[c_arg].first()->is_XMMRegister()) { never@3500: freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; never@3500: } never@3500: #endif never@3500: break; never@3500: } duke@435: case T_OBJECT: never@3500: assert(!is_critical_native, "no oop arguments"); duke@435: object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], duke@435: ((i == 0) && (!is_static)), duke@435: &receiver_offset); duke@435: break; duke@435: case T_VOID: duke@435: break; duke@435: duke@435: case T_FLOAT: duke@435: float_move(masm, in_regs[i], out_regs[c_arg]); duke@435: break; duke@435: duke@435: case T_DOUBLE: duke@435: assert( i + 1 < total_in_args && duke@435: in_sig_bt[i + 1] == T_VOID && duke@435: out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); duke@435: double_move(masm, in_regs[i], out_regs[c_arg]); duke@435: break; duke@435: duke@435: case T_LONG : duke@435: long_move(masm, in_regs[i], out_regs[c_arg]); duke@435: break; duke@435: duke@435: case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); duke@435: duke@435: default: duke@435: move32_64(masm, in_regs[i], out_regs[c_arg]); duke@435: } duke@435: } duke@435: duke@435: // point c_arg at the first arg that is already loaded in case we duke@435: // need to spill before we call out never@3608: int c_arg = total_c_args - total_in_args; duke@435: duke@435: // Pre-load a static method's oop into r14. Used both by locking code and duke@435: // the normal JNI call code. never@3500: if (method->is_static() && !is_critical_native) { duke@435: duke@435: // load oop into a register coleenp@4251: __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror())); duke@435: duke@435: // Now handlize the static class mirror it's known not-null. never@739: __ movptr(Address(rsp, klass_offset), oop_handle_reg); duke@435: map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); duke@435: duke@435: // Now get the handle never@739: __ lea(oop_handle_reg, Address(rsp, klass_offset)); duke@435: // store the klass handle as second argument never@739: __ movptr(c_rarg1, oop_handle_reg); duke@435: // and protect the arg if we must spill duke@435: c_arg--; duke@435: } duke@435: duke@435: // Change state to native (we save the return address in the thread, since it might not duke@435: // be pushed on the stack when we do a a stack traversal). It is enough that the pc() duke@435: // points into the right code segment. It does not have to be the correct return pc. duke@435: // We use the same pc/oopMap repeatedly when we call out duke@435: duke@435: intptr_t the_pc = (intptr_t) __ pc(); duke@435: oop_maps->add_gc_map(the_pc - start, map); duke@435: duke@435: __ set_last_Java_frame(rsp, noreg, (address)the_pc); duke@435: duke@435: duke@435: // We have all of the arguments setup at this point. We must not touch any register duke@435: // argument registers at this point (what if we save/restore them there are no oop? duke@435: duke@435: { duke@435: SkipIfEqual skip(masm, &DTraceMethodProbes, false); duke@435: // protect the args we've loaded duke@435: save_args(masm, total_c_args, c_arg, out_regs); coleenp@4037: __ mov_metadata(c_rarg1, method()); duke@435: __ call_VM_leaf( duke@435: CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), duke@435: r15_thread, c_rarg1); duke@435: restore_args(masm, total_c_args, c_arg, out_regs); duke@435: } duke@435: dcubed@1045: // RedefineClasses() tracing support for obsolete method entry dcubed@1045: if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { dcubed@1045: // protect the args we've loaded dcubed@1045: save_args(masm, total_c_args, c_arg, out_regs); coleenp@4037: __ mov_metadata(c_rarg1, method()); dcubed@1045: __ call_VM_leaf( dcubed@1045: CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), dcubed@1045: r15_thread, c_rarg1); dcubed@1045: restore_args(masm, total_c_args, c_arg, out_regs); dcubed@1045: } dcubed@1045: duke@435: // Lock a synchronized method duke@435: duke@435: // Register definitions used by locking and unlocking duke@435: duke@435: const Register swap_reg = rax; // Must use rax for cmpxchg instruction duke@435: const Register obj_reg = rbx; // Will contain the oop duke@435: const Register lock_reg = r13; // Address of compiler lock object (BasicLock) duke@435: const Register old_hdr = r13; // value of old header at unlock time duke@435: duke@435: Label slow_path_lock; duke@435: Label lock_done; duke@435: duke@435: if (method->is_synchronized()) { never@3500: assert(!is_critical_native, "unhandled"); duke@435: duke@435: duke@435: const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); duke@435: duke@435: // Get the handle (the 2nd argument) never@739: __ mov(oop_handle_reg, c_rarg1); duke@435: duke@435: // Get address of the box duke@435: never@739: __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); duke@435: duke@435: // Load the oop from the handle never@739: __ movptr(obj_reg, Address(oop_handle_reg, 0)); duke@435: duke@435: if (UseBiasedLocking) { duke@435: __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock); duke@435: } duke@435: duke@435: // Load immediate 1 into swap_reg %rax duke@435: __ movl(swap_reg, 1); duke@435: duke@435: // Load (object->mark() | 1) into swap_reg %rax never@739: __ orptr(swap_reg, Address(obj_reg, 0)); duke@435: duke@435: // Save (object->mark() | 1) into BasicLock's displaced header never@739: __ movptr(Address(lock_reg, mark_word_offset), swap_reg); duke@435: duke@435: if (os::is_MP()) { duke@435: __ lock(); duke@435: } duke@435: duke@435: // src -> dest iff dest == rax else rax <- dest never@739: __ cmpxchgptr(lock_reg, Address(obj_reg, 0)); duke@435: __ jcc(Assembler::equal, lock_done); duke@435: duke@435: // Hmm should this move to the slow path code area??? duke@435: duke@435: // Test if the oopMark is an obvious stack pointer, i.e., duke@435: // 1) (mark & 3) == 0, and duke@435: // 2) rsp <= mark < mark + os::pagesize() duke@435: // These 3 tests can be done by evaluating the following duke@435: // expression: ((mark - rsp) & (3 - os::vm_page_size())), duke@435: // assuming both stack pointer and pagesize have their duke@435: // least significant 2 bits clear. duke@435: // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg duke@435: never@739: __ subptr(swap_reg, rsp); never@739: __ andptr(swap_reg, 3 - os::vm_page_size()); duke@435: duke@435: // Save the test result, for recursive case, the result is zero never@739: __ movptr(Address(lock_reg, mark_word_offset), swap_reg); duke@435: __ jcc(Assembler::notEqual, slow_path_lock); duke@435: duke@435: // Slow path will re-enter here duke@435: duke@435: __ bind(lock_done); duke@435: } duke@435: duke@435: duke@435: // Finally just about ready to make the JNI call duke@435: duke@435: duke@435: // get JNIEnv* which is first argument to native never@3500: if (!is_critical_native) { never@3500: __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset()))); never@3500: } duke@435: duke@435: // Now set thread in native never@739: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native); duke@435: never@3500: __ call(RuntimeAddress(native_func)); duke@435: kvn@4873: // Verify or restore cpu control state after JNI call kvn@4873: __ restore_cpu_control_state_after_jni(); duke@435: duke@435: // Unpack native results. duke@435: switch (ret_type) { duke@435: case T_BOOLEAN: __ c2bool(rax); break; duke@435: case T_CHAR : __ movzwl(rax, rax); break; duke@435: case T_BYTE : __ sign_extend_byte (rax); break; duke@435: case T_SHORT : __ sign_extend_short(rax); break; duke@435: case T_INT : /* nothing to do */ break; duke@435: case T_DOUBLE : duke@435: case T_FLOAT : duke@435: // Result is in xmm0 we'll save as needed duke@435: break; duke@435: case T_ARRAY: // Really a handle duke@435: case T_OBJECT: // Really a handle duke@435: break; // can't de-handlize until after safepoint check duke@435: case T_VOID: break; duke@435: case T_LONG: break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: duke@435: // Switch thread to "native transition" state before reading the synchronization state. duke@435: // This additional state is necessary because reading and testing the synchronization duke@435: // state is not atomic w.r.t. GC, as this scenario demonstrates: duke@435: // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. duke@435: // VM thread changes sync state to synchronizing and suspends threads for GC. duke@435: // Thread A is resumed to finish this native method, but doesn't block here since it duke@435: // didn't see any synchronization is progress, and escapes. never@739: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans); duke@435: duke@435: if(os::is_MP()) { duke@435: if (UseMembar) { duke@435: // Force this write out before the read below duke@435: __ membar(Assembler::Membar_mask_bits( duke@435: Assembler::LoadLoad | Assembler::LoadStore | duke@435: Assembler::StoreLoad | Assembler::StoreStore)); duke@435: } else { duke@435: // Write serialization page so VM thread can do a pseudo remote membar. duke@435: // We use the current thread pointer to calculate a thread specific duke@435: // offset to write to within the page. This minimizes bus traffic duke@435: // due to cache line collision. duke@435: __ serialize_memory(r15_thread, rcx); duke@435: } duke@435: } duke@435: never@3500: Label after_transition; duke@435: duke@435: // check for safepoint operation in progress and/or pending suspend requests duke@435: { duke@435: Label Continue; duke@435: duke@435: __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()), duke@435: SafepointSynchronize::_not_synchronized); duke@435: duke@435: Label L; duke@435: __ jcc(Assembler::notEqual, L); duke@435: __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0); duke@435: __ jcc(Assembler::equal, Continue); duke@435: __ bind(L); duke@435: duke@435: // Don't use call_VM as it will see a possible pending exception and forward it duke@435: // and never return here preventing us from clearing _last_native_pc down below. duke@435: // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are duke@435: // preserved and correspond to the bcp/locals pointers. So we do a runtime call duke@435: // by hand. duke@435: // duke@435: save_native_result(masm, ret_type, stack_slots); never@739: __ mov(c_rarg0, r15_thread); never@739: __ mov(r12, rsp); // remember sp never@739: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows never@739: __ andptr(rsp, -16); // align stack as required by ABI never@3500: if (!is_critical_native) { never@3500: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); never@3500: } else { never@3500: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); never@3500: } never@739: __ mov(rsp, r12); // restore sp coleenp@548: __ reinit_heapbase(); duke@435: // Restore any method result value duke@435: restore_native_result(masm, ret_type, stack_slots); never@3500: never@3500: if (is_critical_native) { never@3500: // The call above performed the transition to thread_in_Java so never@3500: // skip the transition logic below. never@3500: __ jmpb(after_transition); never@3500: } never@3500: duke@435: __ bind(Continue); duke@435: } duke@435: duke@435: // change thread state duke@435: __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java); never@3500: __ bind(after_transition); duke@435: duke@435: Label reguard; duke@435: Label reguard_done; duke@435: __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled); duke@435: __ jcc(Assembler::equal, reguard); duke@435: __ bind(reguard_done); duke@435: duke@435: // native result if any is live duke@435: duke@435: // Unlock duke@435: Label unlock_done; duke@435: Label slow_path_unlock; duke@435: if (method->is_synchronized()) { duke@435: duke@435: // Get locked oop from the handle we passed to jni never@739: __ movptr(obj_reg, Address(oop_handle_reg, 0)); duke@435: duke@435: Label done; duke@435: duke@435: if (UseBiasedLocking) { duke@435: __ biased_locking_exit(obj_reg, old_hdr, done); duke@435: } duke@435: duke@435: // Simple recursive lock? duke@435: never@739: __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, done); duke@435: duke@435: // Must save rax if if it is live now because cmpxchg must use it duke@435: if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { duke@435: save_native_result(masm, ret_type, stack_slots); duke@435: } duke@435: duke@435: duke@435: // get address of the stack lock never@739: __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); duke@435: // get old displaced header never@739: __ movptr(old_hdr, Address(rax, 0)); duke@435: duke@435: // Atomic swap old header if oop still contains the stack lock duke@435: if (os::is_MP()) { duke@435: __ lock(); duke@435: } never@739: __ cmpxchgptr(old_hdr, Address(obj_reg, 0)); duke@435: __ jcc(Assembler::notEqual, slow_path_unlock); duke@435: duke@435: // slow path re-enters here duke@435: __ bind(unlock_done); duke@435: if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { duke@435: restore_native_result(masm, ret_type, stack_slots); duke@435: } duke@435: duke@435: __ bind(done); duke@435: duke@435: } duke@435: { duke@435: SkipIfEqual skip(masm, &DTraceMethodProbes, false); duke@435: save_native_result(masm, ret_type, stack_slots); coleenp@4037: __ mov_metadata(c_rarg1, method()); duke@435: __ call_VM_leaf( duke@435: CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), duke@435: r15_thread, c_rarg1); duke@435: restore_native_result(masm, ret_type, stack_slots); duke@435: } duke@435: duke@435: __ reset_last_Java_frame(false, true); duke@435: duke@435: // Unpack oop result duke@435: if (ret_type == T_OBJECT || ret_type == T_ARRAY) { duke@435: Label L; never@739: __ testptr(rax, rax); duke@435: __ jcc(Assembler::zero, L); never@739: __ movptr(rax, Address(rax, 0)); duke@435: __ bind(L); duke@435: __ verify_oop(rax); duke@435: } duke@435: never@3500: if (!is_critical_native) { never@3500: // reset handle block never@3500: __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset())); never@3500: __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD); never@3500: } duke@435: duke@435: // pop our frame duke@435: duke@435: __ leave(); duke@435: never@3500: if (!is_critical_native) { never@3500: // Any exception pending? never@3500: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); never@3500: __ jcc(Assembler::notEqual, exception_pending); never@3500: } duke@435: duke@435: // Return duke@435: duke@435: __ ret(0); duke@435: duke@435: // Unexpected paths are out of line and go here duke@435: never@3500: if (!is_critical_native) { never@3500: // forward the exception never@3500: __ bind(exception_pending); never@3500: never@3500: // and forward the exception never@3500: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); never@3500: } duke@435: duke@435: // Slow path locking & unlocking duke@435: if (method->is_synchronized()) { duke@435: duke@435: // BEGIN Slow path lock duke@435: __ bind(slow_path_lock); duke@435: duke@435: // has last_Java_frame setup. No exceptions so do vanilla call not call_VM duke@435: // args are (oop obj, BasicLock* lock, JavaThread* thread) duke@435: duke@435: // protect the args we've loaded duke@435: save_args(masm, total_c_args, c_arg, out_regs); duke@435: never@739: __ mov(c_rarg0, obj_reg); never@739: __ mov(c_rarg1, lock_reg); never@739: __ mov(c_rarg2, r15_thread); duke@435: duke@435: // Not a leaf but we have last_Java_frame setup as we want duke@435: __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); duke@435: restore_args(masm, total_c_args, c_arg, out_regs); duke@435: duke@435: #ifdef ASSERT duke@435: { Label L; never@739: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, L); duke@435: __ stop("no pending exception allowed on exit from monitorenter"); duke@435: __ bind(L); duke@435: } duke@435: #endif duke@435: __ jmp(lock_done); duke@435: duke@435: // END Slow path lock duke@435: duke@435: // BEGIN Slow path unlock duke@435: __ bind(slow_path_unlock); duke@435: duke@435: // If we haven't already saved the native result we must save it now as xmm registers duke@435: // are still exposed. duke@435: duke@435: if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { duke@435: save_native_result(masm, ret_type, stack_slots); duke@435: } duke@435: never@739: __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); never@739: never@739: __ mov(c_rarg0, obj_reg); never@739: __ mov(r12, rsp); // remember sp never@739: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows never@739: __ andptr(rsp, -16); // align stack as required by ABI duke@435: duke@435: // Save pending exception around call to VM (which contains an EXCEPTION_MARK) duke@435: // NOTE that obj_reg == rbx currently never@739: __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset()))); never@739: __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); duke@435: duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C))); never@739: __ mov(rsp, r12); // restore sp coleenp@548: __ reinit_heapbase(); duke@435: #ifdef ASSERT duke@435: { duke@435: Label L; never@739: __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD); duke@435: __ jcc(Assembler::equal, L); duke@435: __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); duke@435: __ bind(L); duke@435: } duke@435: #endif /* ASSERT */ duke@435: never@739: __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx); duke@435: duke@435: if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { duke@435: restore_native_result(masm, ret_type, stack_slots); duke@435: } duke@435: __ jmp(unlock_done); duke@435: duke@435: // END Slow path unlock duke@435: duke@435: } // synchronized duke@435: duke@435: // SLOW PATH Reguard the stack if needed duke@435: duke@435: __ bind(reguard); duke@435: save_native_result(masm, ret_type, stack_slots); never@739: __ mov(r12, rsp); // remember sp never@739: __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows never@739: __ andptr(rsp, -16); // align stack as required by ABI duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages))); never@739: __ mov(rsp, r12); // restore sp coleenp@548: __ reinit_heapbase(); duke@435: restore_native_result(masm, ret_type, stack_slots); duke@435: // and continue duke@435: __ jmp(reguard_done); duke@435: duke@435: duke@435: duke@435: __ flush(); duke@435: duke@435: nmethod *nm = nmethod::new_native_nmethod(method, twisti@2687: compile_id, duke@435: masm->code(), duke@435: vep_offset, duke@435: frame_complete, duke@435: stack_slots / VMRegImpl::slots_per_word, duke@435: (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), duke@435: in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), duke@435: oop_maps); never@3500: never@3500: if (is_critical_native) { never@3500: nm->set_lazy_critical_native(true); never@3500: } never@3500: duke@435: return nm; duke@435: duke@435: } duke@435: kamg@551: #ifdef HAVE_DTRACE_H kamg@551: // --------------------------------------------------------------------------- kamg@551: // Generate a dtrace nmethod for a given signature. The method takes arguments kamg@551: // in the Java compiled code convention, marshals them to the native kamg@551: // abi and then leaves nops at the position you would expect to call a native kamg@551: // function. When the probe is enabled the nops are replaced with a trap kamg@551: // instruction that dtrace inserts and the trace will cause a notification kamg@551: // to dtrace. kamg@551: // kamg@551: // The probes are only able to take primitive types and java/lang/String as kamg@551: // arguments. No other java types are allowed. Strings are converted to utf8 kamg@551: // strings so that from dtrace point of view java strings are converted to C kamg@551: // strings. There is an arbitrary fixed limit on the total space that a method kamg@551: // can use for converting the strings. (256 chars per string in the signature). kamg@551: // So any java string larger then this is truncated. kamg@551: kamg@551: static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; kamg@551: static bool offsets_initialized = false; kamg@551: kamg@551: kamg@551: nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm, kamg@551: methodHandle method) { kamg@551: kamg@551: kamg@551: // generate_dtrace_nmethod is guarded by a mutex so we are sure to kamg@551: // be single threaded in this method. kamg@551: assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); kamg@551: kamg@551: if (!offsets_initialized) { kamg@551: fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize; kamg@551: fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize; kamg@551: fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize; kamg@551: fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize; kamg@551: fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize; kamg@551: fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize; kamg@551: kamg@551: fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize; kamg@551: fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize; kamg@551: fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize; kamg@551: fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize; kamg@551: fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize; kamg@551: fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize; kamg@551: fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize; kamg@551: fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize; kamg@551: kamg@551: offsets_initialized = true; kamg@551: } kamg@551: // Fill in the signature array, for the calling-convention call. kamg@551: int total_args_passed = method->size_of_parameters(); kamg@551: kamg@551: BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); kamg@551: VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); kamg@551: kamg@551: // The signature we are going to use for the trap that dtrace will see kamg@551: // java/lang/String is converted. We drop "this" and any other object kamg@551: // is converted to NULL. (A one-slot java/lang/Long object reference kamg@551: // is converted to a two-slot long, which is why we double the allocation). kamg@551: BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); kamg@551: VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); kamg@551: kamg@551: int i=0; kamg@551: int total_strings = 0; kamg@551: int first_arg_to_pass = 0; kamg@551: int total_c_args = 0; kamg@551: kamg@551: // Skip the receiver as dtrace doesn't want to see it kamg@551: if( !method->is_static() ) { kamg@551: in_sig_bt[i++] = T_OBJECT; kamg@551: first_arg_to_pass = 1; kamg@551: } kamg@551: kamg@551: // We need to convert the java args to where a native (non-jni) function kamg@551: // would expect them. To figure out where they go we convert the java kamg@551: // signature to a C signature. kamg@551: kamg@551: SignatureStream ss(method->signature()); kamg@551: for ( ; !ss.at_return_type(); ss.next()) { kamg@551: BasicType bt = ss.type(); kamg@551: in_sig_bt[i++] = bt; // Collect remaining bits of signature kamg@551: out_sig_bt[total_c_args++] = bt; kamg@551: if( bt == T_OBJECT) { coleenp@2497: Symbol* s = ss.as_symbol_or_null(); // symbol is created kamg@551: if (s == vmSymbols::java_lang_String()) { kamg@551: total_strings++; kamg@551: out_sig_bt[total_c_args-1] = T_ADDRESS; kamg@551: } else if (s == vmSymbols::java_lang_Boolean() || kamg@551: s == vmSymbols::java_lang_Character() || kamg@551: s == vmSymbols::java_lang_Byte() || kamg@551: s == vmSymbols::java_lang_Short() || kamg@551: s == vmSymbols::java_lang_Integer() || kamg@551: s == vmSymbols::java_lang_Float()) { kamg@551: out_sig_bt[total_c_args-1] = T_INT; kamg@551: } else if (s == vmSymbols::java_lang_Long() || kamg@551: s == vmSymbols::java_lang_Double()) { kamg@551: out_sig_bt[total_c_args-1] = T_LONG; kamg@551: out_sig_bt[total_c_args++] = T_VOID; kamg@551: } kamg@551: } else if ( bt == T_LONG || bt == T_DOUBLE ) { kamg@551: in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots kamg@551: // We convert double to long kamg@551: out_sig_bt[total_c_args-1] = T_LONG; kamg@551: out_sig_bt[total_c_args++] = T_VOID; kamg@551: } else if ( bt == T_FLOAT) { kamg@551: // We convert float to int kamg@551: out_sig_bt[total_c_args-1] = T_INT; kamg@551: } kamg@551: } kamg@551: kamg@551: assert(i==total_args_passed, "validly parsed signature"); kamg@551: kamg@551: // Now get the compiled-Java layout as input arguments kamg@551: int comp_args_on_stack; kamg@551: comp_args_on_stack = SharedRuntime::java_calling_convention( kamg@551: in_sig_bt, in_regs, total_args_passed, false); kamg@551: kamg@551: // Now figure out where the args must be stored and how much stack space kamg@551: // they require (neglecting out_preserve_stack_slots but space for storing kamg@551: // the 1st six register arguments). It's weird see int_stk_helper. kamg@551: kamg@551: int out_arg_slots; kamg@551: out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); kamg@551: kamg@551: // Calculate the total number of stack slots we will need. kamg@551: kamg@551: // First count the abi requirement plus all of the outgoing args kamg@551: int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; kamg@551: kamg@551: // Now space for the string(s) we must convert kamg@551: int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1); kamg@551: for (i = 0; i < total_strings ; i++) { kamg@551: string_locs[i] = stack_slots; kamg@551: stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size; kamg@551: } kamg@551: kamg@551: // Plus the temps we might need to juggle register args kamg@551: // regs take two slots each kamg@551: stack_slots += (Argument::n_int_register_parameters_c + kamg@551: Argument::n_float_register_parameters_c) * 2; kamg@551: kamg@551: kamg@551: // + 4 for return address (which we own) and saved rbp, kamg@551: kamg@551: stack_slots += 4; kamg@551: kamg@551: // Ok The space we have allocated will look like: kamg@551: // kamg@551: // kamg@551: // FP-> | | kamg@551: // |---------------------| kamg@551: // | string[n] | kamg@551: // |---------------------| <- string_locs[n] kamg@551: // | string[n-1] | kamg@551: // |---------------------| <- string_locs[n-1] kamg@551: // | ... | kamg@551: // | ... | kamg@551: // |---------------------| <- string_locs[1] kamg@551: // | string[0] | kamg@551: // |---------------------| <- string_locs[0] kamg@551: // | outbound memory | kamg@551: // | based arguments | kamg@551: // | | kamg@551: // |---------------------| kamg@551: // | | kamg@551: // SP-> | out_preserved_slots | kamg@551: // kamg@551: // kamg@551: kamg@551: // Now compute actual number of stack words we need rounding to make kamg@551: // stack properly aligned. kamg@551: stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); kamg@551: kamg@551: int stack_size = stack_slots * VMRegImpl::stack_slot_size; kamg@551: kamg@551: intptr_t start = (intptr_t)__ pc(); kamg@551: kamg@551: // First thing make an ic check to see if we should even be here kamg@551: kamg@551: // We are free to use all registers as temps without saving them and kamg@551: // restoring them except rbp. rbp, is the only callee save register kamg@551: // as far as the interpreter and the compiler(s) are concerned. kamg@551: kamg@551: const Register ic_reg = rax; kamg@551: const Register receiver = rcx; kamg@551: Label hit; kamg@551: Label exception_pending; kamg@551: kamg@551: kamg@551: __ verify_oop(receiver); kamg@551: __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes())); kamg@551: __ jcc(Assembler::equal, hit); kamg@551: kamg@551: __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); kamg@551: kamg@551: // verified entry must be aligned for code patching. kamg@551: // and the first 5 bytes must be in the same cache line kamg@551: // if we align at 8 then we will be sure 5 bytes are in the same line kamg@551: __ align(8); kamg@551: kamg@551: __ bind(hit); kamg@551: kamg@551: int vep_offset = ((intptr_t)__ pc()) - start; kamg@551: kamg@551: kamg@551: // The instruction at the verified entry point must be 5 bytes or longer kamg@551: // because it can be patched on the fly by make_non_entrant. The stack bang kamg@551: // instruction fits that requirement. kamg@551: kamg@551: // Generate stack overflow check kamg@551: kamg@551: if (UseStackBanging) { kamg@551: if (stack_size <= StackShadowPages*os::vm_page_size()) { kamg@551: __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); kamg@551: } else { kamg@551: __ movl(rax, stack_size); kamg@551: __ bang_stack_size(rax, rbx); kamg@551: } kamg@551: } else { kamg@551: // need a 5 byte instruction to allow MT safe patching to non-entrant kamg@551: __ fat_nop(); kamg@551: } kamg@551: kamg@551: assert(((uintptr_t)__ pc() - start - vep_offset) >= 5, kamg@551: "valid size for make_non_entrant"); kamg@551: kamg@551: // Generate a new frame for the wrapper. kamg@551: __ enter(); kamg@551: kamg@551: // -4 because return address is already present and so is saved rbp, kamg@551: if (stack_size - 2*wordSize != 0) { kamg@551: __ subq(rsp, stack_size - 2*wordSize); kamg@551: } kamg@551: kamg@551: // Frame is now completed as far a size and linkage. kamg@551: kamg@551: int frame_complete = ((intptr_t)__ pc()) - start; kamg@551: kamg@551: int c_arg, j_arg; kamg@551: kamg@551: // State of input register args kamg@551: kamg@551: bool live[ConcreteRegisterImpl::number_of_registers]; kamg@551: kamg@551: live[j_rarg0->as_VMReg()->value()] = false; kamg@551: live[j_rarg1->as_VMReg()->value()] = false; kamg@551: live[j_rarg2->as_VMReg()->value()] = false; kamg@551: live[j_rarg3->as_VMReg()->value()] = false; kamg@551: live[j_rarg4->as_VMReg()->value()] = false; kamg@551: live[j_rarg5->as_VMReg()->value()] = false; kamg@551: kamg@551: live[j_farg0->as_VMReg()->value()] = false; kamg@551: live[j_farg1->as_VMReg()->value()] = false; kamg@551: live[j_farg2->as_VMReg()->value()] = false; kamg@551: live[j_farg3->as_VMReg()->value()] = false; kamg@551: live[j_farg4->as_VMReg()->value()] = false; kamg@551: live[j_farg5->as_VMReg()->value()] = false; kamg@551: live[j_farg6->as_VMReg()->value()] = false; kamg@551: live[j_farg7->as_VMReg()->value()] = false; kamg@551: kamg@551: kamg@551: bool rax_is_zero = false; kamg@551: kamg@551: // All args (except strings) destined for the stack are moved first kamg@551: for (j_arg = first_arg_to_pass, c_arg = 0 ; kamg@551: j_arg < total_args_passed ; j_arg++, c_arg++ ) { kamg@551: VMRegPair src = in_regs[j_arg]; kamg@551: VMRegPair dst = out_regs[c_arg]; kamg@551: kamg@551: // Get the real reg value or a dummy (rsp) kamg@551: kamg@551: int src_reg = src.first()->is_reg() ? kamg@551: src.first()->value() : kamg@551: rsp->as_VMReg()->value(); kamg@551: kamg@551: bool useless = in_sig_bt[j_arg] == T_ARRAY || kamg@551: (in_sig_bt[j_arg] == T_OBJECT && kamg@551: out_sig_bt[c_arg] != T_INT && kamg@551: out_sig_bt[c_arg] != T_ADDRESS && kamg@551: out_sig_bt[c_arg] != T_LONG); kamg@551: kamg@551: live[src_reg] = !useless; kamg@551: kamg@551: if (dst.first()->is_stack()) { kamg@551: kamg@551: // Even though a string arg in a register is still live after this loop kamg@551: // after the string conversion loop (next) it will be dead so we take kamg@551: // advantage of that now for simpler code to manage live. kamg@551: kamg@551: live[src_reg] = false; kamg@551: switch (in_sig_bt[j_arg]) { kamg@551: kamg@551: case T_ARRAY: kamg@551: case T_OBJECT: kamg@551: { kamg@551: Address stack_dst(rsp, reg2offset_out(dst.first())); kamg@551: kamg@551: if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { kamg@551: // need to unbox a one-word value kamg@551: Register in_reg = rax; kamg@551: if ( src.first()->is_reg() ) { kamg@551: in_reg = src.first()->as_Register(); kamg@551: } else { kamg@551: __ movq(rax, Address(rbp, reg2offset_in(src.first()))); kamg@551: rax_is_zero = false; kamg@551: } kamg@551: Label skipUnbox; kamg@551: __ movptr(Address(rsp, reg2offset_out(dst.first())), kamg@551: (int32_t)NULL_WORD); kamg@551: __ testq(in_reg, in_reg); kamg@551: __ jcc(Assembler::zero, skipUnbox); kamg@551: kvn@600: BasicType bt = out_sig_bt[c_arg]; kvn@600: int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); kamg@551: Address src1(in_reg, box_offset); kvn@600: if ( bt == T_LONG ) { kamg@551: __ movq(in_reg, src1); kamg@551: __ movq(stack_dst, in_reg); kamg@551: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); kamg@551: ++c_arg; // skip over T_VOID to keep the loop indices in sync kamg@551: } else { kamg@551: __ movl(in_reg, src1); kamg@551: __ movl(stack_dst, in_reg); kamg@551: } kamg@551: kamg@551: __ bind(skipUnbox); kamg@551: } else if (out_sig_bt[c_arg] != T_ADDRESS) { kamg@551: // Convert the arg to NULL kamg@551: if (!rax_is_zero) { kamg@551: __ xorq(rax, rax); kamg@551: rax_is_zero = true; kamg@551: } kamg@551: __ movq(stack_dst, rax); kamg@551: } kamg@551: } kamg@551: break; kamg@551: kamg@551: case T_VOID: kamg@551: break; kamg@551: kamg@551: case T_FLOAT: kamg@551: // This does the right thing since we know it is destined for the kamg@551: // stack kamg@551: float_move(masm, src, dst); kamg@551: break; kamg@551: kamg@551: case T_DOUBLE: kamg@551: // This does the right thing since we know it is destined for the kamg@551: // stack kamg@551: double_move(masm, src, dst); kamg@551: break; kamg@551: kamg@551: case T_LONG : kamg@551: long_move(masm, src, dst); kamg@551: break; kamg@551: kamg@551: case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); kamg@551: kamg@551: default: kamg@551: move32_64(masm, src, dst); kamg@551: } kamg@551: } kamg@551: kamg@551: } kamg@551: kamg@551: // If we have any strings we must store any register based arg to the stack kamg@551: // This includes any still live xmm registers too. kamg@551: kamg@551: int sid = 0; kamg@551: kamg@551: if (total_strings > 0 ) { kamg@551: for (j_arg = first_arg_to_pass, c_arg = 0 ; kamg@551: j_arg < total_args_passed ; j_arg++, c_arg++ ) { kamg@551: VMRegPair src = in_regs[j_arg]; kamg@551: VMRegPair dst = out_regs[c_arg]; kamg@551: kamg@551: if (src.first()->is_reg()) { kamg@551: Address src_tmp(rbp, fp_offset[src.first()->value()]); kamg@551: kamg@551: // string oops were left untouched by the previous loop even if the kamg@551: // eventual (converted) arg is destined for the stack so park them kamg@551: // away now (except for first) kamg@551: kamg@551: if (out_sig_bt[c_arg] == T_ADDRESS) { kamg@551: Address utf8_addr = Address( kamg@551: rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); kamg@551: if (sid != 1) { kamg@551: // The first string arg won't be killed until after the utf8 kamg@551: // conversion kamg@551: __ movq(utf8_addr, src.first()->as_Register()); kamg@551: } kamg@551: } else if (dst.first()->is_reg()) { kamg@551: if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) { kamg@551: kamg@551: // Convert the xmm register to an int and store it in the reserved kamg@551: // location for the eventual c register arg kamg@551: XMMRegister f = src.first()->as_XMMRegister(); kamg@551: if (in_sig_bt[j_arg] == T_FLOAT) { kamg@551: __ movflt(src_tmp, f); kamg@551: } else { kamg@551: __ movdbl(src_tmp, f); kamg@551: } kamg@551: } else { kamg@551: // If the arg is an oop type we don't support don't bother to store kamg@551: // it remember string was handled above. kamg@551: bool useless = in_sig_bt[j_arg] == T_ARRAY || kamg@551: (in_sig_bt[j_arg] == T_OBJECT && kamg@551: out_sig_bt[c_arg] != T_INT && kamg@551: out_sig_bt[c_arg] != T_LONG); kamg@551: kamg@551: if (!useless) { kamg@551: __ movq(src_tmp, src.first()->as_Register()); kamg@551: } kamg@551: } kamg@551: } kamg@551: } kamg@551: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { kamg@551: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); kamg@551: ++c_arg; // skip over T_VOID to keep the loop indices in sync kamg@551: } kamg@551: } kamg@551: kamg@551: // Now that the volatile registers are safe, convert all the strings kamg@551: sid = 0; kamg@551: kamg@551: for (j_arg = first_arg_to_pass, c_arg = 0 ; kamg@551: j_arg < total_args_passed ; j_arg++, c_arg++ ) { kamg@551: if (out_sig_bt[c_arg] == T_ADDRESS) { kamg@551: // It's a string kamg@551: Address utf8_addr = Address( kamg@551: rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); kamg@551: // The first string we find might still be in the original java arg kamg@551: // register kamg@551: kamg@551: VMReg src = in_regs[j_arg].first(); kamg@551: kamg@551: // We will need to eventually save the final argument to the trap kamg@551: // in the von-volatile location dedicated to src. This is the offset kamg@551: // from fp we will use. kamg@551: int src_off = src->is_reg() ? kamg@551: fp_offset[src->value()] : reg2offset_in(src); kamg@551: kamg@551: // This is where the argument will eventually reside kamg@551: VMRegPair dst = out_regs[c_arg]; kamg@551: kamg@551: if (src->is_reg()) { kamg@551: if (sid == 1) { kamg@551: __ movq(c_rarg0, src->as_Register()); kamg@551: } else { kamg@551: __ movq(c_rarg0, utf8_addr); kamg@551: } kamg@551: } else { kamg@551: // arg is still in the original location kamg@551: __ movq(c_rarg0, Address(rbp, reg2offset_in(src))); kamg@551: } kamg@551: Label done, convert; kamg@551: kamg@551: // see if the oop is NULL kamg@551: __ testq(c_rarg0, c_rarg0); kamg@551: __ jcc(Assembler::notEqual, convert); kamg@551: kamg@551: if (dst.first()->is_reg()) { kamg@551: // Save the ptr to utf string in the origina src loc or the tmp kamg@551: // dedicated to it kamg@551: __ movq(Address(rbp, src_off), c_rarg0); kamg@551: } else { kamg@551: __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0); kamg@551: } kamg@551: __ jmp(done); kamg@551: kamg@551: __ bind(convert); kamg@551: kamg@551: __ lea(c_rarg1, utf8_addr); kamg@551: if (dst.first()->is_reg()) { kamg@551: __ movq(Address(rbp, src_off), c_rarg1); kamg@551: } else { kamg@551: __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1); kamg@551: } kamg@551: // And do the conversion kamg@551: __ call(RuntimeAddress( kamg@551: CAST_FROM_FN_PTR(address, SharedRuntime::get_utf))); kamg@551: kamg@551: __ bind(done); kamg@551: } kamg@551: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { kamg@551: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); kamg@551: ++c_arg; // skip over T_VOID to keep the loop indices in sync kamg@551: } kamg@551: } kamg@551: // The get_utf call killed all the c_arg registers kamg@551: live[c_rarg0->as_VMReg()->value()] = false; kamg@551: live[c_rarg1->as_VMReg()->value()] = false; kamg@551: live[c_rarg2->as_VMReg()->value()] = false; kamg@551: live[c_rarg3->as_VMReg()->value()] = false; kamg@551: live[c_rarg4->as_VMReg()->value()] = false; kamg@551: live[c_rarg5->as_VMReg()->value()] = false; kamg@551: kamg@551: live[c_farg0->as_VMReg()->value()] = false; kamg@551: live[c_farg1->as_VMReg()->value()] = false; kamg@551: live[c_farg2->as_VMReg()->value()] = false; kamg@551: live[c_farg3->as_VMReg()->value()] = false; kamg@551: live[c_farg4->as_VMReg()->value()] = false; kamg@551: live[c_farg5->as_VMReg()->value()] = false; kamg@551: live[c_farg6->as_VMReg()->value()] = false; kamg@551: live[c_farg7->as_VMReg()->value()] = false; kamg@551: } kamg@551: kamg@551: // Now we can finally move the register args to their desired locations kamg@551: kamg@551: rax_is_zero = false; kamg@551: kamg@551: for (j_arg = first_arg_to_pass, c_arg = 0 ; kamg@551: j_arg < total_args_passed ; j_arg++, c_arg++ ) { kamg@551: kamg@551: VMRegPair src = in_regs[j_arg]; kamg@551: VMRegPair dst = out_regs[c_arg]; kamg@551: kamg@551: // Only need to look for args destined for the interger registers (since we kamg@551: // convert float/double args to look like int/long outbound) kamg@551: if (dst.first()->is_reg()) { kamg@551: Register r = dst.first()->as_Register(); kamg@551: kamg@551: // Check if the java arg is unsupported and thereofre useless kamg@551: bool useless = in_sig_bt[j_arg] == T_ARRAY || kamg@551: (in_sig_bt[j_arg] == T_OBJECT && kamg@551: out_sig_bt[c_arg] != T_INT && kamg@551: out_sig_bt[c_arg] != T_ADDRESS && kamg@551: out_sig_bt[c_arg] != T_LONG); kamg@551: kamg@551: kamg@551: // If we're going to kill an existing arg save it first kamg@551: if (live[dst.first()->value()]) { kamg@551: // you can't kill yourself kamg@551: if (src.first() != dst.first()) { kamg@551: __ movq(Address(rbp, fp_offset[dst.first()->value()]), r); kamg@551: } kamg@551: } kamg@551: if (src.first()->is_reg()) { kamg@551: if (live[src.first()->value()] ) { kamg@551: if (in_sig_bt[j_arg] == T_FLOAT) { kamg@551: __ movdl(r, src.first()->as_XMMRegister()); kamg@551: } else if (in_sig_bt[j_arg] == T_DOUBLE) { kamg@551: __ movdq(r, src.first()->as_XMMRegister()); kamg@551: } else if (r != src.first()->as_Register()) { kamg@551: if (!useless) { kamg@551: __ movq(r, src.first()->as_Register()); kamg@551: } kamg@551: } kamg@551: } else { kamg@551: // If the arg is an oop type we don't support don't bother to store kamg@551: // it kamg@551: if (!useless) { kamg@551: if (in_sig_bt[j_arg] == T_DOUBLE || kamg@551: in_sig_bt[j_arg] == T_LONG || kamg@551: in_sig_bt[j_arg] == T_OBJECT ) { kamg@551: __ movq(r, Address(rbp, fp_offset[src.first()->value()])); kamg@551: } else { kamg@551: __ movl(r, Address(rbp, fp_offset[src.first()->value()])); kamg@551: } kamg@551: } kamg@551: } kamg@551: live[src.first()->value()] = false; kamg@551: } else if (!useless) { kamg@551: // full sized move even for int should be ok kamg@551: __ movq(r, Address(rbp, reg2offset_in(src.first()))); kamg@551: } kamg@551: kamg@551: // At this point r has the original java arg in the final location kamg@551: // (assuming it wasn't useless). If the java arg was an oop kamg@551: // we have a bit more to do kamg@551: kamg@551: if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) { kamg@551: if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { kamg@551: // need to unbox a one-word value kamg@551: Label skip; kamg@551: __ testq(r, r); kamg@551: __ jcc(Assembler::equal, skip); kvn@600: BasicType bt = out_sig_bt[c_arg]; kvn@600: int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); kamg@551: Address src1(r, box_offset); kvn@600: if ( bt == T_LONG ) { kamg@551: __ movq(r, src1); kamg@551: } else { kamg@551: __ movl(r, src1); kamg@551: } kamg@551: __ bind(skip); kamg@551: kamg@551: } else if (out_sig_bt[c_arg] != T_ADDRESS) { kamg@551: // Convert the arg to NULL kamg@551: __ xorq(r, r); kamg@551: } kamg@551: } kamg@551: kamg@551: // dst can longer be holding an input value kamg@551: live[dst.first()->value()] = false; kamg@551: } kamg@551: if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { kamg@551: assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); kamg@551: ++c_arg; // skip over T_VOID to keep the loop indices in sync kamg@551: } kamg@551: } kamg@551: kamg@551: kamg@551: // Ok now we are done. Need to place the nop that dtrace wants in order to kamg@551: // patch in the trap kamg@551: int patch_offset = ((intptr_t)__ pc()) - start; kamg@551: kamg@551: __ nop(); kamg@551: kamg@551: kamg@551: // Return kamg@551: kamg@551: __ leave(); kamg@551: __ ret(0); kamg@551: kamg@551: __ flush(); kamg@551: kamg@551: nmethod *nm = nmethod::new_dtrace_nmethod( kamg@551: method, masm->code(), vep_offset, patch_offset, frame_complete, kamg@551: stack_slots / VMRegImpl::slots_per_word); kamg@551: return nm; kamg@551: kamg@551: } kamg@551: kamg@551: #endif // HAVE_DTRACE_H kamg@551: duke@435: // this function returns the adjust size (in number of words) to a c2i adapter duke@435: // activation for use during deoptimization duke@435: int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) { twisti@1861: return (callee_locals - callee_parameters) * Interpreter::stackElementWords; duke@435: } duke@435: duke@435: duke@435: uint SharedRuntime::out_preserve_stack_slots() { duke@435: return 0; duke@435: } duke@435: duke@435: //------------------------------generate_deopt_blob---------------------------- duke@435: void SharedRuntime::generate_deopt_blob() { duke@435: // Allocate space for the code duke@435: ResourceMark rm; duke@435: // Setup code generation tools duke@435: CodeBuffer buffer("deopt_blob", 2048, 1024); duke@435: MacroAssembler* masm = new MacroAssembler(&buffer); duke@435: int frame_size_in_words; duke@435: OopMap* map = NULL; duke@435: OopMapSet *oop_maps = new OopMapSet(); duke@435: duke@435: // ------------- duke@435: // This code enters when returning to a de-optimized nmethod. A return duke@435: // address has been pushed on the the stack, and return values are in duke@435: // registers. duke@435: // If we are doing a normal deopt then we were called from the patched duke@435: // nmethod from the point we returned to the nmethod. So the return duke@435: // address on the stack is wrong by NativeCall::instruction_size duke@435: // We will adjust the value so it looks like we have the original return duke@435: // address on the stack (like when we eagerly deoptimized). duke@435: // In the case of an exception pending when deoptimizing, we enter duke@435: // with a return address on the stack that points after the call we patched duke@435: // into the exception handler. We have the following register state from, duke@435: // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). duke@435: // rax: exception oop duke@435: // rbx: exception handler duke@435: // rdx: throwing pc duke@435: // So in this case we simply jam rdx into the useless return address and duke@435: // the stack looks just like we want. duke@435: // duke@435: // At this point we need to de-opt. We save the argument return duke@435: // registers. We call the first C routine, fetch_unroll_info(). This duke@435: // routine captures the return values and returns a structure which duke@435: // describes the current frame size and the sizes of all replacement frames. duke@435: // The current frame is compiled code and may contain many inlined duke@435: // functions, each with their own JVM state. We pop the current frame, then duke@435: // push all the new frames. Then we call the C routine unpack_frames() to duke@435: // populate these frames. Finally unpack_frames() returns us the new target duke@435: // address. Notice that callee-save registers are BLOWN here; they have duke@435: // already been captured in the vframeArray at the time the return PC was duke@435: // patched. duke@435: address start = __ pc(); duke@435: Label cont; duke@435: duke@435: // Prolog for non exception case! duke@435: duke@435: // Save everything in sight. duke@435: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); duke@435: duke@435: // Normal deoptimization. Save exec mode for unpack_frames. coleenp@548: __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved duke@435: __ jmp(cont); never@739: never@739: int reexecute_offset = __ pc() - start; never@739: never@739: // Reexecute case never@739: // return address is the pc describes what bci to do re-execute at never@739: never@739: // No need to update map as each call to save_live_registers will produce identical oopmap never@739: (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); never@739: never@739: __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved never@739: __ jmp(cont); never@739: duke@435: int exception_offset = __ pc() - start; duke@435: duke@435: // Prolog for exception case duke@435: never@739: // all registers are dead at this entry point, except for rax, and never@739: // rdx which contain the exception oop and exception pc never@739: // respectively. Set them in TLS and fall thru to the never@739: // unpack_with_exception_in_tls entry point. never@739: never@739: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); never@739: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax); never@739: never@739: int exception_in_tls_offset = __ pc() - start; never@739: never@739: // new implementation because exception oop is now passed in JavaThread never@739: never@739: // Prolog for exception case never@739: // All registers must be preserved because they might be used by LinearScan never@739: // Exceptiop oop and throwing PC are passed in JavaThread never@739: // tos: stack at point of call to method that threw the exception (i.e. only never@739: // args are on the stack, no return address) never@739: never@739: // make room on stack for the return address never@739: // It will be patched later with the throwing pc. The correct value is not never@739: // available now because loading it from memory would destroy registers. never@739: __ push(0); duke@435: duke@435: // Save everything in sight. duke@435: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); duke@435: never@739: // Now it is safe to overwrite any register never@739: duke@435: // Deopt during an exception. Save exec mode for unpack_frames. coleenp@548: __ movl(r14, Deoptimization::Unpack_exception); // callee-saved duke@435: never@739: // load throwing pc from JavaThread and patch it as the return address never@739: // of the current frame. Then clear the field in JavaThread never@739: never@739: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); never@739: __ movptr(Address(rbp, wordSize), rdx); never@739: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); never@739: never@739: #ifdef ASSERT never@739: // verify that there is really an exception oop in JavaThread never@739: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); never@739: __ verify_oop(rax); never@739: never@739: // verify that there is no pending exception never@739: Label no_pending_exception; never@739: __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); never@739: __ testptr(rax, rax); never@739: __ jcc(Assembler::zero, no_pending_exception); never@739: __ stop("must not have pending exception here"); never@739: __ bind(no_pending_exception); never@739: #endif never@739: duke@435: __ bind(cont); duke@435: duke@435: // Call C code. Need thread and this frame, but NOT official VM entry duke@435: // crud. We cannot block on this call, no GC can happen. duke@435: // duke@435: // UnrollBlock* fetch_unroll_info(JavaThread* thread) duke@435: duke@435: // fetch_unroll_info needs to call last_java_frame(). duke@435: duke@435: __ set_last_Java_frame(noreg, noreg, NULL); duke@435: #ifdef ASSERT duke@435: { Label L; never@739: __ cmpptr(Address(r15_thread, duke@435: JavaThread::last_Java_fp_offset()), never@739: (int32_t)0); duke@435: __ jcc(Assembler::equal, L); duke@435: __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); duke@435: __ bind(L); duke@435: } duke@435: #endif // ASSERT never@739: __ mov(c_rarg0, r15_thread); duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); duke@435: duke@435: // Need to have an oopmap that tells fetch_unroll_info where to duke@435: // find any register it might need. duke@435: oop_maps->add_gc_map(__ pc() - start, map); duke@435: duke@435: __ reset_last_Java_frame(false, false); duke@435: duke@435: // Load UnrollBlock* into rdi never@739: __ mov(rdi, rax); never@739: never@739: Label noException; never@1117: __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending? never@739: __ jcc(Assembler::notEqual, noException); never@739: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); never@739: // QQQ this is useless it was NULL above never@739: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); never@739: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); never@739: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); never@739: never@739: __ verify_oop(rax); never@739: never@739: // Overwrite the result registers with the exception results. never@739: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); never@739: // I think this is useless never@739: __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx); never@739: never@739: __ bind(noException); duke@435: duke@435: // Only register save data is on the stack. duke@435: // Now restore the result registers. Everything else is either dead duke@435: // or captured in the vframeArray. duke@435: RegisterSaver::restore_result_registers(masm); duke@435: duke@435: // All of the register save area has been popped of the stack. Only the duke@435: // return address remains. duke@435: duke@435: // Pop all the frames we must move/replace. duke@435: // duke@435: // Frame picture (youngest to oldest) duke@435: // 1: self-frame (no frame link) duke@435: // 2: deopting frame (no frame link) duke@435: // 3: caller of deopting frame (could be compiled/interpreted). duke@435: // duke@435: // Note: by leaving the return address of self-frame on the stack duke@435: // and using the size of frame 2 to adjust the stack duke@435: // when we are done the return to frame 3 will still be on the stack. duke@435: duke@435: // Pop deoptimized frame duke@435: __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); never@739: __ addptr(rsp, rcx); duke@435: duke@435: // rsp should be pointing at the return address to the caller (3) duke@435: duke@435: // Stack bang to make sure there's enough room for these interpreter frames. duke@435: if (UseStackBanging) { duke@435: __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); duke@435: __ bang_stack_size(rbx, rcx); duke@435: } duke@435: duke@435: // Load address of array of frame pcs into rcx never@739: __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); duke@435: duke@435: // Trash the old pc never@739: __ addptr(rsp, wordSize); duke@435: duke@435: // Load address of array of frame sizes into rsi never@739: __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); duke@435: duke@435: // Load counter into rdx duke@435: __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); duke@435: duke@435: // Pick up the initial fp we should save bdelsart@3130: __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); duke@435: duke@435: // Now adjust the caller's stack to make up for the extra locals duke@435: // but record the original sp so that we can save it in the skeletal interpreter duke@435: // frame and the stack walking of interpreter_sender will get the unextended sp duke@435: // value and not the "real" sp value. duke@435: duke@435: const Register sender_sp = r8; duke@435: never@739: __ mov(sender_sp, rsp); duke@435: __ movl(rbx, Address(rdi, duke@435: Deoptimization::UnrollBlock:: duke@435: caller_adjustment_offset_in_bytes())); never@739: __ subptr(rsp, rbx); duke@435: duke@435: // Push interpreter frames in a loop duke@435: Label loop; duke@435: __ bind(loop); never@739: __ movptr(rbx, Address(rsi, 0)); // Load frame size never@739: #ifdef CC_INTERP never@739: __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and never@739: #ifdef ASSERT never@739: __ push(0xDEADDEAD); // Make a recognizable pattern never@739: __ push(0xDEADDEAD); never@739: #else /* ASSERT */ never@739: __ subptr(rsp, 2*wordSize); // skip the "static long no_param" never@739: #endif /* ASSERT */ never@739: #else never@739: __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand never@739: #endif // CC_INTERP never@739: __ pushptr(Address(rcx, 0)); // Save return address duke@435: __ enter(); // Save old & set new ebp never@739: __ subptr(rsp, rbx); // Prolog never@739: #ifdef CC_INTERP never@739: __ movptr(Address(rbp, never@739: -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), never@739: sender_sp); // Make it walkable never@739: #else /* CC_INTERP */ duke@435: // This value is corrected by layout_activation_impl never@739: __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); never@739: __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable never@739: #endif /* CC_INTERP */ never@739: __ mov(sender_sp, rsp); // Pass sender_sp to next frame never@739: __ addptr(rsi, wordSize); // Bump array pointer (sizes) never@739: __ addptr(rcx, wordSize); // Bump array pointer (pcs) duke@435: __ decrementl(rdx); // Decrement counter duke@435: __ jcc(Assembler::notZero, loop); never@739: __ pushptr(Address(rcx, 0)); // Save final return address duke@435: duke@435: // Re-push self-frame duke@435: __ enter(); // Save old & set new ebp duke@435: duke@435: // Allocate a full sized register save area. duke@435: // Return address and rbp are in place, so we allocate two less words. never@739: __ subptr(rsp, (frame_size_in_words - 2) * wordSize); duke@435: duke@435: // Restore frame locals after moving the frame duke@435: __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0); never@739: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); duke@435: duke@435: // Call C code. Need thread but NOT official VM entry duke@435: // crud. We cannot block on this call, no GC can happen. Call should duke@435: // restore return values to their stack-slots with the new SP. duke@435: // duke@435: // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) duke@435: duke@435: // Use rbp because the frames look interpreted now never@3253: // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. never@3253: // Don't need the precise return PC here, just precise enough to point into this code blob. never@3253: address the_pc = __ pc(); never@3253: __ set_last_Java_frame(noreg, rbp, the_pc); never@3253: never@3253: __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI never@739: __ mov(c_rarg0, r15_thread); coleenp@548: __ movl(c_rarg1, r14); // second arg: exec_mode duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); never@3253: // Revert SP alignment after call since we're going to do some SP relative addressing below never@3253: __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset())); duke@435: duke@435: // Set an oopmap for the call site never@3253: // Use the same PC we used for the last java frame never@3253: oop_maps->add_gc_map(the_pc - start, duke@435: new OopMap( frame_size_in_words, 0 )); duke@435: never@3253: // Clear fp AND pc never@3253: __ reset_last_Java_frame(true, true); duke@435: duke@435: // Collect return values duke@435: __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes())); never@739: __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes())); never@739: // I think this is useless (throwing pc?) never@739: __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes())); duke@435: duke@435: // Pop self-frame. duke@435: __ leave(); // Epilog duke@435: duke@435: // Jump to interpreter duke@435: __ ret(0); duke@435: duke@435: // Make sure all code is generated duke@435: masm->flush(); duke@435: never@739: _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); never@739: _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); duke@435: } duke@435: duke@435: #ifdef COMPILER2 duke@435: //------------------------------generate_uncommon_trap_blob-------------------- duke@435: void SharedRuntime::generate_uncommon_trap_blob() { duke@435: // Allocate space for the code duke@435: ResourceMark rm; duke@435: // Setup code generation tools duke@435: CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); duke@435: MacroAssembler* masm = new MacroAssembler(&buffer); duke@435: duke@435: assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); duke@435: duke@435: address start = __ pc(); duke@435: duke@435: // Push self-frame. We get here with a return address on the duke@435: // stack, so rsp is 8-byte aligned until we allocate our frame. never@739: __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog! duke@435: duke@435: // No callee saved registers. rbp is assumed implicitly saved never@739: __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); duke@435: duke@435: // compiler left unloaded_class_index in j_rarg0 move to where the duke@435: // runtime expects it. duke@435: __ movl(c_rarg1, j_rarg0); duke@435: duke@435: __ set_last_Java_frame(noreg, noreg, NULL); duke@435: duke@435: // Call C code. Need thread but NOT official VM entry duke@435: // crud. We cannot block on this call, no GC can happen. Call should duke@435: // capture callee-saved registers as well as return values. duke@435: // Thread is in rdi already. duke@435: // duke@435: // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); duke@435: never@739: __ mov(c_rarg0, r15_thread); duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); duke@435: duke@435: // Set an oopmap for the call site duke@435: OopMapSet* oop_maps = new OopMapSet(); duke@435: OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); duke@435: duke@435: // location of rbp is known implicitly by the frame sender code duke@435: duke@435: oop_maps->add_gc_map(__ pc() - start, map); duke@435: duke@435: __ reset_last_Java_frame(false, false); duke@435: duke@435: // Load UnrollBlock* into rdi never@739: __ mov(rdi, rax); duke@435: duke@435: // Pop all the frames we must move/replace. duke@435: // duke@435: // Frame picture (youngest to oldest) duke@435: // 1: self-frame (no frame link) duke@435: // 2: deopting frame (no frame link) duke@435: // 3: caller of deopting frame (could be compiled/interpreted). duke@435: duke@435: // Pop self-frame. We have no frame, and must rely only on rax and rsp. never@739: __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog! duke@435: duke@435: // Pop deoptimized frame (int) duke@435: __ movl(rcx, Address(rdi, duke@435: Deoptimization::UnrollBlock:: duke@435: size_of_deoptimized_frame_offset_in_bytes())); never@739: __ addptr(rsp, rcx); duke@435: duke@435: // rsp should be pointing at the return address to the caller (3) duke@435: duke@435: // Stack bang to make sure there's enough room for these interpreter frames. duke@435: if (UseStackBanging) { duke@435: __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); duke@435: __ bang_stack_size(rbx, rcx); duke@435: } duke@435: duke@435: // Load address of array of frame pcs into rcx (address*) never@739: __ movptr(rcx, never@739: Address(rdi, never@739: Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); duke@435: duke@435: // Trash the return pc never@739: __ addptr(rsp, wordSize); duke@435: duke@435: // Load address of array of frame sizes into rsi (intptr_t*) never@739: __ movptr(rsi, Address(rdi, never@739: Deoptimization::UnrollBlock:: never@739: frame_sizes_offset_in_bytes())); duke@435: duke@435: // Counter duke@435: __ movl(rdx, Address(rdi, duke@435: Deoptimization::UnrollBlock:: duke@435: number_of_frames_offset_in_bytes())); // (int) duke@435: duke@435: // Pick up the initial fp we should save never@739: __ movptr(rbp, never@739: Address(rdi, bdelsart@3130: Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); duke@435: duke@435: // Now adjust the caller's stack to make up for the extra locals but duke@435: // record the original sp so that we can save it in the skeletal duke@435: // interpreter frame and the stack walking of interpreter_sender duke@435: // will get the unextended sp value and not the "real" sp value. duke@435: duke@435: const Register sender_sp = r8; duke@435: never@739: __ mov(sender_sp, rsp); duke@435: __ movl(rbx, Address(rdi, duke@435: Deoptimization::UnrollBlock:: duke@435: caller_adjustment_offset_in_bytes())); // (int) never@739: __ subptr(rsp, rbx); duke@435: duke@435: // Push interpreter frames in a loop duke@435: Label loop; duke@435: __ bind(loop); never@739: __ movptr(rbx, Address(rsi, 0)); // Load frame size never@739: __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand never@739: __ pushptr(Address(rcx, 0)); // Save return address never@739: __ enter(); // Save old & set new rbp never@739: __ subptr(rsp, rbx); // Prolog coleenp@955: #ifdef CC_INTERP coleenp@955: __ movptr(Address(rbp, coleenp@955: -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), coleenp@955: sender_sp); // Make it walkable coleenp@955: #else // CC_INTERP never@739: __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), never@739: sender_sp); // Make it walkable duke@435: // This value is corrected by layout_activation_impl never@739: __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); coleenp@955: #endif // CC_INTERP never@739: __ mov(sender_sp, rsp); // Pass sender_sp to next frame never@739: __ addptr(rsi, wordSize); // Bump array pointer (sizes) never@739: __ addptr(rcx, wordSize); // Bump array pointer (pcs) never@739: __ decrementl(rdx); // Decrement counter duke@435: __ jcc(Assembler::notZero, loop); never@739: __ pushptr(Address(rcx, 0)); // Save final return address duke@435: duke@435: // Re-push self-frame duke@435: __ enter(); // Save old & set new rbp never@739: __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt); duke@435: // Prolog duke@435: duke@435: // Use rbp because the frames look interpreted now never@3253: // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. never@3253: // Don't need the precise return PC here, just precise enough to point into this code blob. never@3253: address the_pc = __ pc(); never@3253: __ set_last_Java_frame(noreg, rbp, the_pc); duke@435: duke@435: // Call C code. Need thread but NOT official VM entry duke@435: // crud. We cannot block on this call, no GC can happen. Call should duke@435: // restore return values to their stack-slots with the new SP. duke@435: // Thread is in rdi already. duke@435: // duke@435: // BasicType unpack_frames(JavaThread* thread, int exec_mode); duke@435: never@3253: __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI never@739: __ mov(c_rarg0, r15_thread); duke@435: __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap); duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); duke@435: duke@435: // Set an oopmap for the call site never@3253: // Use the same PC we used for the last java frame never@3253: oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); never@3253: never@3253: // Clear fp AND pc never@3253: __ reset_last_Java_frame(true, true); duke@435: duke@435: // Pop self-frame. duke@435: __ leave(); // Epilog duke@435: duke@435: // Jump to interpreter duke@435: __ ret(0); duke@435: duke@435: // Make sure all code is generated duke@435: masm->flush(); duke@435: duke@435: _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, duke@435: SimpleRuntimeFrame::framesize >> 1); duke@435: } duke@435: #endif // COMPILER2 duke@435: duke@435: duke@435: //------------------------------generate_handler_blob------ duke@435: // duke@435: // Generate a special Compile2Runtime blob that saves all registers, duke@435: // and setup oopmap. duke@435: // kvn@4103: SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { duke@435: assert(StubRoutines::forward_exception_entry() != NULL, duke@435: "must be generated before"); duke@435: duke@435: ResourceMark rm; duke@435: OopMapSet *oop_maps = new OopMapSet(); duke@435: OopMap* map; duke@435: duke@435: // Allocate space for the code. Setup code generation tools. duke@435: CodeBuffer buffer("handler_blob", 2048, 1024); duke@435: MacroAssembler* masm = new MacroAssembler(&buffer); duke@435: duke@435: address start = __ pc(); duke@435: address call_pc = NULL; duke@435: int frame_size_in_words; kvn@4103: bool cause_return = (poll_type == POLL_AT_RETURN); kvn@4103: bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP); duke@435: duke@435: // Make room for return address (or push it again) duke@435: if (!cause_return) { never@739: __ push(rbx); duke@435: } duke@435: duke@435: // Save registers, fpu state, and flags kvn@4103: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors); duke@435: duke@435: // The following is basically a call_VM. However, we need the precise duke@435: // address of the call in order to generate an oopmap. Hence, we do all the duke@435: // work outselves. duke@435: duke@435: __ set_last_Java_frame(noreg, noreg, NULL); duke@435: duke@435: // The return address must always be correct so that frame constructor never duke@435: // sees an invalid pc. duke@435: duke@435: if (!cause_return) { duke@435: // overwrite the dummy value we pushed on entry never@739: __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset())); never@739: __ movptr(Address(rbp, wordSize), c_rarg0); duke@435: } duke@435: duke@435: // Do the call never@739: __ mov(c_rarg0, r15_thread); duke@435: __ call(RuntimeAddress(call_ptr)); duke@435: duke@435: // Set an oopmap for the call site. This oopmap will map all duke@435: // oop-registers and debug-info registers as callee-saved. This duke@435: // will allow deoptimization at this safepoint to find all possible duke@435: // debug-info recordings, as well as let GC find all oops. duke@435: duke@435: oop_maps->add_gc_map( __ pc() - start, map); duke@435: duke@435: Label noException; duke@435: duke@435: __ reset_last_Java_frame(false, false); duke@435: never@739: __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, noException); duke@435: duke@435: // Exception pending duke@435: kvn@4103: RegisterSaver::restore_live_registers(masm, save_vectors); duke@435: duke@435: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); duke@435: duke@435: // No exception case duke@435: __ bind(noException); duke@435: duke@435: // Normal exit, restore registers and exit. kvn@4103: RegisterSaver::restore_live_registers(masm, save_vectors); duke@435: duke@435: __ ret(0); duke@435: duke@435: // Make sure all code is generated duke@435: masm->flush(); duke@435: duke@435: // Fill-out other meta info duke@435: return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); duke@435: } duke@435: duke@435: // duke@435: // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss duke@435: // duke@435: // Generate a stub that calls into vm to find out the proper destination duke@435: // of a java call. All the argument registers are live at this point duke@435: // but since this is generic code we don't know what they are and the caller duke@435: // must do any gc of the args. duke@435: // never@2950: RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { duke@435: assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); duke@435: duke@435: // allocate space for the code duke@435: ResourceMark rm; duke@435: duke@435: CodeBuffer buffer(name, 1000, 512); duke@435: MacroAssembler* masm = new MacroAssembler(&buffer); duke@435: duke@435: int frame_size_in_words; duke@435: duke@435: OopMapSet *oop_maps = new OopMapSet(); duke@435: OopMap* map = NULL; duke@435: duke@435: int start = __ offset(); duke@435: duke@435: map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); duke@435: duke@435: int frame_complete = __ offset(); duke@435: duke@435: __ set_last_Java_frame(noreg, noreg, NULL); duke@435: never@739: __ mov(c_rarg0, r15_thread); duke@435: duke@435: __ call(RuntimeAddress(destination)); duke@435: duke@435: duke@435: // Set an oopmap for the call site. duke@435: // We need this not only for callee-saved registers, but also for volatile duke@435: // registers that the compiler might be keeping live across a safepoint. duke@435: duke@435: oop_maps->add_gc_map( __ offset() - start, map); duke@435: duke@435: // rax contains the address we are going to jump to assuming no exception got installed duke@435: duke@435: // clear last_Java_sp duke@435: __ reset_last_Java_frame(false, false); duke@435: // check for pending exceptions duke@435: Label pending; never@739: __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::notEqual, pending); duke@435: coleenp@4037: // get the returned Method* coleenp@4037: __ get_vm_result_2(rbx, r15_thread); never@739: __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx); never@739: never@739: __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); duke@435: duke@435: RegisterSaver::restore_live_registers(masm); duke@435: duke@435: // We are back the the original state on entry and ready to go. duke@435: duke@435: __ jmp(rax); duke@435: duke@435: // Pending exception after the safepoint duke@435: duke@435: __ bind(pending); duke@435: duke@435: RegisterSaver::restore_live_registers(masm); duke@435: duke@435: // exception pending => remove activation and forward to exception handler duke@435: duke@435: __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD); duke@435: never@739: __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); duke@435: __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); duke@435: duke@435: // ------------- duke@435: // make sure all code is generated duke@435: masm->flush(); duke@435: duke@435: // return the blob duke@435: // frame_size_words or bytes?? duke@435: return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); duke@435: } duke@435: duke@435: duke@435: #ifdef COMPILER2 duke@435: // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame duke@435: // duke@435: //------------------------------generate_exception_blob--------------------------- duke@435: // creates exception blob at the end duke@435: // Using exception blob, this code is jumped from a compiled method. duke@435: // (see emit_exception_handler in x86_64.ad file) duke@435: // duke@435: // Given an exception pc at a call we call into the runtime for the duke@435: // handler in this method. This handler might merely restore state duke@435: // (i.e. callee save registers) unwind the frame and jump to the duke@435: // exception handler for the nmethod if there is no Java level handler duke@435: // for the nmethod. duke@435: // duke@435: // This code is entered with a jmp. duke@435: // duke@435: // Arguments: duke@435: // rax: exception oop duke@435: // rdx: exception pc duke@435: // duke@435: // Results: duke@435: // rax: exception oop duke@435: // rdx: exception pc in caller or ??? duke@435: // destination: exception handler of caller duke@435: // duke@435: // Note: the exception pc MUST be at a call (precise debug information) duke@435: // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved. duke@435: // duke@435: duke@435: void OptoRuntime::generate_exception_blob() { duke@435: assert(!OptoRuntime::is_callee_saved_register(RDX_num), ""); duke@435: assert(!OptoRuntime::is_callee_saved_register(RAX_num), ""); duke@435: assert(!OptoRuntime::is_callee_saved_register(RCX_num), ""); duke@435: duke@435: assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); duke@435: duke@435: // Allocate space for the code duke@435: ResourceMark rm; duke@435: // Setup code generation tools duke@435: CodeBuffer buffer("exception_blob", 2048, 1024); duke@435: MacroAssembler* masm = new MacroAssembler(&buffer); duke@435: duke@435: duke@435: address start = __ pc(); duke@435: duke@435: // Exception pc is 'return address' for stack walker never@739: __ push(rdx); never@739: __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog duke@435: duke@435: // Save callee-saved registers. See x86_64.ad. duke@435: duke@435: // rbp is an implicitly saved callee saved register (i.e. the calling duke@435: // convention will save restore it in prolog/epilog) Other than that duke@435: // there are no callee save registers now that adapter frames are gone. duke@435: never@739: __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); duke@435: duke@435: // Store exception in Thread object. We cannot pass any arguments to the duke@435: // handle_exception call, since we do not want to make any assumption duke@435: // about the size of the frame where the exception happened in. duke@435: // c_rarg0 is either rdi (Linux) or rcx (Windows). never@739: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax); never@739: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); duke@435: duke@435: // This call does all the hard work. It checks if an exception handler duke@435: // exists in the method. duke@435: // If so, it returns the handler address. duke@435: // If not, it prepares for stack-unwinding, restoring the callee-save duke@435: // registers of the frame being removed. duke@435: // duke@435: // address OptoRuntime::handle_exception_C(JavaThread* thread) duke@435: roland@3607: // At a method handle call, the stack may not be properly aligned roland@3607: // when returning with an exception. roland@3607: address the_pc = __ pc(); roland@3607: __ set_last_Java_frame(noreg, noreg, the_pc); never@739: __ mov(c_rarg0, r15_thread); roland@3607: __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack duke@435: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); duke@435: duke@435: // Set an oopmap for the call site. This oopmap will only be used if we duke@435: // are unwinding the stack. Hence, all locations will be dead. duke@435: // Callee-saved registers will be the same as the frame above (i.e., duke@435: // handle_exception_stub), since they were restored when we got the duke@435: // exception. duke@435: duke@435: OopMapSet* oop_maps = new OopMapSet(); duke@435: roland@3607: oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); roland@3607: roland@3607: __ reset_last_Java_frame(false, true); duke@435: duke@435: // Restore callee-saved registers duke@435: duke@435: // rbp is an implicitly saved callee saved register (i.e. the calling duke@435: // convention will save restore it in prolog/epilog) Other than that duke@435: // there are no callee save registers no that adapter frames are gone. duke@435: never@739: __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt)); never@739: never@739: __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog never@739: __ pop(rdx); // No need for exception pc anymore duke@435: duke@435: // rax: exception handler duke@435: twisti@1803: // Restore SP from BP if the exception PC is a MethodHandle call site. twisti@1803: __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0); twisti@1922: __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save); twisti@1570: duke@435: // We have a handler in rax (could be deopt blob). never@739: __ mov(r8, rax); duke@435: duke@435: // Get the exception oop never@739: __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); duke@435: // Get the exception pc in case we are deoptimized never@739: __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); duke@435: #ifdef ASSERT duke@435: __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD); duke@435: __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD); duke@435: #endif duke@435: // Clear the exception oop so GC no longer processes it as a root. duke@435: __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD); duke@435: duke@435: // rax: exception oop duke@435: // r8: exception handler duke@435: // rdx: exception pc duke@435: // Jump to handler duke@435: duke@435: __ jmp(r8); duke@435: duke@435: // Make sure all code is generated duke@435: masm->flush(); duke@435: duke@435: // Set exception blob duke@435: _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); duke@435: } duke@435: #endif // COMPILER2