duke@435: /* xdono@631: * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: // We have interfaces for the following instructions: duke@435: // - NativeInstruction duke@435: // - - NativeCall duke@435: // - - NativeMovConstReg duke@435: // - - NativeMovConstRegPatching duke@435: // - - NativeMovRegMem duke@435: // - - NativeMovRegMemPatching duke@435: // - - NativeJump duke@435: // - - NativeIllegalOpCode duke@435: // - - NativeGeneralJump duke@435: // - - NativeReturn duke@435: // - - NativeReturnX (return with argument) duke@435: // - - NativePushConst duke@435: // - - NativeTstRegMem duke@435: duke@435: // The base class for different kinds of native instruction abstractions. duke@435: // Provides the primitive operations to manipulate code relative to this. duke@435: duke@435: class NativeInstruction VALUE_OBJ_CLASS_SPEC { duke@435: friend class Relocation; duke@435: duke@435: public: duke@435: enum Intel_specific_constants { duke@435: nop_instruction_code = 0x90, duke@435: nop_instruction_size = 1 duke@435: }; duke@435: duke@435: bool is_nop() { return ubyte_at(0) == nop_instruction_code; } kamg@551: bool is_dtrace_trap(); duke@435: inline bool is_call(); duke@435: inline bool is_illegal(); duke@435: inline bool is_return(); duke@435: inline bool is_jump(); duke@435: inline bool is_cond_jump(); duke@435: inline bool is_safepoint_poll(); duke@435: inline bool is_mov_literal64(); duke@435: duke@435: protected: duke@435: address addr_at(int offset) const { return address(this) + offset; } duke@435: duke@435: s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } duke@435: u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } duke@435: duke@435: jint int_at(int offset) const { return *(jint*) addr_at(offset); } duke@435: duke@435: intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } duke@435: duke@435: oop oop_at (int offset) const { return *(oop*) addr_at(offset); } duke@435: duke@435: duke@435: void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } duke@435: void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } duke@435: void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } duke@435: void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } duke@435: duke@435: // This doesn't really do anything on Intel, but it is the place where duke@435: // cache invalidation belongs, generically: duke@435: void wrote(int offset); duke@435: duke@435: public: duke@435: duke@435: // unit test stuff duke@435: static void test() {} // override for testing duke@435: duke@435: inline friend NativeInstruction* nativeInstruction_at(address address); duke@435: }; duke@435: duke@435: inline NativeInstruction* nativeInstruction_at(address address) { duke@435: NativeInstruction* inst = (NativeInstruction*)address; duke@435: #ifdef ASSERT duke@435: //inst->verify(); duke@435: #endif duke@435: return inst; duke@435: } duke@435: duke@435: inline NativeCall* nativeCall_at(address address); duke@435: // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off duke@435: // instructions (used to manipulate inline caches, primitive & dll calls, etc.). duke@435: duke@435: class NativeCall: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0xE8, duke@435: instruction_size = 5, duke@435: instruction_offset = 0, duke@435: displacement_offset = 1, duke@435: return_address_offset = 5 duke@435: }; duke@435: duke@435: enum { cache_line_size = BytesPerWord }; // conservative estimate! duke@435: duke@435: address instruction_address() const { return addr_at(instruction_offset); } duke@435: address next_instruction_address() const { return addr_at(return_address_offset); } duke@435: int displacement() const { return (jint) int_at(displacement_offset); } duke@435: address displacement_address() const { return addr_at(displacement_offset); } duke@435: address return_address() const { return addr_at(return_address_offset); } duke@435: address destination() const; duke@435: void set_destination(address dest) { duke@435: #ifdef AMD64 duke@435: assert((labs((intptr_t) dest - (intptr_t) return_address()) & duke@435: 0xFFFFFFFF00000000) == 0, duke@435: "must be 32bit offset"); duke@435: #endif // AMD64 duke@435: set_int_at(displacement_offset, dest - return_address()); duke@435: } duke@435: void set_destination_mt_safe(address dest); duke@435: duke@435: void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } duke@435: void verify(); duke@435: void print(); duke@435: duke@435: // Creation duke@435: inline friend NativeCall* nativeCall_at(address address); duke@435: inline friend NativeCall* nativeCall_before(address return_address); duke@435: duke@435: static bool is_call_at(address instr) { duke@435: return ((*instr) & 0xFF) == NativeCall::instruction_code; duke@435: } duke@435: duke@435: static bool is_call_before(address return_address) { duke@435: return is_call_at(return_address - NativeCall::return_address_offset); duke@435: } duke@435: duke@435: static bool is_call_to(address instr, address target) { duke@435: return nativeInstruction_at(instr)->is_call() && duke@435: nativeCall_at(instr)->destination() == target; duke@435: } duke@435: duke@435: // MT-safe patching of a call instruction. duke@435: static void insert(address code_pos, address entry); duke@435: duke@435: static void replace_mt_safe(address instr_addr, address code_buffer); duke@435: }; duke@435: duke@435: inline NativeCall* nativeCall_at(address address) { duke@435: NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); duke@435: #ifdef ASSERT duke@435: call->verify(); duke@435: #endif duke@435: return call; duke@435: } duke@435: duke@435: inline NativeCall* nativeCall_before(address return_address) { duke@435: NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); duke@435: #ifdef ASSERT duke@435: call->verify(); duke@435: #endif duke@435: return call; duke@435: } duke@435: duke@435: // An interface for accessing/manipulating native mov reg, imm32 instructions. duke@435: // (used to manipulate inlined 32bit data dll calls, etc.) duke@435: class NativeMovConstReg: public NativeInstruction { duke@435: #ifdef AMD64 duke@435: static const bool has_rex = true; duke@435: static const int rex_size = 1; duke@435: #else duke@435: static const bool has_rex = false; duke@435: static const int rex_size = 0; duke@435: #endif // AMD64 duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0xB8, duke@435: instruction_size = 1 + rex_size + wordSize, duke@435: instruction_offset = 0, duke@435: data_offset = 1 + rex_size, duke@435: next_instruction_offset = instruction_size, duke@435: register_mask = 0x07 duke@435: }; duke@435: duke@435: address instruction_address() const { return addr_at(instruction_offset); } duke@435: address next_instruction_address() const { return addr_at(next_instruction_offset); } duke@435: intptr_t data() const { return ptr_at(data_offset); } duke@435: void set_data(intptr_t x) { set_ptr_at(data_offset, x); } duke@435: duke@435: void verify(); duke@435: void print(); duke@435: duke@435: // unit test stuff duke@435: static void test() {} duke@435: duke@435: // Creation duke@435: inline friend NativeMovConstReg* nativeMovConstReg_at(address address); duke@435: inline friend NativeMovConstReg* nativeMovConstReg_before(address address); duke@435: }; duke@435: duke@435: inline NativeMovConstReg* nativeMovConstReg_at(address address) { duke@435: NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: duke@435: inline NativeMovConstReg* nativeMovConstReg_before(address address) { duke@435: NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: duke@435: class NativeMovConstRegPatching: public NativeMovConstReg { duke@435: private: duke@435: friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { duke@435: NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: }; duke@435: duke@435: // An interface for accessing/manipulating native moves of the form: never@739: // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) never@739: // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg never@739: // mov[s/z]x[w/b/q] [reg + offset], reg duke@435: // fld_s [reg+offset] duke@435: // fld_d [reg+offset] duke@435: // fstp_s [reg + offset] duke@435: // fstp_d [reg + offset] never@739: // mov_literal64 scratch, ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) duke@435: // duke@435: // Warning: These routines must be able to handle any instruction sequences duke@435: // that are generated as a result of the load/store byte,word,long duke@435: // macros. For example: The load_unsigned_byte instruction generates duke@435: // an xor reg,reg inst prior to generating the movb instruction. This duke@435: // class must skip the xor instruction. duke@435: duke@435: class NativeMovRegMem: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { never@739: instruction_prefix_wide_lo = Assembler::REX, never@739: instruction_prefix_wide_hi = Assembler::REX_WRXB, duke@435: instruction_code_xor = 0x33, duke@435: instruction_extended_prefix = 0x0F, never@739: instruction_code_mem2reg_movslq = 0x63, duke@435: instruction_code_mem2reg_movzxb = 0xB6, duke@435: instruction_code_mem2reg_movsxb = 0xBE, duke@435: instruction_code_mem2reg_movzxw = 0xB7, duke@435: instruction_code_mem2reg_movsxw = 0xBF, duke@435: instruction_operandsize_prefix = 0x66, never@739: instruction_code_reg2mem = 0x89, never@739: instruction_code_mem2reg = 0x8b, duke@435: instruction_code_reg2memb = 0x88, duke@435: instruction_code_mem2regb = 0x8a, duke@435: instruction_code_float_s = 0xd9, duke@435: instruction_code_float_d = 0xdd, duke@435: instruction_code_long_volatile = 0xdf, duke@435: instruction_code_xmm_ss_prefix = 0xf3, duke@435: instruction_code_xmm_sd_prefix = 0xf2, duke@435: instruction_code_xmm_code = 0x0f, duke@435: instruction_code_xmm_load = 0x10, duke@435: instruction_code_xmm_store = 0x11, duke@435: instruction_code_xmm_lpd = 0x12, duke@435: duke@435: instruction_size = 4, duke@435: instruction_offset = 0, duke@435: data_offset = 2, duke@435: next_instruction_offset = 4 duke@435: }; duke@435: never@739: // helper never@739: int instruction_start() const; duke@435: never@739: address instruction_address() const; duke@435: never@739: address next_instruction_address() const; never@739: never@739: int offset() const; never@739: never@739: void set_offset(int x); duke@435: duke@435: void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } duke@435: duke@435: void verify(); duke@435: void print (); duke@435: duke@435: // unit test stuff duke@435: static void test() {} duke@435: duke@435: private: duke@435: inline friend NativeMovRegMem* nativeMovRegMem_at (address address); duke@435: }; duke@435: duke@435: inline NativeMovRegMem* nativeMovRegMem_at (address address) { duke@435: NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: duke@435: class NativeMovRegMemPatching: public NativeMovRegMem { duke@435: private: duke@435: friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { duke@435: NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: }; duke@435: duke@435: duke@435: duke@435: // An interface for accessing/manipulating native leal instruction of form: duke@435: // leal reg, [reg + offset] duke@435: duke@435: class NativeLoadAddress: public NativeMovRegMem { never@739: #ifdef AMD64 never@739: static const bool has_rex = true; never@739: static const int rex_size = 1; never@739: #else never@739: static const bool has_rex = false; never@739: static const int rex_size = 0; never@739: #endif // AMD64 duke@435: public: duke@435: enum Intel_specific_constants { never@739: instruction_prefix_wide = Assembler::REX_W, never@739: instruction_prefix_wide_extended = Assembler::REX_WB, never@739: lea_instruction_code = 0x8D, never@739: mov64_instruction_code = 0xB8 duke@435: }; duke@435: duke@435: void verify(); duke@435: void print (); duke@435: duke@435: // unit test stuff duke@435: static void test() {} duke@435: duke@435: private: duke@435: friend NativeLoadAddress* nativeLoadAddress_at (address address) { duke@435: NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); duke@435: #ifdef ASSERT duke@435: test->verify(); duke@435: #endif duke@435: return test; duke@435: } duke@435: }; duke@435: duke@435: // jump rel32off duke@435: duke@435: class NativeJump: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0xe9, duke@435: instruction_size = 5, duke@435: instruction_offset = 0, duke@435: data_offset = 1, duke@435: next_instruction_offset = 5 duke@435: }; duke@435: duke@435: address instruction_address() const { return addr_at(instruction_offset); } duke@435: address next_instruction_address() const { return addr_at(next_instruction_offset); } duke@435: address jump_destination() const { duke@435: address dest = (int_at(data_offset)+next_instruction_address()); never@739: // 32bit used to encode unresolved jmp as jmp -1 never@739: // 64bit can't produce this so it used jump to self. never@739: // Now 32bit and 64bit use jump to self as the unresolved address never@739: // which the inline cache code (and relocs) know about never@739: duke@435: // return -1 if jump to self duke@435: dest = (dest == (address) this) ? (address) -1 : dest; duke@435: return dest; duke@435: } duke@435: duke@435: void set_jump_destination(address dest) { duke@435: intptr_t val = dest - next_instruction_address(); never@749: if (dest == (address) -1) { never@749: val = -5; // jump to self never@749: } duke@435: #ifdef AMD64 never@739: assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1"); duke@435: #endif // AMD64 duke@435: set_int_at(data_offset, (jint)val); duke@435: } duke@435: duke@435: // Creation duke@435: inline friend NativeJump* nativeJump_at(address address); duke@435: duke@435: void verify(); duke@435: duke@435: // Unit testing stuff duke@435: static void test() {} duke@435: duke@435: // Insertion of native jump instruction duke@435: static void insert(address code_pos, address entry); duke@435: // MT-safe insertion of native jump at verified method entry duke@435: static void check_verified_entry_alignment(address entry, address verified_entry); duke@435: static void patch_verified_entry(address entry, address verified_entry, address dest); duke@435: }; duke@435: duke@435: inline NativeJump* nativeJump_at(address address) { duke@435: NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); duke@435: #ifdef ASSERT duke@435: jump->verify(); duke@435: #endif duke@435: return jump; duke@435: } duke@435: duke@435: // Handles all kinds of jump on Intel. Long/far, conditional/unconditional duke@435: class NativeGeneralJump: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: // Constants does not apply, since the lengths and offsets depends on the actual jump duke@435: // used duke@435: // Instruction codes: duke@435: // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) duke@435: // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) duke@435: unconditional_long_jump = 0xe9, duke@435: unconditional_short_jump = 0xeb, duke@435: instruction_size = 5 duke@435: }; duke@435: duke@435: address instruction_address() const { return addr_at(0); } duke@435: address jump_destination() const; duke@435: duke@435: // Creation duke@435: inline friend NativeGeneralJump* nativeGeneralJump_at(address address); duke@435: duke@435: // Insertion of native general jump instruction duke@435: static void insert_unconditional(address code_pos, address entry); duke@435: static void replace_mt_safe(address instr_addr, address code_buffer); duke@435: duke@435: void verify(); duke@435: }; duke@435: duke@435: inline NativeGeneralJump* nativeGeneralJump_at(address address) { duke@435: NativeGeneralJump* jump = (NativeGeneralJump*)(address); duke@435: debug_only(jump->verify();) duke@435: return jump; duke@435: } duke@435: duke@435: class NativePopReg : public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0x58, duke@435: instruction_size = 1, duke@435: instruction_offset = 0, duke@435: data_offset = 1, duke@435: next_instruction_offset = 1 duke@435: }; duke@435: duke@435: // Insert a pop instruction duke@435: static void insert(address code_pos, Register reg); duke@435: }; duke@435: duke@435: duke@435: class NativeIllegalInstruction: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B duke@435: instruction_size = 2, duke@435: instruction_offset = 0, duke@435: next_instruction_offset = 2 duke@435: }; duke@435: duke@435: // Insert illegal opcode as specific address duke@435: static void insert(address code_pos); duke@435: }; duke@435: duke@435: // return instruction that does not pop values of the stack duke@435: class NativeReturn: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0xC3, duke@435: instruction_size = 1, duke@435: instruction_offset = 0, duke@435: next_instruction_offset = 1 duke@435: }; duke@435: }; duke@435: duke@435: // return instruction that does pop values of the stack duke@435: class NativeReturnX: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code = 0xC2, duke@435: instruction_size = 2, duke@435: instruction_offset = 0, duke@435: next_instruction_offset = 2 duke@435: }; duke@435: }; duke@435: duke@435: // Simple test vs memory duke@435: class NativeTstRegMem: public NativeInstruction { duke@435: public: duke@435: enum Intel_specific_constants { duke@435: instruction_code_memXregl = 0x85 duke@435: }; duke@435: }; duke@435: duke@435: inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } duke@435: inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } duke@435: inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || duke@435: ubyte_at(0) == NativeReturnX::instruction_code; } duke@435: inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || duke@435: ubyte_at(0) == 0xEB; /* short jump */ } duke@435: inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || duke@435: (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } duke@435: inline bool NativeInstruction::is_safepoint_poll() { duke@435: #ifdef AMD64 never@739: if ( ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && never@739: ubyte_at(1) == 0x05 ) { // 00 rax 101 never@739: address fault = addr_at(6) + int_at(2); never@739: return os::is_poll_address(fault); never@739: } else { never@739: return false; never@739: } duke@435: #else never@739: return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg || duke@435: ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && duke@435: (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ duke@435: (os::is_poll_address((address)int_at(2))); duke@435: #endif // AMD64 duke@435: } duke@435: duke@435: inline bool NativeInstruction::is_mov_literal64() { duke@435: #ifdef AMD64 duke@435: return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && duke@435: (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); duke@435: #else duke@435: return false; duke@435: #endif // AMD64 duke@435: }