duke@435: /*
duke@435:  * Copyright 2000-2005 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: // native word offsets from memory address (little endian)
duke@435: enum {
duke@435:   pd_lo_word_offset_in_bytes = 0,
duke@435:   pd_hi_word_offset_in_bytes = BytesPerWord
duke@435: };
duke@435: 
duke@435: // explicit rounding operations are required to implement the strictFP mode
duke@435: enum {
duke@435:   pd_strict_fp_requires_explicit_rounding = true
duke@435: };
duke@435: 
duke@435: 
duke@435: // registers
duke@435: enum {
never@739:   pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
never@739:   pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of registers used during code emission
never@739:   pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers,    // number of registers used during code emission
duke@435: 
never@739: #ifdef _LP64
never@739:   #define UNALLOCATED 4    // rsp, rbp, r15, r10
never@739: #else
never@739:   #define UNALLOCATED 2    // rsp, rbp
never@739: #endif // LP64
never@739: 
never@739:   pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED,  // number of registers killed by calls
never@739:   pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map,  // number of registers killed by calls
never@739:   pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map,  // number of registers killed by calls
never@739: 
never@739:   pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
duke@435:   pd_nof_fpu_regs_reg_alloc = 6,  // number of registers that are visible to register allocator
duke@435: 
never@739:   pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
never@739:   pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
never@739:   pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
duke@435:   pd_first_cpu_reg = 0,
never@739:   pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
duke@435:   pd_first_byte_reg = 2,
duke@435:   pd_last_byte_reg = 5,
duke@435:   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
duke@435:   pd_last_fpu_reg =  pd_first_fpu_reg + 7,
duke@435:   pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
never@739:   pd_last_xmm_reg =  pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
duke@435: };
duke@435: 
duke@435: 
duke@435: // encoding of float value in debug info:
duke@435: enum {
duke@435:   pd_float_saved_as_double = true
duke@435: };