aoqi@1: /*
aoqi@1:  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
aoqi@1:  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
aoqi@1:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@1:  *
aoqi@1:  * This code is free software; you can redistribute it and/or modify it
aoqi@1:  * under the terms of the GNU General Public License version 2 only, as
aoqi@1:  * published by the Free Software Foundation.
aoqi@1:  *
aoqi@1:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@1:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@1:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@1:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@1:  * accompanied this code).
aoqi@1:  *
aoqi@1:  * You should have received a copy of the GNU General Public License version
aoqi@1:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@1:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@1:  *
aoqi@1:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@1:  * or visit www.oracle.com if you need additional information or have any
aoqi@1:  * questions.
aoqi@1:  *
aoqi@1:  */
aoqi@1: 
aoqi@1: // Interface for updating the instruction cache.  Whenever the VM modifies
aoqi@1: // code, part of the processor instruction cache potentially has to be flushed.
aoqi@1: 
aoqi@1: // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
aoqi@1: // after the next jump, and the VM never modifies instructions directly ahead
aoqi@1: // of the instruction fetch path.
aoqi@1: 
aoqi@1: // [phh] It's not clear that the above comment is correct, because on an MP
aoqi@1: // system where the dcaches are not snooped, only the thread doing the invalidate
aoqi@1: // will see the update.  Even in the snooped case, a memory fence would be
aoqi@1: // necessary if stores weren't ordered.  Fortunately, they are on all known
aoqi@1: // x86 implementations.
aoqi@1: 
aoqi@1: class ICache : public AbstractICache {
aoqi@1:  public:
aoqi@1:   enum {
aoqi@1:     stub_size      = 0,                 // Size of the icache flush stub in bytes
aoqi@1: 		//FIXME aoqi
aoqi@1:     //line_size      = BytesPerWord,      // conservative
aoqi@1:     //log2_line_size = LogBytesPerWord    // log2(line_size)
aoqi@1: 		line_size      = 32,  // flush instruction affects a dword
aoqi@1: 		log2_line_size = 5    // log2(line_size)
aoqi@1:   };
aoqi@1: 
aoqi@1: 	//nothing to do
aoqi@1: 	static void initialize() {}
aoqi@1: 	
aoqi@1: 	static void call_flush_stub(address start, int lines);
aoqi@1: 
aoqi@1: 	static void invalidate_word(address addr);
aoqi@1: 		  
aoqi@1: 	static void invalidate_range(address start, int nbytes);
aoqi@1: 
aoqi@1: 	static void invalidate_all();
aoqi@1: 
aoqi@1: };