aoqi@1: /* aoqi@1: * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. aoqi@1: * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. aoqi@1: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@1: * aoqi@1: * This code is free software; you can redistribute it and/or modify it aoqi@1: * under the terms of the GNU General Public License version 2 only, as aoqi@1: * published by the Free Software Foundation. aoqi@1: * aoqi@1: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@1: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@1: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@1: * version 2 for more details (a copy is included in the LICENSE file that aoqi@1: * accompanied this code). aoqi@1: * aoqi@1: * You should have received a copy of the GNU General Public License version aoqi@1: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@1: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@1: * aoqi@1: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@1: * or visit www.oracle.com if you need additional information or have any aoqi@1: * questions. aoqi@1: * aoqi@1: */ aoqi@1: aoqi@1: #ifndef CPU_MIPS_VM_BYTES_MIPS_HPP aoqi@1: #define CPU_MIPS_VM_BYTES_MIPS_HPP aoqi@1: aoqi@1: #include "memory/allocation.hpp" aoqi@1: aoqi@1: class Bytes: AllStatic { aoqi@1: private: aoqi@1: // Helper function for swap_u8, not used in Loongson. aoqi@1: static inline u8 swap_u8_base(u4 x, u4 y) {} // compiler-dependent implementation aoqi@1: aoqi@1: public: aoqi@1: // Returns true if the byte ordering used by Java is different from the native byte ordering aoqi@1: // of the underlying machine. For example, this is true for Intel x86, but false for Solaris aoqi@1: // on Sparc. aoqi@1: // we use mipsel, so return true aoqi@1: static inline bool is_Java_byte_ordering_different(){ return true; } aoqi@1: aoqi@1: aoqi@1: // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering aoqi@1: // (no special code is needed since x86 CPUs can access unaligned data) aoqi@1: static inline u2 get_native_u2(address p) { aoqi@1: if ((intptr_t)p & 0x1) { aoqi@1: return ((u2)p[1] << 8) | (u2)p[0]; aoqi@1: } else { aoqi@1: return *(u2*)p; aoqi@1: } aoqi@1: } aoqi@1: aoqi@1: static inline u4 get_native_u4(address p) { aoqi@1: if ((intptr_t)p & 3) { aoqi@1: u4 res; aoqi@1: __asm__ __volatile__ ( aoqi@1: " .set push\n" aoqi@1: " .set mips64\n" aoqi@1: " .set noreorder\n" aoqi@1: aoqi@1: " lwr %[res], 0(%[addr]) \n" aoqi@1: " lwl %[res], 3(%[addr]) \n" aoqi@1: aoqi@1: " .set pop" aoqi@1: : [res] "=&r" (res) aoqi@1: : [addr] "r" (p) aoqi@1: : "memory" aoqi@1: ); aoqi@1: return res; aoqi@1: } else { aoqi@1: return *(u4*)p; aoqi@1: } aoqi@1: } aoqi@1: aoqi@1: static inline u8 get_native_u8(address p) { aoqi@1: u8 res; aoqi@1: u8 temp; aoqi@1: // u4 tp;//tmp register aoqi@1: __asm__ __volatile__ ( aoqi@1: " .set push\n" aoqi@1: " .set mips64\n" aoqi@1: " .set noreorder\n" aoqi@1: " .set noat\n" aoqi@1: " andi $1,%[addr],0x7 \n" aoqi@1: " beqz $1,1f \n" aoqi@1: " nop \n" aoqi@1: " ldr %[temp], 0(%[addr]) \n" aoqi@1: " ldl %[temp], 7(%[addr]) \n" aoqi@1: " b 2f \n" aoqi@1: " nop \n" aoqi@1: " 1:\t ld %[temp],0(%[addr]) \n" aoqi@1: " 2:\t sd %[temp], %[res] \n" aoqi@1: aoqi@1: " .set at\n" aoqi@1: " .set pop\n" aoqi@1: : [addr]"=r"(p), [temp]"=r" (temp) aoqi@1: : "[addr]"(p), "[temp]" (temp), [res]"m" (*(volatile jint*)&res) aoqi@1: : "memory" aoqi@1: ); aoqi@1: aoqi@1: return res; aoqi@1: } aoqi@1: //use mips unaligned load instructions aoqi@1: static inline void put_native_u2(address p, u2 x) { aoqi@1: if((intptr_t)p & 0x1) { aoqi@1: p[0] = (u_char)(x); aoqi@1: p[1] = (u_char)(x>>8); aoqi@1: } else { aoqi@1: *(u2*)p = x; aoqi@1: } aoqi@1: } aoqi@1: static inline void put_native_u4(address p, u4 x) { Jin@6: /* 2016/5/8 Jin: refer to sparc implementation. Jin@6: Note that sparc is big-endian, while mips is little-endian */ Jin@6: switch ( intptr_t(p) & 3 ) { Jin@6: case 0: *(u4*)p = x; Jin@6: break; Jin@6: Jin@6: case 2: ((u2*)p)[1] = x >> 16; Jin@6: ((u2*)p)[0] = x; Jin@6: break; Jin@6: Jin@6: default: ((u1*)p)[3] = x >> 24; Jin@6: ((u1*)p)[2] = x >> 16; Jin@6: ((u1*)p)[1] = x >> 8; Jin@6: ((u1*)p)[0] = x; Jin@6: break; Jin@6: } aoqi@1: /* if ((int)p&3) { aoqi@1: __asm__ __volatile__ ( aoqi@1: " .set push\n" aoqi@1: " .set mips64\n" aoqi@1: " .set noreorder\n" aoqi@1: aoqi@1: " swr %[x], 0(%[addr]) \n" aoqi@1: " swl %[x], 3(%[addr]) \n" aoqi@1: aoqi@1: " .set pop" aoqi@1: : aoqi@1: : [addr] "r" (p), [x] "r" (x) aoqi@1: : "memory" aoqi@1: ); aoqi@1: } else { aoqi@1: *(u4*)p = x; aoqi@1: }*/ aoqi@1: } aoqi@1: static inline void put_native_u8(address p, u8 x) { Jin@6: /* 2016/5/8 Jin: refer to sparc implementation. Jin@6: Note that sparc is big-endian, while mips is little-endian */ Jin@6: switch ( intptr_t(p) & 7 ) { Jin@6: case 0: *(u8*)p = x; Jin@6: break; Jin@6: Jin@6: case 4: ((u4*)p)[1] = x >> 32; Jin@6: ((u4*)p)[0] = x; Jin@6: break; Jin@6: Jin@6: case 2: ((u2*)p)[3] = x >> 48; Jin@6: ((u2*)p)[2] = x >> 32; Jin@6: ((u2*)p)[1] = x >> 16; Jin@6: ((u2*)p)[0] = x; Jin@6: break; Jin@6: Jin@6: default: ((u1*)p)[7] = x >> 56; Jin@6: ((u1*)p)[6] = x >> 48; Jin@6: ((u1*)p)[5] = x >> 40; Jin@6: ((u1*)p)[4] = x >> 32; Jin@6: ((u1*)p)[3] = x >> 24; Jin@6: ((u1*)p)[2] = x >> 16; Jin@6: ((u1*)p)[1] = x >> 8; Jin@6: ((u1*)p)[0] = x; Jin@6: } aoqi@1: /*if ((int)p&7) { aoqi@1: aoqi@1: __asm__ __volatile__ ( aoqi@1: " .set push\n" aoqi@1: " .set mips64\n" aoqi@1: " .set noreorder\n" aoqi@1: " .set noat\n" aoqi@1: " sdr %[x], 0(%[addr]) \n" aoqi@1: " sdl %[x], 7(%[addr]) \n" aoqi@1: aoqi@1: " .set at\n" aoqi@1: " .set pop\n" aoqi@1: : aoqi@1: : [addr] "r" (p), [x]"r" (x) aoqi@1: : "memory" aoqi@1: ); aoqi@1: } else { aoqi@1: aoqi@1: *(u8*)p = x; aoqi@1: }*/ aoqi@1: aoqi@1: } aoqi@1: aoqi@1: aoqi@1: // Efficient reading and writing of unaligned unsigned data in Java aoqi@1: // byte ordering (i.e. big-endian ordering). Byte-order reversal is aoqi@1: // needed since x86 CPUs use little-endian format. aoqi@1: static inline u2 get_Java_u2(address p) { return swap_u2(get_native_u2(p)); } aoqi@1: static inline u4 get_Java_u4(address p) { return swap_u4(get_native_u4(p)); } aoqi@1: static inline u8 get_Java_u8(address p) { return swap_u8(get_native_u8(p)); } aoqi@1: aoqi@1: static inline void put_Java_u2(address p, u2 x) { put_native_u2(p, swap_u2(x)); } aoqi@1: static inline void put_Java_u4(address p, u4 x) { put_native_u4(p, swap_u4(x)); } aoqi@1: static inline void put_Java_u8(address p, u8 x) { put_native_u8(p, swap_u8(x)); } aoqi@1: aoqi@1: aoqi@1: // Efficient swapping of byte ordering aoqi@1: static inline u2 swap_u2(u2 x); // compiler-dependent implementation aoqi@1: static inline u4 swap_u4(u4 x); // compiler-dependent implementation aoqi@1: static inline u8 swap_u8(u8 x); aoqi@1: }; aoqi@1: aoqi@1: aoqi@1: // The following header contains the implementations of swap_u2, swap_u4, and swap_u8[_base] aoqi@1: #ifdef TARGET_OS_ARCH_linux_mips aoqi@1: # include "bytes_linux_mips.inline.hpp" aoqi@1: #endif aoqi@1: #ifdef TARGET_OS_ARCH_solaris_mips aoqi@1: # include "bytes_solaris_mips.inline.hpp" aoqi@1: #endif aoqi@1: #ifdef TARGET_OS_ARCH_windows_mips aoqi@1: # include "bytes_windows_mips.inline.hpp" aoqi@1: #endif aoqi@1: #ifdef TARGET_OS_ARCH_bsd_mips aoqi@1: # include "bytes_bsd_mips.inline.hpp" aoqi@1: #endif aoqi@1: aoqi@1: aoqi@1: #endif // CPU_MIPS_VM_BYTES_MIPS_HPP aoqi@1: