duke@435: /* jrose@1100: * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: class BiasedLockingCounters; duke@435: duke@435: // promises that the system will not use traps 16-31 duke@435: #define ST_RESERVED_FOR_USER_0 0x10 duke@435: duke@435: /* Written: David Ungar 4/19/97 */ duke@435: duke@435: // Contains all the definitions needed for sparc assembly code generation. duke@435: duke@435: // Register aliases for parts of the system: duke@435: duke@435: // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe duke@435: // across context switches in V8+ ABI. Of course, there are no 64 bit regs duke@435: // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. duke@435: duke@435: // g2-g4 are scratch registers called "application globals". Their duke@435: // meaning is reserved to the "compilation system"--which means us! duke@435: // They are are not supposed to be touched by ordinary C code, although duke@435: // highly-optimized C code might steal them for temps. They are safe duke@435: // across thread switches, and the ABI requires that they be safe duke@435: // across function calls. duke@435: // duke@435: // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered duke@435: // across func calls, and V8+ also allows g5 to be clobbered across duke@435: // func calls. Also, g1 and g5 can get touched while doing shared duke@435: // library loading. duke@435: // duke@435: // We must not touch g7 (it is the thread-self register) and g6 is duke@435: // reserved for certain tools. g0, of course, is always zero. duke@435: // duke@435: // (Sources: SunSoft Compilers Group, thread library engineers.) duke@435: duke@435: // %%%% The interpreter should be revisited to reduce global scratch regs. duke@435: duke@435: // This global always holds the current JavaThread pointer: duke@435: duke@435: REGISTER_DECLARATION(Register, G2_thread , G2); coleenp@548: REGISTER_DECLARATION(Register, G6_heapbase , G6); duke@435: duke@435: // The following globals are part of the Java calling convention: duke@435: duke@435: REGISTER_DECLARATION(Register, G5_method , G5); duke@435: REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); duke@435: REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); duke@435: duke@435: // The following globals are used for the new C1 & interpreter calling convention: duke@435: REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument duke@435: duke@435: // This local is used to preserve G2_thread in the interpreter and in stubs: duke@435: REGISTER_DECLARATION(Register, L7_thread_cache , L7); duke@435: duke@435: // These globals are used as scratch registers in the interpreter: duke@435: duke@435: REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch duke@435: REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME duke@435: REGISTER_DECLARATION(Register, G3_scratch , G3); duke@435: REGISTER_DECLARATION(Register, G4_scratch , G4); duke@435: duke@435: // These globals are used as short-lived scratch registers in the compiler: duke@435: duke@435: REGISTER_DECLARATION(Register, Gtemp , G5); duke@435: jrose@1145: // JSR 292 fixed register usages: jrose@1145: REGISTER_DECLARATION(Register, G5_method_type , G5); jrose@1145: REGISTER_DECLARATION(Register, G3_method_handle , G3); jrose@1145: duke@435: // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, duke@435: // because a single patchable "set" instruction (NativeMovConstReg, duke@435: // or NativeMovConstPatching for compiler1) instruction duke@435: // serves to set up either quantity, depending on whether the compiled duke@435: // call site is an inline cache or is megamorphic. See the function duke@435: // CompiledIC::set_to_megamorphic. duke@435: // jrose@1145: // If a inline cache targets an interpreted method, then the jrose@1145: // G5 register will be used twice during the call. First, jrose@1145: // the call site will be patched to load a compiledICHolder jrose@1145: // into G5. (This is an ordered pair of ic_klass, method.) jrose@1145: // The c2i adapter will first check the ic_klass, then load jrose@1145: // G5_method with the method part of the pair just before jrose@1145: // jumping into the interpreter. duke@435: // duke@435: // Note that G5_method is only the method-self for the interpreter, duke@435: // and is logically unrelated to G5_megamorphic_method. duke@435: // duke@435: // Invariants on G2_thread (the JavaThread pointer): duke@435: // - it should not be used for any other purpose anywhere duke@435: // - it must be re-initialized by StubRoutines::call_stub() duke@435: // - it must be preserved around every use of call_VM duke@435: duke@435: // We can consider using g2/g3/g4 to cache more values than the duke@435: // JavaThread, such as the card-marking base or perhaps pointers into duke@435: // Eden. It's something of a waste to use them as scratch temporaries, duke@435: // since they are not supposed to be volatile. (Of course, if we find duke@435: // that Java doesn't benefit from application globals, then we can just duke@435: // use them as ordinary temporaries.) duke@435: // duke@435: // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, duke@435: // it makes sense to use them routinely for procedure linkage, duke@435: // whenever the On registers are not applicable. Examples: G5_method, duke@435: // G5_inline_cache_klass, and a double handful of miscellaneous compiler duke@435: // stubs. This means that compiler stubs, etc., should be kept to a duke@435: // maximum of two or three G-register arguments. duke@435: duke@435: duke@435: // stub frames duke@435: duke@435: REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself duke@435: duke@435: // Interpreter frames duke@435: duke@435: #ifdef CC_INTERP duke@435: REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer duke@435: REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch duke@435: REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) duke@435: REGISTER_DECLARATION(Register, L2_scratch , L2); duke@435: REGISTER_DECLARATION(Register, L3_scratch , L3); duke@435: REGISTER_DECLARATION(Register, L4_scratch , L4); duke@435: REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses duke@435: REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses duke@435: REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache duke@435: REGISTER_DECLARATION(Register, O5_savedSP , O5); duke@435: REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply duke@435: // a copy SP, so in 64-bit it's a biased value. The bias duke@435: // is added and removed as needed in the frame code. duke@435: // Interface to signature handler duke@435: REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler duke@435: REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler duke@435: duke@435: #else duke@435: REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer duke@435: REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode duke@435: REGISTER_DECLARATION(Register, Lmethod , L2); duke@435: REGISTER_DECLARATION(Register, Llocals , L3); duke@435: REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler duke@435: // must match Llocals in asm interpreter duke@435: REGISTER_DECLARATION(Register, Lmonitors , L4); duke@435: REGISTER_DECLARATION(Register, Lbyte_code , L5); duke@435: // When calling out from the interpreter we record SP so that we can remove any extra stack duke@435: // space allocated during adapter transitions. This register is only live from the point duke@435: // of the call until we return. duke@435: REGISTER_DECLARATION(Register, Llast_SP , L5); duke@435: REGISTER_DECLARATION(Register, Lscratch , L5); duke@435: REGISTER_DECLARATION(Register, Lscratch2 , L6); duke@435: REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache duke@435: duke@435: REGISTER_DECLARATION(Register, O5_savedSP , O5); duke@435: REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply duke@435: // a copy SP, so in 64-bit it's a biased value. The bias duke@435: // is added and removed as needed in the frame code. duke@435: REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables duke@435: REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode duke@435: REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data duke@435: #endif /* CC_INTERP */ duke@435: duke@435: // NOTE: Lscratch2 and LcpoolCache point to the same registers in duke@435: // the interpreter code. If Lscratch2 needs to be used for some duke@435: // purpose than LcpoolCache should be restore after that for duke@435: // the interpreter to work right duke@435: // (These assignments must be compatible with L7_thread_cache; see above.) duke@435: duke@435: // Since Lbcp points into the middle of the method object, duke@435: // it is temporarily converted into a "bcx" during GC. duke@435: duke@435: // Exception processing duke@435: // These registers are passed into exception handlers. duke@435: // All exception handlers require the exception object being thrown. duke@435: // In addition, an nmethod's exception handler must be passed duke@435: // the address of the call site within the nmethod, to allow duke@435: // proper selection of the applicable catch block. duke@435: // (Interpreter frames use their own bcp() for this purpose.) duke@435: // duke@435: // The Oissuing_pc value is not always needed. When jumping to a duke@435: // handler that is known to be interpreted, the Oissuing_pc value can be duke@435: // omitted. An actual catch block in compiled code receives (from its duke@435: // nmethod's exception handler) the thrown exception in the Oexception, duke@435: // but it doesn't need the Oissuing_pc. duke@435: // duke@435: // If an exception handler (either interpreted or compiled) duke@435: // discovers there is no applicable catch block, it updates duke@435: // the Oissuing_pc to the continuation PC of its own caller, duke@435: // pops back to that caller's stack frame, and executes that duke@435: // caller's exception handler. Obviously, this process will duke@435: // iterate until the control stack is popped back to a method duke@435: // containing an applicable catch block. A key invariant is duke@435: // that the Oissuing_pc value is always a value local to duke@435: // the method whose exception handler is currently executing. duke@435: // duke@435: // Note: The issuing PC value is __not__ a raw return address (I7 value). duke@435: // It is a "return pc", the address __following__ the call. duke@435: // Raw return addresses are converted to issuing PCs by frame::pc(), duke@435: // or by stubs. Issuing PCs can be used directly with PC range tables. duke@435: // duke@435: REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown duke@435: REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from duke@435: duke@435: duke@435: // These must occur after the declarations above duke@435: #ifndef DONT_USE_REGISTER_DEFINES duke@435: duke@435: #define Gthread AS_REGISTER(Register, Gthread) duke@435: #define Gmethod AS_REGISTER(Register, Gmethod) duke@435: #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) duke@435: #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) duke@435: #define Gargs AS_REGISTER(Register, Gargs) duke@435: #define Lthread_cache AS_REGISTER(Register, Lthread_cache) duke@435: #define Gframe_size AS_REGISTER(Register, Gframe_size) duke@435: #define Gtemp AS_REGISTER(Register, Gtemp) duke@435: duke@435: #ifdef CC_INTERP duke@435: #define Lstate AS_REGISTER(Register, Lstate) duke@435: #define Lesp AS_REGISTER(Register, Lesp) duke@435: #define L1_scratch AS_REGISTER(Register, L1_scratch) duke@435: #define Lmirror AS_REGISTER(Register, Lmirror) duke@435: #define L2_scratch AS_REGISTER(Register, L2_scratch) duke@435: #define L3_scratch AS_REGISTER(Register, L3_scratch) duke@435: #define L4_scratch AS_REGISTER(Register, L4_scratch) duke@435: #define Lscratch AS_REGISTER(Register, Lscratch) duke@435: #define Lscratch2 AS_REGISTER(Register, Lscratch2) duke@435: #define L7_scratch AS_REGISTER(Register, L7_scratch) duke@435: #define Ostate AS_REGISTER(Register, Ostate) duke@435: #else duke@435: #define Lesp AS_REGISTER(Register, Lesp) duke@435: #define Lbcp AS_REGISTER(Register, Lbcp) duke@435: #define Lmethod AS_REGISTER(Register, Lmethod) duke@435: #define Llocals AS_REGISTER(Register, Llocals) duke@435: #define Lmonitors AS_REGISTER(Register, Lmonitors) duke@435: #define Lbyte_code AS_REGISTER(Register, Lbyte_code) duke@435: #define Lscratch AS_REGISTER(Register, Lscratch) duke@435: #define Lscratch2 AS_REGISTER(Register, Lscratch2) duke@435: #define LcpoolCache AS_REGISTER(Register, LcpoolCache) duke@435: #endif /* ! CC_INTERP */ duke@435: duke@435: #define Lentry_args AS_REGISTER(Register, Lentry_args) duke@435: #define I5_savedSP AS_REGISTER(Register, I5_savedSP) duke@435: #define O5_savedSP AS_REGISTER(Register, O5_savedSP) duke@435: #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) duke@435: #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) duke@435: #define IdispatchTables AS_REGISTER(Register, IdispatchTables) duke@435: duke@435: #define Oexception AS_REGISTER(Register, Oexception) duke@435: #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) duke@435: duke@435: duke@435: #endif duke@435: duke@435: // Address is an abstraction used to represent a memory location. duke@435: // duke@435: // Note: A register location is represented via a Register, not duke@435: // via an address for efficiency & simplicity reasons. duke@435: duke@435: class Address VALUE_OBJ_CLASS_SPEC { duke@435: private: twisti@1162: Register _base; // Base register. twisti@1162: RegisterOrConstant _index_or_disp; // Index register or constant displacement. twisti@1162: RelocationHolder _rspec; twisti@1162: twisti@1162: public: twisti@1162: Address() : _base(noreg), _index_or_disp(noreg) {} twisti@1162: twisti@1162: Address(Register base, RegisterOrConstant index_or_disp) twisti@1162: : _base(base), twisti@1162: _index_or_disp(index_or_disp) { twisti@1162: } twisti@1162: twisti@1162: Address(Register base, Register index) twisti@1162: : _base(base), twisti@1162: _index_or_disp(index) { twisti@1162: } twisti@1162: twisti@1162: Address(Register base, int disp) twisti@1162: : _base(base), twisti@1162: _index_or_disp(disp) { twisti@1162: } twisti@1162: twisti@1162: #ifdef ASSERT twisti@1162: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@1162: Address(Register base, ByteSize disp) twisti@1162: : _base(base), twisti@1162: _index_or_disp(in_bytes(disp)) { twisti@1162: } duke@435: #endif twisti@1162: twisti@1162: // accessors twisti@1162: Register base() const { return _base; } twisti@1162: Register index() const { return _index_or_disp.as_register(); } twisti@1162: int disp() const { return _index_or_disp.as_constant(); } twisti@1162: twisti@1162: bool has_index() const { return _index_or_disp.is_register(); } twisti@1162: bool has_disp() const { return _index_or_disp.is_constant(); } twisti@1162: twisti@1162: const relocInfo::relocType rtype() { return _rspec.type(); } twisti@1162: const RelocationHolder& rspec() { return _rspec; } twisti@1162: twisti@1162: RelocationHolder rspec(int offset) const { twisti@1162: return offset == 0 ? _rspec : _rspec.plus(offset); twisti@1162: } twisti@1162: twisti@1162: inline bool is_simm13(int offset = 0); // check disp+offset for overflow twisti@1162: twisti@1162: Address plus_disp(int plusdisp) const { // bump disp by a small amount twisti@1162: assert(_index_or_disp.is_constant(), "must have a displacement"); twisti@1162: Address a(base(), disp() + plusdisp); twisti@1162: return a; twisti@1162: } twisti@1162: twisti@1162: Address after_save() const { twisti@1162: Address a = (*this); twisti@1162: a._base = a._base->after_save(); twisti@1162: return a; twisti@1162: } twisti@1162: twisti@1162: Address after_restore() const { twisti@1162: Address a = (*this); twisti@1162: a._base = a._base->after_restore(); twisti@1162: return a; twisti@1162: } twisti@1162: twisti@1162: // Convert the raw encoding form into the form expected by the twisti@1162: // constructor for Address. twisti@1162: static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); twisti@1162: twisti@1162: friend class Assembler; twisti@1162: }; twisti@1162: twisti@1162: twisti@1162: class AddressLiteral VALUE_OBJ_CLASS_SPEC { twisti@1162: private: twisti@1162: address _address; twisti@1162: RelocationHolder _rspec; twisti@1162: twisti@1162: RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { twisti@1162: switch (rtype) { duke@435: case relocInfo::external_word_type: twisti@1162: return external_word_Relocation::spec(addr); duke@435: case relocInfo::internal_word_type: twisti@1162: return internal_word_Relocation::spec(addr); duke@435: #ifdef _LP64 duke@435: case relocInfo::opt_virtual_call_type: duke@435: return opt_virtual_call_Relocation::spec(); duke@435: case relocInfo::static_call_type: duke@435: return static_call_Relocation::spec(); duke@435: case relocInfo::runtime_call_type: duke@435: return runtime_call_Relocation::spec(); duke@435: #endif duke@435: case relocInfo::none: duke@435: return RelocationHolder(); duke@435: default: duke@435: ShouldNotReachHere(); duke@435: return RelocationHolder(); duke@435: } duke@435: } duke@435: twisti@1162: protected: twisti@1162: // creation twisti@1162: AddressLiteral() : _address(NULL), _rspec(NULL) {} twisti@1162: duke@435: public: twisti@1162: AddressLiteral(address addr, RelocationHolder const& rspec) twisti@1162: : _address(addr), twisti@1162: _rspec(rspec) {} twisti@1162: twisti@1162: // Some constructors to avoid casting at the call site. twisti@1162: AddressLiteral(jobject obj, RelocationHolder const& rspec) twisti@1162: : _address((address) obj), twisti@1162: _rspec(rspec) {} twisti@1162: twisti@1162: AddressLiteral(intptr_t value, RelocationHolder const& rspec) twisti@1162: : _address((address) value), twisti@1162: _rspec(rspec) {} twisti@1162: twisti@1162: AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: // Some constructors to avoid casting at the call site. twisti@1162: AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: duke@435: #ifdef _LP64 twisti@1162: // 32-bit complains about a multiple declaration for int*. twisti@1162: AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} duke@435: #endif twisti@1162: twisti@1162: AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) twisti@1162: : _address((address) addr), twisti@1162: _rspec(rspec_from_rtype(rtype, (address) addr)) {} twisti@1162: twisti@1162: intptr_t value() const { return (intptr_t) _address; } twisti@1162: int low10() const; twisti@1162: twisti@1162: const relocInfo::relocType rtype() const { return _rspec.type(); } twisti@1162: const RelocationHolder& rspec() const { return _rspec; } twisti@1162: twisti@1162: RelocationHolder rspec(int offset) const { duke@435: return offset == 0 ? _rspec : _rspec.plus(offset); duke@435: } duke@435: }; duke@435: duke@435: duke@435: inline Address RegisterImpl::address_in_saved_window() const { twisti@1162: return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); duke@435: } duke@435: duke@435: duke@435: duke@435: // Argument is an abstraction used to represent an outgoing duke@435: // actual argument or an incoming formal parameter, whether duke@435: // it resides in memory or in a register, in a manner consistent duke@435: // with the SPARC Application Binary Interface, or ABI. This is duke@435: // often referred to as the native or C calling convention. duke@435: duke@435: class Argument VALUE_OBJ_CLASS_SPEC { duke@435: private: duke@435: int _number; duke@435: bool _is_in; duke@435: duke@435: public: duke@435: #ifdef _LP64 duke@435: enum { duke@435: n_register_parameters = 6, // only 6 registers may contain integer parameters duke@435: n_float_register_parameters = 16 // Can have up to 16 floating registers duke@435: }; duke@435: #else duke@435: enum { duke@435: n_register_parameters = 6 // only 6 registers may contain integer parameters duke@435: }; duke@435: #endif duke@435: duke@435: // creation duke@435: Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} duke@435: duke@435: int number() const { return _number; } duke@435: bool is_in() const { return _is_in; } duke@435: bool is_out() const { return !is_in(); } duke@435: duke@435: Argument successor() const { return Argument(number() + 1, is_in()); } duke@435: Argument as_in() const { return Argument(number(), true ); } duke@435: Argument as_out() const { return Argument(number(), false); } duke@435: duke@435: // locating register-based arguments: duke@435: bool is_register() const { return _number < n_register_parameters; } duke@435: duke@435: #ifdef _LP64 duke@435: // locating Floating Point register-based arguments: duke@435: bool is_float_register() const { return _number < n_float_register_parameters; } duke@435: duke@435: FloatRegister as_float_register() const { duke@435: assert(is_float_register(), "must be a register argument"); duke@435: return as_FloatRegister(( number() *2 ) + 1); duke@435: } duke@435: FloatRegister as_double_register() const { duke@435: assert(is_float_register(), "must be a register argument"); duke@435: return as_FloatRegister(( number() *2 )); duke@435: } duke@435: #endif duke@435: duke@435: Register as_register() const { duke@435: assert(is_register(), "must be a register argument"); duke@435: return is_in() ? as_iRegister(number()) : as_oRegister(number()); duke@435: } duke@435: duke@435: // locating memory-based arguments duke@435: Address as_address() const { duke@435: assert(!is_register(), "must be a memory argument"); duke@435: return address_in_frame(); duke@435: } duke@435: duke@435: // When applied to a register-based argument, give the corresponding address duke@435: // into the 6-word area "into which callee may store register arguments" duke@435: // (This is a different place than the corresponding register-save area location.) twisti@1162: Address address_in_frame() const; duke@435: duke@435: // debugging duke@435: const char* name() const; duke@435: duke@435: friend class Assembler; duke@435: }; duke@435: duke@435: duke@435: // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction duke@435: // level; i.e., what you write duke@435: // is what you get. The Assembler is generating code into a CodeBuffer. duke@435: duke@435: class Assembler : public AbstractAssembler { duke@435: protected: duke@435: duke@435: static void print_instruction(int inst); duke@435: static int patched_branch(int dest_pos, int inst, int inst_pos); duke@435: static int branch_destination(int inst, int pos); duke@435: duke@435: duke@435: friend class AbstractAssembler; twisti@1162: friend class AddressLiteral; duke@435: duke@435: // code patchers need various routines like inv_wdisp() duke@435: friend class NativeInstruction; duke@435: friend class NativeGeneralJump; duke@435: friend class Relocation; duke@435: friend class Label; duke@435: duke@435: public: duke@435: // op carries format info; see page 62 & 267 duke@435: duke@435: enum ops { duke@435: call_op = 1, // fmt 1 duke@435: branch_op = 0, // also sethi (fmt2) duke@435: arith_op = 2, // fmt 3, arith & misc duke@435: ldst_op = 3 // fmt 3, load/store duke@435: }; duke@435: duke@435: enum op2s { duke@435: bpr_op2 = 3, duke@435: fb_op2 = 6, duke@435: fbp_op2 = 5, duke@435: br_op2 = 2, duke@435: bp_op2 = 1, duke@435: cb_op2 = 7, // V8 duke@435: sethi_op2 = 4 duke@435: }; duke@435: duke@435: enum op3s { duke@435: // selected op3s duke@435: add_op3 = 0x00, duke@435: and_op3 = 0x01, duke@435: or_op3 = 0x02, duke@435: xor_op3 = 0x03, duke@435: sub_op3 = 0x04, duke@435: andn_op3 = 0x05, duke@435: orn_op3 = 0x06, duke@435: xnor_op3 = 0x07, duke@435: addc_op3 = 0x08, duke@435: mulx_op3 = 0x09, duke@435: umul_op3 = 0x0a, duke@435: smul_op3 = 0x0b, duke@435: subc_op3 = 0x0c, duke@435: udivx_op3 = 0x0d, duke@435: udiv_op3 = 0x0e, duke@435: sdiv_op3 = 0x0f, duke@435: duke@435: addcc_op3 = 0x10, duke@435: andcc_op3 = 0x11, duke@435: orcc_op3 = 0x12, duke@435: xorcc_op3 = 0x13, duke@435: subcc_op3 = 0x14, duke@435: andncc_op3 = 0x15, duke@435: orncc_op3 = 0x16, duke@435: xnorcc_op3 = 0x17, duke@435: addccc_op3 = 0x18, duke@435: umulcc_op3 = 0x1a, duke@435: smulcc_op3 = 0x1b, duke@435: subccc_op3 = 0x1c, duke@435: udivcc_op3 = 0x1e, duke@435: sdivcc_op3 = 0x1f, duke@435: duke@435: taddcc_op3 = 0x20, duke@435: tsubcc_op3 = 0x21, duke@435: taddcctv_op3 = 0x22, duke@435: tsubcctv_op3 = 0x23, duke@435: mulscc_op3 = 0x24, duke@435: sll_op3 = 0x25, duke@435: sllx_op3 = 0x25, duke@435: srl_op3 = 0x26, duke@435: srlx_op3 = 0x26, duke@435: sra_op3 = 0x27, duke@435: srax_op3 = 0x27, duke@435: rdreg_op3 = 0x28, duke@435: membar_op3 = 0x28, duke@435: duke@435: flushw_op3 = 0x2b, duke@435: movcc_op3 = 0x2c, duke@435: sdivx_op3 = 0x2d, duke@435: popc_op3 = 0x2e, duke@435: movr_op3 = 0x2f, duke@435: duke@435: sir_op3 = 0x30, duke@435: wrreg_op3 = 0x30, duke@435: saved_op3 = 0x31, duke@435: duke@435: fpop1_op3 = 0x34, duke@435: fpop2_op3 = 0x35, duke@435: impdep1_op3 = 0x36, duke@435: impdep2_op3 = 0x37, duke@435: jmpl_op3 = 0x38, duke@435: rett_op3 = 0x39, duke@435: trap_op3 = 0x3a, duke@435: flush_op3 = 0x3b, duke@435: save_op3 = 0x3c, duke@435: restore_op3 = 0x3d, duke@435: done_op3 = 0x3e, duke@435: retry_op3 = 0x3e, duke@435: duke@435: lduw_op3 = 0x00, duke@435: ldub_op3 = 0x01, duke@435: lduh_op3 = 0x02, duke@435: ldd_op3 = 0x03, duke@435: stw_op3 = 0x04, duke@435: stb_op3 = 0x05, duke@435: sth_op3 = 0x06, duke@435: std_op3 = 0x07, duke@435: ldsw_op3 = 0x08, duke@435: ldsb_op3 = 0x09, duke@435: ldsh_op3 = 0x0a, duke@435: ldx_op3 = 0x0b, duke@435: duke@435: ldstub_op3 = 0x0d, duke@435: stx_op3 = 0x0e, duke@435: swap_op3 = 0x0f, duke@435: duke@435: stwa_op3 = 0x14, duke@435: stxa_op3 = 0x1e, duke@435: duke@435: ldf_op3 = 0x20, duke@435: ldfsr_op3 = 0x21, duke@435: ldqf_op3 = 0x22, duke@435: lddf_op3 = 0x23, duke@435: stf_op3 = 0x24, duke@435: stfsr_op3 = 0x25, duke@435: stqf_op3 = 0x26, duke@435: stdf_op3 = 0x27, duke@435: duke@435: prefetch_op3 = 0x2d, duke@435: duke@435: duke@435: ldc_op3 = 0x30, duke@435: ldcsr_op3 = 0x31, duke@435: lddc_op3 = 0x33, duke@435: stc_op3 = 0x34, duke@435: stcsr_op3 = 0x35, duke@435: stdcq_op3 = 0x36, duke@435: stdc_op3 = 0x37, duke@435: duke@435: casa_op3 = 0x3c, duke@435: casxa_op3 = 0x3e, duke@435: duke@435: alt_bit_op3 = 0x10, duke@435: cc_bit_op3 = 0x10 duke@435: }; duke@435: duke@435: enum opfs { duke@435: // selected opfs duke@435: fmovs_opf = 0x01, duke@435: fmovd_opf = 0x02, duke@435: duke@435: fnegs_opf = 0x05, duke@435: fnegd_opf = 0x06, duke@435: duke@435: fadds_opf = 0x41, duke@435: faddd_opf = 0x42, duke@435: fsubs_opf = 0x45, duke@435: fsubd_opf = 0x46, duke@435: duke@435: fmuls_opf = 0x49, duke@435: fmuld_opf = 0x4a, duke@435: fdivs_opf = 0x4d, duke@435: fdivd_opf = 0x4e, duke@435: duke@435: fcmps_opf = 0x51, duke@435: fcmpd_opf = 0x52, duke@435: duke@435: fstox_opf = 0x81, duke@435: fdtox_opf = 0x82, duke@435: fxtos_opf = 0x84, duke@435: fxtod_opf = 0x88, duke@435: fitos_opf = 0xc4, duke@435: fdtos_opf = 0xc6, duke@435: fitod_opf = 0xc8, duke@435: fstod_opf = 0xc9, duke@435: fstoi_opf = 0xd1, duke@435: fdtoi_opf = 0xd2 duke@435: }; duke@435: duke@435: enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 }; duke@435: duke@435: enum Condition { duke@435: // for FBfcc & FBPfcc instruction duke@435: f_never = 0, duke@435: f_notEqual = 1, duke@435: f_notZero = 1, duke@435: f_lessOrGreater = 2, duke@435: f_unorderedOrLess = 3, duke@435: f_less = 4, duke@435: f_unorderedOrGreater = 5, duke@435: f_greater = 6, duke@435: f_unordered = 7, duke@435: f_always = 8, duke@435: f_equal = 9, duke@435: f_zero = 9, duke@435: f_unorderedOrEqual = 10, duke@435: f_greaterOrEqual = 11, duke@435: f_unorderedOrGreaterOrEqual = 12, duke@435: f_lessOrEqual = 13, duke@435: f_unorderedOrLessOrEqual = 14, duke@435: f_ordered = 15, duke@435: duke@435: // V8 coproc, pp 123 v8 manual duke@435: duke@435: cp_always = 8, duke@435: cp_never = 0, duke@435: cp_3 = 7, duke@435: cp_2 = 6, duke@435: cp_2or3 = 5, duke@435: cp_1 = 4, duke@435: cp_1or3 = 3, duke@435: cp_1or2 = 2, duke@435: cp_1or2or3 = 1, duke@435: cp_0 = 9, duke@435: cp_0or3 = 10, duke@435: cp_0or2 = 11, duke@435: cp_0or2or3 = 12, duke@435: cp_0or1 = 13, duke@435: cp_0or1or3 = 14, duke@435: cp_0or1or2 = 15, duke@435: duke@435: duke@435: // for integers duke@435: duke@435: never = 0, duke@435: equal = 1, duke@435: zero = 1, duke@435: lessEqual = 2, duke@435: less = 3, duke@435: lessEqualUnsigned = 4, duke@435: lessUnsigned = 5, duke@435: carrySet = 5, duke@435: negative = 6, duke@435: overflowSet = 7, duke@435: always = 8, duke@435: notEqual = 9, duke@435: notZero = 9, duke@435: greater = 10, duke@435: greaterEqual = 11, duke@435: greaterUnsigned = 12, duke@435: greaterEqualUnsigned = 13, duke@435: carryClear = 13, duke@435: positive = 14, duke@435: overflowClear = 15 duke@435: }; duke@435: duke@435: enum CC { duke@435: icc = 0, xcc = 2, duke@435: // ptr_cc is the correct condition code for a pointer or intptr_t: duke@435: ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), duke@435: fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 duke@435: }; duke@435: duke@435: enum PrefetchFcn { duke@435: severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 duke@435: }; duke@435: duke@435: public: duke@435: // Helper functions for groups of instructions duke@435: duke@435: enum Predict { pt = 1, pn = 0 }; // pt = predict taken duke@435: duke@435: enum Membar_mask_bits { // page 184, v9 duke@435: StoreStore = 1 << 3, duke@435: LoadStore = 1 << 2, duke@435: StoreLoad = 1 << 1, duke@435: LoadLoad = 1 << 0, duke@435: duke@435: Sync = 1 << 6, duke@435: MemIssue = 1 << 5, duke@435: Lookaside = 1 << 4 duke@435: }; duke@435: duke@435: // test if x is within signed immediate range for nbits duke@435: static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); } duke@435: duke@435: // test if -4096 <= x <= 4095 duke@435: static bool is_simm13(int x) { return is_simm(x, 13); } duke@435: duke@435: enum ASIs { // page 72, v9 duke@435: ASI_PRIMARY = 0x80, duke@435: ASI_PRIMARY_LITTLE = 0x88 duke@435: // add more from book as needed duke@435: }; duke@435: duke@435: protected: duke@435: // helpers duke@435: duke@435: // x is supposed to fit in a field "nbits" wide duke@435: // and be sign-extended. Check the range. duke@435: duke@435: static void assert_signed_range(intptr_t x, int nbits) { duke@435: assert( nbits == 32 duke@435: || -(1 << nbits-1) <= x && x < ( 1 << nbits-1), duke@435: "value out of range"); duke@435: } duke@435: duke@435: static void assert_signed_word_disp_range(intptr_t x, int nbits) { duke@435: assert( (x & 3) == 0, "not word aligned"); duke@435: assert_signed_range(x, nbits + 2); duke@435: } duke@435: duke@435: static void assert_unsigned_const(int x, int nbits) { duke@435: assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); duke@435: } duke@435: duke@435: // fields: note bits numbered from LSB = 0, duke@435: // fields known by inclusive bit range duke@435: duke@435: static int fmask(juint hi_bit, juint lo_bit) { duke@435: assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); duke@435: return (1 << ( hi_bit-lo_bit + 1 )) - 1; duke@435: } duke@435: duke@435: // inverse of u_field duke@435: duke@435: static int inv_u_field(int x, int hi_bit, int lo_bit) { duke@435: juint r = juint(x) >> lo_bit; duke@435: r &= fmask( hi_bit, lo_bit); duke@435: return int(r); duke@435: } duke@435: duke@435: duke@435: // signed version: extract from field and sign-extend duke@435: duke@435: static int inv_s_field(int x, int hi_bit, int lo_bit) { duke@435: int sign_shift = 31 - hi_bit; duke@435: return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); duke@435: } duke@435: duke@435: // given a field that ranges from hi_bit to lo_bit (inclusive, duke@435: // LSB = 0), and an unsigned value for the field, duke@435: // shift it into the field duke@435: duke@435: #ifdef ASSERT duke@435: static int u_field(int x, int hi_bit, int lo_bit) { duke@435: assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, duke@435: "value out of range"); duke@435: int r = x << lo_bit; duke@435: assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); duke@435: return r; duke@435: } duke@435: #else duke@435: // make sure this is inlined as it will reduce code size significantly duke@435: #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) duke@435: #endif duke@435: duke@435: static int inv_op( int x ) { return inv_u_field(x, 31, 30); } duke@435: static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } duke@435: static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } duke@435: static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } duke@435: duke@435: static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } duke@435: duke@435: static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } duke@435: static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } duke@435: static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } duke@435: duke@435: static int op( int x) { return u_field(x, 31, 30); } duke@435: static int rd( Register r) { return u_field(r->encoding(), 29, 25); } duke@435: static int fcn( int x) { return u_field(x, 29, 25); } duke@435: static int op3( int x) { return u_field(x, 24, 19); } duke@435: static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } duke@435: static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } duke@435: static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } duke@435: static int cond( int x) { return u_field(x, 28, 25); } duke@435: static int cond_mov( int x) { return u_field(x, 17, 14); } duke@435: static int rcond( RCondition x) { return u_field(x, 12, 10); } duke@435: static int op2( int x) { return u_field(x, 24, 22); } duke@435: static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } duke@435: static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } duke@435: static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } duke@435: static int imm_asi( int x) { return u_field(x, 12, 5); } duke@435: static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } duke@435: static int opf_low6( int w) { return u_field(w, 10, 5); } duke@435: static int opf_low5( int w) { return u_field(w, 9, 5); } duke@435: static int trapcc( CC cc) { return u_field(cc, 12, 11); } duke@435: static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit duke@435: static int opf( int x) { return u_field(x, 13, 5); } duke@435: duke@435: static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } duke@435: static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } duke@435: duke@435: static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; duke@435: static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; duke@435: static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; duke@435: duke@435: // some float instructions use this encoding on the op3 field duke@435: static int alt_op3(int op, FloatRegisterImpl::Width w) { duke@435: int r; duke@435: switch(w) { duke@435: case FloatRegisterImpl::S: r = op + 0; break; duke@435: case FloatRegisterImpl::D: r = op + 3; break; duke@435: case FloatRegisterImpl::Q: r = op + 2; break; duke@435: default: ShouldNotReachHere(); break; duke@435: } duke@435: return op3(r); duke@435: } duke@435: duke@435: duke@435: // compute inverse of simm duke@435: static int inv_simm(int x, int nbits) { duke@435: return (int)(x << (32 - nbits)) >> (32 - nbits); duke@435: } duke@435: duke@435: static int inv_simm13( int x ) { return inv_simm(x, 13); } duke@435: duke@435: // signed immediate, in low bits, nbits long duke@435: static int simm(int x, int nbits) { duke@435: assert_signed_range(x, nbits); duke@435: return x & (( 1 << nbits ) - 1); duke@435: } duke@435: duke@435: // compute inverse of wdisp16 duke@435: static intptr_t inv_wdisp16(int x, intptr_t pos) { duke@435: int lo = x & (( 1 << 14 ) - 1); duke@435: int hi = (x >> 20) & 3; duke@435: if (hi >= 2) hi |= ~1; duke@435: return (((hi << 14) | lo) << 2) + pos; duke@435: } duke@435: duke@435: // word offset, 14 bits at LSend, 2 bits at B21, B20 duke@435: static int wdisp16(intptr_t x, intptr_t off) { duke@435: intptr_t xx = x - off; duke@435: assert_signed_word_disp_range(xx, 16); duke@435: int r = (xx >> 2) & ((1 << 14) - 1) duke@435: | ( ( (xx>>(2+14)) & 3 ) << 20 ); duke@435: assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); duke@435: return r; duke@435: } duke@435: duke@435: duke@435: // word displacement in low-order nbits bits duke@435: duke@435: static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { duke@435: int pre_sign_extend = x & (( 1 << nbits ) - 1); duke@435: int r = pre_sign_extend >= ( 1 << (nbits-1) ) duke@435: ? pre_sign_extend | ~(( 1 << nbits ) - 1) duke@435: : pre_sign_extend; duke@435: return (r << 2) + pos; duke@435: } duke@435: duke@435: static int wdisp( intptr_t x, intptr_t off, int nbits ) { duke@435: intptr_t xx = x - off; duke@435: assert_signed_word_disp_range(xx, nbits); duke@435: int r = (xx >> 2) & (( 1 << nbits ) - 1); duke@435: assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); duke@435: return r; duke@435: } duke@435: duke@435: duke@435: // Extract the top 32 bits in a 64 bit word duke@435: static int32_t hi32( int64_t x ) { duke@435: int32_t r = int32_t( (uint64_t)x >> 32 ); duke@435: return r; duke@435: } duke@435: duke@435: // given a sethi instruction, extract the constant, left-justified duke@435: static int inv_hi22( int x ) { duke@435: return x << 10; duke@435: } duke@435: duke@435: // create an imm22 field, given a 32-bit left-justified constant duke@435: static int hi22( int x ) { duke@435: int r = int( juint(x) >> 10 ); duke@435: assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); duke@435: return r; duke@435: } duke@435: duke@435: // create a low10 __value__ (not a field) for a given a 32-bit constant duke@435: static int low10( int x ) { duke@435: return x & ((1 << 10) - 1); duke@435: } duke@435: duke@435: // instruction only in v9 duke@435: static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } duke@435: duke@435: // instruction only in v8 duke@435: static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } duke@435: duke@435: // instruction deprecated in v9 duke@435: static void v9_dep() { } // do nothing for now duke@435: duke@435: // some float instructions only exist for single prec. on v8 duke@435: static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } duke@435: duke@435: // v8 has no CC field duke@435: static void v8_no_cc(CC cc) { if (cc) v9_only(); } duke@435: duke@435: protected: duke@435: // Simple delay-slot scheme: duke@435: // In order to check the programmer, the assembler keeps track of deley slots. duke@435: // It forbids CTIs in delay slots (conservative, but should be OK). duke@435: // Also, when putting an instruction into a delay slot, you must say duke@435: // asm->delayed()->add(...), in order to check that you don't omit duke@435: // delay-slot instructions. duke@435: // To implement this, we use a simple FSA duke@435: duke@435: #ifdef ASSERT duke@435: #define CHECK_DELAY duke@435: #endif duke@435: #ifdef CHECK_DELAY duke@435: enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; duke@435: #endif duke@435: duke@435: public: duke@435: // Tells assembler next instruction must NOT be in delay slot. duke@435: // Use at start of multinstruction macros. duke@435: void assert_not_delayed() { duke@435: // This is a separate overloading to avoid creation of string constants duke@435: // in non-asserted code--with some compilers this pollutes the object code. duke@435: #ifdef CHECK_DELAY duke@435: assert_not_delayed("next instruction should not be a delay slot"); duke@435: #endif duke@435: } duke@435: void assert_not_delayed(const char* msg) { duke@435: #ifdef CHECK_DELAY duke@435: assert_msg ( delay_state == no_delay, msg); duke@435: #endif duke@435: } duke@435: duke@435: protected: duke@435: // Delay slot helpers duke@435: // cti is called when emitting control-transfer instruction, duke@435: // BEFORE doing the emitting. duke@435: // Only effective when assertion-checking is enabled. duke@435: void cti() { duke@435: #ifdef CHECK_DELAY duke@435: assert_not_delayed("cti should not be in delay slot"); duke@435: #endif duke@435: } duke@435: duke@435: // called when emitting cti with a delay slot, AFTER emitting duke@435: void has_delay_slot() { duke@435: #ifdef CHECK_DELAY duke@435: assert_not_delayed("just checking"); duke@435: delay_state = at_delay_slot; duke@435: #endif duke@435: } duke@435: duke@435: public: duke@435: // Tells assembler you know that next instruction is delayed duke@435: Assembler* delayed() { duke@435: #ifdef CHECK_DELAY duke@435: assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); duke@435: delay_state = filling_delay_slot; duke@435: #endif duke@435: return this; duke@435: } duke@435: duke@435: void flush() { duke@435: #ifdef CHECK_DELAY duke@435: assert ( delay_state == no_delay, "ending code with a delay slot"); duke@435: #endif duke@435: AbstractAssembler::flush(); duke@435: } duke@435: duke@435: inline void emit_long(int); // shadows AbstractAssembler::emit_long duke@435: inline void emit_data(int x) { emit_long(x); } duke@435: inline void emit_data(int, RelocationHolder const&); duke@435: inline void emit_data(int, relocInfo::relocType rtype); duke@435: // helper for above fcns duke@435: inline void check_delay(); duke@435: duke@435: duke@435: public: duke@435: // instructions, refer to page numbers in the SPARC Architecture Manual, V9 duke@435: duke@435: // pp 135 (addc was addx in v8) duke@435: twisti@1162: inline void add(Register s1, Register s2, Register d ); twisti@1162: inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none); twisti@1162: inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); twisti@1162: inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); twisti@1162: inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); } duke@435: duke@435: void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 136 duke@435: duke@435: inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L); duke@435: duke@435: protected: // use MacroAssembler::br instead duke@435: duke@435: // pp 138 duke@435: duke@435: inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void fb( Condition c, bool a, Label& L ); duke@435: duke@435: // pp 141 duke@435: duke@435: inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); duke@435: duke@435: public: duke@435: duke@435: // pp 144 duke@435: duke@435: inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void br( Condition c, bool a, Label& L ); duke@435: duke@435: // pp 146 duke@435: duke@435: inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); duke@435: duke@435: // pp 121 (V8) duke@435: duke@435: inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void cb( Condition c, bool a, Label& L ); duke@435: duke@435: // pp 149 duke@435: duke@435: inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); duke@435: inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); duke@435: duke@435: // pp 150 duke@435: duke@435: // These instructions compare the contents of s2 with the contents of duke@435: // memory at address in s1. If the values are equal, the contents of memory duke@435: // at address s1 is swapped with the data in d. If the values are not equal, duke@435: // the the contents of memory at s1 is loaded into d, without the swap. duke@435: duke@435: void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } duke@435: void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } duke@435: duke@435: // pp 152 duke@435: duke@435: void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } duke@435: void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } duke@435: void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } duke@435: void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } duke@435: void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 155 duke@435: duke@435: void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); } duke@435: void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); } duke@435: duke@435: // pp 156 duke@435: duke@435: void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } duke@435: void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } duke@435: duke@435: // pp 157 duke@435: duke@435: void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } duke@435: void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } duke@435: duke@435: // pp 159 duke@435: duke@435: void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } duke@435: void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } duke@435: duke@435: // pp 160 duke@435: duke@435: void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } duke@435: duke@435: // pp 161 duke@435: duke@435: void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); } duke@435: void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); } duke@435: duke@435: // pp 162 duke@435: duke@435: void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } duke@435: duke@435: void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } duke@435: duke@435: // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available duke@435: // on v8 to do negation of single, double and quad precision floats. duke@435: duke@435: void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } duke@435: duke@435: void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } duke@435: duke@435: // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available duke@435: // on v8 to do abs operation on single/double/quad precision floats. duke@435: duke@435: void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } duke@435: duke@435: // pp 163 duke@435: duke@435: void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } duke@435: void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } duke@435: void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } duke@435: duke@435: // pp 164 duke@435: duke@435: void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } duke@435: duke@435: // pp 165 duke@435: duke@435: inline void flush( Register s1, Register s2 ); duke@435: inline void flush( Register s1, int simm13a); duke@435: duke@435: // pp 167 duke@435: duke@435: void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); } duke@435: duke@435: // pp 168 duke@435: duke@435: void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); } duke@435: // v8 unimp == illtrap(0) duke@435: duke@435: // pp 169 duke@435: duke@435: void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } duke@435: void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } duke@435: duke@435: // pp 149 (v8) duke@435: duke@435: void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } duke@435: void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } duke@435: duke@435: // pp 170 duke@435: duke@435: void jmpl( Register s1, Register s2, Register d ); duke@435: void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); duke@435: duke@435: // 171 duke@435: twisti@1441: inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); twisti@1162: inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); twisti@1162: inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); twisti@1162: twisti@1162: inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); duke@435: duke@435: duke@435: inline void ldfsr( Register s1, Register s2 ); duke@435: inline void ldfsr( Register s1, int simm13a); duke@435: inline void ldxfsr( Register s1, Register s2 ); duke@435: inline void ldxfsr( Register s1, int simm13a); duke@435: duke@435: // pp 94 (v8) duke@435: duke@435: inline void ldc( Register s1, Register s2, int crd ); duke@435: inline void ldc( Register s1, int simm13a, int crd); duke@435: inline void lddc( Register s1, Register s2, int crd ); duke@435: inline void lddc( Register s1, int simm13a, int crd); duke@435: inline void ldcsr( Register s1, Register s2, int crd ); duke@435: inline void ldcsr( Register s1, int simm13a, int crd); duke@435: duke@435: duke@435: // 173 duke@435: duke@435: void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 175, lduw is ld on v8 duke@435: duke@435: inline void ldsb( Register s1, Register s2, Register d ); duke@435: inline void ldsb( Register s1, int simm13a, Register d); duke@435: inline void ldsh( Register s1, Register s2, Register d ); duke@435: inline void ldsh( Register s1, int simm13a, Register d); duke@435: inline void ldsw( Register s1, Register s2, Register d ); duke@435: inline void ldsw( Register s1, int simm13a, Register d); duke@435: inline void ldub( Register s1, Register s2, Register d ); duke@435: inline void ldub( Register s1, int simm13a, Register d); duke@435: inline void lduh( Register s1, Register s2, Register d ); duke@435: inline void lduh( Register s1, int simm13a, Register d); duke@435: inline void lduw( Register s1, Register s2, Register d ); duke@435: inline void lduw( Register s1, int simm13a, Register d); duke@435: inline void ldx( Register s1, Register s2, Register d ); duke@435: inline void ldx( Register s1, int simm13a, Register d); duke@435: inline void ld( Register s1, Register s2, Register d ); duke@435: inline void ld( Register s1, int simm13a, Register d); duke@435: inline void ldd( Register s1, Register s2, Register d ); duke@435: inline void ldd( Register s1, int simm13a, Register d); duke@435: twisti@1162: #ifdef ASSERT twisti@1162: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@1162: inline void ld( Register s1, ByteSize simm13a, Register d); twisti@1162: #endif twisti@1162: twisti@1162: inline void ldsb(const Address& a, Register d, int offset = 0); twisti@1162: inline void ldsh(const Address& a, Register d, int offset = 0); twisti@1162: inline void ldsw(const Address& a, Register d, int offset = 0); twisti@1162: inline void ldub(const Address& a, Register d, int offset = 0); twisti@1162: inline void lduh(const Address& a, Register d, int offset = 0); twisti@1162: inline void lduw(const Address& a, Register d, int offset = 0); twisti@1162: inline void ldx( const Address& a, Register d, int offset = 0); twisti@1162: inline void ld( const Address& a, Register d, int offset = 0); twisti@1162: inline void ldd( const Address& a, Register d, int offset = 0); duke@435: jrose@1100: inline void ldub( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ldsb( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void lduh( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ldsh( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void lduw( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ldsw( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ldx( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ld( Register s1, RegisterOrConstant s2, Register d ); jrose@1100: inline void ldd( Register s1, RegisterOrConstant s2, Register d ); jrose@1057: duke@435: // pp 177 duke@435: duke@435: void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 179 duke@435: duke@435: inline void ldstub( Register s1, Register s2, Register d ); duke@435: inline void ldstub( Register s1, int simm13a, Register d); duke@435: duke@435: // pp 180 duke@435: duke@435: void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 181 duke@435: duke@435: void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } duke@435: void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 183 duke@435: duke@435: void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } duke@435: duke@435: // pp 185 duke@435: duke@435: void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } duke@435: duke@435: // pp 189 duke@435: duke@435: void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } duke@435: duke@435: // pp 191 duke@435: duke@435: void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } duke@435: void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } duke@435: duke@435: // pp 195 duke@435: duke@435: void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } duke@435: void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } duke@435: duke@435: // pp 196 duke@435: duke@435: void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } duke@435: void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } duke@435: void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 197 duke@435: duke@435: void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 199 duke@435: duke@435: void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } duke@435: void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 201 duke@435: duke@435: void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); } duke@435: duke@435: duke@435: // pp 202 duke@435: duke@435: void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } duke@435: void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } duke@435: duke@435: // pp 203 duke@435: duke@435: void prefetch( Register s1, Register s2, PrefetchFcn f); duke@435: void prefetch( Register s1, int simm13a, PrefetchFcn f); duke@435: void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); duke@435: duke@435: // pp 208 duke@435: duke@435: // not implementing read privileged register duke@435: duke@435: inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } duke@435: inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } duke@435: inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } duke@435: inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! duke@435: inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } duke@435: inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } duke@435: duke@435: // pp 213 duke@435: duke@435: inline void rett( Register s1, Register s2); duke@435: inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); duke@435: duke@435: // pp 214 duke@435: duke@435: void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } ysr@777: void save( Register s1, int simm13a, Register d ) { ysr@777: // make sure frame is at least large enough for the register save area ysr@777: assert(-simm13a >= 16 * wordSize, "frame too small"); ysr@777: emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); ysr@777: } duke@435: duke@435: void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } duke@435: void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 216 duke@435: duke@435: void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); } duke@435: void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); } duke@435: duke@435: // pp 217 duke@435: duke@435: inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); duke@435: // pp 218 duke@435: duke@435: void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } duke@435: void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } duke@435: void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } duke@435: void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } duke@435: void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } duke@435: void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } duke@435: duke@435: void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } duke@435: void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } duke@435: void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } duke@435: void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } duke@435: void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } duke@435: void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } duke@435: duke@435: // pp 220 duke@435: duke@435: void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } duke@435: duke@435: // pp 221 duke@435: duke@435: void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } duke@435: duke@435: // pp 222 duke@435: twisti@1441: inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); twisti@1441: inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); duke@435: inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); duke@435: inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); duke@435: duke@435: inline void stfsr( Register s1, Register s2 ); duke@435: inline void stfsr( Register s1, int simm13a); duke@435: inline void stxfsr( Register s1, Register s2 ); duke@435: inline void stxfsr( Register s1, int simm13a); duke@435: duke@435: // pp 224 duke@435: duke@435: void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // p 226 duke@435: duke@435: inline void stb( Register d, Register s1, Register s2 ); duke@435: inline void stb( Register d, Register s1, int simm13a); duke@435: inline void sth( Register d, Register s1, Register s2 ); duke@435: inline void sth( Register d, Register s1, int simm13a); duke@435: inline void stw( Register d, Register s1, Register s2 ); duke@435: inline void stw( Register d, Register s1, int simm13a); duke@435: inline void st( Register d, Register s1, Register s2 ); duke@435: inline void st( Register d, Register s1, int simm13a); duke@435: inline void stx( Register d, Register s1, Register s2 ); duke@435: inline void stx( Register d, Register s1, int simm13a); duke@435: inline void std( Register d, Register s1, Register s2 ); duke@435: inline void std( Register d, Register s1, int simm13a); duke@435: twisti@1162: #ifdef ASSERT twisti@1162: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@1162: inline void st( Register d, Register s1, ByteSize simm13a); twisti@1162: #endif twisti@1162: duke@435: inline void stb( Register d, const Address& a, int offset = 0 ); duke@435: inline void sth( Register d, const Address& a, int offset = 0 ); duke@435: inline void stw( Register d, const Address& a, int offset = 0 ); duke@435: inline void stx( Register d, const Address& a, int offset = 0 ); duke@435: inline void st( Register d, const Address& a, int offset = 0 ); duke@435: inline void std( Register d, const Address& a, int offset = 0 ); duke@435: jrose@1100: inline void stb( Register d, Register s1, RegisterOrConstant s2 ); jrose@1100: inline void sth( Register d, Register s1, RegisterOrConstant s2 ); jrose@1100: inline void stw( Register d, Register s1, RegisterOrConstant s2 ); jrose@1100: inline void stx( Register d, Register s1, RegisterOrConstant s2 ); jrose@1100: inline void std( Register d, Register s1, RegisterOrConstant s2 ); jrose@1100: inline void st( Register d, Register s1, RegisterOrConstant s2 ); jrose@1057: duke@435: // pp 177 duke@435: duke@435: void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 97 (v8) duke@435: duke@435: inline void stc( int crd, Register s1, Register s2 ); duke@435: inline void stc( int crd, Register s1, int simm13a); duke@435: inline void stdc( int crd, Register s1, Register s2 ); duke@435: inline void stdc( int crd, Register s1, int simm13a); duke@435: inline void stcsr( int crd, Register s1, Register s2 ); duke@435: inline void stcsr( int crd, Register s1, int simm13a); duke@435: inline void stdcq( int crd, Register s1, Register s2 ); duke@435: inline void stdcq( int crd, Register s1, int simm13a); duke@435: duke@435: // pp 230 duke@435: duke@435: void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } duke@435: void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 231 duke@435: duke@435: inline void swap( Register s1, Register s2, Register d ); duke@435: inline void swap( Register s1, int simm13a, Register d); duke@435: inline void swap( Address& a, Register d, int offset = 0 ); duke@435: duke@435: // pp 232 duke@435: duke@435: void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } duke@435: void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 234, note op in book is wrong, see pp 268 duke@435: duke@435: void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } duke@435: void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 235 duke@435: duke@435: void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } duke@435: void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } duke@435: void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } duke@435: duke@435: // pp 237 duke@435: duke@435: void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } duke@435: void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } duke@435: // simple uncond. trap duke@435: void trap( int trapa ) { trap( always, icc, G0, trapa ); } duke@435: duke@435: // pp 239 omit write priv register for now duke@435: duke@435: inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } duke@435: inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } duke@435: inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | duke@435: rs1(s) | duke@435: op3(wrreg_op3) | duke@435: u_field(2, 29, 25) | duke@435: u_field(1, 13, 13) | duke@435: simm(simm13a, 13)); } duke@435: inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } duke@435: inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } duke@435: ysr@777: // For a given register condition, return the appropriate condition code ysr@777: // Condition (the one you would use to get the same effect after "tst" on ysr@777: // the target register.) ysr@777: Assembler::Condition reg_cond_to_cc_cond(RCondition in); ysr@777: duke@435: duke@435: // Creation duke@435: Assembler(CodeBuffer* code) : AbstractAssembler(code) { duke@435: #ifdef CHECK_DELAY duke@435: delay_state = no_delay; duke@435: #endif duke@435: } duke@435: duke@435: // Testing duke@435: #ifndef PRODUCT duke@435: void test_v9(); duke@435: void test_v8_onlys(); duke@435: #endif duke@435: }; duke@435: duke@435: duke@435: class RegistersForDebugging : public StackObj { duke@435: public: duke@435: intptr_t i[8], l[8], o[8], g[8]; duke@435: float f[32]; duke@435: double d[32]; duke@435: duke@435: void print(outputStream* s); duke@435: duke@435: static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } duke@435: static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } duke@435: static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } duke@435: static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } duke@435: static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } duke@435: static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } duke@435: duke@435: // gen asm code to save regs duke@435: static void save_registers(MacroAssembler* a); duke@435: duke@435: // restore global registers in case C code disturbed them duke@435: static void restore_registers(MacroAssembler* a, Register r); ysr@777: ysr@777: duke@435: }; duke@435: duke@435: duke@435: // MacroAssembler extends Assembler by a few frequently used macros. duke@435: // duke@435: // Most of the standard SPARC synthetic ops are defined here. duke@435: // Instructions for which a 'better' code sequence exists depending duke@435: // on arguments should also go in here. duke@435: duke@435: #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) duke@435: #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) twisti@1162: #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) twisti@1162: #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) duke@435: duke@435: duke@435: class MacroAssembler: public Assembler { duke@435: protected: duke@435: // Support for VM calls duke@435: // This is the base routine called by the different versions of call_VM_leaf. The interpreter duke@435: // may customize this version by overriding it for its purposes (e.g., to save/restore duke@435: // additional registers when doing a VM call). duke@435: #ifdef CC_INTERP duke@435: #define VIRTUAL duke@435: #else duke@435: #define VIRTUAL virtual duke@435: #endif duke@435: duke@435: VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); duke@435: duke@435: // duke@435: // It is imperative that all calls into the VM are handled via the call_VM macros. duke@435: // They make sure that the stack linkage is setup correctly. call_VM's correspond duke@435: // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. duke@435: // duke@435: // This is the base routine called by the different versions of call_VM. The interpreter duke@435: // may customize this version by overriding it for its purposes (e.g., to save/restore duke@435: // additional registers when doing a VM call). duke@435: // duke@435: // A non-volatile java_thread_cache register should be specified so duke@435: // that the G2_thread value can be preserved across the call. duke@435: // (If java_thread_cache is noreg, then a slow get_thread call duke@435: // will re-initialize the G2_thread.) call_VM_base returns the register that contains the duke@435: // thread. duke@435: // duke@435: // If no last_java_sp is specified (noreg) than SP will be used instead. duke@435: duke@435: virtual void call_VM_base( duke@435: Register oop_result, // where an oop-result ends up if any; use noreg otherwise duke@435: Register java_thread_cache, // the thread if computed before ; use noreg otherwise duke@435: Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise duke@435: address entry_point, // the entry point duke@435: int number_of_arguments, // the number of arguments (w/o thread) to pop after call duke@435: bool check_exception=true // flag which indicates if exception should be checked duke@435: ); duke@435: duke@435: // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. duke@435: // The implementation is only non-empty for the InterpreterMacroAssembler, duke@435: // as only the interpreter handles and ForceEarlyReturn PopFrame requests. duke@435: virtual void check_and_handle_popframe(Register scratch_reg); duke@435: virtual void check_and_handle_earlyret(Register scratch_reg); duke@435: duke@435: public: duke@435: MacroAssembler(CodeBuffer* code) : Assembler(code) {} duke@435: duke@435: // Support for NULL-checks duke@435: // duke@435: // Generates code that causes a NULL OS exception if the content of reg is NULL. duke@435: // If the accessed location is M[reg + offset] and the offset is known, provide the duke@435: // offset. No explicit code generation is needed if the offset is within a certain duke@435: // range (0 <= offset <= page_size). duke@435: // duke@435: // %%%%%% Currently not done for SPARC duke@435: duke@435: void null_check(Register reg, int offset = -1); duke@435: static bool needs_explicit_null_check(intptr_t offset); duke@435: duke@435: // support for delayed instructions duke@435: MacroAssembler* delayed() { Assembler::delayed(); return this; } duke@435: duke@435: // branches that use right instruction for v8 vs. v9 duke@435: inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void br( Condition c, bool a, Predict p, Label& L ); duke@435: inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void fb( Condition c, bool a, Predict p, Label& L ); duke@435: duke@435: // compares register with zero and branches (V9 and V8 instructions) duke@435: void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); duke@435: // Compares a pointer register with zero and branches on (not)null. duke@435: // Does a test & branch on 32-bit systems and a register-branch on 64-bit. duke@435: void br_null ( Register s1, bool a, Predict p, Label& L ); duke@435: void br_notnull( Register s1, bool a, Predict p, Label& L ); duke@435: ysr@777: // These versions will do the most efficient thing on v8 and v9. Perhaps ysr@777: // this is what the routine above was meant to do, but it didn't (and ysr@777: // didn't cover both target address kinds.) ysr@777: void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); ysr@777: void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L); ysr@777: duke@435: inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); duke@435: duke@435: // Branch that tests xcc in LP64 and icc in !LP64 duke@435: inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void brx( Condition c, bool a, Predict p, Label& L ); duke@435: duke@435: // unconditional short branch duke@435: inline void ba( bool a, Label& L ); duke@435: duke@435: // Branch that tests fp condition codes duke@435: inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); duke@435: duke@435: // get PC the best way duke@435: inline int get_pc( Register d ); duke@435: duke@435: // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) duke@435: inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } duke@435: inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } duke@435: duke@435: inline void jmp( Register s1, Register s2 ); duke@435: inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); duke@435: duke@435: inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); duke@435: inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); duke@435: inline void callr( Register s1, Register s2 ); duke@435: inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); duke@435: duke@435: // Emits nothing on V8 duke@435: inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); duke@435: inline void iprefetch( Label& L); duke@435: duke@435: inline void tst( Register s ) { orcc( G0, s, G0 ); } duke@435: duke@435: #ifdef PRODUCT duke@435: inline void ret( bool trace = TraceJumps ) { if (trace) { duke@435: mov(I7, O7); // traceable register duke@435: JMP(O7, 2 * BytesPerInstWord); duke@435: } else { duke@435: jmpl( I7, 2 * BytesPerInstWord, G0 ); duke@435: } duke@435: } duke@435: duke@435: inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); duke@435: else jmpl( O7, 2 * BytesPerInstWord, G0 ); } duke@435: #else duke@435: void ret( bool trace = TraceJumps ); duke@435: void retl( bool trace = TraceJumps ); duke@435: #endif /* PRODUCT */ duke@435: duke@435: // Required platform-specific helpers for Label::patch_instructions. duke@435: // They _shadow_ the declarations in AbstractAssembler, which are undefined. duke@435: void pd_patch_instruction(address branch, address target); duke@435: #ifndef PRODUCT duke@435: static void pd_print_patched_instruction(address branch); duke@435: #endif duke@435: duke@435: // sethi Macro handles optimizations and relocations twisti@1162: private: twisti@1162: void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); twisti@1162: public: twisti@1162: void sethi(const AddressLiteral& addrlit, Register d); twisti@1162: void patchable_sethi(const AddressLiteral& addrlit, Register d); duke@435: duke@435: // compute the size of a sethi/set duke@435: static int size_of_sethi( address a, bool worst_case = false ); duke@435: static int worst_case_size_of_set(); duke@435: duke@435: // set may be either setsw or setuw (high 32 bits may be zero or sign) twisti@1162: private: twisti@1162: void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); twisti@1162: public: twisti@1162: void set(const AddressLiteral& addrlit, Register d); twisti@1162: void set(intptr_t value, Register d); twisti@1162: void set(address addr, Register d, RelocationHolder const& rspec); twisti@1162: void patchable_set(const AddressLiteral& addrlit, Register d); twisti@1162: void patchable_set(intptr_t value, Register d); twisti@1162: void set64(jlong value, Register d, Register tmp); duke@435: duke@435: // sign-extend 32 to 64 duke@435: inline void signx( Register s, Register d ) { sra( s, G0, d); } duke@435: inline void signx( Register d ) { sra( d, G0, d); } duke@435: duke@435: inline void not1( Register s, Register d ) { xnor( s, G0, d ); } duke@435: inline void not1( Register d ) { xnor( d, G0, d ); } duke@435: duke@435: inline void neg( Register s, Register d ) { sub( G0, s, d ); } duke@435: inline void neg( Register d ) { sub( G0, d, d ); } duke@435: duke@435: inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } duke@435: inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } duke@435: // Functions for isolating 64 bit atomic swaps for LP64 duke@435: // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's duke@435: inline void cas_ptr( Register s1, Register s2, Register d) { duke@435: #ifdef _LP64 duke@435: casx( s1, s2, d ); duke@435: #else duke@435: cas( s1, s2, d ); duke@435: #endif duke@435: } duke@435: duke@435: // Functions for isolating 64 bit shifts for LP64 duke@435: inline void sll_ptr( Register s1, Register s2, Register d ); duke@435: inline void sll_ptr( Register s1, int imm6a, Register d ); jrose@1100: inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); duke@435: inline void srl_ptr( Register s1, Register s2, Register d ); duke@435: inline void srl_ptr( Register s1, int imm6a, Register d ); duke@435: duke@435: // little-endian duke@435: inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } duke@435: inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } duke@435: duke@435: inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } duke@435: inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } duke@435: duke@435: inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } duke@435: inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } duke@435: duke@435: inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } duke@435: inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } duke@435: duke@435: inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } duke@435: inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } duke@435: duke@435: inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } duke@435: inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } duke@435: duke@435: inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } duke@435: inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } duke@435: duke@435: inline void clr( Register d ) { or3( G0, G0, d ); } duke@435: duke@435: inline void clrb( Register s1, Register s2); duke@435: inline void clrh( Register s1, Register s2); duke@435: inline void clr( Register s1, Register s2); duke@435: inline void clrx( Register s1, Register s2); duke@435: duke@435: inline void clrb( Register s1, int simm13a); duke@435: inline void clrh( Register s1, int simm13a); duke@435: inline void clr( Register s1, int simm13a); duke@435: inline void clrx( Register s1, int simm13a); duke@435: duke@435: // copy & clear upper word duke@435: inline void clruw( Register s, Register d ) { srl( s, G0, d); } duke@435: // clear upper word duke@435: inline void clruwu( Register d ) { srl( d, G0, d); } duke@435: duke@435: // membar psuedo instruction. takes into account target memory model. duke@435: inline void membar( Assembler::Membar_mask_bits const7a ); duke@435: duke@435: // returns if membar generates anything. duke@435: inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); duke@435: duke@435: // mov pseudo instructions duke@435: inline void mov( Register s, Register d) { duke@435: if ( s != d ) or3( G0, s, d); duke@435: else assert_not_delayed(); // Put something useful in the delay slot! duke@435: } duke@435: duke@435: inline void mov_or_nop( Register s, Register d) { duke@435: if ( s != d ) or3( G0, s, d); duke@435: else nop(); duke@435: } duke@435: duke@435: inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } duke@435: duke@435: // address pseudos: make these names unlike instruction names to avoid confusion duke@435: inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); twisti@1162: inline void load_contents(AddressLiteral& addrlit, Register d, int offset = 0); twisti@1162: inline void load_ptr_contents(AddressLiteral& addrlit, Register d, int offset = 0); twisti@1162: inline void store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0); twisti@1162: inline void store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0); twisti@1162: inline void jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset = 0); twisti@1162: inline void jump_to(AddressLiteral& addrlit, Register temp, int offset = 0); twisti@1162: inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); duke@435: duke@435: // ring buffer traceable jumps duke@435: duke@435: void jmp2( Register r1, Register r2, const char* file, int line ); duke@435: void jmp ( Register r1, int offset, const char* file, int line ); duke@435: twisti@1162: void jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); twisti@1162: void jump (AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); duke@435: duke@435: duke@435: // argument pseudos: duke@435: duke@435: inline void load_argument( Argument& a, Register d ); duke@435: inline void store_argument( Register s, Argument& a ); duke@435: inline void store_ptr_argument( Register s, Argument& a ); duke@435: inline void store_float_argument( FloatRegister s, Argument& a ); duke@435: inline void store_double_argument( FloatRegister s, Argument& a ); duke@435: inline void store_long_argument( Register s, Argument& a ); duke@435: duke@435: // handy macros: duke@435: duke@435: inline void round_to( Register r, int modulus ) { duke@435: assert_not_delayed(); duke@435: inc( r, modulus - 1 ); duke@435: and3( r, -modulus, r ); duke@435: } duke@435: duke@435: // -------------------------------------------------- duke@435: duke@435: // Functions for isolating 64 bit loads for LP64 duke@435: // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's duke@435: // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's twisti@1162: inline void ld_ptr(Register s1, Register s2, Register d); twisti@1162: inline void ld_ptr(Register s1, int simm13a, Register d); twisti@1162: inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); twisti@1162: inline void ld_ptr(const Address& a, Register d, int offset = 0); twisti@1162: inline void st_ptr(Register d, Register s1, Register s2); twisti@1162: inline void st_ptr(Register d, Register s1, int simm13a); twisti@1162: inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); twisti@1162: inline void st_ptr(Register d, const Address& a, int offset = 0); twisti@1162: twisti@1162: #ifdef ASSERT twisti@1162: // ByteSize is only a class when ASSERT is defined, otherwise it's an int. twisti@1162: inline void ld_ptr(Register s1, ByteSize simm13a, Register d); twisti@1162: inline void st_ptr(Register d, Register s1, ByteSize simm13a); twisti@1162: #endif duke@435: duke@435: // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's duke@435: // st_long will perform st for 32 bit VM's and stx for 64 bit VM's twisti@1162: inline void ld_long(Register s1, Register s2, Register d); twisti@1162: inline void ld_long(Register s1, int simm13a, Register d); twisti@1162: inline void ld_long(Register s1, RegisterOrConstant s2, Register d); twisti@1162: inline void ld_long(const Address& a, Register d, int offset = 0); twisti@1162: inline void st_long(Register d, Register s1, Register s2); twisti@1162: inline void st_long(Register d, Register s1, int simm13a); twisti@1162: inline void st_long(Register d, Register s1, RegisterOrConstant s2); twisti@1162: inline void st_long(Register d, const Address& a, int offset = 0); jrose@1057: jrose@1058: // Helpers for address formation. jrose@1058: // They update the dest in place, whether it is a register or constant. jrose@1058: // They emit no code at all if src is a constant zero. jrose@1058: // If dest is a constant and src is a register, the temp argument jrose@1058: // is required, and becomes the result. jrose@1058: // If dest is a register and src is a non-simm13 constant, jrose@1058: // the temp argument is required, and is used to materialize the constant. jrose@1100: void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src, jrose@1058: Register temp = noreg ); jrose@1100: void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src, jrose@1058: Register temp = noreg ); twisti@1441: twisti@1441: RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) { twisti@1441: guarantee(Rtemp != noreg, "constant offset overflow"); twisti@1441: if (is_simm13(roc.constant_or_zero())) twisti@1441: return roc; // register or short constant twisti@1441: set(roc.as_constant(), Rtemp); twisti@1441: return RegisterOrConstant(Rtemp); jrose@1058: } jrose@1058: duke@435: // -------------------------------------------------- duke@435: duke@435: public: duke@435: // traps as per trap.h (SPARC ABI?) duke@435: duke@435: void breakpoint_trap(); duke@435: void breakpoint_trap(Condition c, CC cc = icc); duke@435: void flush_windows_trap(); duke@435: void clean_windows_trap(); duke@435: void get_psr_trap(); duke@435: void set_psr_trap(); duke@435: duke@435: // V8/V9 flush_windows duke@435: void flush_windows(); duke@435: duke@435: // Support for serializing memory accesses between threads duke@435: void serialize_memory(Register thread, Register tmp1, Register tmp2); duke@435: duke@435: // Stack frame creation/removal duke@435: void enter(); duke@435: void leave(); duke@435: duke@435: // V8/V9 integer multiply duke@435: void mult(Register s1, Register s2, Register d); duke@435: void mult(Register s1, int simm13a, Register d); duke@435: duke@435: // V8/V9 read and write of condition codes. duke@435: void read_ccr(Register d); duke@435: void write_ccr(Register s); duke@435: duke@435: // Manipulation of C++ bools duke@435: // These are idioms to flag the need for care with accessing bools but on duke@435: // this platform we assume byte size duke@435: twisti@1162: inline void stbool(Register d, const Address& a) { stb(d, a); } twisti@1162: inline void ldbool(const Address& a, Register d) { ldsb(a, d); } duke@435: inline void tstbool( Register s ) { tst(s); } duke@435: inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } duke@435: coleenp@548: // klass oop manipulations if compressed kvn@599: void load_klass(Register src_oop, Register klass); kvn@599: void store_klass(Register klass, Register dst_oop); coleenp@602: void store_klass_gap(Register s, Register dst_oop); coleenp@548: coleenp@548: // oop manipulations twisti@1162: void load_heap_oop(const Address& s, Register d); coleenp@548: void load_heap_oop(Register s1, Register s2, Register d); coleenp@548: void load_heap_oop(Register s1, int simm13a, Register d); coleenp@548: void store_heap_oop(Register d, Register s1, Register s2); coleenp@548: void store_heap_oop(Register d, Register s1, int simm13a); coleenp@548: void store_heap_oop(Register d, const Address& a, int offset = 0); coleenp@548: coleenp@548: void encode_heap_oop(Register src, Register dst); coleenp@548: void encode_heap_oop(Register r) { coleenp@548: encode_heap_oop(r, r); coleenp@548: } coleenp@548: void decode_heap_oop(Register src, Register dst); coleenp@548: void decode_heap_oop(Register r) { coleenp@548: decode_heap_oop(r, r); coleenp@548: } coleenp@548: void encode_heap_oop_not_null(Register r); coleenp@548: void decode_heap_oop_not_null(Register r); kvn@559: void encode_heap_oop_not_null(Register src, Register dst); kvn@559: void decode_heap_oop_not_null(Register src, Register dst); coleenp@548: duke@435: // Support for managing the JavaThread pointer (i.e.; the reference to duke@435: // thread-local information). duke@435: void get_thread(); // load G2_thread duke@435: void verify_thread(); // verify G2_thread contents duke@435: void save_thread (const Register threache); // save to cache duke@435: void restore_thread(const Register thread_cache); // restore from cache duke@435: duke@435: // Support for last Java frame (but use call_VM instead where possible) duke@435: void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); duke@435: void reset_last_Java_frame(void); duke@435: duke@435: // Call into the VM. duke@435: // Passes the thread pointer (in O0) as a prepended argument. duke@435: // Makes sure oop return values are visible to the GC. duke@435: void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); duke@435: duke@435: // these overloadings are not presently used on SPARC: duke@435: void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); duke@435: void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); duke@435: duke@435: void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); duke@435: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); duke@435: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); duke@435: void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); duke@435: duke@435: void get_vm_result (Register oop_result); duke@435: void get_vm_result_2(Register oop_result); duke@435: duke@435: // vm result is currently getting hijacked to for oop preservation duke@435: void set_vm_result(Register oop_result); duke@435: duke@435: // if call_VM_base was called with check_exceptions=false, then call duke@435: // check_and_forward_exception to handle exceptions when it is safe duke@435: void check_and_forward_exception(Register scratch_reg); duke@435: duke@435: private: duke@435: // For V8 duke@435: void read_ccr_trap(Register ccr_save); duke@435: void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); duke@435: duke@435: #ifdef ASSERT duke@435: // For V8 debugging. Uses V8 instruction sequence and checks duke@435: // result with V9 insturctions rdccr and wrccr. duke@435: // Uses Gscatch and Gscatch2 duke@435: void read_ccr_v8_assert(Register ccr_save); duke@435: void write_ccr_v8_assert(Register ccr_save); duke@435: #endif // ASSERT duke@435: duke@435: public: ysr@777: ysr@777: // Write to card table for - register is destroyed afterwards. ysr@777: void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); ysr@777: ysr@777: void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); ysr@777: ysr@777: #ifndef SERIALGC ysr@777: // Array store and offset ysr@777: void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs); ysr@777: ysr@777: void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); ysr@777: ysr@777: // May do filtering, depending on the boolean arguments. ysr@777: void g1_card_table_write(jbyte* byte_map_base, ysr@777: Register tmp, Register obj, Register new_val, ysr@777: bool region_filter, bool null_filter); ysr@777: #endif // SERIALGC duke@435: duke@435: // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack duke@435: void push_fTOS(); duke@435: duke@435: // pops double TOS element from CPU stack and pushes on FPU stack duke@435: void pop_fTOS(); duke@435: duke@435: void empty_FPU_stack(); duke@435: duke@435: void push_IU_state(); duke@435: void pop_IU_state(); duke@435: duke@435: void push_FPU_state(); duke@435: void pop_FPU_state(); duke@435: duke@435: void push_CPU_state(); duke@435: void pop_CPU_state(); duke@435: coleenp@548: // if heap base register is used - reinit it with the correct value coleenp@548: void reinit_heapbase(); coleenp@548: duke@435: // Debugging duke@435: void _verify_oop(Register reg, const char * msg, const char * file, int line); duke@435: void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); duke@435: duke@435: #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) duke@435: #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) duke@435: duke@435: // only if +VerifyOops duke@435: void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); duke@435: // only if +VerifyFPU duke@435: void stop(const char* msg); // prints msg, dumps registers and stops execution duke@435: void warn(const char* msg); // prints msg, but don't stop duke@435: void untested(const char* what = ""); duke@435: void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); } duke@435: void should_not_reach_here() { stop("should not reach here"); } duke@435: void print_CPU_state(); duke@435: duke@435: // oops in code twisti@1162: AddressLiteral allocate_oop_address(jobject obj); // allocate_index twisti@1162: AddressLiteral constant_oop_address(jobject obj); // find_index twisti@1162: inline void set_oop (jobject obj, Register d); // uses allocate_oop_address twisti@1162: inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address twisti@1162: inline void set_oop (AddressLiteral& obj_addr, Register d); // same as load_address duke@435: kvn@599: void set_narrow_oop( jobject obj, Register d ); kvn@599: duke@435: // nop padding duke@435: void align(int modulus); duke@435: duke@435: // declare a safepoint duke@435: void safepoint(); duke@435: duke@435: // factor out part of stop into subroutine to save space duke@435: void stop_subroutine(); duke@435: // factor out part of verify_oop into subroutine to save space duke@435: void verify_oop_subroutine(); duke@435: duke@435: // side-door communication with signalHandler in os_solaris.cpp duke@435: static address _verify_oop_implicit_branch[3]; duke@435: duke@435: #ifndef PRODUCT duke@435: static void test(); duke@435: #endif duke@435: duke@435: // convert an incoming arglist to varargs format; put the pointer in d duke@435: void set_varargs( Argument a, Register d ); duke@435: duke@435: int total_frame_size_in_bytes(int extraWords); duke@435: duke@435: // used when extraWords known statically duke@435: void save_frame(int extraWords); duke@435: void save_frame_c1(int size_in_bytes); duke@435: // make a frame, and simultaneously pass up one or two register value duke@435: // into the new register window duke@435: void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); duke@435: duke@435: // give no. (outgoing) params, calc # of words will need on frame duke@435: void calc_mem_param_words(Register Rparam_words, Register Rresult); duke@435: duke@435: // used to calculate frame size dynamically duke@435: // result is in bytes and must be negated for save inst duke@435: void calc_frame_size(Register extraWords, Register resultReg); duke@435: duke@435: // calc and also save duke@435: void calc_frame_size_and_save(Register extraWords, Register resultReg); duke@435: duke@435: static void debug(char* msg, RegistersForDebugging* outWindow); duke@435: duke@435: // implementations of bytecodes used by both interpreter and compiler duke@435: duke@435: void lcmp( Register Ra_hi, Register Ra_low, duke@435: Register Rb_hi, Register Rb_low, duke@435: Register Rresult); duke@435: duke@435: void lneg( Register Rhi, Register Rlow ); duke@435: duke@435: void lshl( Register Rin_high, Register Rin_low, Register Rcount, duke@435: Register Rout_high, Register Rout_low, Register Rtemp ); duke@435: duke@435: void lshr( Register Rin_high, Register Rin_low, Register Rcount, duke@435: Register Rout_high, Register Rout_low, Register Rtemp ); duke@435: duke@435: void lushr( Register Rin_high, Register Rin_low, Register Rcount, duke@435: Register Rout_high, Register Rout_low, Register Rtemp ); duke@435: duke@435: #ifdef _LP64 duke@435: void lcmp( Register Ra, Register Rb, Register Rresult); duke@435: #endif duke@435: duke@435: void float_cmp( bool is_float, int unordered_result, duke@435: FloatRegister Fa, FloatRegister Fb, duke@435: Register Rresult); duke@435: duke@435: void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); duke@435: void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } duke@435: void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); duke@435: void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); duke@435: duke@435: void save_all_globals_into_locals(); duke@435: void restore_globals_from_locals(); duke@435: duke@435: void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, duke@435: address lock_addr=0, bool use_call_vm=false); duke@435: void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, duke@435: address lock_addr=0, bool use_call_vm=false); duke@435: void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; duke@435: duke@435: // These set the icc condition code to equal if the lock succeeded duke@435: // and notEqual if it failed and requires a slow case kvn@855: void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, kvn@855: Register Rscratch, kvn@855: BiasedLockingCounters* counters = NULL, kvn@855: bool try_bias = UseBiasedLocking); kvn@855: void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, kvn@855: Register Rscratch, kvn@855: bool try_bias = UseBiasedLocking); duke@435: duke@435: // Biased locking support duke@435: // Upon entry, lock_reg must point to the lock record on the stack, duke@435: // obj_reg must contain the target object, and mark_reg must contain duke@435: // the target object's header. duke@435: // Destroys mark_reg if an attempt is made to bias an anonymously duke@435: // biased lock. In this case a failure will go either to the slow duke@435: // case or fall through with the notEqual condition code set with duke@435: // the expectation that the slow case in the runtime will be called. duke@435: // In the fall-through case where the CAS-based lock is done, duke@435: // mark_reg is not destroyed. duke@435: void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, duke@435: Label& done, Label* slow_case = NULL, duke@435: BiasedLockingCounters* counters = NULL); duke@435: // Upon entry, the base register of mark_addr must contain the oop. duke@435: // Destroys temp_reg. duke@435: duke@435: // If allow_delay_slot_filling is set to true, the next instruction duke@435: // emitted after this one will go in an annulled delay slot if the duke@435: // biased locking exit case failed. duke@435: void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); duke@435: duke@435: // allocation duke@435: void eden_allocate( duke@435: Register obj, // result: pointer to object after successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at compile time duke@435: Register t1, // temp register duke@435: Register t2, // temp register duke@435: Label& slow_case // continuation point if fast allocation fails duke@435: ); duke@435: void tlab_allocate( duke@435: Register obj, // result: pointer to object after successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at compile time duke@435: Register t1, // temp register duke@435: Label& slow_case // continuation point if fast allocation fails duke@435: ); duke@435: void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); duke@435: jrose@1058: // interface method calling jrose@1058: void lookup_interface_method(Register recv_klass, jrose@1058: Register intf_klass, jrose@1100: RegisterOrConstant itable_index, jrose@1058: Register method_result, jrose@1058: Register temp_reg, Register temp2_reg, jrose@1058: Label& no_such_interface); jrose@1058: jrose@1079: // Test sub_klass against super_klass, with fast and slow paths. jrose@1079: jrose@1079: // The fast path produces a tri-state answer: yes / no / maybe-slow. jrose@1079: // One of the three labels can be NULL, meaning take the fall-through. jrose@1079: // If super_check_offset is -1, the value is loaded up from super_klass. jrose@1079: // No registers are killed, except temp_reg and temp2_reg. jrose@1079: // If super_check_offset is not -1, temp2_reg is not used and can be noreg. jrose@1079: void check_klass_subtype_fast_path(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Register temp2_reg, jrose@1079: Label* L_success, jrose@1079: Label* L_failure, jrose@1079: Label* L_slow_path, jrose@1100: RegisterOrConstant super_check_offset = RegisterOrConstant(-1), jrose@1079: Register instanceof_hack = noreg); jrose@1079: jrose@1079: // The rest of the type check; must be wired to a corresponding fast path. jrose@1079: // It does not repeat the fast path logic, so don't use it standalone. jrose@1079: // The temp_reg can be noreg, if no temps are available. jrose@1079: // It can also be sub_klass or super_klass, meaning it's OK to kill that one. jrose@1079: // Updates the sub's secondary super cache as necessary. jrose@1079: void check_klass_subtype_slow_path(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Register temp2_reg, jrose@1079: Register temp3_reg, jrose@1079: Register temp4_reg, jrose@1079: Label* L_success, jrose@1079: Label* L_failure); jrose@1079: jrose@1079: // Simplified, combined version, good for typical uses. jrose@1079: // Falls through on failure. jrose@1079: void check_klass_subtype(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Register temp2_reg, jrose@1079: Label& L_success); jrose@1079: jrose@1145: // method handles (JSR 292) jrose@1145: void check_method_handle_type(Register mtype_reg, Register mh_reg, jrose@1145: Register temp_reg, jrose@1145: Label& wrong_method_type); jrose@1145: void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); jrose@1145: // offset relative to Gargs of argument at tos[arg_slot]. jrose@1145: // (arg_slot == 0 means the last argument, not the first). jrose@1145: RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, jrose@1145: int extra_slot_offset = 0); jrose@1145: jrose@1079: duke@435: // Stack overflow checking duke@435: duke@435: // Note: this clobbers G3_scratch duke@435: void bang_stack_with_offset(int offset) { duke@435: // stack grows down, caller passes positive offset duke@435: assert(offset > 0, "must bang with negative offset"); duke@435: set((-offset)+STACK_BIAS, G3_scratch); duke@435: st(G0, SP, G3_scratch); duke@435: } duke@435: duke@435: // Writes to stack successive pages until offset reached to check for duke@435: // stack overflow + shadow pages. Clobbers tsp and scratch registers. duke@435: void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); duke@435: jrose@1100: virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); jrose@1057: duke@435: void verify_tlab(); duke@435: duke@435: Condition negate_condition(Condition cond); duke@435: duke@435: // Helper functions for statistics gathering. duke@435: // Conditionally (non-atomically) increments passed counter address, preserving condition codes. duke@435: void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); duke@435: // Unconditional increment. twisti@1162: void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); twisti@1162: void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); duke@435: kvn@1421: // Compare char[] arrays aligned to 4 bytes. kvn@1421: void char_arrays_equals(Register ary1, Register ary2, kvn@1421: Register limit, Register result, kvn@1421: Register chr1, Register chr2, Label& Ldone); kvn@1421: duke@435: #undef VIRTUAL duke@435: duke@435: }; duke@435: duke@435: /** duke@435: * class SkipIfEqual: duke@435: * duke@435: * Instantiating this class will result in assembly code being output that will duke@435: * jump around any code emitted between the creation of the instance and it's duke@435: * automatic destruction at the end of a scope block, depending on the value of duke@435: * the flag passed to the constructor, which will be checked at run-time. duke@435: */ duke@435: class SkipIfEqual : public StackObj { duke@435: private: duke@435: MacroAssembler* _masm; duke@435: Label _label; duke@435: duke@435: public: duke@435: // 'temp' is a temp register that this object can use (and trash) duke@435: SkipIfEqual(MacroAssembler*, Register temp, duke@435: const bool* flag_addr, Assembler::Condition condition); duke@435: ~SkipIfEqual(); duke@435: }; duke@435: duke@435: #ifdef ASSERT duke@435: // On RISC, there's no benefit to verifying instruction boundaries. duke@435: inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } duke@435: #endif