duke@435: /* zgu@4492: * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * trims@1907: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA trims@1907: * or visit www.oracle.com if you need additional information or have any trims@1907: * questions. duke@435: * duke@435: */ duke@435: stefank@2314: #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP stefank@2314: #define CPU_X86_VM_ASSEMBLER_X86_HPP stefank@2314: twisti@4318: #include "asm/register.hpp" twisti@4318: duke@435: class BiasedLockingCounters; duke@435: duke@435: // Contains all the definitions needed for x86 assembly code generation. duke@435: duke@435: // Calling convention duke@435: class Argument VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum { duke@435: #ifdef _LP64 duke@435: #ifdef _WIN64 duke@435: n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) duke@435: #else duke@435: n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) duke@435: #endif // _WIN64 duke@435: n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... duke@435: n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... duke@435: #else duke@435: n_register_parameters = 0 // 0 registers used to pass arguments duke@435: #endif // _LP64 duke@435: }; duke@435: }; duke@435: duke@435: duke@435: #ifdef _LP64 duke@435: // Symbolically name the register arguments used by the c calling convention. duke@435: // Windows is different from linux/solaris. So much for standards... duke@435: duke@435: #ifdef _WIN64 duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg2, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg3, r9); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); duke@435: duke@435: #else duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rdi); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rsi); duke@435: REGISTER_DECLARATION(Register, c_rarg2, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg3, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg4, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg5, r9); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); never@739: REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); never@739: REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); never@739: REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); never@739: REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); duke@435: duke@435: #endif // _WIN64 duke@435: duke@435: // Symbolically name the register arguments used by the Java calling convention. duke@435: // We have control over the convention for java so we can do what we please. duke@435: // What pleases us is to offset the java calling convention so that when duke@435: // we call a suitable jni method the arguments are lined up and we don't duke@435: // have to do little shuffling. A suitable jni method is non-static and a duke@435: // small number of arguments (two fewer args on windows) duke@435: // duke@435: // |-------------------------------------------------------| duke@435: // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | duke@435: // |-------------------------------------------------------| duke@435: // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) duke@435: // | rdi rsi rdx rcx r8 r9 | solaris/linux duke@435: // |-------------------------------------------------------| duke@435: // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | duke@435: // |-------------------------------------------------------| duke@435: duke@435: REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); duke@435: REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); duke@435: REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); duke@435: // Windows runs out of register args here duke@435: #ifdef _WIN64 duke@435: REGISTER_DECLARATION(Register, j_rarg3, rdi); duke@435: REGISTER_DECLARATION(Register, j_rarg4, rsi); duke@435: #else duke@435: REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); duke@435: REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); duke@435: #endif /* _WIN64 */ duke@435: REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); never@739: REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); never@739: REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); never@739: REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); never@739: REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); duke@435: duke@435: REGISTER_DECLARATION(Register, rscratch1, r10); // volatile duke@435: REGISTER_DECLARATION(Register, rscratch2, r11); // volatile duke@435: never@739: REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved duke@435: REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved duke@435: never@739: #else never@739: // rscratch1 will apear in 32bit code that is dead but of course must compile never@739: // Using noreg ensures if the dead code is incorrectly live and executed it never@739: // will cause an assertion failure never@739: #define rscratch1 noreg iveresov@2344: #define rscratch2 noreg never@739: duke@435: #endif // _LP64 duke@435: twisti@1919: // JSR 292 fixed register usages: twisti@1919: REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); twisti@1919: duke@435: // Address is an abstraction used to represent a memory location duke@435: // using any of the amd64 addressing modes with one object. duke@435: // duke@435: // Note: A register location is represented via a Register, not duke@435: // via an address for efficiency & simplicity reasons. duke@435: duke@435: class ArrayAddress; duke@435: duke@435: class Address VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum ScaleFactor { duke@435: no_scale = -1, duke@435: times_1 = 0, duke@435: times_2 = 1, duke@435: times_4 = 2, never@739: times_8 = 3, never@739: times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) duke@435: }; jrose@1057: static ScaleFactor times(int size) { jrose@1057: assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); jrose@1057: if (size == 8) return times_8; jrose@1057: if (size == 4) return times_4; jrose@1057: if (size == 2) return times_2; jrose@1057: return times_1; jrose@1057: } jrose@1057: static int scale_size(ScaleFactor scale) { jrose@1057: assert(scale != no_scale, ""); jrose@1057: assert(((1 << (int)times_1) == 1 && jrose@1057: (1 << (int)times_2) == 2 && jrose@1057: (1 << (int)times_4) == 4 && jrose@1057: (1 << (int)times_8) == 8), ""); jrose@1057: return (1 << (int)scale); jrose@1057: } duke@435: duke@435: private: duke@435: Register _base; duke@435: Register _index; duke@435: ScaleFactor _scale; duke@435: int _disp; duke@435: RelocationHolder _rspec; duke@435: never@739: // Easily misused constructors make them private never@739: // %%% can we make these go away? never@739: NOT_LP64(Address(address loc, RelocationHolder spec);) never@739: Address(int disp, address loc, relocInfo::relocType rtype); never@739: Address(int disp, address loc, RelocationHolder spec); duke@435: duke@435: public: never@739: never@739: int disp() { return _disp; } duke@435: // creation duke@435: Address() duke@435: : _base(noreg), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(0) { duke@435: } duke@435: duke@435: // No default displacement otherwise Register can be implicitly duke@435: // converted to 0(Register) which is quite a different animal. duke@435: duke@435: Address(Register base, int disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(disp) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, int disp = 0) duke@435: : _base (base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp (disp) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } duke@435: jrose@1100: Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) jrose@1057: : _base (base), jrose@1057: _index(index.register_or_noreg()), jrose@1057: _scale(scale), jrose@1057: _disp (disp + (index.constant_or_zero() * scale_size(scale))) { jrose@1057: if (!index.is_register()) scale = Address::no_scale; jrose@1057: assert(!_index->is_valid() == (scale == Address::no_scale), jrose@1057: "inconsistent address"); jrose@1057: } jrose@1057: jrose@1057: Address plus_disp(int disp) const { jrose@1057: Address a = (*this); jrose@1057: a._disp += disp; jrose@1057: return a; jrose@1057: } never@2895: Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { never@2895: Address a = (*this); never@2895: a._disp += disp.constant_or_zero() * scale_size(scale); never@2895: if (disp.is_register()) { never@2895: assert(!a.index()->is_valid(), "competing indexes"); never@2895: a._index = disp.as_register(); never@2895: a._scale = scale; never@2895: } never@2895: return a; never@2895: } never@2895: bool is_same_address(Address a) const { never@2895: // disregard _rspec never@2895: return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; never@2895: } jrose@1057: duke@435: // The following two overloads are used in connection with the duke@435: // ByteSize type (see sizes.hpp). They simplify the use of duke@435: // ByteSize'd arguments in assembly code. Note that their equivalent duke@435: // for the optimized build are the member functions with int disp duke@435: // argument since ByteSize is mapped to an int type in that case. duke@435: // duke@435: // Note: DO NOT introduce similar overloaded functions for WordSize duke@435: // arguments as in the optimized mode, both ByteSize and WordSize duke@435: // are mapped to the same type and thus the compiler cannot make a duke@435: // distinction anymore (=> compiler errors). duke@435: duke@435: #ifdef ASSERT duke@435: Address(Register base, ByteSize disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(in_bytes(disp)) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, ByteSize disp) duke@435: : _base(base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp(in_bytes(disp)) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } jrose@1057: jrose@1100: Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) jrose@1057: : _base (base), jrose@1057: _index(index.register_or_noreg()), jrose@1057: _scale(scale), jrose@1057: _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { jrose@1057: if (!index.is_register()) scale = Address::no_scale; jrose@1057: assert(!_index->is_valid() == (scale == Address::no_scale), jrose@1057: "inconsistent address"); jrose@1057: } jrose@1057: duke@435: #endif // ASSERT duke@435: duke@435: // accessors ysr@777: bool uses(Register reg) const { return _base == reg || _index == reg; } ysr@777: Register base() const { return _base; } ysr@777: Register index() const { return _index; } ysr@777: ScaleFactor scale() const { return _scale; } ysr@777: int disp() const { return _disp; } duke@435: duke@435: // Convert the raw encoding form into the form expected by the constructor for duke@435: // Address. An index of 4 (rsp) corresponds to having no index, so convert duke@435: // that to noreg for the Address constructor. coleenp@4037: static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); duke@435: duke@435: static Address make_array(ArrayAddress); duke@435: duke@435: private: duke@435: bool base_needs_rex() const { duke@435: return _base != noreg && _base->encoding() >= 8; duke@435: } duke@435: duke@435: bool index_needs_rex() const { duke@435: return _index != noreg &&_index->encoding() >= 8; duke@435: } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class LIR_Assembler; // base/index/scale/disp duke@435: }; duke@435: duke@435: // duke@435: // AddressLiteral has been split out from Address because operands of this type duke@435: // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out duke@435: // the few instructions that need to deal with address literals are unique and the duke@435: // MacroAssembler does not have to implement every instruction in the Assembler duke@435: // in order to search for address literals that may need special handling depending duke@435: // on the instruction and the platform. As small step on the way to merging i486/amd64 duke@435: // directories. duke@435: // duke@435: class AddressLiteral VALUE_OBJ_CLASS_SPEC { duke@435: friend class ArrayAddress; duke@435: RelocationHolder _rspec; duke@435: // Typically we use AddressLiterals we want to use their rval duke@435: // However in some situations we want the lval (effect address) of the item. duke@435: // We provide a special factory for making those lvals. duke@435: bool _is_lval; duke@435: duke@435: // If the target is far we'll need to load the ea of this to duke@435: // a register to reach it. Otherwise if near we can do rip duke@435: // relative addressing. duke@435: duke@435: address _target; duke@435: duke@435: protected: duke@435: // creation duke@435: AddressLiteral() duke@435: : _is_lval(false), duke@435: _target(NULL) duke@435: {} duke@435: duke@435: public: duke@435: duke@435: duke@435: AddressLiteral(address target, relocInfo::relocType rtype); duke@435: duke@435: AddressLiteral(address target, RelocationHolder const& rspec) duke@435: : _rspec(rspec), duke@435: _is_lval(false), duke@435: _target(target) duke@435: {} duke@435: duke@435: AddressLiteral addr() { duke@435: AddressLiteral ret = *this; duke@435: ret._is_lval = true; duke@435: return ret; duke@435: } duke@435: duke@435: duke@435: private: duke@435: duke@435: address target() { return _target; } duke@435: bool is_lval() { return _is_lval; } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: const RelocationHolder& rspec() const { return _rspec; } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class Address; duke@435: friend class LIR_Assembler; duke@435: }; duke@435: duke@435: // Convience classes duke@435: class RuntimeAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} duke@435: duke@435: }; duke@435: duke@435: class ExternalAddress: public AddressLiteral { never@2737: private: never@2737: static relocInfo::relocType reloc_for_target(address target) { never@2737: // Sometimes ExternalAddress is used for values which aren't never@2737: // exactly addresses, like the card table base. never@2737: // external_word_type can't be used for values in the first page never@2737: // so just skip the reloc in that case. never@2737: return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; never@2737: } never@2737: never@2737: public: never@2737: never@2737: ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} duke@435: duke@435: }; duke@435: duke@435: class InternalAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} duke@435: duke@435: }; duke@435: duke@435: // x86 can do array addressing as a single operation since disp can be an absolute duke@435: // address amd64 can't. We create a class that expresses the concept but does extra duke@435: // magic on amd64 to get the final result duke@435: duke@435: class ArrayAddress VALUE_OBJ_CLASS_SPEC { duke@435: private: duke@435: duke@435: AddressLiteral _base; duke@435: Address _index; duke@435: duke@435: public: duke@435: duke@435: ArrayAddress() {}; duke@435: ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; duke@435: AddressLiteral base() { return _base; } duke@435: Address index() { return _index; } duke@435: duke@435: }; duke@435: never@739: const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); duke@435: duke@435: // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction duke@435: // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write duke@435: // is what you get. The Assembler is generating code into a CodeBuffer. duke@435: duke@435: class Assembler : public AbstractAssembler { duke@435: friend class AbstractAssembler; // for the non-virtual hack duke@435: friend class LIR_Assembler; // as_Address() never@739: friend class StubGenerator; duke@435: duke@435: public: duke@435: enum Condition { // The x86 condition codes used for conditional jumps/moves. duke@435: zero = 0x4, duke@435: notZero = 0x5, duke@435: equal = 0x4, duke@435: notEqual = 0x5, duke@435: less = 0xc, duke@435: lessEqual = 0xe, duke@435: greater = 0xf, duke@435: greaterEqual = 0xd, duke@435: below = 0x2, duke@435: belowEqual = 0x6, duke@435: above = 0x7, duke@435: aboveEqual = 0x3, duke@435: overflow = 0x0, duke@435: noOverflow = 0x1, duke@435: carrySet = 0x2, duke@435: carryClear = 0x3, duke@435: negative = 0x8, duke@435: positive = 0x9, duke@435: parity = 0xa, duke@435: noParity = 0xb duke@435: }; duke@435: duke@435: enum Prefix { duke@435: // segment overrides duke@435: CS_segment = 0x2e, duke@435: SS_segment = 0x36, duke@435: DS_segment = 0x3e, duke@435: ES_segment = 0x26, duke@435: FS_segment = 0x64, duke@435: GS_segment = 0x65, duke@435: duke@435: REX = 0x40, duke@435: duke@435: REX_B = 0x41, duke@435: REX_X = 0x42, duke@435: REX_XB = 0x43, duke@435: REX_R = 0x44, duke@435: REX_RB = 0x45, duke@435: REX_RX = 0x46, duke@435: REX_RXB = 0x47, duke@435: duke@435: REX_W = 0x48, duke@435: duke@435: REX_WB = 0x49, duke@435: REX_WX = 0x4A, duke@435: REX_WXB = 0x4B, duke@435: REX_WR = 0x4C, duke@435: REX_WRB = 0x4D, duke@435: REX_WRX = 0x4E, kvn@3388: REX_WRXB = 0x4F, kvn@3388: kvn@3388: VEX_3bytes = 0xC4, kvn@3388: VEX_2bytes = 0xC5 kvn@3388: }; kvn@3388: kvn@3388: enum VexPrefix { kvn@3388: VEX_B = 0x20, kvn@3388: VEX_X = 0x40, kvn@3388: VEX_R = 0x80, kvn@3388: VEX_W = 0x80 kvn@3388: }; kvn@3388: kvn@3388: enum VexSimdPrefix { kvn@3388: VEX_SIMD_NONE = 0x0, kvn@3388: VEX_SIMD_66 = 0x1, kvn@3388: VEX_SIMD_F3 = 0x2, kvn@3388: VEX_SIMD_F2 = 0x3 kvn@3388: }; kvn@3388: kvn@3388: enum VexOpcode { kvn@3388: VEX_OPCODE_NONE = 0x0, kvn@3388: VEX_OPCODE_0F = 0x1, kvn@3388: VEX_OPCODE_0F_38 = 0x2, kvn@3388: VEX_OPCODE_0F_3A = 0x3 duke@435: }; duke@435: duke@435: enum WhichOperand { duke@435: // input to locate_operand, and format code for relocations never@739: imm_operand = 0, // embedded 32-bit|64-bit immediate operand duke@435: disp32_operand = 1, // embedded 32-bit displacement or address duke@435: call32_operand = 2, // embedded 32-bit self-relative displacement never@739: #ifndef _LP64 duke@435: _WhichOperand_limit = 3 never@739: #else never@739: narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop never@739: _WhichOperand_limit = 4 never@739: #endif duke@435: }; duke@435: never@739: never@739: never@739: // NOTE: The general philopsophy of the declarations here is that 64bit versions never@739: // of instructions are freely declared without the need for wrapping them an ifdef. never@739: // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) never@739: // In the .cpp file the implementations are wrapped so that they are dropped out zgu@4492: // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL never@739: // to the size it was prior to merging up the 32bit and 64bit assemblers. never@739: // never@739: // This does mean you'll get a linker/runtime error if you use a 64bit only instruction never@739: // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. never@739: never@739: private: never@739: never@739: never@739: // 64bit prefixes never@739: int prefix_and_encode(int reg_enc, bool byteinst = false); never@739: int prefixq_and_encode(int reg_enc); never@739: never@739: int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); never@739: int prefixq_and_encode(int dst_enc, int src_enc); never@739: never@739: void prefix(Register reg); never@739: void prefix(Address adr); never@739: void prefixq(Address adr); never@739: never@739: void prefix(Address adr, Register reg, bool byteinst = false); kvn@3388: void prefix(Address adr, XMMRegister reg); never@739: void prefixq(Address adr, Register reg); kvn@3388: void prefixq(Address adr, XMMRegister reg); never@739: never@739: void prefetch_prefix(Address src); never@739: kvn@3388: void rex_prefix(Address adr, XMMRegister xreg, kvn@3388: VexSimdPrefix pre, VexOpcode opc, bool rex_w); kvn@3388: int rex_prefix_and_encode(int dst_enc, int src_enc, kvn@3388: VexSimdPrefix pre, VexOpcode opc, bool rex_w); kvn@3388: kvn@3388: void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, kvn@3388: int nds_enc, VexSimdPrefix pre, VexOpcode opc, kvn@3388: bool vector256); kvn@3388: kvn@3388: void vex_prefix(Address adr, int nds_enc, int xreg_enc, kvn@3388: VexSimdPrefix pre, VexOpcode opc, kvn@3388: bool vex_w, bool vector256); kvn@3388: kvn@3390: void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, kvn@3390: VexSimdPrefix pre, bool vector256 = false) { kvn@3882: int dst_enc = dst->encoding(); kvn@3882: int nds_enc = nds->is_valid() ? nds->encoding() : 0; kvn@3882: vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); kvn@3390: } kvn@3390: kvn@3388: int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, kvn@3388: VexSimdPrefix pre, VexOpcode opc, kvn@3388: bool vex_w, bool vector256); kvn@3388: kvn@3390: int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, kvn@3882: VexSimdPrefix pre, bool vector256 = false, kvn@3882: VexOpcode opc = VEX_OPCODE_0F) { kvn@3882: int src_enc = src->encoding(); kvn@3882: int dst_enc = dst->encoding(); kvn@3882: int nds_enc = nds->is_valid() ? nds->encoding() : 0; kvn@3882: return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); kvn@3390: } kvn@3388: kvn@3388: void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, kvn@3388: VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, kvn@3388: bool rex_w = false, bool vector256 = false); kvn@3388: kvn@3388: void simd_prefix(XMMRegister dst, Address src, kvn@3388: VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { kvn@3388: simd_prefix(dst, xnoreg, src, pre, opc); kvn@3388: } kvn@4001: kvn@3388: void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { kvn@3388: simd_prefix(src, dst, pre); kvn@3388: } kvn@3388: void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, kvn@3388: VexSimdPrefix pre) { kvn@3388: bool rex_w = true; kvn@3388: simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); kvn@3388: } kvn@3388: kvn@3388: int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, kvn@3388: VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, kvn@3388: bool rex_w = false, bool vector256 = false); kvn@3388: kvn@3388: // Move/convert 32-bit integer value. kvn@3388: int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, kvn@3388: VexSimdPrefix pre) { kvn@3388: // It is OK to cast from Register to XMMRegister to pass argument here kvn@3388: // since only encoding is used in simd_prefix_and_encode() and number of kvn@3388: // Gen and Xmm registers are the same. kvn@3388: return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); kvn@3388: } kvn@3388: int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { kvn@3388: return simd_prefix_and_encode(dst, xnoreg, src, pre); kvn@3388: } kvn@3388: int simd_prefix_and_encode(Register dst, XMMRegister src, kvn@3388: VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { kvn@3388: return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); kvn@3388: } kvn@3388: kvn@3388: // Move/convert 64-bit integer value. kvn@3388: int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, kvn@3388: VexSimdPrefix pre) { kvn@3388: bool rex_w = true; kvn@3388: return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); kvn@3388: } kvn@3388: int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { kvn@3388: return simd_prefix_and_encode_q(dst, xnoreg, src, pre); kvn@3388: } kvn@3388: int simd_prefix_and_encode_q(Register dst, XMMRegister src, kvn@3388: VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { kvn@3388: bool rex_w = true; kvn@3388: return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); kvn@3388: } kvn@3388: never@739: // Helper functions for groups of instructions never@739: void emit_arith_b(int op1, int op2, Register dst, int imm8); never@739: never@739: void emit_arith(int op1, int op2, Register dst, int32_t imm32); kvn@3574: // Force generation of a 4 byte immediate value even if it fits into 8bit kvn@3574: void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); never@739: void emit_arith(int op1, int op2, Register dst, Register src); never@739: kvn@4001: void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); kvn@4001: void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); kvn@4001: void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); kvn@4001: void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); kvn@4001: void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, kvn@4001: Address src, VexSimdPrefix pre, bool vector256); kvn@4001: void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, kvn@4001: XMMRegister src, VexSimdPrefix pre, bool vector256); kvn@4001: never@739: void emit_operand(Register reg, never@739: Register base, Register index, Address::ScaleFactor scale, never@739: int disp, never@739: RelocationHolder const& rspec, never@739: int rip_relative_correction = 0); never@739: never@739: void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); never@739: never@739: // operands that only take the original 32bit registers never@739: void emit_operand32(Register reg, Address adr); never@739: never@739: void emit_operand(XMMRegister reg, never@739: Register base, Register index, Address::ScaleFactor scale, never@739: int disp, never@739: RelocationHolder const& rspec); never@739: never@739: void emit_operand(XMMRegister reg, Address adr); never@739: never@739: void emit_operand(MMXRegister reg, Address adr); never@739: never@739: // workaround gcc (3.2.1-7) bug never@739: void emit_operand(Address adr, MMXRegister reg); never@739: never@739: never@739: // Immediate-to-memory forms never@739: void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); never@739: never@739: void emit_farith(int b1, int b2, int i); never@739: duke@435: duke@435: protected: never@739: #ifdef ASSERT never@739: void check_relocation(RelocationHolder const& rspec, int format); never@739: #endif never@739: never@739: void emit_data(jint data, relocInfo::relocType rtype, int format); never@739: void emit_data(jint data, RelocationHolder const& rspec, int format); never@739: void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); never@739: void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); never@739: never@739: bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); never@739: never@739: // These are all easily abused and hence protected never@739: never@739: // 32BIT ONLY SECTION never@739: #ifndef _LP64 never@739: // Make these disappear in 64bit mode since they would never be correct never@739: void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: kvn@1077: void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: never@739: void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: #else never@739: // 64BIT ONLY SECTION never@739: void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY kvn@1077: kvn@1077: void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); kvn@1077: void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); kvn@1077: kvn@1077: void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); kvn@1077: void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); never@739: #endif // _LP64 never@739: never@739: // These are unique in that we are ensured by the caller that the 32bit never@739: // relative in these instructions will always be able to reach the potentially never@739: // 64bit address described by entry. Since they can take a 64bit address they never@739: // don't have the 32 suffix like the other instructions in this class. never@739: never@739: void call_literal(address entry, RelocationHolder const& rspec); never@739: void jmp_literal(address entry, RelocationHolder const& rspec); never@739: never@739: // Avoid using directly section never@739: // Instructions in this section are actually usable by anyone without danger never@739: // of failure but have performance issues that are addressed my enhanced never@739: // instructions which will do the proper thing base on the particular cpu. never@739: // We protect them because we don't trust you... never@739: duke@435: // Don't use next inc() and dec() methods directly. INC & DEC instructions duke@435: // could cause a partial flag stall since they don't set CF flag. duke@435: // Use MacroAssembler::decrement() & MacroAssembler::increment() methods duke@435: // which call inc() & dec() or add() & sub() in accordance with duke@435: // the product flag UseIncDec value. duke@435: duke@435: void decl(Register dst); duke@435: void decl(Address dst); never@739: void decq(Register dst); never@739: void decq(Address dst); duke@435: duke@435: void incl(Register dst); duke@435: void incl(Address dst); never@739: void incq(Register dst); never@739: void incq(Address dst); never@739: never@739: // New cpus require use of movsd and movss to avoid partial register stall never@739: // when loading from memory. But for old Opteron use movlpd instead of movsd. never@739: // The selection is done in MacroAssembler::movdbl() and movflt(). never@739: never@739: // Move Scalar Single-Precision Floating-Point Values never@739: void movss(XMMRegister dst, Address src); never@739: void movss(XMMRegister dst, XMMRegister src); never@739: void movss(Address dst, XMMRegister src); never@739: never@739: // Move Scalar Double-Precision Floating-Point Values never@739: void movsd(XMMRegister dst, Address src); never@739: void movsd(XMMRegister dst, XMMRegister src); never@739: void movsd(Address dst, XMMRegister src); never@739: void movlpd(XMMRegister dst, Address src); never@739: never@739: // New cpus require use of movaps and movapd to avoid partial register stall never@739: // when moving between registers. never@739: void movaps(XMMRegister dst, XMMRegister src); never@739: void movapd(XMMRegister dst, XMMRegister src); never@739: never@739: // End avoid using directly never@739: never@739: never@739: // Instruction prefixes never@739: void prefix(Prefix p); never@739: never@739: public: never@739: never@739: // Creation never@739: Assembler(CodeBuffer* code) : AbstractAssembler(code) {} never@739: never@739: // Decoding never@739: static address locate_operand(address inst, WhichOperand which); never@739: static address locate_next_instruction(address inst); never@739: never@739: // Utilities iveresov@2686: static bool is_polling_page_far() NOT_LP64({ return false;}); iveresov@2686: never@739: // Generic instructions never@739: // Does 32bit or 64bit as needed for the platform. In some sense these never@739: // belong in macro assembler but there is no need for both varieties to exist never@739: never@739: void lea(Register dst, Address src); never@739: never@739: void mov(Register dst, Register src); never@739: never@739: void pusha(); never@739: void popa(); never@739: never@739: void pushf(); never@739: void popf(); never@739: never@739: void push(int32_t imm32); never@739: never@739: void push(Register src); never@739: never@739: void pop(Register dst); never@739: never@739: // These are dummies to prevent surprise implicit conversions to Register never@739: void push(void* v); never@739: void pop(void* v); never@739: never@739: // These do register sized moves/scans never@739: void rep_mov(); kvn@4410: void rep_stos(); kvn@4410: void rep_stosb(); never@739: void repne_scan(); never@739: #ifdef _LP64 never@739: void repne_scanl(); never@739: #endif never@739: never@739: // Vanilla instructions in lexical order never@739: phh@2423: void adcl(Address dst, int32_t imm32); phh@2423: void adcl(Address dst, Register src); never@739: void adcl(Register dst, int32_t imm32); never@739: void adcl(Register dst, Address src); never@739: void adcl(Register dst, Register src); never@739: never@739: void adcq(Register dst, int32_t imm32); never@739: void adcq(Register dst, Address src); never@739: void adcq(Register dst, Register src); never@739: never@739: void addl(Address dst, int32_t imm32); never@739: void addl(Address dst, Register src); never@739: void addl(Register dst, int32_t imm32); never@739: void addl(Register dst, Address src); never@739: void addl(Register dst, Register src); never@739: never@739: void addq(Address dst, int32_t imm32); never@739: void addq(Address dst, Register src); never@739: void addq(Register dst, int32_t imm32); never@739: void addq(Register dst, Address src); never@739: void addq(Register dst, Register src); never@739: duke@435: void addr_nop_4(); duke@435: void addr_nop_5(); duke@435: void addr_nop_7(); duke@435: void addr_nop_8(); duke@435: never@739: // Add Scalar Double-Precision Floating-Point Values never@739: void addsd(XMMRegister dst, Address src); never@739: void addsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Add Scalar Single-Precision Floating-Point Values never@739: void addss(XMMRegister dst, Address src); never@739: void addss(XMMRegister dst, XMMRegister src); never@739: kvn@4205: // AES instructions kvn@4205: void aesdec(XMMRegister dst, Address src); kvn@4205: void aesdec(XMMRegister dst, XMMRegister src); kvn@4205: void aesdeclast(XMMRegister dst, Address src); kvn@4205: void aesdeclast(XMMRegister dst, XMMRegister src); kvn@4205: void aesenc(XMMRegister dst, Address src); kvn@4205: void aesenc(XMMRegister dst, XMMRegister src); kvn@4205: void aesenclast(XMMRegister dst, Address src); kvn@4205: void aesenclast(XMMRegister dst, XMMRegister src); kvn@4205: kvn@4205: kvn@3388: void andl(Address dst, int32_t imm32); never@739: void andl(Register dst, int32_t imm32); never@739: void andl(Register dst, Address src); never@739: void andl(Register dst, Register src); never@739: never@2980: void andq(Address dst, int32_t imm32); never@739: void andq(Register dst, int32_t imm32); never@739: void andq(Register dst, Address src); never@739: void andq(Register dst, Register src); never@739: twisti@1210: void bsfl(Register dst, Register src); twisti@1210: void bsrl(Register dst, Register src); twisti@1210: twisti@1210: #ifdef _LP64 twisti@1210: void bsfq(Register dst, Register src); twisti@1210: void bsrq(Register dst, Register src); twisti@1210: #endif twisti@1210: never@739: void bswapl(Register reg); never@739: never@739: void bswapq(Register reg); never@739: duke@435: void call(Label& L, relocInfo::relocType rtype); duke@435: void call(Register reg); // push pc; pc <- reg duke@435: void call(Address adr); // push pc; pc <- adr duke@435: never@739: void cdql(); never@739: never@739: void cdqq(); never@739: twisti@4318: void cld(); never@739: never@739: void clflush(Address adr); never@739: never@739: void cmovl(Condition cc, Register dst, Register src); never@739: void cmovl(Condition cc, Register dst, Address src); never@739: never@739: void cmovq(Condition cc, Register dst, Register src); never@739: void cmovq(Condition cc, Register dst, Address src); never@739: never@739: never@739: void cmpb(Address dst, int imm8); never@739: never@739: void cmpl(Address dst, int32_t imm32); never@739: never@739: void cmpl(Register dst, int32_t imm32); never@739: void cmpl(Register dst, Register src); never@739: void cmpl(Register dst, Address src); never@739: never@739: void cmpq(Address dst, int32_t imm32); never@739: void cmpq(Address dst, Register src); never@739: never@739: void cmpq(Register dst, int32_t imm32); never@739: void cmpq(Register dst, Register src); never@739: void cmpq(Register dst, Address src); never@739: never@739: // these are dummies used to catch attempting to convert NULL to Register never@739: void cmpl(Register dst, void* junk); // dummy never@739: void cmpq(Register dst, void* junk); // dummy never@739: never@739: void cmpw(Address dst, int imm16); never@739: never@739: void cmpxchg8 (Address adr); never@739: never@739: void cmpxchgl(Register reg, Address adr); never@739: never@739: void cmpxchgq(Register reg, Address adr); never@739: never@739: // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS never@739: void comisd(XMMRegister dst, Address src); kvn@3388: void comisd(XMMRegister dst, XMMRegister src); never@739: never@739: // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS never@739: void comiss(XMMRegister dst, Address src); kvn@3388: void comiss(XMMRegister dst, XMMRegister src); never@739: never@739: // Identify processor type and features twisti@4318: void cpuid(); never@739: never@739: // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value never@739: void cvtsd2ss(XMMRegister dst, XMMRegister src); kvn@3388: void cvtsd2ss(XMMRegister dst, Address src); never@739: never@739: // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value never@739: void cvtsi2sdl(XMMRegister dst, Register src); kvn@3388: void cvtsi2sdl(XMMRegister dst, Address src); never@739: void cvtsi2sdq(XMMRegister dst, Register src); kvn@3388: void cvtsi2sdq(XMMRegister dst, Address src); never@739: never@739: // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value never@739: void cvtsi2ssl(XMMRegister dst, Register src); kvn@3388: void cvtsi2ssl(XMMRegister dst, Address src); never@739: void cvtsi2ssq(XMMRegister dst, Register src); kvn@3388: void cvtsi2ssq(XMMRegister dst, Address src); never@739: never@739: // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value never@739: void cvtdq2pd(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value never@739: void cvtdq2ps(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value never@739: void cvtss2sd(XMMRegister dst, XMMRegister src); kvn@3388: void cvtss2sd(XMMRegister dst, Address src); never@739: never@739: // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer never@739: void cvttsd2sil(Register dst, Address src); never@739: void cvttsd2sil(Register dst, XMMRegister src); never@739: void cvttsd2siq(Register dst, XMMRegister src); never@739: never@739: // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer never@739: void cvttss2sil(Register dst, XMMRegister src); never@739: void cvttss2siq(Register dst, XMMRegister src); never@739: never@739: // Divide Scalar Double-Precision Floating-Point Values never@739: void divsd(XMMRegister dst, Address src); never@739: void divsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Divide Scalar Single-Precision Floating-Point Values never@739: void divss(XMMRegister dst, Address src); never@739: void divss(XMMRegister dst, XMMRegister src); never@739: never@739: void emms(); never@739: never@739: void fabs(); never@739: never@739: void fadd(int i); never@739: never@739: void fadd_d(Address src); never@739: void fadd_s(Address src); never@739: never@739: // "Alternate" versions of x87 instructions place result down in FPU never@739: // stack instead of on TOS never@739: never@739: void fadda(int i); // "alternate" fadd never@739: void faddp(int i = 1); never@739: never@739: void fchs(); never@739: never@739: void fcom(int i); never@739: never@739: void fcomp(int i = 1); never@739: void fcomp_d(Address src); never@739: void fcomp_s(Address src); never@739: never@739: void fcompp(); never@739: never@739: void fcos(); never@739: never@739: void fdecstp(); never@739: never@739: void fdiv(int i); never@739: void fdiv_d(Address src); never@739: void fdivr_s(Address src); never@739: void fdiva(int i); // "alternate" fdiv never@739: void fdivp(int i = 1); never@739: never@739: void fdivr(int i); never@739: void fdivr_d(Address src); never@739: void fdiv_s(Address src); never@739: never@739: void fdivra(int i); // "alternate" reversed fdiv never@739: never@739: void fdivrp(int i = 1); never@739: never@739: void ffree(int i = 0); never@739: never@739: void fild_d(Address adr); never@739: void fild_s(Address adr); never@739: never@739: void fincstp(); never@739: never@739: void finit(); never@739: never@739: void fist_s (Address adr); never@739: void fistp_d(Address adr); never@739: void fistp_s(Address adr); never@739: never@739: void fld1(); never@739: never@739: void fld_d(Address adr); never@739: void fld_s(Address adr); never@739: void fld_s(int index); never@739: void fld_x(Address adr); // extended-precision (80-bit) format never@739: never@739: void fldcw(Address src); never@739: never@739: void fldenv(Address src); never@739: never@739: void fldlg2(); never@739: never@739: void fldln2(); never@739: never@739: void fldz(); never@739: never@739: void flog(); never@739: void flog10(); never@739: never@739: void fmul(int i); never@739: never@739: void fmul_d(Address src); never@739: void fmul_s(Address src); never@739: never@739: void fmula(int i); // "alternate" fmul never@739: never@739: void fmulp(int i = 1); never@739: never@739: void fnsave(Address dst); never@739: never@739: void fnstcw(Address src); never@739: never@739: void fnstsw_ax(); never@739: never@739: void fprem(); never@739: void fprem1(); never@739: never@739: void frstor(Address src); never@739: never@739: void fsin(); never@739: never@739: void fsqrt(); never@739: never@739: void fst_d(Address adr); never@739: void fst_s(Address adr); never@739: never@739: void fstp_d(Address adr); never@739: void fstp_d(int index); never@739: void fstp_s(Address adr); never@739: void fstp_x(Address adr); // extended-precision (80-bit) format never@739: never@739: void fsub(int i); never@739: void fsub_d(Address src); never@739: void fsub_s(Address src); never@739: never@739: void fsuba(int i); // "alternate" fsub never@739: never@739: void fsubp(int i = 1); never@739: never@739: void fsubr(int i); never@739: void fsubr_d(Address src); never@739: void fsubr_s(Address src); never@739: never@739: void fsubra(int i); // "alternate" reversed fsub never@739: never@739: void fsubrp(int i = 1); never@739: never@739: void ftan(); never@739: never@739: void ftst(); never@739: never@739: void fucomi(int i = 1); never@739: void fucomip(int i = 1); never@739: never@739: void fwait(); never@739: never@739: void fxch(int i = 1); never@739: never@739: void fxrstor(Address src); never@739: never@739: void fxsave(Address dst); never@739: never@739: void fyl2x(); roland@3787: void frndint(); roland@3787: void f2xm1(); roland@3787: void fldl2e(); never@739: never@739: void hlt(); never@739: never@739: void idivl(Register src); kvn@2275: void divl(Register src); // Unsigned division never@739: never@739: void idivq(Register src); never@739: never@739: void imull(Register dst, Register src); never@739: void imull(Register dst, Register src, int value); never@739: never@739: void imulq(Register dst, Register src); never@739: void imulq(Register dst, Register src, int value); never@739: duke@435: duke@435: // jcc is the generic conditional branch generator to run- duke@435: // time routines, jcc is used for branches to labels. jcc duke@435: // takes a branch opcode (cc) and a label (L) and generates duke@435: // either a backward branch or a forward branch and links it duke@435: // to the label fixup chain. Usage: duke@435: // duke@435: // Label L; // unbound label duke@435: // jcc(cc, L); // forward branch to unbound label duke@435: // bind(L); // bind label to the current pc duke@435: // jcc(cc, L); // backward branch to bound label duke@435: // bind(L); // illegal: a label may be bound only once duke@435: // duke@435: // Note: The same Label can be used for forward and backward branches duke@435: // but it may be bound only once. duke@435: kvn@3049: void jcc(Condition cc, Label& L, bool maybe_short = true); duke@435: duke@435: // Conditional jump to a 8-bit offset to L. duke@435: // WARNING: be very careful using this for forward jumps. If the label is duke@435: // not bound within an 8-bit offset of this instruction, a run-time error duke@435: // will occur. duke@435: void jccb(Condition cc, Label& L); duke@435: never@739: void jmp(Address entry); // pc <- entry never@739: never@739: // Label operations & relative jumps (PPUM Appendix D) kvn@3049: void jmp(Label& L, bool maybe_short = true); // unconditional jump to L never@739: never@739: void jmp(Register entry); // pc <- entry never@739: never@739: // Unconditional 8-bit offset jump to L. never@739: // WARNING: be very careful using this for forward jumps. If the label is never@739: // not bound within an 8-bit offset of this instruction, a run-time error never@739: // will occur. never@739: void jmpb(Label& L); never@739: never@739: void ldmxcsr( Address src ); never@739: never@739: void leal(Register dst, Address src); never@739: never@739: void leaq(Register dst, Address src); never@739: twisti@4318: void lfence(); never@739: never@739: void lock(); never@739: twisti@1210: void lzcntl(Register dst, Register src); twisti@1210: twisti@1210: #ifdef _LP64 twisti@1210: void lzcntq(Register dst, Register src); twisti@1210: #endif twisti@1210: never@739: enum Membar_mask_bits { never@739: StoreStore = 1 << 3, never@739: LoadStore = 1 << 2, never@739: StoreLoad = 1 << 1, never@739: LoadLoad = 1 << 0 never@739: }; never@739: never@1106: // Serializes memory and blows flags never@739: void membar(Membar_mask_bits order_constraint) { never@1106: if (os::is_MP()) { never@1106: // We only have to handle StoreLoad never@1106: if (order_constraint & StoreLoad) { never@1106: // All usable chips support "locked" instructions which suffice never@1106: // as barriers, and are much faster than the alternative of never@1106: // using cpuid instruction. We use here a locked add [esp],0. never@1106: // This is conveniently otherwise a no-op except for blowing never@1106: // flags. never@1106: // Any change to this code may need to revisit other places in never@1106: // the code where this idiom is used, in particular the never@1106: // orderAccess code. never@1106: lock(); never@1106: addl(Address(rsp, 0), 0);// Assert the lock# signal here never@1106: } never@1106: } never@739: } never@739: never@739: void mfence(); never@739: never@739: // Moves never@739: never@739: void mov64(Register dst, int64_t imm64); never@739: never@739: void movb(Address dst, Register src); never@739: void movb(Address dst, int imm8); never@739: void movb(Register dst, Address src); never@739: never@739: void movdl(XMMRegister dst, Register src); never@739: void movdl(Register dst, XMMRegister src); kvn@2602: void movdl(XMMRegister dst, Address src); kvn@3882: void movdl(Address dst, XMMRegister src); never@739: never@739: // Move Double Quadword never@739: void movdq(XMMRegister dst, Register src); never@739: void movdq(Register dst, XMMRegister src); never@739: never@739: // Move Aligned Double Quadword never@739: void movdqa(XMMRegister dst, XMMRegister src); never@739: kvn@840: // Move Unaligned Double Quadword kvn@840: void movdqu(Address dst, XMMRegister src); kvn@840: void movdqu(XMMRegister dst, Address src); kvn@840: void movdqu(XMMRegister dst, XMMRegister src); kvn@840: kvn@3882: // Move Unaligned 256bit Vector kvn@3882: void vmovdqu(Address dst, XMMRegister src); kvn@3882: void vmovdqu(XMMRegister dst, Address src); kvn@3882: void vmovdqu(XMMRegister dst, XMMRegister src); kvn@3882: kvn@3882: // Move lower 64bit to high 64bit in 128bit register kvn@3882: void movlhps(XMMRegister dst, XMMRegister src); kvn@3882: never@739: void movl(Register dst, int32_t imm32); never@739: void movl(Address dst, int32_t imm32); never@739: void movl(Register dst, Register src); never@739: void movl(Register dst, Address src); never@739: void movl(Address dst, Register src); never@739: never@739: // These dummies prevent using movl from converting a zero (like NULL) into Register never@739: // by giving the compiler two choices it can't resolve never@739: never@739: void movl(Address dst, void* junk); never@739: void movl(Register dst, void* junk); never@739: never@739: #ifdef _LP64 never@739: void movq(Register dst, Register src); never@739: void movq(Register dst, Address src); phh@2423: void movq(Address dst, Register src); never@739: #endif never@739: never@739: void movq(Address dst, MMXRegister src ); never@739: void movq(MMXRegister dst, Address src ); never@739: never@739: #ifdef _LP64 never@739: // These dummies prevent using movq from converting a zero (like NULL) into Register never@739: // by giving the compiler two choices it can't resolve never@739: never@739: void movq(Address dst, void* dummy); never@739: void movq(Register dst, void* dummy); never@739: #endif never@739: never@739: // Move Quadword never@739: void movq(Address dst, XMMRegister src); never@739: void movq(XMMRegister dst, Address src); never@739: never@739: void movsbl(Register dst, Address src); never@739: void movsbl(Register dst, Register src); never@739: never@739: #ifdef _LP64 twisti@1059: void movsbq(Register dst, Address src); twisti@1059: void movsbq(Register dst, Register src); twisti@1059: never@739: // Move signed 32bit immediate to 64bit extending sign phh@2423: void movslq(Address dst, int32_t imm64); never@739: void movslq(Register dst, int32_t imm64); never@739: never@739: void movslq(Register dst, Address src); never@739: void movslq(Register dst, Register src); never@739: void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous never@739: #endif never@739: never@739: void movswl(Register dst, Address src); never@739: void movswl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movswq(Register dst, Address src); twisti@1059: void movswq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void movw(Address dst, int imm16); never@739: void movw(Register dst, Address src); never@739: void movw(Address dst, Register src); never@739: never@739: void movzbl(Register dst, Address src); never@739: void movzbl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movzbq(Register dst, Address src); twisti@1059: void movzbq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void movzwl(Register dst, Address src); never@739: void movzwl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movzwq(Register dst, Address src); twisti@1059: void movzwq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void mull(Address src); never@739: void mull(Register src); never@739: never@739: // Multiply Scalar Double-Precision Floating-Point Values never@739: void mulsd(XMMRegister dst, Address src); never@739: void mulsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Multiply Scalar Single-Precision Floating-Point Values never@739: void mulss(XMMRegister dst, Address src); never@739: void mulss(XMMRegister dst, XMMRegister src); never@739: never@739: void negl(Register dst); never@739: never@739: #ifdef _LP64 never@739: void negq(Register dst); never@739: #endif never@739: never@739: void nop(int i = 1); never@739: never@739: void notl(Register dst); never@739: never@739: #ifdef _LP64 never@739: void notq(Register dst); never@739: #endif never@739: never@739: void orl(Address dst, int32_t imm32); never@739: void orl(Register dst, int32_t imm32); never@739: void orl(Register dst, Address src); never@739: void orl(Register dst, Register src); never@739: never@739: void orq(Address dst, int32_t imm32); never@739: void orq(Register dst, int32_t imm32); never@739: void orq(Register dst, Address src); never@739: void orq(Register dst, Register src); never@739: kvn@3388: // Pack with unsigned saturation kvn@3388: void packuswb(XMMRegister dst, XMMRegister src); kvn@3388: void packuswb(XMMRegister dst, Address src); kvn@4479: void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4479: kvn@4479: // Pemutation of 64bit words kvn@4479: void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); kvn@3388: cfang@1116: // SSE4.2 string instructions cfang@1116: void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); cfang@1116: void pcmpestri(XMMRegister xmm1, Address src, int imm8); cfang@1116: kvn@3388: // SSE4.1 packed move kvn@3388: void pmovzxbw(XMMRegister dst, XMMRegister src); kvn@3388: void pmovzxbw(XMMRegister dst, Address src); kvn@3388: roland@1495: #ifndef _LP64 // no 32bit push/pop on amd64 never@739: void popl(Address dst); roland@1495: #endif never@739: never@739: #ifdef _LP64 never@739: void popq(Address dst); never@739: #endif never@739: twisti@1078: void popcntl(Register dst, Address src); twisti@1078: void popcntl(Register dst, Register src); twisti@1078: twisti@1078: #ifdef _LP64 twisti@1078: void popcntq(Register dst, Address src); twisti@1078: void popcntq(Register dst, Register src); twisti@1078: #endif twisti@1078: never@739: // Prefetches (SSE, SSE2, 3DNOW only) never@739: never@739: void prefetchnta(Address src); never@739: void prefetchr(Address src); never@739: void prefetcht0(Address src); never@739: void prefetcht1(Address src); never@739: void prefetcht2(Address src); never@739: void prefetchw(Address src); never@739: kvn@4205: // Shuffle Bytes kvn@4205: void pshufb(XMMRegister dst, XMMRegister src); kvn@4205: void pshufb(XMMRegister dst, Address src); kvn@4205: never@739: // Shuffle Packed Doublewords never@739: void pshufd(XMMRegister dst, XMMRegister src, int mode); never@739: void pshufd(XMMRegister dst, Address src, int mode); never@739: never@739: // Shuffle Packed Low Words never@739: void pshuflw(XMMRegister dst, XMMRegister src, int mode); never@739: void pshuflw(XMMRegister dst, Address src, int mode); never@739: kvn@2602: // Shift Right by bytes Logical DoubleQuadword Immediate kvn@2602: void psrldq(XMMRegister dst, int shift); kvn@2602: kvn@4413: // Logical Compare 128bit cfang@1116: void ptest(XMMRegister dst, XMMRegister src); cfang@1116: void ptest(XMMRegister dst, Address src); kvn@4413: // Logical Compare 256bit kvn@4413: void vptest(XMMRegister dst, XMMRegister src); kvn@4413: void vptest(XMMRegister dst, Address src); cfang@1116: never@739: // Interleave Low Bytes never@739: void punpcklbw(XMMRegister dst, XMMRegister src); kvn@3388: void punpcklbw(XMMRegister dst, Address src); kvn@3388: kvn@3388: // Interleave Low Doublewords kvn@3388: void punpckldq(XMMRegister dst, XMMRegister src); kvn@3388: void punpckldq(XMMRegister dst, Address src); never@739: kvn@3929: // Interleave Low Quadwords kvn@3929: void punpcklqdq(XMMRegister dst, XMMRegister src); kvn@3929: roland@1495: #ifndef _LP64 // no 32bit push/pop on amd64 never@739: void pushl(Address src); roland@1495: #endif never@739: never@739: void pushq(Address src); never@739: never@739: void rcll(Register dst, int imm8); never@739: never@739: void rclq(Register dst, int imm8); never@739: never@739: void ret(int imm16); duke@435: duke@435: void sahf(); duke@435: never@739: void sarl(Register dst, int imm8); never@739: void sarl(Register dst); never@739: never@739: void sarq(Register dst, int imm8); never@739: void sarq(Register dst); never@739: never@739: void sbbl(Address dst, int32_t imm32); never@739: void sbbl(Register dst, int32_t imm32); never@739: void sbbl(Register dst, Address src); never@739: void sbbl(Register dst, Register src); never@739: never@739: void sbbq(Address dst, int32_t imm32); never@739: void sbbq(Register dst, int32_t imm32); never@739: void sbbq(Register dst, Address src); never@739: void sbbq(Register dst, Register src); never@739: never@739: void setb(Condition cc, Register dst); never@739: never@739: void shldl(Register dst, Register src); never@739: never@739: void shll(Register dst, int imm8); never@739: void shll(Register dst); never@739: never@739: void shlq(Register dst, int imm8); never@739: void shlq(Register dst); never@739: never@739: void shrdl(Register dst, Register src); never@739: never@739: void shrl(Register dst, int imm8); never@739: void shrl(Register dst); never@739: never@739: void shrq(Register dst, int imm8); never@739: void shrq(Register dst); never@739: never@739: void smovl(); // QQQ generic? never@739: never@739: // Compute Square Root of Scalar Double-Precision Floating-Point Value never@739: void sqrtsd(XMMRegister dst, Address src); never@739: void sqrtsd(XMMRegister dst, XMMRegister src); never@739: twisti@2350: // Compute Square Root of Scalar Single-Precision Floating-Point Value twisti@2350: void sqrtss(XMMRegister dst, Address src); twisti@2350: void sqrtss(XMMRegister dst, XMMRegister src); twisti@2350: twisti@4318: void std(); never@739: never@739: void stmxcsr( Address dst ); never@739: never@739: void subl(Address dst, int32_t imm32); never@739: void subl(Address dst, Register src); never@739: void subl(Register dst, int32_t imm32); never@739: void subl(Register dst, Address src); never@739: void subl(Register dst, Register src); never@739: never@739: void subq(Address dst, int32_t imm32); never@739: void subq(Address dst, Register src); never@739: void subq(Register dst, int32_t imm32); never@739: void subq(Register dst, Address src); never@739: void subq(Register dst, Register src); never@739: kvn@3574: // Force generation of a 4 byte immediate value even if it fits into 8bit kvn@3574: void subl_imm32(Register dst, int32_t imm32); kvn@3574: void subq_imm32(Register dst, int32_t imm32); never@739: never@739: // Subtract Scalar Double-Precision Floating-Point Values never@739: void subsd(XMMRegister dst, Address src); never@739: void subsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Subtract Scalar Single-Precision Floating-Point Values never@739: void subss(XMMRegister dst, Address src); duke@435: void subss(XMMRegister dst, XMMRegister src); never@739: never@739: void testb(Register dst, int imm8); never@739: never@739: void testl(Register dst, int32_t imm32); never@739: void testl(Register dst, Register src); never@739: void testl(Register dst, Address src); never@739: never@739: void testq(Register dst, int32_t imm32); never@739: void testq(Register dst, Register src); never@739: never@739: never@739: // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS never@739: void ucomisd(XMMRegister dst, Address src); never@739: void ucomisd(XMMRegister dst, XMMRegister src); never@739: never@739: // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS never@739: void ucomiss(XMMRegister dst, Address src); duke@435: void ucomiss(XMMRegister dst, XMMRegister src); never@739: never@739: void xaddl(Address dst, Register src); never@739: never@739: void xaddq(Address dst, Register src); never@739: never@739: void xchgl(Register reg, Address adr); never@739: void xchgl(Register dst, Register src); never@739: never@739: void xchgq(Register reg, Address adr); never@739: void xchgq(Register dst, Register src); never@739: kvn@3388: // Get Value of Extended Control Register twisti@4318: void xgetbv(); kvn@3388: never@739: void xorl(Register dst, int32_t imm32); never@739: void xorl(Register dst, Address src); never@739: void xorl(Register dst, Register src); never@739: never@739: void xorq(Register dst, Address src); never@739: void xorq(Register dst, Register src); never@739: kvn@3388: void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 kvn@3388: kvn@3929: // AVX 3-operands scalar instructions (encoded with VEX prefix) kvn@4001: kvn@3390: void vaddsd(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vaddss(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vdivsd(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vdivss(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vmulsd(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vmulss(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vsubsd(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3390: void vsubss(XMMRegister dst, XMMRegister nds, Address src); kvn@3390: void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3929: kvn@4001: kvn@4001: //====================VECTOR ARITHMETIC===================================== kvn@4001: kvn@4001: // Add Packed Floating-Point Values kvn@4001: void addpd(XMMRegister dst, XMMRegister src); kvn@4001: void addps(XMMRegister dst, XMMRegister src); kvn@4001: void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Subtract Packed Floating-Point Values kvn@4001: void subpd(XMMRegister dst, XMMRegister src); kvn@4001: void subps(XMMRegister dst, XMMRegister src); kvn@4001: void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Multiply Packed Floating-Point Values kvn@4001: void mulpd(XMMRegister dst, XMMRegister src); kvn@4001: void mulps(XMMRegister dst, XMMRegister src); kvn@4001: void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Divide Packed Floating-Point Values kvn@4001: void divpd(XMMRegister dst, XMMRegister src); kvn@4001: void divps(XMMRegister dst, XMMRegister src); kvn@4001: void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Bitwise Logical AND of Packed Floating-Point Values kvn@4001: void andpd(XMMRegister dst, XMMRegister src); kvn@4001: void andps(XMMRegister dst, XMMRegister src); kvn@4001: void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Bitwise Logical XOR of Packed Floating-Point Values kvn@4001: void xorpd(XMMRegister dst, XMMRegister src); kvn@4001: void xorps(XMMRegister dst, XMMRegister src); kvn@3882: void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@3882: void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Add packed integers kvn@4001: void paddb(XMMRegister dst, XMMRegister src); kvn@4001: void paddw(XMMRegister dst, XMMRegister src); kvn@4001: void paddd(XMMRegister dst, XMMRegister src); kvn@4001: void paddq(XMMRegister dst, XMMRegister src); kvn@4001: void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Sub packed integers kvn@4001: void psubb(XMMRegister dst, XMMRegister src); kvn@4001: void psubw(XMMRegister dst, XMMRegister src); kvn@4001: void psubd(XMMRegister dst, XMMRegister src); kvn@4001: void psubq(XMMRegister dst, XMMRegister src); kvn@4001: void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Multiply packed integers (only shorts and ints) kvn@4001: void pmullw(XMMRegister dst, XMMRegister src); kvn@4001: void pmulld(XMMRegister dst, XMMRegister src); kvn@4001: void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Shift left packed integers kvn@4001: void psllw(XMMRegister dst, int shift); kvn@4001: void pslld(XMMRegister dst, int shift); kvn@4001: void psllq(XMMRegister dst, int shift); kvn@4001: void psllw(XMMRegister dst, XMMRegister shift); kvn@4001: void pslld(XMMRegister dst, XMMRegister shift); kvn@4001: void psllq(XMMRegister dst, XMMRegister shift); kvn@4001: void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: kvn@4001: // Logical shift right packed integers kvn@4001: void psrlw(XMMRegister dst, int shift); kvn@4001: void psrld(XMMRegister dst, int shift); kvn@4001: void psrlq(XMMRegister dst, int shift); kvn@4001: void psrlw(XMMRegister dst, XMMRegister shift); kvn@4001: void psrld(XMMRegister dst, XMMRegister shift); kvn@4001: void psrlq(XMMRegister dst, XMMRegister shift); kvn@4001: void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: kvn@4001: // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) kvn@4001: void psraw(XMMRegister dst, int shift); kvn@4001: void psrad(XMMRegister dst, int shift); kvn@4001: void psraw(XMMRegister dst, XMMRegister shift); kvn@4001: void psrad(XMMRegister dst, XMMRegister shift); kvn@4001: void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); kvn@4001: void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); kvn@4001: kvn@4001: // And packed integers kvn@4001: void pand(XMMRegister dst, XMMRegister src); kvn@4001: void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Or packed integers kvn@4001: void por(XMMRegister dst, XMMRegister src); kvn@4001: void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Xor packed integers kvn@4001: void pxor(XMMRegister dst, XMMRegister src); kvn@3929: void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); kvn@4001: void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); kvn@4001: kvn@4001: // Copy low 128bit into high 128bit of YMM registers. kvn@3882: void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3929: void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); kvn@3882: kvn@4103: // Load/store high 128bit of YMM registers which does not destroy other half. kvn@4103: void vinsertf128h(XMMRegister dst, Address src); kvn@4103: void vinserti128h(XMMRegister dst, Address src); kvn@4103: void vextractf128h(Address dst, XMMRegister src); kvn@4103: void vextracti128h(Address dst, XMMRegister src); kvn@4103: kvn@4411: // duplicate 4-bytes integer data from src into 8 locations in dest kvn@4411: void vpbroadcastd(XMMRegister dst, XMMRegister src); kvn@4411: kvn@3882: // AVX instruction which is used to clear upper 128 bits of YMM registers and kvn@3882: // to avoid transaction penalty between AVX and SSE states. There is no kvn@3882: // penalty if legacy SSE instructions are encoded using VEX prefix because kvn@3882: // they always clear upper 128 bits. It should be used before calling kvn@3882: // runtime code and native libraries. kvn@3882: void vzeroupper(); kvn@3390: kvn@3388: protected: kvn@3388: // Next instructions require address alignment 16 bytes SSE mode. kvn@3388: // They should be called only from corresponding MacroAssembler instructions. kvn@3388: void andpd(XMMRegister dst, Address src); kvn@3388: void andps(XMMRegister dst, Address src); never@739: void xorpd(XMMRegister dst, Address src); never@739: void xorps(XMMRegister dst, Address src); kvn@3388: duke@435: }; duke@435: stefank@2314: #endif // CPU_X86_VM_ASSEMBLER_X86_HPP