twisti@1020: /*
twisti@1020:  * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.
twisti@1020:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@1020:  *
twisti@1020:  * This code is free software; you can redistribute it and/or modify it
twisti@1020:  * under the terms of the GNU General Public License version 2 only, as
twisti@1020:  * published by the Free Software Foundation.
twisti@1020:  *
twisti@1020:  * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@1020:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@1020:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
twisti@1020:  * version 2 for more details (a copy is included in the LICENSE file that
twisti@1020:  * accompanied this code).
twisti@1020:  *
twisti@1020:  * You should have received a copy of the GNU General Public License version
twisti@1020:  * 2 along with this work; if not, write to the Free Software Foundation,
twisti@1020:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@1020:  *
twisti@1020:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
twisti@1020:  * CA 95054 USA or visit www.sun.com if you need additional information or
twisti@1020:  * have any questions.
twisti@1020:  *
twisti@1020:  */
twisti@1020: 
twisti@1020: class VM_Version : public Abstract_VM_Version {
twisti@1020: public:
twisti@1020:   // cpuid result register layouts.  These are all unions of a uint32_t
twisti@1020:   // (in case anyone wants access to the register as a whole) and a bitfield.
twisti@1020: 
twisti@1020:   union StdCpuid1Eax {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t stepping   : 4,
twisti@1020:                model      : 4,
twisti@1020:                family     : 4,
twisti@1020:                proc_type  : 2,
twisti@1020:                           : 2,
twisti@1020:                ext_model  : 4,
twisti@1020:                ext_family : 8,
twisti@1020:                           : 4;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union StdCpuid1Ebx { // example, unused
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t brand_id         : 8,
twisti@1020:                clflush_size     : 8,
twisti@1020:                threads_per_cpu  : 8,
twisti@1020:                apic_id          : 8;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union StdCpuid1Ecx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t sse3     : 1,
twisti@1020:                         : 2,
twisti@1020:                monitor  : 1,
twisti@1020:                         : 1,
twisti@1020:                vmx      : 1,
twisti@1020:                         : 1,
twisti@1020:                est      : 1,
twisti@1020:                         : 1,
twisti@1020:                ssse3    : 1,
twisti@1020:                cid      : 1,
twisti@1020:                         : 2,
twisti@1020:                cmpxchg16: 1,
twisti@1020:                         : 4,
twisti@1020:                dca      : 1,
twisti@1020:                sse4_1   : 1,
twisti@1020:                sse4_2   : 1,
twisti@1078:                         : 2,
twisti@1078:                popcnt   : 1,
twisti@1078:                         : 8;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union StdCpuid1Edx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t          : 4,
twisti@1020:                tsc      : 1,
twisti@1020:                         : 3,
twisti@1020:                cmpxchg8 : 1,
twisti@1020:                         : 6,
twisti@1020:                cmov     : 1,
twisti@1020:                         : 7,
twisti@1020:                mmx      : 1,
twisti@1020:                fxsr     : 1,
twisti@1020:                sse      : 1,
twisti@1020:                sse2     : 1,
twisti@1020:                         : 1,
twisti@1020:                ht       : 1,
twisti@1020:                         : 3;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union DcpCpuid4Eax {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t cache_type    : 5,
twisti@1020:                              : 21,
twisti@1020:                cores_per_cpu : 6;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union DcpCpuid4Ebx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t L1_line_size  : 12,
twisti@1020:                partitions    : 10,
twisti@1020:                associativity : 10;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union ExtCpuid1Ecx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t LahfSahf     : 1,
twisti@1020:                CmpLegacy    : 1,
twisti@1020:                             : 4,
twisti@1020:                abm          : 1,
twisti@1020:                sse4a        : 1,
twisti@1020:                misalignsse  : 1,
twisti@1020:                prefetchw    : 1,
twisti@1020:                             : 22;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union ExtCpuid1Edx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t           : 22,
twisti@1020:                mmx_amd   : 1,
twisti@1020:                mmx       : 1,
twisti@1020:                fxsr      : 1,
twisti@1020:                          : 4,
twisti@1020:                long_mode : 1,
twisti@1020:                tdnow2    : 1,
twisti@1020:                tdnow     : 1;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union ExtCpuid5Ex {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t L1_line_size : 8,
twisti@1020:                L1_tag_lines : 8,
twisti@1020:                L1_assoc     : 8,
twisti@1020:                L1_size      : 8;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020:   union ExtCpuid8Ecx {
twisti@1020:     uint32_t value;
twisti@1020:     struct {
twisti@1020:       uint32_t cores_per_cpu : 8,
twisti@1020:                              : 24;
twisti@1020:     } bits;
twisti@1020:   };
twisti@1020: 
twisti@1020: protected:
twisti@1020:    static int _cpu;
twisti@1020:    static int _model;
twisti@1020:    static int _stepping;
twisti@1020:    static int _cpuFeatures;     // features returned by the "cpuid" instruction
twisti@1020:                                 // 0 if this instruction is not available
twisti@1020:    static const char* _features_str;
twisti@1020: 
twisti@1020:    enum {
twisti@1020:      CPU_CX8    = (1 << 0), // next bits are from cpuid 1 (EDX)
twisti@1020:      CPU_CMOV   = (1 << 1),
twisti@1020:      CPU_FXSR   = (1 << 2),
twisti@1020:      CPU_HT     = (1 << 3),
twisti@1020:      CPU_MMX    = (1 << 4),
twisti@1020:      CPU_3DNOW  = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
twisti@1020:      CPU_SSE    = (1 << 6),
twisti@1020:      CPU_SSE2   = (1 << 7),
twisti@1020:      CPU_SSE3   = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
twisti@1020:      CPU_SSSE3  = (1 << 9),
twisti@1020:      CPU_SSE4A  = (1 << 10),
twisti@1020:      CPU_SSE4_1 = (1 << 11),
twisti@1078:      CPU_SSE4_2 = (1 << 12),
twisti@1078:      CPU_POPCNT = (1 << 13)
twisti@1020:    } cpuFeatureFlags;
twisti@1020: 
twisti@1020:   // cpuid information block.  All info derived from executing cpuid with
twisti@1020:   // various function numbers is stored here.  Intel and AMD info is
twisti@1020:   // merged in this block: accessor methods disentangle it.
twisti@1020:   //
twisti@1020:   // The info block is laid out in subblocks of 4 dwords corresponding to
twisti@1020:   // eax, ebx, ecx and edx, whether or not they contain anything useful.
twisti@1020:   struct CpuidInfo {
twisti@1020:     // cpuid function 0
twisti@1020:     uint32_t std_max_function;
twisti@1020:     uint32_t std_vendor_name_0;
twisti@1020:     uint32_t std_vendor_name_1;
twisti@1020:     uint32_t std_vendor_name_2;
twisti@1020: 
twisti@1020:     // cpuid function 1
twisti@1020:     StdCpuid1Eax std_cpuid1_eax;
twisti@1020:     StdCpuid1Ebx std_cpuid1_ebx;
twisti@1020:     StdCpuid1Ecx std_cpuid1_ecx;
twisti@1020:     StdCpuid1Edx std_cpuid1_edx;
twisti@1020: 
twisti@1020:     // cpuid function 4 (deterministic cache parameters)
twisti@1020:     DcpCpuid4Eax dcp_cpuid4_eax;
twisti@1020:     DcpCpuid4Ebx dcp_cpuid4_ebx;
twisti@1020:     uint32_t     dcp_cpuid4_ecx; // unused currently
twisti@1020:     uint32_t     dcp_cpuid4_edx; // unused currently
twisti@1020: 
twisti@1020:     // cpuid function 0x80000000 // example, unused
twisti@1020:     uint32_t ext_max_function;
twisti@1020:     uint32_t ext_vendor_name_0;
twisti@1020:     uint32_t ext_vendor_name_1;
twisti@1020:     uint32_t ext_vendor_name_2;
twisti@1020: 
twisti@1020:     // cpuid function 0x80000001
twisti@1020:     uint32_t     ext_cpuid1_eax; // reserved
twisti@1020:     uint32_t     ext_cpuid1_ebx; // reserved
twisti@1020:     ExtCpuid1Ecx ext_cpuid1_ecx;
twisti@1020:     ExtCpuid1Edx ext_cpuid1_edx;
twisti@1020: 
twisti@1020:     // cpuid functions 0x80000002 thru 0x80000004: example, unused
twisti@1020:     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
twisti@1020:     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
twisti@1020:     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
twisti@1020: 
twisti@1020:     // cpuid function 0x80000005 //AMD L1, Intel reserved
twisti@1020:     uint32_t     ext_cpuid5_eax; // unused currently
twisti@1020:     uint32_t     ext_cpuid5_ebx; // reserved
twisti@1020:     ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
twisti@1020:     ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
twisti@1020: 
twisti@1020:     // cpuid function 0x80000008
twisti@1020:     uint32_t     ext_cpuid8_eax; // unused currently
twisti@1020:     uint32_t     ext_cpuid8_ebx; // reserved
twisti@1020:     ExtCpuid8Ecx ext_cpuid8_ecx;
twisti@1020:     uint32_t     ext_cpuid8_edx; // reserved
twisti@1020:   };
twisti@1020: 
twisti@1020:   // The actual cpuid info block
twisti@1020:   static CpuidInfo _cpuid_info;
twisti@1020: 
twisti@1020:   // Extractors and predicates
twisti@1020:   static uint32_t extended_cpu_family() {
twisti@1020:     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
twisti@1020:     result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
twisti@1020:     return result;
twisti@1020:   }
twisti@1020:   static uint32_t extended_cpu_model() {
twisti@1020:     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
twisti@1020:     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
twisti@1020:     return result;
twisti@1020:   }
twisti@1020:   static uint32_t cpu_stepping() {
twisti@1020:     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
twisti@1020:     return result;
twisti@1020:   }
twisti@1020:   static uint logical_processor_count() {
twisti@1020:     uint result = threads_per_core();
twisti@1020:     return result;
twisti@1020:   }
twisti@1020:   static uint32_t feature_flags() {
twisti@1020:     uint32_t result = 0;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
twisti@1020:       result |= CPU_CX8;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
twisti@1020:       result |= CPU_CMOV;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || is_amd() &&
twisti@1020:         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)
twisti@1020:       result |= CPU_FXSR;
twisti@1020:     // HT flag is set for multi-core processors also.
twisti@1020:     if (threads_per_core() > 1)
twisti@1020:       result |= CPU_HT;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || is_amd() &&
twisti@1020:         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)
twisti@1020:       result |= CPU_MMX;
twisti@1020:     if (is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow != 0)
twisti@1020:       result |= CPU_3DNOW;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
twisti@1020:       result |= CPU_SSE;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
twisti@1020:       result |= CPU_SSE2;
twisti@1020:     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
twisti@1020:       result |= CPU_SSE3;
twisti@1020:     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
twisti@1020:       result |= CPU_SSSE3;
twisti@1020:     if (is_amd() && _cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
twisti@1020:       result |= CPU_SSE4A;
twisti@1020:     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
twisti@1020:       result |= CPU_SSE4_1;
twisti@1020:     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
twisti@1020:       result |= CPU_SSE4_2;
twisti@1078:     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
twisti@1078:       result |= CPU_POPCNT;
twisti@1020:     return result;
twisti@1020:   }
twisti@1020: 
twisti@1020:   static void get_processor_features();
twisti@1020: 
twisti@1020: public:
twisti@1020:   // Offsets for cpuid asm stub
twisti@1020:   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
twisti@1020:   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
twisti@1020:   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
twisti@1020:   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
twisti@1020:   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
twisti@1020:   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
twisti@1020: 
twisti@1020:   // Initialization
twisti@1020:   static void initialize();
twisti@1020: 
twisti@1020:   // Asserts
twisti@1020:   static void assert_is_initialized() {
twisti@1020:     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
twisti@1020:   }
twisti@1020: 
twisti@1020:   //
twisti@1020:   // Processor family:
twisti@1020:   //       3   -  386
twisti@1020:   //       4   -  486
twisti@1020:   //       5   -  Pentium
twisti@1020:   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
twisti@1020:   //              Pentium M, Core Solo, Core Duo, Core2 Duo
twisti@1020:   //    family 6 model:   9,        13,       14,        15
twisti@1020:   //    0x0f   -  Pentium 4, Opteron
twisti@1020:   //
twisti@1020:   // Note: The cpu family should be used to select between
twisti@1020:   //       instruction sequences which are valid on all Intel
twisti@1020:   //       processors.  Use the feature test functions below to
twisti@1020:   //       determine whether a particular instruction is supported.
twisti@1020:   //
twisti@1020:   static int  cpu_family()        { return _cpu;}
twisti@1020:   static bool is_P6()             { return cpu_family() >= 6; }
twisti@1020: 
twisti@1020:   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
twisti@1020:   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
twisti@1020: 
twisti@1020:   static uint cores_per_cpu()  {
twisti@1020:     uint result = 1;
twisti@1020:     if (is_intel()) {
twisti@1020:       result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
twisti@1020:     } else if (is_amd()) {
twisti@1020:       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
twisti@1020:     }
twisti@1020:     return result;
twisti@1020:   }
twisti@1020: 
twisti@1020:   static uint threads_per_core()  {
twisti@1020:     uint result = 1;
twisti@1020:     if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
twisti@1020:       result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
twisti@1020:                cores_per_cpu();
twisti@1020:     }
twisti@1020:     return result;
twisti@1020:   }
twisti@1020: 
twisti@1020:   static intx L1_data_cache_line_size()  {
twisti@1020:     intx result = 0;
twisti@1020:     if (is_intel()) {
twisti@1020:       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
twisti@1020:     } else if (is_amd()) {
twisti@1020:       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
twisti@1020:     }
twisti@1020:     if (result < 32) // not defined ?
twisti@1020:       result = 32;   // 32 bytes by default on x86 and other x64
twisti@1020:     return result;
twisti@1020:   }
twisti@1020: 
twisti@1020:   //
twisti@1020:   // Feature identification
twisti@1020:   //
twisti@1020:   static bool supports_cpuid()    { return _cpuFeatures  != 0; }
twisti@1020:   static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
twisti@1020:   static bool supports_cmov()     { return (_cpuFeatures & CPU_CMOV) != 0; }
twisti@1020:   static bool supports_fxsr()     { return (_cpuFeatures & CPU_FXSR) != 0; }
twisti@1020:   static bool supports_ht()       { return (_cpuFeatures & CPU_HT) != 0; }
twisti@1020:   static bool supports_mmx()      { return (_cpuFeatures & CPU_MMX) != 0; }
twisti@1020:   static bool supports_sse()      { return (_cpuFeatures & CPU_SSE) != 0; }
twisti@1020:   static bool supports_sse2()     { return (_cpuFeatures & CPU_SSE2) != 0; }
twisti@1020:   static bool supports_sse3()     { return (_cpuFeatures & CPU_SSE3) != 0; }
twisti@1020:   static bool supports_ssse3()    { return (_cpuFeatures & CPU_SSSE3)!= 0; }
twisti@1020:   static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }
twisti@1020:   static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }
twisti@1078:   static bool supports_popcnt()   { return (_cpuFeatures & CPU_POPCNT) != 0; }
twisti@1020:   //
twisti@1020:   // AMD features
twisti@1020:   //
twisti@1020:   static bool supports_3dnow()    { return (_cpuFeatures & CPU_3DNOW) != 0; }
twisti@1020:   static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
twisti@1020:   static bool supports_3dnow2()   { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; }
twisti@1020:   static bool supports_sse4a()    { return (_cpuFeatures & CPU_SSE4A) != 0; }
twisti@1020: 
twisti@1020:   static bool supports_compare_and_exchange() { return true; }
twisti@1020: 
twisti@1020:   static const char* cpu_features()           { return _features_str; }
twisti@1020: 
twisti@1020:   static intx allocate_prefetch_distance() {
twisti@1020:     // This method should be called before allocate_prefetch_style().
twisti@1020:     //
twisti@1020:     // Hardware prefetching (distance/size in bytes):
twisti@1020:     // Pentium 3 -  64 /  32
twisti@1020:     // Pentium 4 - 256 / 128
twisti@1020:     // Athlon    -  64 /  32 ????
twisti@1020:     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
twisti@1020:     // Core      - 128 /  64
twisti@1020:     //
twisti@1020:     // Software prefetching (distance in bytes / instruction with best score):
twisti@1020:     // Pentium 3 - 128 / prefetchnta
twisti@1020:     // Pentium 4 - 512 / prefetchnta
twisti@1020:     // Athlon    - 128 / prefetchnta
twisti@1020:     // Opteron   - 256 / prefetchnta
twisti@1020:     // Core      - 256 / prefetchnta
twisti@1020:     // It will be used only when AllocatePrefetchStyle > 0
twisti@1020: 
twisti@1020:     intx count = AllocatePrefetchDistance;
twisti@1020:     if (count < 0) {   // default ?
twisti@1020:       if (is_amd()) {  // AMD
twisti@1020:         if (supports_sse2())
twisti@1020:           count = 256; // Opteron
twisti@1020:         else
twisti@1020:           count = 128; // Athlon
twisti@1020:       } else {         // Intel
twisti@1020:         if (supports_sse2())
twisti@1020:           if (cpu_family() == 6) {
twisti@1020:             count = 256; // Pentium M, Core, Core2
twisti@1020:           } else {
twisti@1020:             count = 512; // Pentium 4
twisti@1020:           }
twisti@1020:         else
twisti@1020:           count = 128; // Pentium 3 (and all other old CPUs)
twisti@1020:       }
twisti@1020:     }
twisti@1020:     return count;
twisti@1020:   }
twisti@1020:   static intx allocate_prefetch_style() {
twisti@1020:     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
twisti@1020:     // Return 0 if AllocatePrefetchDistance was not defined.
twisti@1020:     return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
twisti@1020:   }
twisti@1020: 
twisti@1020:   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
twisti@1020:   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
twisti@1020:   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
twisti@1020:   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
twisti@1020: 
twisti@1020:   // gc copy/scan is disabled if prefetchw isn't supported, because
twisti@1020:   // Prefetch::write emits an inlined prefetchw on Linux.
twisti@1020:   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
twisti@1020:   // The used prefetcht0 instruction works for both amd64 and em64t.
twisti@1020:   static intx prefetch_copy_interval_in_bytes() {
twisti@1020:     intx interval = PrefetchCopyIntervalInBytes;
twisti@1020:     return interval >= 0 ? interval : 576;
twisti@1020:   }
twisti@1020:   static intx prefetch_scan_interval_in_bytes() {
twisti@1020:     intx interval = PrefetchScanIntervalInBytes;
twisti@1020:     return interval >= 0 ? interval : 576;
twisti@1020:   }
twisti@1020:   static intx prefetch_fields_ahead() {
twisti@1020:     intx count = PrefetchFieldsAhead;
twisti@1020:     return count >= 0 ? count : 1;
twisti@1020:   }
twisti@1020: };