duke@435: /* twisti@1059: * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: class BiasedLockingCounters; duke@435: duke@435: // Contains all the definitions needed for x86 assembly code generation. duke@435: duke@435: // Calling convention duke@435: class Argument VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum { duke@435: #ifdef _LP64 duke@435: #ifdef _WIN64 duke@435: n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) duke@435: #else duke@435: n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) duke@435: #endif // _WIN64 duke@435: n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... duke@435: n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... duke@435: #else duke@435: n_register_parameters = 0 // 0 registers used to pass arguments duke@435: #endif // _LP64 duke@435: }; duke@435: }; duke@435: duke@435: duke@435: #ifdef _LP64 duke@435: // Symbolically name the register arguments used by the c calling convention. duke@435: // Windows is different from linux/solaris. So much for standards... duke@435: duke@435: #ifdef _WIN64 duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg2, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg3, r9); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); duke@435: duke@435: #else duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rdi); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rsi); duke@435: REGISTER_DECLARATION(Register, c_rarg2, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg3, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg4, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg5, r9); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); never@739: REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); never@739: REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); never@739: REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); never@739: REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); duke@435: duke@435: #endif // _WIN64 duke@435: duke@435: // Symbolically name the register arguments used by the Java calling convention. duke@435: // We have control over the convention for java so we can do what we please. duke@435: // What pleases us is to offset the java calling convention so that when duke@435: // we call a suitable jni method the arguments are lined up and we don't duke@435: // have to do little shuffling. A suitable jni method is non-static and a duke@435: // small number of arguments (two fewer args on windows) duke@435: // duke@435: // |-------------------------------------------------------| duke@435: // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | duke@435: // |-------------------------------------------------------| duke@435: // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) duke@435: // | rdi rsi rdx rcx r8 r9 | solaris/linux duke@435: // |-------------------------------------------------------| duke@435: // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | duke@435: // |-------------------------------------------------------| duke@435: duke@435: REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); duke@435: REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); duke@435: REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); duke@435: // Windows runs out of register args here duke@435: #ifdef _WIN64 duke@435: REGISTER_DECLARATION(Register, j_rarg3, rdi); duke@435: REGISTER_DECLARATION(Register, j_rarg4, rsi); duke@435: #else duke@435: REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); duke@435: REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); duke@435: #endif /* _WIN64 */ duke@435: REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); duke@435: never@739: REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); never@739: REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); never@739: REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); never@739: REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); never@739: REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); never@739: REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); never@739: REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); never@739: REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); duke@435: duke@435: REGISTER_DECLARATION(Register, rscratch1, r10); // volatile duke@435: REGISTER_DECLARATION(Register, rscratch2, r11); // volatile duke@435: never@739: REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved duke@435: REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved duke@435: never@739: #else never@739: // rscratch1 will apear in 32bit code that is dead but of course must compile never@739: // Using noreg ensures if the dead code is incorrectly live and executed it never@739: // will cause an assertion failure never@739: #define rscratch1 noreg never@739: duke@435: #endif // _LP64 duke@435: duke@435: // Address is an abstraction used to represent a memory location duke@435: // using any of the amd64 addressing modes with one object. duke@435: // duke@435: // Note: A register location is represented via a Register, not duke@435: // via an address for efficiency & simplicity reasons. duke@435: duke@435: class ArrayAddress; duke@435: duke@435: class Address VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum ScaleFactor { duke@435: no_scale = -1, duke@435: times_1 = 0, duke@435: times_2 = 1, duke@435: times_4 = 2, never@739: times_8 = 3, never@739: times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) duke@435: }; jrose@1057: static ScaleFactor times(int size) { jrose@1057: assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); jrose@1057: if (size == 8) return times_8; jrose@1057: if (size == 4) return times_4; jrose@1057: if (size == 2) return times_2; jrose@1057: return times_1; jrose@1057: } jrose@1057: static int scale_size(ScaleFactor scale) { jrose@1057: assert(scale != no_scale, ""); jrose@1057: assert(((1 << (int)times_1) == 1 && jrose@1057: (1 << (int)times_2) == 2 && jrose@1057: (1 << (int)times_4) == 4 && jrose@1057: (1 << (int)times_8) == 8), ""); jrose@1057: return (1 << (int)scale); jrose@1057: } duke@435: duke@435: private: duke@435: Register _base; duke@435: Register _index; duke@435: ScaleFactor _scale; duke@435: int _disp; duke@435: RelocationHolder _rspec; duke@435: never@739: // Easily misused constructors make them private never@739: // %%% can we make these go away? never@739: NOT_LP64(Address(address loc, RelocationHolder spec);) never@739: Address(int disp, address loc, relocInfo::relocType rtype); never@739: Address(int disp, address loc, RelocationHolder spec); duke@435: duke@435: public: never@739: never@739: int disp() { return _disp; } duke@435: // creation duke@435: Address() duke@435: : _base(noreg), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(0) { duke@435: } duke@435: duke@435: // No default displacement otherwise Register can be implicitly duke@435: // converted to 0(Register) which is quite a different animal. duke@435: duke@435: Address(Register base, int disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(disp) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, int disp = 0) duke@435: : _base (base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp (disp) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } duke@435: jrose@1100: Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) jrose@1057: : _base (base), jrose@1057: _index(index.register_or_noreg()), jrose@1057: _scale(scale), jrose@1057: _disp (disp + (index.constant_or_zero() * scale_size(scale))) { jrose@1057: if (!index.is_register()) scale = Address::no_scale; jrose@1057: assert(!_index->is_valid() == (scale == Address::no_scale), jrose@1057: "inconsistent address"); jrose@1057: } jrose@1057: jrose@1057: Address plus_disp(int disp) const { jrose@1057: Address a = (*this); jrose@1057: a._disp += disp; jrose@1057: return a; jrose@1057: } jrose@1057: duke@435: // The following two overloads are used in connection with the duke@435: // ByteSize type (see sizes.hpp). They simplify the use of duke@435: // ByteSize'd arguments in assembly code. Note that their equivalent duke@435: // for the optimized build are the member functions with int disp duke@435: // argument since ByteSize is mapped to an int type in that case. duke@435: // duke@435: // Note: DO NOT introduce similar overloaded functions for WordSize duke@435: // arguments as in the optimized mode, both ByteSize and WordSize duke@435: // are mapped to the same type and thus the compiler cannot make a duke@435: // distinction anymore (=> compiler errors). duke@435: duke@435: #ifdef ASSERT duke@435: Address(Register base, ByteSize disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(in_bytes(disp)) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, ByteSize disp) duke@435: : _base(base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp(in_bytes(disp)) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } jrose@1057: jrose@1100: Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) jrose@1057: : _base (base), jrose@1057: _index(index.register_or_noreg()), jrose@1057: _scale(scale), jrose@1057: _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { jrose@1057: if (!index.is_register()) scale = Address::no_scale; jrose@1057: assert(!_index->is_valid() == (scale == Address::no_scale), jrose@1057: "inconsistent address"); jrose@1057: } jrose@1057: duke@435: #endif // ASSERT duke@435: duke@435: // accessors ysr@777: bool uses(Register reg) const { return _base == reg || _index == reg; } ysr@777: Register base() const { return _base; } ysr@777: Register index() const { return _index; } ysr@777: ScaleFactor scale() const { return _scale; } ysr@777: int disp() const { return _disp; } duke@435: duke@435: // Convert the raw encoding form into the form expected by the constructor for duke@435: // Address. An index of 4 (rsp) corresponds to having no index, so convert duke@435: // that to noreg for the Address constructor. twisti@1059: static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); duke@435: duke@435: static Address make_array(ArrayAddress); duke@435: duke@435: private: duke@435: bool base_needs_rex() const { duke@435: return _base != noreg && _base->encoding() >= 8; duke@435: } duke@435: duke@435: bool index_needs_rex() const { duke@435: return _index != noreg &&_index->encoding() >= 8; duke@435: } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class LIR_Assembler; // base/index/scale/disp duke@435: }; duke@435: duke@435: // duke@435: // AddressLiteral has been split out from Address because operands of this type duke@435: // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out duke@435: // the few instructions that need to deal with address literals are unique and the duke@435: // MacroAssembler does not have to implement every instruction in the Assembler duke@435: // in order to search for address literals that may need special handling depending duke@435: // on the instruction and the platform. As small step on the way to merging i486/amd64 duke@435: // directories. duke@435: // duke@435: class AddressLiteral VALUE_OBJ_CLASS_SPEC { duke@435: friend class ArrayAddress; duke@435: RelocationHolder _rspec; duke@435: // Typically we use AddressLiterals we want to use their rval duke@435: // However in some situations we want the lval (effect address) of the item. duke@435: // We provide a special factory for making those lvals. duke@435: bool _is_lval; duke@435: duke@435: // If the target is far we'll need to load the ea of this to duke@435: // a register to reach it. Otherwise if near we can do rip duke@435: // relative addressing. duke@435: duke@435: address _target; duke@435: duke@435: protected: duke@435: // creation duke@435: AddressLiteral() duke@435: : _is_lval(false), duke@435: _target(NULL) duke@435: {} duke@435: duke@435: public: duke@435: duke@435: duke@435: AddressLiteral(address target, relocInfo::relocType rtype); duke@435: duke@435: AddressLiteral(address target, RelocationHolder const& rspec) duke@435: : _rspec(rspec), duke@435: _is_lval(false), duke@435: _target(target) duke@435: {} duke@435: duke@435: AddressLiteral addr() { duke@435: AddressLiteral ret = *this; duke@435: ret._is_lval = true; duke@435: return ret; duke@435: } duke@435: duke@435: duke@435: private: duke@435: duke@435: address target() { return _target; } duke@435: bool is_lval() { return _is_lval; } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: const RelocationHolder& rspec() const { return _rspec; } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class Address; duke@435: friend class LIR_Assembler; duke@435: }; duke@435: duke@435: // Convience classes duke@435: class RuntimeAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} duke@435: duke@435: }; duke@435: duke@435: class OopAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} duke@435: duke@435: }; duke@435: duke@435: class ExternalAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} duke@435: duke@435: }; duke@435: duke@435: class InternalAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} duke@435: duke@435: }; duke@435: duke@435: // x86 can do array addressing as a single operation since disp can be an absolute duke@435: // address amd64 can't. We create a class that expresses the concept but does extra duke@435: // magic on amd64 to get the final result duke@435: duke@435: class ArrayAddress VALUE_OBJ_CLASS_SPEC { duke@435: private: duke@435: duke@435: AddressLiteral _base; duke@435: Address _index; duke@435: duke@435: public: duke@435: duke@435: ArrayAddress() {}; duke@435: ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; duke@435: AddressLiteral base() { return _base; } duke@435: Address index() { return _index; } duke@435: duke@435: }; duke@435: never@739: const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); duke@435: duke@435: // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction duke@435: // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write duke@435: // is what you get. The Assembler is generating code into a CodeBuffer. duke@435: duke@435: class Assembler : public AbstractAssembler { duke@435: friend class AbstractAssembler; // for the non-virtual hack duke@435: friend class LIR_Assembler; // as_Address() never@739: friend class StubGenerator; duke@435: duke@435: public: duke@435: enum Condition { // The x86 condition codes used for conditional jumps/moves. duke@435: zero = 0x4, duke@435: notZero = 0x5, duke@435: equal = 0x4, duke@435: notEqual = 0x5, duke@435: less = 0xc, duke@435: lessEqual = 0xe, duke@435: greater = 0xf, duke@435: greaterEqual = 0xd, duke@435: below = 0x2, duke@435: belowEqual = 0x6, duke@435: above = 0x7, duke@435: aboveEqual = 0x3, duke@435: overflow = 0x0, duke@435: noOverflow = 0x1, duke@435: carrySet = 0x2, duke@435: carryClear = 0x3, duke@435: negative = 0x8, duke@435: positive = 0x9, duke@435: parity = 0xa, duke@435: noParity = 0xb duke@435: }; duke@435: duke@435: enum Prefix { duke@435: // segment overrides duke@435: CS_segment = 0x2e, duke@435: SS_segment = 0x36, duke@435: DS_segment = 0x3e, duke@435: ES_segment = 0x26, duke@435: FS_segment = 0x64, duke@435: GS_segment = 0x65, duke@435: duke@435: REX = 0x40, duke@435: duke@435: REX_B = 0x41, duke@435: REX_X = 0x42, duke@435: REX_XB = 0x43, duke@435: REX_R = 0x44, duke@435: REX_RB = 0x45, duke@435: REX_RX = 0x46, duke@435: REX_RXB = 0x47, duke@435: duke@435: REX_W = 0x48, duke@435: duke@435: REX_WB = 0x49, duke@435: REX_WX = 0x4A, duke@435: REX_WXB = 0x4B, duke@435: REX_WR = 0x4C, duke@435: REX_WRB = 0x4D, duke@435: REX_WRX = 0x4E, duke@435: REX_WRXB = 0x4F duke@435: }; duke@435: duke@435: enum WhichOperand { duke@435: // input to locate_operand, and format code for relocations never@739: imm_operand = 0, // embedded 32-bit|64-bit immediate operand duke@435: disp32_operand = 1, // embedded 32-bit displacement or address duke@435: call32_operand = 2, // embedded 32-bit self-relative displacement never@739: #ifndef _LP64 duke@435: _WhichOperand_limit = 3 never@739: #else never@739: narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop never@739: _WhichOperand_limit = 4 never@739: #endif duke@435: }; duke@435: never@739: never@739: never@739: // NOTE: The general philopsophy of the declarations here is that 64bit versions never@739: // of instructions are freely declared without the need for wrapping them an ifdef. never@739: // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) never@739: // In the .cpp file the implementations are wrapped so that they are dropped out never@739: // of the resulting jvm. This is done mostly to keep the footprint of KERNEL never@739: // to the size it was prior to merging up the 32bit and 64bit assemblers. never@739: // never@739: // This does mean you'll get a linker/runtime error if you use a 64bit only instruction never@739: // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. never@739: never@739: private: never@739: never@739: never@739: // 64bit prefixes never@739: int prefix_and_encode(int reg_enc, bool byteinst = false); never@739: int prefixq_and_encode(int reg_enc); never@739: never@739: int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); never@739: int prefixq_and_encode(int dst_enc, int src_enc); never@739: never@739: void prefix(Register reg); never@739: void prefix(Address adr); never@739: void prefixq(Address adr); never@739: never@739: void prefix(Address adr, Register reg, bool byteinst = false); never@739: void prefixq(Address adr, Register reg); never@739: never@739: void prefix(Address adr, XMMRegister reg); never@739: never@739: void prefetch_prefix(Address src); never@739: never@739: // Helper functions for groups of instructions never@739: void emit_arith_b(int op1, int op2, Register dst, int imm8); never@739: never@739: void emit_arith(int op1, int op2, Register dst, int32_t imm32); never@739: // only 32bit?? never@739: void emit_arith(int op1, int op2, Register dst, jobject obj); never@739: void emit_arith(int op1, int op2, Register dst, Register src); never@739: never@739: void emit_operand(Register reg, never@739: Register base, Register index, Address::ScaleFactor scale, never@739: int disp, never@739: RelocationHolder const& rspec, never@739: int rip_relative_correction = 0); never@739: never@739: void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); never@739: never@739: // operands that only take the original 32bit registers never@739: void emit_operand32(Register reg, Address adr); never@739: never@739: void emit_operand(XMMRegister reg, never@739: Register base, Register index, Address::ScaleFactor scale, never@739: int disp, never@739: RelocationHolder const& rspec); never@739: never@739: void emit_operand(XMMRegister reg, Address adr); never@739: never@739: void emit_operand(MMXRegister reg, Address adr); never@739: never@739: // workaround gcc (3.2.1-7) bug never@739: void emit_operand(Address adr, MMXRegister reg); never@739: never@739: never@739: // Immediate-to-memory forms never@739: void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); never@739: never@739: void emit_farith(int b1, int b2, int i); never@739: duke@435: duke@435: protected: never@739: #ifdef ASSERT never@739: void check_relocation(RelocationHolder const& rspec, int format); never@739: #endif never@739: never@739: inline void emit_long64(jlong x); never@739: never@739: void emit_data(jint data, relocInfo::relocType rtype, int format); never@739: void emit_data(jint data, RelocationHolder const& rspec, int format); never@739: void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); never@739: void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); never@739: never@739: never@739: bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); never@739: never@739: // These are all easily abused and hence protected never@739: never@739: // 32BIT ONLY SECTION never@739: #ifndef _LP64 never@739: // Make these disappear in 64bit mode since they would never be correct never@739: void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: kvn@1077: void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: never@739: void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY never@739: #else never@739: // 64BIT ONLY SECTION never@739: void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY kvn@1077: kvn@1077: void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); kvn@1077: void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); kvn@1077: kvn@1077: void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); kvn@1077: void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); never@739: #endif // _LP64 never@739: never@739: // These are unique in that we are ensured by the caller that the 32bit never@739: // relative in these instructions will always be able to reach the potentially never@739: // 64bit address described by entry. Since they can take a 64bit address they never@739: // don't have the 32 suffix like the other instructions in this class. never@739: never@739: void call_literal(address entry, RelocationHolder const& rspec); never@739: void jmp_literal(address entry, RelocationHolder const& rspec); never@739: never@739: // Avoid using directly section never@739: // Instructions in this section are actually usable by anyone without danger never@739: // of failure but have performance issues that are addressed my enhanced never@739: // instructions which will do the proper thing base on the particular cpu. never@739: // We protect them because we don't trust you... never@739: duke@435: // Don't use next inc() and dec() methods directly. INC & DEC instructions duke@435: // could cause a partial flag stall since they don't set CF flag. duke@435: // Use MacroAssembler::decrement() & MacroAssembler::increment() methods duke@435: // which call inc() & dec() or add() & sub() in accordance with duke@435: // the product flag UseIncDec value. duke@435: duke@435: void decl(Register dst); duke@435: void decl(Address dst); never@739: void decq(Register dst); never@739: void decq(Address dst); duke@435: duke@435: void incl(Register dst); duke@435: void incl(Address dst); never@739: void incq(Register dst); never@739: void incq(Address dst); never@739: never@739: // New cpus require use of movsd and movss to avoid partial register stall never@739: // when loading from memory. But for old Opteron use movlpd instead of movsd. never@739: // The selection is done in MacroAssembler::movdbl() and movflt(). never@739: never@739: // Move Scalar Single-Precision Floating-Point Values never@739: void movss(XMMRegister dst, Address src); never@739: void movss(XMMRegister dst, XMMRegister src); never@739: void movss(Address dst, XMMRegister src); never@739: never@739: // Move Scalar Double-Precision Floating-Point Values never@739: void movsd(XMMRegister dst, Address src); never@739: void movsd(XMMRegister dst, XMMRegister src); never@739: void movsd(Address dst, XMMRegister src); never@739: void movlpd(XMMRegister dst, Address src); never@739: never@739: // New cpus require use of movaps and movapd to avoid partial register stall never@739: // when moving between registers. never@739: void movaps(XMMRegister dst, XMMRegister src); never@739: void movapd(XMMRegister dst, XMMRegister src); never@739: never@739: // End avoid using directly never@739: never@739: never@739: // Instruction prefixes never@739: void prefix(Prefix p); never@739: never@739: public: never@739: never@739: // Creation never@739: Assembler(CodeBuffer* code) : AbstractAssembler(code) {} never@739: never@739: // Decoding never@739: static address locate_operand(address inst, WhichOperand which); never@739: static address locate_next_instruction(address inst); never@739: never@739: // Utilities never@739: never@739: #ifdef _LP64 never@739: static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } never@739: static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } never@739: #else never@739: static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); } never@739: static bool is_simm32(int32_t x) { return true; } never@739: #endif // LP64 never@739: never@739: // Generic instructions never@739: // Does 32bit or 64bit as needed for the platform. In some sense these never@739: // belong in macro assembler but there is no need for both varieties to exist never@739: never@739: void lea(Register dst, Address src); never@739: never@739: void mov(Register dst, Register src); never@739: never@739: void pusha(); never@739: void popa(); never@739: never@739: void pushf(); never@739: void popf(); never@739: never@739: void push(int32_t imm32); never@739: never@739: void push(Register src); never@739: never@739: void pop(Register dst); never@739: never@739: // These are dummies to prevent surprise implicit conversions to Register never@739: void push(void* v); never@739: void pop(void* v); never@739: never@739: never@739: // These do register sized moves/scans never@739: void rep_mov(); never@739: void rep_set(); never@739: void repne_scan(); never@739: #ifdef _LP64 never@739: void repne_scanl(); never@739: #endif never@739: never@739: // Vanilla instructions in lexical order never@739: never@739: void adcl(Register dst, int32_t imm32); never@739: void adcl(Register dst, Address src); never@739: void adcl(Register dst, Register src); never@739: never@739: void adcq(Register dst, int32_t imm32); never@739: void adcq(Register dst, Address src); never@739: void adcq(Register dst, Register src); never@739: never@739: never@739: void addl(Address dst, int32_t imm32); never@739: void addl(Address dst, Register src); never@739: void addl(Register dst, int32_t imm32); never@739: void addl(Register dst, Address src); never@739: void addl(Register dst, Register src); never@739: never@739: void addq(Address dst, int32_t imm32); never@739: void addq(Address dst, Register src); never@739: void addq(Register dst, int32_t imm32); never@739: void addq(Register dst, Address src); never@739: void addq(Register dst, Register src); never@739: never@739: duke@435: void addr_nop_4(); duke@435: void addr_nop_5(); duke@435: void addr_nop_7(); duke@435: void addr_nop_8(); duke@435: never@739: // Add Scalar Double-Precision Floating-Point Values never@739: void addsd(XMMRegister dst, Address src); never@739: void addsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Add Scalar Single-Precision Floating-Point Values never@739: void addss(XMMRegister dst, Address src); never@739: void addss(XMMRegister dst, XMMRegister src); never@739: never@739: void andl(Register dst, int32_t imm32); never@739: void andl(Register dst, Address src); never@739: void andl(Register dst, Register src); never@739: never@739: void andq(Register dst, int32_t imm32); never@739: void andq(Register dst, Address src); never@739: void andq(Register dst, Register src); never@739: never@739: never@739: // Bitwise Logical AND of Packed Double-Precision Floating-Point Values never@739: void andpd(XMMRegister dst, Address src); never@739: void andpd(XMMRegister dst, XMMRegister src); never@739: twisti@1210: void bsfl(Register dst, Register src); twisti@1210: void bsrl(Register dst, Register src); twisti@1210: twisti@1210: #ifdef _LP64 twisti@1210: void bsfq(Register dst, Register src); twisti@1210: void bsrq(Register dst, Register src); twisti@1210: #endif twisti@1210: never@739: void bswapl(Register reg); never@739: never@739: void bswapq(Register reg); never@739: duke@435: void call(Label& L, relocInfo::relocType rtype); duke@435: void call(Register reg); // push pc; pc <- reg duke@435: void call(Address adr); // push pc; pc <- adr duke@435: never@739: void cdql(); never@739: never@739: void cdqq(); never@739: never@739: void cld() { emit_byte(0xfc); } never@739: never@739: void clflush(Address adr); never@739: never@739: void cmovl(Condition cc, Register dst, Register src); never@739: void cmovl(Condition cc, Register dst, Address src); never@739: never@739: void cmovq(Condition cc, Register dst, Register src); never@739: void cmovq(Condition cc, Register dst, Address src); never@739: never@739: never@739: void cmpb(Address dst, int imm8); never@739: never@739: void cmpl(Address dst, int32_t imm32); never@739: never@739: void cmpl(Register dst, int32_t imm32); never@739: void cmpl(Register dst, Register src); never@739: void cmpl(Register dst, Address src); never@739: never@739: void cmpq(Address dst, int32_t imm32); never@739: void cmpq(Address dst, Register src); never@739: never@739: void cmpq(Register dst, int32_t imm32); never@739: void cmpq(Register dst, Register src); never@739: void cmpq(Register dst, Address src); never@739: never@739: // these are dummies used to catch attempting to convert NULL to Register never@739: void cmpl(Register dst, void* junk); // dummy never@739: void cmpq(Register dst, void* junk); // dummy never@739: never@739: void cmpw(Address dst, int imm16); never@739: never@739: void cmpxchg8 (Address adr); never@739: never@739: void cmpxchgl(Register reg, Address adr); never@739: never@739: void cmpxchgq(Register reg, Address adr); never@739: never@739: // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS never@739: void comisd(XMMRegister dst, Address src); never@739: never@739: // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS never@739: void comiss(XMMRegister dst, Address src); never@739: never@739: // Identify processor type and features never@739: void cpuid() { never@739: emit_byte(0x0F); never@739: emit_byte(0xA2); never@739: } never@739: never@739: // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value never@739: void cvtsd2ss(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value never@739: void cvtsi2sdl(XMMRegister dst, Register src); never@739: void cvtsi2sdq(XMMRegister dst, Register src); never@739: never@739: // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value never@739: void cvtsi2ssl(XMMRegister dst, Register src); never@739: void cvtsi2ssq(XMMRegister dst, Register src); never@739: never@739: // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value never@739: void cvtdq2pd(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value never@739: void cvtdq2ps(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value never@739: void cvtss2sd(XMMRegister dst, XMMRegister src); never@739: never@739: // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer never@739: void cvttsd2sil(Register dst, Address src); never@739: void cvttsd2sil(Register dst, XMMRegister src); never@739: void cvttsd2siq(Register dst, XMMRegister src); never@739: never@739: // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer never@739: void cvttss2sil(Register dst, XMMRegister src); never@739: void cvttss2siq(Register dst, XMMRegister src); never@739: never@739: // Divide Scalar Double-Precision Floating-Point Values never@739: void divsd(XMMRegister dst, Address src); never@739: void divsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Divide Scalar Single-Precision Floating-Point Values never@739: void divss(XMMRegister dst, Address src); never@739: void divss(XMMRegister dst, XMMRegister src); never@739: never@739: void emms(); never@739: never@739: void fabs(); never@739: never@739: void fadd(int i); never@739: never@739: void fadd_d(Address src); never@739: void fadd_s(Address src); never@739: never@739: // "Alternate" versions of x87 instructions place result down in FPU never@739: // stack instead of on TOS never@739: never@739: void fadda(int i); // "alternate" fadd never@739: void faddp(int i = 1); never@739: never@739: void fchs(); never@739: never@739: void fcom(int i); never@739: never@739: void fcomp(int i = 1); never@739: void fcomp_d(Address src); never@739: void fcomp_s(Address src); never@739: never@739: void fcompp(); never@739: never@739: void fcos(); never@739: never@739: void fdecstp(); never@739: never@739: void fdiv(int i); never@739: void fdiv_d(Address src); never@739: void fdivr_s(Address src); never@739: void fdiva(int i); // "alternate" fdiv never@739: void fdivp(int i = 1); never@739: never@739: void fdivr(int i); never@739: void fdivr_d(Address src); never@739: void fdiv_s(Address src); never@739: never@739: void fdivra(int i); // "alternate" reversed fdiv never@739: never@739: void fdivrp(int i = 1); never@739: never@739: void ffree(int i = 0); never@739: never@739: void fild_d(Address adr); never@739: void fild_s(Address adr); never@739: never@739: void fincstp(); never@739: never@739: void finit(); never@739: never@739: void fist_s (Address adr); never@739: void fistp_d(Address adr); never@739: void fistp_s(Address adr); never@739: never@739: void fld1(); never@739: never@739: void fld_d(Address adr); never@739: void fld_s(Address adr); never@739: void fld_s(int index); never@739: void fld_x(Address adr); // extended-precision (80-bit) format never@739: never@739: void fldcw(Address src); never@739: never@739: void fldenv(Address src); never@739: never@739: void fldlg2(); never@739: never@739: void fldln2(); never@739: never@739: void fldz(); never@739: never@739: void flog(); never@739: void flog10(); never@739: never@739: void fmul(int i); never@739: never@739: void fmul_d(Address src); never@739: void fmul_s(Address src); never@739: never@739: void fmula(int i); // "alternate" fmul never@739: never@739: void fmulp(int i = 1); never@739: never@739: void fnsave(Address dst); never@739: never@739: void fnstcw(Address src); never@739: never@739: void fnstsw_ax(); never@739: never@739: void fprem(); never@739: void fprem1(); never@739: never@739: void frstor(Address src); never@739: never@739: void fsin(); never@739: never@739: void fsqrt(); never@739: never@739: void fst_d(Address adr); never@739: void fst_s(Address adr); never@739: never@739: void fstp_d(Address adr); never@739: void fstp_d(int index); never@739: void fstp_s(Address adr); never@739: void fstp_x(Address adr); // extended-precision (80-bit) format never@739: never@739: void fsub(int i); never@739: void fsub_d(Address src); never@739: void fsub_s(Address src); never@739: never@739: void fsuba(int i); // "alternate" fsub never@739: never@739: void fsubp(int i = 1); never@739: never@739: void fsubr(int i); never@739: void fsubr_d(Address src); never@739: void fsubr_s(Address src); never@739: never@739: void fsubra(int i); // "alternate" reversed fsub never@739: never@739: void fsubrp(int i = 1); never@739: never@739: void ftan(); never@739: never@739: void ftst(); never@739: never@739: void fucomi(int i = 1); never@739: void fucomip(int i = 1); never@739: never@739: void fwait(); never@739: never@739: void fxch(int i = 1); never@739: never@739: void fxrstor(Address src); never@739: never@739: void fxsave(Address dst); never@739: never@739: void fyl2x(); never@739: never@739: void hlt(); never@739: never@739: void idivl(Register src); never@739: never@739: void idivq(Register src); never@739: never@739: void imull(Register dst, Register src); never@739: void imull(Register dst, Register src, int value); never@739: never@739: void imulq(Register dst, Register src); never@739: void imulq(Register dst, Register src, int value); never@739: duke@435: duke@435: // jcc is the generic conditional branch generator to run- duke@435: // time routines, jcc is used for branches to labels. jcc duke@435: // takes a branch opcode (cc) and a label (L) and generates duke@435: // either a backward branch or a forward branch and links it duke@435: // to the label fixup chain. Usage: duke@435: // duke@435: // Label L; // unbound label duke@435: // jcc(cc, L); // forward branch to unbound label duke@435: // bind(L); // bind label to the current pc duke@435: // jcc(cc, L); // backward branch to bound label duke@435: // bind(L); // illegal: a label may be bound only once duke@435: // duke@435: // Note: The same Label can be used for forward and backward branches duke@435: // but it may be bound only once. duke@435: duke@435: void jcc(Condition cc, Label& L, duke@435: relocInfo::relocType rtype = relocInfo::none); duke@435: duke@435: // Conditional jump to a 8-bit offset to L. duke@435: // WARNING: be very careful using this for forward jumps. If the label is duke@435: // not bound within an 8-bit offset of this instruction, a run-time error duke@435: // will occur. duke@435: void jccb(Condition cc, Label& L); duke@435: never@739: void jmp(Address entry); // pc <- entry never@739: never@739: // Label operations & relative jumps (PPUM Appendix D) never@739: void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L never@739: never@739: void jmp(Register entry); // pc <- entry never@739: never@739: // Unconditional 8-bit offset jump to L. never@739: // WARNING: be very careful using this for forward jumps. If the label is never@739: // not bound within an 8-bit offset of this instruction, a run-time error never@739: // will occur. never@739: void jmpb(Label& L); never@739: never@739: void ldmxcsr( Address src ); never@739: never@739: void leal(Register dst, Address src); never@739: never@739: void leaq(Register dst, Address src); never@739: never@739: void lfence() { never@739: emit_byte(0x0F); never@739: emit_byte(0xAE); never@739: emit_byte(0xE8); never@739: } never@739: never@739: void lock(); never@739: twisti@1210: void lzcntl(Register dst, Register src); twisti@1210: twisti@1210: #ifdef _LP64 twisti@1210: void lzcntq(Register dst, Register src); twisti@1210: #endif twisti@1210: never@739: enum Membar_mask_bits { never@739: StoreStore = 1 << 3, never@739: LoadStore = 1 << 2, never@739: StoreLoad = 1 << 1, never@739: LoadLoad = 1 << 0 never@739: }; never@739: never@1106: // Serializes memory and blows flags never@739: void membar(Membar_mask_bits order_constraint) { never@1106: if (os::is_MP()) { never@1106: // We only have to handle StoreLoad never@1106: if (order_constraint & StoreLoad) { never@1106: // All usable chips support "locked" instructions which suffice never@1106: // as barriers, and are much faster than the alternative of never@1106: // using cpuid instruction. We use here a locked add [esp],0. never@1106: // This is conveniently otherwise a no-op except for blowing never@1106: // flags. never@1106: // Any change to this code may need to revisit other places in never@1106: // the code where this idiom is used, in particular the never@1106: // orderAccess code. never@1106: lock(); never@1106: addl(Address(rsp, 0), 0);// Assert the lock# signal here never@1106: } never@1106: } never@739: } never@739: never@739: void mfence(); never@739: never@739: // Moves never@739: never@739: void mov64(Register dst, int64_t imm64); never@739: never@739: void movb(Address dst, Register src); never@739: void movb(Address dst, int imm8); never@739: void movb(Register dst, Address src); never@739: never@739: void movdl(XMMRegister dst, Register src); never@739: void movdl(Register dst, XMMRegister src); never@739: never@739: // Move Double Quadword never@739: void movdq(XMMRegister dst, Register src); never@739: void movdq(Register dst, XMMRegister src); never@739: never@739: // Move Aligned Double Quadword never@739: void movdqa(Address dst, XMMRegister src); never@739: void movdqa(XMMRegister dst, Address src); never@739: void movdqa(XMMRegister dst, XMMRegister src); never@739: kvn@840: // Move Unaligned Double Quadword kvn@840: void movdqu(Address dst, XMMRegister src); kvn@840: void movdqu(XMMRegister dst, Address src); kvn@840: void movdqu(XMMRegister dst, XMMRegister src); kvn@840: never@739: void movl(Register dst, int32_t imm32); never@739: void movl(Address dst, int32_t imm32); never@739: void movl(Register dst, Register src); never@739: void movl(Register dst, Address src); never@739: void movl(Address dst, Register src); never@739: never@739: // These dummies prevent using movl from converting a zero (like NULL) into Register never@739: // by giving the compiler two choices it can't resolve never@739: never@739: void movl(Address dst, void* junk); never@739: void movl(Register dst, void* junk); never@739: never@739: #ifdef _LP64 never@739: void movq(Register dst, Register src); never@739: void movq(Register dst, Address src); never@739: void movq(Address dst, Register src); never@739: #endif never@739: never@739: void movq(Address dst, MMXRegister src ); never@739: void movq(MMXRegister dst, Address src ); never@739: never@739: #ifdef _LP64 never@739: // These dummies prevent using movq from converting a zero (like NULL) into Register never@739: // by giving the compiler two choices it can't resolve never@739: never@739: void movq(Address dst, void* dummy); never@739: void movq(Register dst, void* dummy); never@739: #endif never@739: never@739: // Move Quadword never@739: void movq(Address dst, XMMRegister src); never@739: void movq(XMMRegister dst, Address src); never@739: never@739: void movsbl(Register dst, Address src); never@739: void movsbl(Register dst, Register src); never@739: never@739: #ifdef _LP64 twisti@1059: void movsbq(Register dst, Address src); twisti@1059: void movsbq(Register dst, Register src); twisti@1059: never@739: // Move signed 32bit immediate to 64bit extending sign never@739: void movslq(Address dst, int32_t imm64); never@739: void movslq(Register dst, int32_t imm64); never@739: never@739: void movslq(Register dst, Address src); never@739: void movslq(Register dst, Register src); never@739: void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous never@739: #endif never@739: never@739: void movswl(Register dst, Address src); never@739: void movswl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movswq(Register dst, Address src); twisti@1059: void movswq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void movw(Address dst, int imm16); never@739: void movw(Register dst, Address src); never@739: void movw(Address dst, Register src); never@739: never@739: void movzbl(Register dst, Address src); never@739: void movzbl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movzbq(Register dst, Address src); twisti@1059: void movzbq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void movzwl(Register dst, Address src); never@739: void movzwl(Register dst, Register src); never@739: twisti@1059: #ifdef _LP64 twisti@1059: void movzwq(Register dst, Address src); twisti@1059: void movzwq(Register dst, Register src); twisti@1059: #endif twisti@1059: never@739: void mull(Address src); never@739: void mull(Register src); never@739: never@739: // Multiply Scalar Double-Precision Floating-Point Values never@739: void mulsd(XMMRegister dst, Address src); never@739: void mulsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Multiply Scalar Single-Precision Floating-Point Values never@739: void mulss(XMMRegister dst, Address src); never@739: void mulss(XMMRegister dst, XMMRegister src); never@739: never@739: void negl(Register dst); never@739: never@739: #ifdef _LP64 never@739: void negq(Register dst); never@739: #endif never@739: never@739: void nop(int i = 1); never@739: never@739: void notl(Register dst); never@739: never@739: #ifdef _LP64 never@739: void notq(Register dst); never@739: #endif never@739: never@739: void orl(Address dst, int32_t imm32); never@739: void orl(Register dst, int32_t imm32); never@739: void orl(Register dst, Address src); never@739: void orl(Register dst, Register src); never@739: never@739: void orq(Address dst, int32_t imm32); never@739: void orq(Register dst, int32_t imm32); never@739: void orq(Register dst, Address src); never@739: void orq(Register dst, Register src); never@739: cfang@1116: // SSE4.2 string instructions cfang@1116: void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); cfang@1116: void pcmpestri(XMMRegister xmm1, Address src, int imm8); cfang@1116: never@739: void popl(Address dst); never@739: never@739: #ifdef _LP64 never@739: void popq(Address dst); never@739: #endif never@739: twisti@1078: void popcntl(Register dst, Address src); twisti@1078: void popcntl(Register dst, Register src); twisti@1078: twisti@1078: #ifdef _LP64 twisti@1078: void popcntq(Register dst, Address src); twisti@1078: void popcntq(Register dst, Register src); twisti@1078: #endif twisti@1078: never@739: // Prefetches (SSE, SSE2, 3DNOW only) never@739: never@739: void prefetchnta(Address src); never@739: void prefetchr(Address src); never@739: void prefetcht0(Address src); never@739: void prefetcht1(Address src); never@739: void prefetcht2(Address src); never@739: void prefetchw(Address src); never@739: never@739: // Shuffle Packed Doublewords never@739: void pshufd(XMMRegister dst, XMMRegister src, int mode); never@739: void pshufd(XMMRegister dst, Address src, int mode); never@739: never@739: // Shuffle Packed Low Words never@739: void pshuflw(XMMRegister dst, XMMRegister src, int mode); never@739: void pshuflw(XMMRegister dst, Address src, int mode); never@739: never@739: // Shift Right Logical Quadword Immediate never@739: void psrlq(XMMRegister dst, int shift); never@739: cfang@1116: // Logical Compare Double Quadword cfang@1116: void ptest(XMMRegister dst, XMMRegister src); cfang@1116: void ptest(XMMRegister dst, Address src); cfang@1116: never@739: // Interleave Low Bytes never@739: void punpcklbw(XMMRegister dst, XMMRegister src); never@739: never@739: void pushl(Address src); never@739: never@739: void pushq(Address src); never@739: never@739: // Xor Packed Byte Integer Values never@739: void pxor(XMMRegister dst, Address src); never@739: void pxor(XMMRegister dst, XMMRegister src); never@739: never@739: void rcll(Register dst, int imm8); never@739: never@739: void rclq(Register dst, int imm8); never@739: never@739: void ret(int imm16); duke@435: duke@435: void sahf(); duke@435: never@739: void sarl(Register dst, int imm8); never@739: void sarl(Register dst); never@739: never@739: void sarq(Register dst, int imm8); never@739: void sarq(Register dst); never@739: never@739: void sbbl(Address dst, int32_t imm32); never@739: void sbbl(Register dst, int32_t imm32); never@739: void sbbl(Register dst, Address src); never@739: void sbbl(Register dst, Register src); never@739: never@739: void sbbq(Address dst, int32_t imm32); never@739: void sbbq(Register dst, int32_t imm32); never@739: void sbbq(Register dst, Address src); never@739: void sbbq(Register dst, Register src); never@739: never@739: void setb(Condition cc, Register dst); never@739: never@739: void shldl(Register dst, Register src); never@739: never@739: void shll(Register dst, int imm8); never@739: void shll(Register dst); never@739: never@739: void shlq(Register dst, int imm8); never@739: void shlq(Register dst); never@739: never@739: void shrdl(Register dst, Register src); never@739: never@739: void shrl(Register dst, int imm8); never@739: void shrl(Register dst); never@739: never@739: void shrq(Register dst, int imm8); never@739: void shrq(Register dst); never@739: never@739: void smovl(); // QQQ generic? never@739: never@739: // Compute Square Root of Scalar Double-Precision Floating-Point Value never@739: void sqrtsd(XMMRegister dst, Address src); never@739: void sqrtsd(XMMRegister dst, XMMRegister src); never@739: never@739: void std() { emit_byte(0xfd); } never@739: never@739: void stmxcsr( Address dst ); never@739: never@739: void subl(Address dst, int32_t imm32); never@739: void subl(Address dst, Register src); never@739: void subl(Register dst, int32_t imm32); never@739: void subl(Register dst, Address src); never@739: void subl(Register dst, Register src); never@739: never@739: void subq(Address dst, int32_t imm32); never@739: void subq(Address dst, Register src); never@739: void subq(Register dst, int32_t imm32); never@739: void subq(Register dst, Address src); never@739: void subq(Register dst, Register src); never@739: never@739: never@739: // Subtract Scalar Double-Precision Floating-Point Values never@739: void subsd(XMMRegister dst, Address src); never@739: void subsd(XMMRegister dst, XMMRegister src); never@739: never@739: // Subtract Scalar Single-Precision Floating-Point Values never@739: void subss(XMMRegister dst, Address src); duke@435: void subss(XMMRegister dst, XMMRegister src); never@739: never@739: void testb(Register dst, int imm8); never@739: never@739: void testl(Register dst, int32_t imm32); never@739: void testl(Register dst, Register src); never@739: void testl(Register dst, Address src); never@739: never@739: void testq(Register dst, int32_t imm32); never@739: void testq(Register dst, Register src); never@739: never@739: never@739: // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS never@739: void ucomisd(XMMRegister dst, Address src); never@739: void ucomisd(XMMRegister dst, XMMRegister src); never@739: never@739: // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS never@739: void ucomiss(XMMRegister dst, Address src); duke@435: void ucomiss(XMMRegister dst, XMMRegister src); never@739: never@739: void xaddl(Address dst, Register src); never@739: never@739: void xaddq(Address dst, Register src); never@739: never@739: void xchgl(Register reg, Address adr); never@739: void xchgl(Register dst, Register src); never@739: never@739: void xchgq(Register reg, Address adr); never@739: void xchgq(Register dst, Register src); never@739: never@739: void xorl(Register dst, int32_t imm32); never@739: void xorl(Register dst, Address src); never@739: void xorl(Register dst, Register src); never@739: never@739: void xorq(Register dst, Address src); never@739: void xorq(Register dst, Register src); never@739: never@739: // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values never@739: void xorpd(XMMRegister dst, Address src); never@739: void xorpd(XMMRegister dst, XMMRegister src); never@739: never@739: // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values never@739: void xorps(XMMRegister dst, Address src); duke@435: void xorps(XMMRegister dst, XMMRegister src); never@739: never@739: void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 duke@435: }; duke@435: duke@435: duke@435: // MacroAssembler extends Assembler by frequently used macros. duke@435: // duke@435: // Instructions for which a 'better' code sequence exists depending duke@435: // on arguments should also go in here. duke@435: duke@435: class MacroAssembler: public Assembler { ysr@777: friend class LIR_Assembler; ysr@777: friend class Runtime1; // as_Address() duke@435: protected: duke@435: duke@435: Address as_Address(AddressLiteral adr); duke@435: Address as_Address(ArrayAddress adr); duke@435: duke@435: // Support for VM calls duke@435: // duke@435: // This is the base routine called by the different versions of call_VM_leaf. The interpreter duke@435: // may customize this version by overriding it for its purposes (e.g., to save/restore duke@435: // additional registers when doing a VM call). duke@435: #ifdef CC_INTERP duke@435: // c++ interpreter never wants to use interp_masm version of call_VM duke@435: #define VIRTUAL duke@435: #else duke@435: #define VIRTUAL virtual duke@435: #endif duke@435: duke@435: VIRTUAL void call_VM_leaf_base( duke@435: address entry_point, // the entry point duke@435: int number_of_arguments // the number of arguments to pop after the call duke@435: ); duke@435: duke@435: // This is the base routine called by the different versions of call_VM. The interpreter duke@435: // may customize this version by overriding it for its purposes (e.g., to save/restore duke@435: // additional registers when doing a VM call). duke@435: // duke@435: // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base duke@435: // returns the register which contains the thread upon return. If a thread register has been duke@435: // specified, the return value will correspond to that register. If no last_java_sp is specified duke@435: // (noreg) than rsp will be used instead. duke@435: VIRTUAL void call_VM_base( // returns the register containing the thread upon return duke@435: Register oop_result, // where an oop-result ends up if any; use noreg otherwise duke@435: Register java_thread, // the thread if computed before ; use noreg otherwise duke@435: Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise duke@435: address entry_point, // the entry point duke@435: int number_of_arguments, // the number of arguments (w/o thread) to pop after the call duke@435: bool check_exceptions // whether to check for pending exceptions after return duke@435: ); duke@435: duke@435: // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. duke@435: // The implementation is only non-empty for the InterpreterMacroAssembler, duke@435: // as only the interpreter handles PopFrame and ForceEarlyReturn requests. duke@435: virtual void check_and_handle_popframe(Register java_thread); duke@435: virtual void check_and_handle_earlyret(Register java_thread); duke@435: duke@435: void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); duke@435: duke@435: // helpers for FPU flag access duke@435: // tmp is a temporary register, if none is available use noreg duke@435: void save_rax (Register tmp); duke@435: void restore_rax(Register tmp); duke@435: duke@435: public: duke@435: MacroAssembler(CodeBuffer* code) : Assembler(code) {} duke@435: duke@435: // Support for NULL-checks duke@435: // duke@435: // Generates code that causes a NULL OS exception if the content of reg is NULL. duke@435: // If the accessed location is M[reg + offset] and the offset is known, provide the duke@435: // offset. No explicit code generation is needed if the offset is within a certain duke@435: // range (0 <= offset <= page_size). duke@435: duke@435: void null_check(Register reg, int offset = -1); kvn@603: static bool needs_explicit_null_check(intptr_t offset); duke@435: duke@435: // Required platform-specific helpers for Label::patch_instructions. duke@435: // They _shadow_ the declarations in AbstractAssembler, which are undefined. duke@435: void pd_patch_instruction(address branch, address target); duke@435: #ifndef PRODUCT duke@435: static void pd_print_patched_instruction(address branch); duke@435: #endif duke@435: duke@435: // The following 4 methods return the offset of the appropriate move instruction duke@435: jrose@1057: // Support for fast byte/short loading with zero extension (depending on particular CPU) duke@435: int load_unsigned_byte(Register dst, Address src); jrose@1057: int load_unsigned_short(Register dst, Address src); jrose@1057: jrose@1057: // Support for fast byte/short loading with sign extension (depending on particular CPU) duke@435: int load_signed_byte(Register dst, Address src); jrose@1057: int load_signed_short(Register dst, Address src); duke@435: duke@435: // Support for sign-extension (hi:lo = extend_sign(lo)) duke@435: void extend_sign(Register hi, Register lo); duke@435: jrose@1057: // Loading values by size and signed-ness jrose@1057: void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed); jrose@1057: duke@435: // Support for inc/dec with optimal instruction selection depending on value never@739: never@739: void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } never@739: void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } never@739: never@739: void decrementl(Address dst, int value = 1); never@739: void decrementl(Register reg, int value = 1); never@739: never@739: void decrementq(Register reg, int value = 1); never@739: void decrementq(Address dst, int value = 1); never@739: never@739: void incrementl(Address dst, int value = 1); never@739: void incrementl(Register reg, int value = 1); never@739: never@739: void incrementq(Register reg, int value = 1); never@739: void incrementq(Address dst, int value = 1); never@739: duke@435: duke@435: // Support optimal SSE move instructions. duke@435: void movflt(XMMRegister dst, XMMRegister src) { duke@435: if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } duke@435: else { movss (dst, src); return; } duke@435: } duke@435: void movflt(XMMRegister dst, Address src) { movss(dst, src); } duke@435: void movflt(XMMRegister dst, AddressLiteral src); duke@435: void movflt(Address dst, XMMRegister src) { movss(dst, src); } duke@435: duke@435: void movdbl(XMMRegister dst, XMMRegister src) { duke@435: if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } duke@435: else { movsd (dst, src); return; } duke@435: } duke@435: duke@435: void movdbl(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void movdbl(XMMRegister dst, Address src) { duke@435: if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } duke@435: else { movlpd(dst, src); return; } duke@435: } duke@435: void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } duke@435: never@739: void incrementl(AddressLiteral dst); never@739: void incrementl(ArrayAddress dst); duke@435: duke@435: // Alignment duke@435: void align(int modulus); duke@435: duke@435: // Misc duke@435: void fat_nop(); // 5 byte nop duke@435: duke@435: // Stack frame creation/removal duke@435: void enter(); duke@435: void leave(); duke@435: duke@435: // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) duke@435: // The pointer will be loaded into the thread register. duke@435: void get_thread(Register thread); duke@435: apetrusenko@797: duke@435: // Support for VM calls duke@435: // duke@435: // It is imperative that all calls into the VM are handled via the call_VM macros. duke@435: // They make sure that the stack linkage is setup correctly. call_VM's correspond duke@435: // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. duke@435: never@739: never@739: void call_VM(Register oop_result, never@739: address entry_point, never@739: bool check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: address entry_point, never@739: Register arg_1, never@739: bool check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: address entry_point, never@739: Register arg_1, Register arg_2, never@739: bool check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: address entry_point, never@739: Register arg_1, Register arg_2, Register arg_3, never@739: bool check_exceptions = true); never@739: never@739: // Overloadings with last_Java_sp never@739: void call_VM(Register oop_result, never@739: Register last_java_sp, never@739: address entry_point, never@739: int number_of_arguments = 0, never@739: bool check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: Register last_java_sp, never@739: address entry_point, never@739: Register arg_1, bool never@739: check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: Register last_java_sp, never@739: address entry_point, never@739: Register arg_1, Register arg_2, never@739: bool check_exceptions = true); never@739: void call_VM(Register oop_result, never@739: Register last_java_sp, never@739: address entry_point, never@739: Register arg_1, Register arg_2, Register arg_3, never@739: bool check_exceptions = true); never@739: never@739: void call_VM_leaf(address entry_point, never@739: int number_of_arguments = 0); never@739: void call_VM_leaf(address entry_point, never@739: Register arg_1); never@739: void call_VM_leaf(address entry_point, never@739: Register arg_1, Register arg_2); never@739: void call_VM_leaf(address entry_point, never@739: Register arg_1, Register arg_2, Register arg_3); duke@435: duke@435: // last Java Frame (fills frame anchor) never@739: void set_last_Java_frame(Register thread, never@739: Register last_java_sp, never@739: Register last_java_fp, never@739: address last_java_pc); never@739: never@739: // thread in the default location (r15_thread on 64bit) never@739: void set_last_Java_frame(Register last_java_sp, never@739: Register last_java_fp, never@739: address last_java_pc); never@739: duke@435: void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); duke@435: never@739: // thread in the default location (r15_thread on 64bit) never@739: void reset_last_Java_frame(bool clear_fp, bool clear_pc); never@739: duke@435: // Stores duke@435: void store_check(Register obj); // store check for obj - register is destroyed afterwards duke@435: void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) duke@435: apetrusenko@797: void g1_write_barrier_pre(Register obj, apetrusenko@797: #ifndef _LP64 apetrusenko@797: Register thread, apetrusenko@797: #endif apetrusenko@797: Register tmp, apetrusenko@797: Register tmp2, apetrusenko@797: bool tosca_live); apetrusenko@797: void g1_write_barrier_post(Register store_addr, apetrusenko@797: Register new_val, apetrusenko@797: #ifndef _LP64 apetrusenko@797: Register thread, apetrusenko@797: #endif apetrusenko@797: Register tmp, apetrusenko@797: Register tmp2); ysr@777: ysr@777: duke@435: // split store_check(Register obj) to enhance instruction interleaving duke@435: void store_check_part_1(Register obj); duke@435: void store_check_part_2(Register obj); duke@435: duke@435: // C 'boolean' to Java boolean: x == 0 ? 0 : 1 duke@435: void c2bool(Register x); duke@435: duke@435: // C++ bool manipulation duke@435: duke@435: void movbool(Register dst, Address src); duke@435: void movbool(Address dst, bool boolconst); duke@435: void movbool(Address dst, Register src); duke@435: void testbool(Register dst); duke@435: never@739: // oop manipulations never@739: void load_klass(Register dst, Register src); never@739: void store_klass(Register dst, Register src); never@739: never@739: void load_prototype_header(Register dst, Register src); never@739: never@739: #ifdef _LP64 never@739: void store_klass_gap(Register dst, Register src); never@739: never@739: void load_heap_oop(Register dst, Address src); never@739: void store_heap_oop(Address dst, Register src); johnc@1482: johnc@1482: // This dummy is to prevent a call to store_heap_oop from johnc@1482: // converting a zero (like NULL) into a Register by giving johnc@1482: // the compiler two choices it can't resolve johnc@1482: johnc@1482: void store_heap_oop(Address dst, void* dummy); johnc@1482: johnc@1482: // Used for storing NULL. All other oop constants should be johnc@1482: // stored using routines that take a jobject. johnc@1482: void store_heap_oop_null(Address dst); johnc@1482: never@739: void encode_heap_oop(Register r); never@739: void decode_heap_oop(Register r); never@739: void encode_heap_oop_not_null(Register r); never@739: void decode_heap_oop_not_null(Register r); never@739: void encode_heap_oop_not_null(Register dst, Register src); never@739: void decode_heap_oop_not_null(Register dst, Register src); never@739: never@739: void set_narrow_oop(Register dst, jobject obj); kvn@1077: void set_narrow_oop(Address dst, jobject obj); kvn@1077: void cmp_narrow_oop(Register dst, jobject obj); kvn@1077: void cmp_narrow_oop(Address dst, jobject obj); never@739: never@739: // if heap base register is used - reinit it with the correct value never@739: void reinit_heapbase(); never@739: #endif // _LP64 never@739: never@739: // Int division/remainder for Java duke@435: // (as idivl, but checks for special case as described in JVM spec.) duke@435: // returns idivl instruction offset for implicit exception handling duke@435: int corrected_idivl(Register reg); duke@435: never@739: // Long division/remainder for Java never@739: // (as idivq, but checks for special case as described in JVM spec.) never@739: // returns idivq instruction offset for implicit exception handling never@739: int corrected_idivq(Register reg); never@739: duke@435: void int3(); duke@435: never@739: // Long operation macros for a 32bit cpu duke@435: // Long negation for Java duke@435: void lneg(Register hi, Register lo); duke@435: duke@435: // Long multiplication for Java never@739: // (destroys contents of eax, ebx, ecx and edx) duke@435: void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y duke@435: duke@435: // Long shifts for Java duke@435: // (semantics as described in JVM spec.) duke@435: void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) duke@435: void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) duke@435: duke@435: // Long compare for Java duke@435: // (semantics as described in JVM spec.) duke@435: void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) duke@435: never@739: never@739: // misc never@739: never@739: // Sign extension never@739: void sign_extend_short(Register reg); never@739: void sign_extend_byte(Register reg); never@739: never@739: // Division by power of 2, rounding towards 0 never@739: void division_with_shift(Register reg, int shift_value); never@739: duke@435: // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: duke@435: // duke@435: // CF (corresponds to C0) if x < y duke@435: // PF (corresponds to C2) if unordered duke@435: // ZF (corresponds to C3) if x = y duke@435: // duke@435: // The arguments are in reversed order on the stack (i.e., top of stack is first argument). duke@435: // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) duke@435: void fcmp(Register tmp); duke@435: // Variant of the above which allows y to be further down the stack duke@435: // and which only pops x and y if specified. If pop_right is duke@435: // specified then pop_left must also be specified. duke@435: void fcmp(Register tmp, int index, bool pop_left, bool pop_right); duke@435: duke@435: // Floating-point comparison for Java duke@435: // Compares the top-most stack entries on the FPU stack and stores the result in dst. duke@435: // The arguments are in reversed order on the stack (i.e., top of stack is first argument). duke@435: // (semantics as described in JVM spec.) duke@435: void fcmp2int(Register dst, bool unordered_is_less); duke@435: // Variant of the above which allows y to be further down the stack duke@435: // and which only pops x and y if specified. If pop_right is duke@435: // specified then pop_left must also be specified. duke@435: void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); duke@435: duke@435: // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) duke@435: // tmp is a temporary register, if none is available use noreg duke@435: void fremr(Register tmp); duke@435: duke@435: duke@435: // same as fcmp2int, but using SSE2 duke@435: void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); duke@435: void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); duke@435: duke@435: // Inlined sin/cos generator for Java; must not use CPU instruction duke@435: // directly on Intel as it does not have high enough precision duke@435: // outside of the range [-pi/4, pi/4]. Extra argument indicate the duke@435: // number of FPU stack slots in use; all but the topmost will duke@435: // require saving if a slow case is necessary. Assumes argument is duke@435: // on FP TOS; result is on FP TOS. No cpu registers are changed by duke@435: // this code. duke@435: void trigfunc(char trig, int num_fpu_regs_in_use = 1); duke@435: duke@435: // branch to L if FPU flag C2 is set/not set duke@435: // tmp is a temporary register, if none is available use noreg duke@435: void jC2 (Register tmp, Label& L); duke@435: void jnC2(Register tmp, Label& L); duke@435: duke@435: // Pop ST (ffree & fincstp combined) duke@435: void fpop(); duke@435: duke@435: // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack duke@435: void push_fTOS(); duke@435: duke@435: // pops double TOS element from CPU stack and pushes on FPU stack duke@435: void pop_fTOS(); duke@435: duke@435: void empty_FPU_stack(); duke@435: duke@435: void push_IU_state(); duke@435: void pop_IU_state(); duke@435: duke@435: void push_FPU_state(); duke@435: void pop_FPU_state(); duke@435: duke@435: void push_CPU_state(); duke@435: void pop_CPU_state(); duke@435: duke@435: // Round up to a power of two duke@435: void round_to(Register reg, int modulus); duke@435: duke@435: // Callee saved registers handling duke@435: void push_callee_saved_registers(); duke@435: void pop_callee_saved_registers(); duke@435: duke@435: // allocation duke@435: void eden_allocate( duke@435: Register obj, // result: pointer to object after successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at compile time duke@435: Register t1, // temp register duke@435: Label& slow_case // continuation point if fast allocation fails duke@435: ); duke@435: void tlab_allocate( duke@435: Register obj, // result: pointer to object after successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at compile time duke@435: Register t1, // temp register duke@435: Register t2, // temp register duke@435: Label& slow_case // continuation point if fast allocation fails duke@435: ); duke@435: void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); duke@435: jrose@1058: // interface method calling jrose@1058: void lookup_interface_method(Register recv_klass, jrose@1058: Register intf_klass, jrose@1100: RegisterOrConstant itable_index, jrose@1058: Register method_result, jrose@1058: Register scan_temp, jrose@1058: Label& no_such_interface); jrose@1058: jrose@1079: // Test sub_klass against super_klass, with fast and slow paths. jrose@1079: jrose@1079: // The fast path produces a tri-state answer: yes / no / maybe-slow. jrose@1079: // One of the three labels can be NULL, meaning take the fall-through. jrose@1079: // If super_check_offset is -1, the value is loaded up from super_klass. jrose@1079: // No registers are killed, except temp_reg. jrose@1079: void check_klass_subtype_fast_path(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Label* L_success, jrose@1079: Label* L_failure, jrose@1079: Label* L_slow_path, jrose@1100: RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); jrose@1079: jrose@1079: // The rest of the type check; must be wired to a corresponding fast path. jrose@1079: // It does not repeat the fast path logic, so don't use it standalone. jrose@1079: // The temp_reg and temp2_reg can be noreg, if no temps are available. jrose@1079: // Updates the sub's secondary super cache as necessary. jrose@1079: // If set_cond_codes, condition codes will be Z on success, NZ on failure. jrose@1079: void check_klass_subtype_slow_path(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Register temp2_reg, jrose@1079: Label* L_success, jrose@1079: Label* L_failure, jrose@1079: bool set_cond_codes = false); jrose@1079: jrose@1079: // Simplified, combined version, good for typical uses. jrose@1079: // Falls through on failure. jrose@1079: void check_klass_subtype(Register sub_klass, jrose@1079: Register super_klass, jrose@1079: Register temp_reg, jrose@1079: Label& L_success); jrose@1079: jrose@1145: // method handles (JSR 292) jrose@1145: void check_method_handle_type(Register mtype_reg, Register mh_reg, jrose@1145: Register temp_reg, jrose@1145: Label& wrong_method_type); jrose@1145: void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, jrose@1145: Register temp_reg); jrose@1145: void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); jrose@1145: Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); jrose@1145: jrose@1145: duke@435: //---- duke@435: void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 duke@435: duke@435: // Debugging never@739: never@739: // only if +VerifyOops never@739: void verify_oop(Register reg, const char* s = "broken oop"); duke@435: void verify_oop_addr(Address addr, const char * s = "broken oop addr"); duke@435: never@739: // only if +VerifyFPU never@739: void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); never@739: never@739: // prints msg, dumps registers and stops execution never@739: void stop(const char* msg); never@739: never@739: // prints msg and continues never@739: void warn(const char* msg); never@739: never@739: static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); never@739: static void debug64(char* msg, int64_t pc, int64_t regs[]); never@739: duke@435: void os_breakpoint(); never@739: duke@435: void untested() { stop("untested"); } never@739: duke@435: void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); } never@739: duke@435: void should_not_reach_here() { stop("should not reach here"); } never@739: duke@435: void print_CPU_state(); duke@435: duke@435: // Stack overflow checking duke@435: void bang_stack_with_offset(int offset) { duke@435: // stack grows down, caller passes positive offset duke@435: assert(offset > 0, "must bang with negative offset"); duke@435: movl(Address(rsp, (-offset)), rax); duke@435: } duke@435: duke@435: // Writes to stack successive pages until offset reached to check for duke@435: // stack overflow + shadow pages. Also, clobbers tmp duke@435: void bang_stack_size(Register size, Register tmp); duke@435: jrose@1100: virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, jrose@1100: Register tmp, jrose@1100: int offset); jrose@1057: duke@435: // Support for serializing memory accesses between threads duke@435: void serialize_memory(Register thread, Register tmp); duke@435: duke@435: void verify_tlab(); duke@435: duke@435: // Biased locking support duke@435: // lock_reg and obj_reg must be loaded up with the appropriate values. duke@435: // swap_reg must be rax, and is killed. duke@435: // tmp_reg is optional. If it is supplied (i.e., != noreg) it will duke@435: // be killed; if not supplied, push/pop will be used internally to duke@435: // allocate a temporary (inefficient, avoid if possible). duke@435: // Optional slow case is for implementations (interpreter and C1) which branch to duke@435: // slow case directly. Leaves condition codes set for C2's Fast_Lock node. duke@435: // Returns offset of first potentially-faulting instruction for null duke@435: // check info (currently consumed only by C1). If duke@435: // swap_reg_contains_mark is true then returns -1 as it is assumed duke@435: // the calling code has already passed any potential faults. kvn@855: int biased_locking_enter(Register lock_reg, Register obj_reg, kvn@855: Register swap_reg, Register tmp_reg, duke@435: bool swap_reg_contains_mark, duke@435: Label& done, Label* slow_case = NULL, duke@435: BiasedLockingCounters* counters = NULL); duke@435: void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); duke@435: duke@435: duke@435: Condition negate_condition(Condition cond); duke@435: duke@435: // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit duke@435: // operands. In general the names are modified to avoid hiding the instruction in Assembler duke@435: // so that we don't need to implement all the varieties in the Assembler with trivial wrappers duke@435: // here in MacroAssembler. The major exception to this rule is call duke@435: duke@435: // Arithmetics duke@435: never@739: never@739: void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } never@739: void addptr(Address dst, Register src); never@739: never@739: void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } never@739: void addptr(Register dst, int32_t src); never@739: void addptr(Register dst, Register src); never@739: never@739: void andptr(Register dst, int32_t src); never@739: void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } never@739: never@739: void cmp8(AddressLiteral src1, int imm); never@739: never@739: // renamed to drag out the casting of address to int32_t/intptr_t duke@435: void cmp32(Register src1, int32_t imm); duke@435: duke@435: void cmp32(AddressLiteral src1, int32_t imm); duke@435: // compare reg - mem, or reg - &mem duke@435: void cmp32(Register src1, AddressLiteral src2); duke@435: duke@435: void cmp32(Register src1, Address src2); duke@435: never@739: #ifndef _LP64 never@739: void cmpoop(Address dst, jobject obj); never@739: void cmpoop(Register dst, jobject obj); never@739: #endif // _LP64 never@739: duke@435: // NOTE src2 must be the lval. This is NOT an mem-mem compare duke@435: void cmpptr(Address src1, AddressLiteral src2); duke@435: duke@435: void cmpptr(Register src1, AddressLiteral src2); duke@435: never@739: void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } never@739: void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } never@739: // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } never@739: never@739: void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } never@739: void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } never@739: never@739: // cmp64 to avoild hiding cmpq never@739: void cmp64(Register src1, AddressLiteral src); never@739: never@739: void cmpxchgptr(Register reg, Address adr); never@739: never@739: void locked_cmpxchgptr(Register reg, AddressLiteral adr); never@739: never@739: never@739: void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } never@739: never@739: never@739: void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } never@739: never@739: void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } never@739: never@739: void shlptr(Register dst, int32_t shift); never@739: void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } never@739: never@739: void shrptr(Register dst, int32_t shift); never@739: void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } never@739: never@739: void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } never@739: void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } never@739: never@739: void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } never@739: never@739: void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } never@739: void subptr(Register dst, int32_t src); never@739: void subptr(Register dst, Register src); never@739: never@739: never@739: void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } never@739: void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } never@739: never@739: void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } never@739: void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } never@739: never@739: void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } never@739: never@739: duke@435: duke@435: // Helper functions for statistics gathering. duke@435: // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. duke@435: void cond_inc32(Condition cond, AddressLiteral counter_addr); duke@435: // Unconditional atomic increment. duke@435: void atomic_incl(AddressLiteral counter_addr); duke@435: duke@435: void lea(Register dst, AddressLiteral adr); duke@435: void lea(Address dst, AddressLiteral adr); never@739: void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } never@739: never@739: void leal32(Register dst, Address src) { leal(dst, src); } never@739: never@739: void test32(Register src1, AddressLiteral src2); never@739: never@739: void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } never@739: void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } never@739: void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } never@739: never@739: void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } never@739: void testptr(Register src1, Register src2); never@739: never@739: void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } never@739: void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } duke@435: duke@435: // Calls duke@435: duke@435: void call(Label& L, relocInfo::relocType rtype); duke@435: void call(Register entry); duke@435: duke@435: // NOTE: this call tranfers to the effective address of entry NOT duke@435: // the address contained by entry. This is because this is more natural duke@435: // for jumps/calls. duke@435: void call(AddressLiteral entry); duke@435: duke@435: // Jumps duke@435: duke@435: // NOTE: these jumps tranfer to the effective address of dst NOT duke@435: // the address contained by dst. This is because this is more natural duke@435: // for jumps/calls. duke@435: void jump(AddressLiteral dst); duke@435: void jump_cc(Condition cc, AddressLiteral dst); duke@435: duke@435: // 32bit can do a case table jump in one instruction but we no longer allow the base duke@435: // to be installed in the Address class. This jump will tranfers to the address duke@435: // contained in the location described by entry (not the address of entry) duke@435: void jump(ArrayAddress entry); duke@435: duke@435: // Floating duke@435: duke@435: void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } duke@435: void andpd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } duke@435: void comiss(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } duke@435: void comisd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void fldcw(Address src) { Assembler::fldcw(src); } duke@435: void fldcw(AddressLiteral src); duke@435: duke@435: void fld_s(int index) { Assembler::fld_s(index); } duke@435: void fld_s(Address src) { Assembler::fld_s(src); } duke@435: void fld_s(AddressLiteral src); duke@435: duke@435: void fld_d(Address src) { Assembler::fld_d(src); } duke@435: void fld_d(AddressLiteral src); duke@435: duke@435: void fld_x(Address src) { Assembler::fld_x(src); } duke@435: void fld_x(AddressLiteral src); duke@435: duke@435: void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } duke@435: void ldmxcsr(AddressLiteral src); duke@435: never@739: private: never@739: // these are private because users should be doing movflt/movdbl never@739: duke@435: void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } duke@435: void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } duke@435: void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } duke@435: void movss(XMMRegister dst, AddressLiteral src); duke@435: never@739: void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } never@739: void movlpd(XMMRegister dst, AddressLiteral src); never@739: never@739: public: never@739: duke@435: void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } duke@435: void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } duke@435: void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } duke@435: void movsd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } duke@435: void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } duke@435: void ucomiss(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } duke@435: void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } duke@435: void ucomisd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values duke@435: void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } duke@435: void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } duke@435: void xorpd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values duke@435: void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } duke@435: void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } duke@435: void xorps(XMMRegister dst, AddressLiteral src); duke@435: duke@435: // Data duke@435: never@739: void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } never@739: never@739: void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } never@739: void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } never@739: duke@435: void movoop(Register dst, jobject obj); duke@435: void movoop(Address dst, jobject obj); duke@435: duke@435: void movptr(ArrayAddress dst, Register src); duke@435: // can this do an lea? duke@435: void movptr(Register dst, ArrayAddress src); duke@435: never@739: void movptr(Register dst, Address src); never@739: duke@435: void movptr(Register dst, AddressLiteral src); duke@435: never@739: void movptr(Register dst, intptr_t src); never@739: void movptr(Register dst, Register src); never@739: void movptr(Address dst, intptr_t src); never@739: never@739: void movptr(Address dst, Register src); never@739: never@739: #ifdef _LP64 never@739: // Generally the next two are only used for moving NULL never@739: // Although there are situations in initializing the mark word where never@739: // they could be used. They are dangerous. never@739: never@739: // They only exist on LP64 so that int32_t and intptr_t are not the same never@739: // and we have ambiguous declarations. never@739: never@739: void movptr(Address dst, int32_t imm32); never@739: void movptr(Register dst, int32_t imm32); never@739: #endif // _LP64 never@739: duke@435: // to avoid hiding movl duke@435: void mov32(AddressLiteral dst, Register src); duke@435: void mov32(Register dst, AddressLiteral src); never@739: duke@435: // to avoid hiding movb duke@435: void movbyte(ArrayAddress dst, int src); duke@435: duke@435: // Can push value or effective address duke@435: void pushptr(AddressLiteral src); duke@435: never@739: void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } never@739: void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } never@739: never@739: void pushoop(jobject obj); never@739: never@739: // sign extend as need a l to ptr sized element never@739: void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } never@739: void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } never@739: kvn@1421: // IndexOf strings. kvn@1421: void string_indexof(Register str1, Register str2, kvn@1421: Register cnt1, Register cnt2, Register result, kvn@1421: XMMRegister vec, Register tmp); kvn@1421: kvn@1421: // Compare strings. kvn@1421: void string_compare(Register str1, Register str2, kvn@1421: Register cnt1, Register cnt2, Register result, kvn@1421: XMMRegister vec1, XMMRegister vec2); kvn@1421: kvn@1421: // Compare char[] arrays. kvn@1421: void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, kvn@1421: Register limit, Register result, Register chr, kvn@1421: XMMRegister vec1, XMMRegister vec2); never@739: duke@435: #undef VIRTUAL duke@435: duke@435: }; duke@435: duke@435: /** duke@435: * class SkipIfEqual: duke@435: * duke@435: * Instantiating this class will result in assembly code being output that will duke@435: * jump around any code emitted between the creation of the instance and it's duke@435: * automatic destruction at the end of a scope block, depending on the value of duke@435: * the flag passed to the constructor, which will be checked at run-time. duke@435: */ duke@435: class SkipIfEqual { duke@435: private: duke@435: MacroAssembler* _masm; duke@435: Label _label; duke@435: duke@435: public: duke@435: SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); duke@435: ~SkipIfEqual(); duke@435: }; duke@435: duke@435: #ifdef ASSERT duke@435: inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } duke@435: #endif