duke@435: /* duke@435: * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: class BiasedLockingCounters; duke@435: duke@435: // Contains all the definitions needed for amd64 assembly code generation. duke@435: duke@435: #ifdef _LP64 duke@435: // Calling convention duke@435: class Argument VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum { duke@435: #ifdef _WIN64 duke@435: n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) duke@435: #else duke@435: n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) duke@435: n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) coleenp@548: #endif // _WIN64 duke@435: n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... duke@435: n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... duke@435: }; duke@435: }; duke@435: duke@435: duke@435: // Symbolically name the register arguments used by the c calling convention. duke@435: // Windows is different from linux/solaris. So much for standards... duke@435: duke@435: #ifdef _WIN64 duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg2, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg3, r9); duke@435: duke@435: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); duke@435: duke@435: #else duke@435: duke@435: REGISTER_DECLARATION(Register, c_rarg0, rdi); duke@435: REGISTER_DECLARATION(Register, c_rarg1, rsi); duke@435: REGISTER_DECLARATION(Register, c_rarg2, rdx); duke@435: REGISTER_DECLARATION(Register, c_rarg3, rcx); duke@435: REGISTER_DECLARATION(Register, c_rarg4, r8); duke@435: REGISTER_DECLARATION(Register, c_rarg5, r9); duke@435: duke@435: REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); duke@435: REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); duke@435: coleenp@548: #endif // _WIN64 duke@435: duke@435: // Symbolically name the register arguments used by the Java calling convention. duke@435: // We have control over the convention for java so we can do what we please. duke@435: // What pleases us is to offset the java calling convention so that when duke@435: // we call a suitable jni method the arguments are lined up and we don't duke@435: // have to do little shuffling. A suitable jni method is non-static and a duke@435: // small number of arguments (two fewer args on windows) duke@435: // duke@435: // |-------------------------------------------------------| duke@435: // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | duke@435: // |-------------------------------------------------------| duke@435: // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) duke@435: // | rdi rsi rdx rcx r8 r9 | solaris/linux duke@435: // |-------------------------------------------------------| duke@435: // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | duke@435: // |-------------------------------------------------------| duke@435: duke@435: REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); duke@435: REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); duke@435: REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); duke@435: // Windows runs out of register args here duke@435: #ifdef _WIN64 duke@435: REGISTER_DECLARATION(Register, j_rarg3, rdi); duke@435: REGISTER_DECLARATION(Register, j_rarg4, rsi); duke@435: #else duke@435: REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); duke@435: REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); coleenp@548: #endif // _WIN64 duke@435: REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); duke@435: duke@435: REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); duke@435: REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); duke@435: duke@435: REGISTER_DECLARATION(Register, rscratch1, r10); // volatile duke@435: REGISTER_DECLARATION(Register, rscratch2, r11); // volatile duke@435: coleenp@548: REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved coleenp@548: REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved duke@435: duke@435: #endif // _LP64 duke@435: duke@435: // Address is an abstraction used to represent a memory location duke@435: // using any of the amd64 addressing modes with one object. duke@435: // duke@435: // Note: A register location is represented via a Register, not duke@435: // via an address for efficiency & simplicity reasons. duke@435: duke@435: class ArrayAddress; duke@435: duke@435: class Address VALUE_OBJ_CLASS_SPEC { duke@435: public: duke@435: enum ScaleFactor { duke@435: no_scale = -1, duke@435: times_1 = 0, duke@435: times_2 = 1, duke@435: times_4 = 2, duke@435: times_8 = 3 duke@435: }; duke@435: duke@435: private: duke@435: Register _base; duke@435: Register _index; duke@435: ScaleFactor _scale; duke@435: int _disp; duke@435: RelocationHolder _rspec; duke@435: duke@435: // Easily misused constructors make them private duke@435: Address(int disp, address loc, relocInfo::relocType rtype); duke@435: Address(int disp, address loc, RelocationHolder spec); duke@435: duke@435: public: duke@435: // creation duke@435: Address() duke@435: : _base(noreg), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(0) { duke@435: } duke@435: duke@435: // No default displacement otherwise Register can be implicitly duke@435: // converted to 0(Register) which is quite a different animal. duke@435: duke@435: Address(Register base, int disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(disp) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, int disp = 0) duke@435: : _base (base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp (disp) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } duke@435: duke@435: // The following two overloads are used in connection with the duke@435: // ByteSize type (see sizes.hpp). They simplify the use of duke@435: // ByteSize'd arguments in assembly code. Note that their equivalent duke@435: // for the optimized build are the member functions with int disp duke@435: // argument since ByteSize is mapped to an int type in that case. duke@435: // duke@435: // Note: DO NOT introduce similar overloaded functions for WordSize duke@435: // arguments as in the optimized mode, both ByteSize and WordSize duke@435: // are mapped to the same type and thus the compiler cannot make a duke@435: // distinction anymore (=> compiler errors). duke@435: duke@435: #ifdef ASSERT duke@435: Address(Register base, ByteSize disp) duke@435: : _base(base), duke@435: _index(noreg), duke@435: _scale(no_scale), duke@435: _disp(in_bytes(disp)) { duke@435: } duke@435: duke@435: Address(Register base, Register index, ScaleFactor scale, ByteSize disp) duke@435: : _base(base), duke@435: _index(index), duke@435: _scale(scale), duke@435: _disp(in_bytes(disp)) { duke@435: assert(!index->is_valid() == (scale == Address::no_scale), duke@435: "inconsistent address"); duke@435: } duke@435: #endif // ASSERT duke@435: duke@435: // accessors duke@435: bool uses(Register reg) const { duke@435: return _base == reg || _index == reg; duke@435: } duke@435: duke@435: // Convert the raw encoding form into the form expected by the constructor for duke@435: // Address. An index of 4 (rsp) corresponds to having no index, so convert duke@435: // that to noreg for the Address constructor. duke@435: static Address make_raw(int base, int index, int scale, int disp); duke@435: duke@435: static Address make_array(ArrayAddress); duke@435: duke@435: private: duke@435: bool base_needs_rex() const { duke@435: return _base != noreg && _base->encoding() >= 8; duke@435: } duke@435: duke@435: bool index_needs_rex() const { duke@435: return _index != noreg &&_index->encoding() >= 8; duke@435: } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class LIR_Assembler; // base/index/scale/disp duke@435: }; duke@435: duke@435: // duke@435: // AddressLiteral has been split out from Address because operands of this type duke@435: // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out duke@435: // the few instructions that need to deal with address literals are unique and the duke@435: // MacroAssembler does not have to implement every instruction in the Assembler duke@435: // in order to search for address literals that may need special handling depending duke@435: // on the instruction and the platform. As small step on the way to merging i486/amd64 duke@435: // directories. duke@435: // duke@435: class AddressLiteral VALUE_OBJ_CLASS_SPEC { duke@435: friend class ArrayAddress; duke@435: RelocationHolder _rspec; duke@435: // Typically we use AddressLiterals we want to use their rval duke@435: // However in some situations we want the lval (effect address) of the item. duke@435: // We provide a special factory for making those lvals. duke@435: bool _is_lval; duke@435: duke@435: // If the target is far we'll need to load the ea of this to duke@435: // a register to reach it. Otherwise if near we can do rip duke@435: // relative addressing. duke@435: duke@435: address _target; duke@435: duke@435: protected: duke@435: // creation duke@435: AddressLiteral() duke@435: : _is_lval(false), duke@435: _target(NULL) duke@435: {} duke@435: duke@435: public: duke@435: duke@435: duke@435: AddressLiteral(address target, relocInfo::relocType rtype); duke@435: duke@435: AddressLiteral(address target, RelocationHolder const& rspec) duke@435: : _rspec(rspec), duke@435: _is_lval(false), duke@435: _target(target) duke@435: {} duke@435: duke@435: AddressLiteral addr() { duke@435: AddressLiteral ret = *this; duke@435: ret._is_lval = true; duke@435: return ret; duke@435: } duke@435: duke@435: duke@435: private: duke@435: duke@435: address target() { return _target; } duke@435: bool is_lval() { return _is_lval; } duke@435: duke@435: relocInfo::relocType reloc() const { return _rspec.type(); } duke@435: const RelocationHolder& rspec() const { return _rspec; } duke@435: duke@435: friend class Assembler; duke@435: friend class MacroAssembler; duke@435: friend class Address; duke@435: friend class LIR_Assembler; duke@435: }; duke@435: duke@435: // Convience classes duke@435: class RuntimeAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} duke@435: duke@435: }; duke@435: duke@435: class OopAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} duke@435: duke@435: }; duke@435: duke@435: class ExternalAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} duke@435: duke@435: }; duke@435: duke@435: class InternalAddress: public AddressLiteral { duke@435: duke@435: public: duke@435: duke@435: InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} duke@435: duke@435: }; duke@435: duke@435: // x86 can do array addressing as a single operation since disp can be an absolute duke@435: // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class duke@435: // that expresses the concept but does extra magic on amd64 to get the final result duke@435: duke@435: class ArrayAddress VALUE_OBJ_CLASS_SPEC { duke@435: private: duke@435: duke@435: AddressLiteral _base; duke@435: Address _index; duke@435: duke@435: public: duke@435: duke@435: ArrayAddress() {}; duke@435: ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; duke@435: AddressLiteral base() { return _base; } duke@435: Address index() { return _index; } duke@435: duke@435: }; duke@435: duke@435: // The amd64 Assembler: Pure assembler doing NO optimizations on duke@435: // the instruction level (e.g. mov rax, 0 is not translated into xor duke@435: // rax, rax!); i.e., what you write is what you get. The Assembler is duke@435: // generating code into a CodeBuffer. duke@435: duke@435: const int FPUStateSizeInWords = 512 / wordSize; duke@435: duke@435: class Assembler : public AbstractAssembler { duke@435: friend class AbstractAssembler; // for the non-virtual hack duke@435: friend class StubGenerator; duke@435: duke@435: duke@435: protected: duke@435: #ifdef ASSERT duke@435: void check_relocation(RelocationHolder const& rspec, int format); duke@435: #endif duke@435: duke@435: inline void emit_long64(jlong x); duke@435: duke@435: void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */); duke@435: void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */); duke@435: void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); duke@435: void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); duke@435: duke@435: // Helper functions for groups of instructions duke@435: void emit_arith_b(int op1, int op2, Register dst, int imm8); duke@435: duke@435: void emit_arith(int op1, int op2, Register dst, int imm32); duke@435: // only x86?? duke@435: void emit_arith(int op1, int op2, Register dst, jobject obj); duke@435: void emit_arith(int op1, int op2, Register dst, Register src); duke@435: duke@435: void emit_operand(Register reg, duke@435: Register base, Register index, Address::ScaleFactor scale, duke@435: int disp, duke@435: RelocationHolder const& rspec, duke@435: int rip_relative_correction = 0); duke@435: void emit_operand(Register reg, Address adr, duke@435: int rip_relative_correction = 0); duke@435: void emit_operand(XMMRegister reg, duke@435: Register base, Register index, Address::ScaleFactor scale, duke@435: int disp, duke@435: RelocationHolder const& rspec, duke@435: int rip_relative_correction = 0); duke@435: void emit_operand(XMMRegister reg, Address adr, duke@435: int rip_relative_correction = 0); duke@435: duke@435: // Immediate-to-memory forms duke@435: void emit_arith_operand(int op1, Register rm, Address adr, int imm32); duke@435: duke@435: void emit_farith(int b1, int b2, int i); duke@435: duke@435: bool reachable(AddressLiteral adr); duke@435: duke@435: // These are all easily abused and hence protected duke@435: duke@435: // Make these disappear in 64bit mode since they would never be correct duke@435: #ifndef _LP64 duke@435: void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); duke@435: void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); duke@435: duke@435: void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); duke@435: void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); duke@435: duke@435: void push_literal32(int32_t imm32, RelocationHolder const& rspec); duke@435: #endif // _LP64 duke@435: duke@435: duke@435: void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); duke@435: duke@435: // These are unique in that we are ensured by the caller that the 32bit duke@435: // relative in these instructions will always be able to reach the potentially duke@435: // 64bit address described by entry. Since they can take a 64bit address they duke@435: // don't have the 32 suffix like the other instructions in this class. duke@435: void jmp_literal(address entry, RelocationHolder const& rspec); duke@435: void call_literal(address entry, RelocationHolder const& rspec); duke@435: duke@435: public: duke@435: enum Condition { // The amd64 condition codes used for conditional jumps/moves. duke@435: zero = 0x4, duke@435: notZero = 0x5, duke@435: equal = 0x4, duke@435: notEqual = 0x5, duke@435: less = 0xc, duke@435: lessEqual = 0xe, duke@435: greater = 0xf, duke@435: greaterEqual = 0xd, duke@435: below = 0x2, duke@435: belowEqual = 0x6, duke@435: above = 0x7, duke@435: aboveEqual = 0x3, duke@435: overflow = 0x0, duke@435: noOverflow = 0x1, duke@435: carrySet = 0x2, duke@435: carryClear = 0x3, duke@435: negative = 0x8, duke@435: positive = 0x9, duke@435: parity = 0xa, duke@435: noParity = 0xb duke@435: }; duke@435: duke@435: enum Prefix { duke@435: // segment overrides duke@435: // XXX remove segment prefixes duke@435: CS_segment = 0x2e, duke@435: SS_segment = 0x36, duke@435: DS_segment = 0x3e, duke@435: ES_segment = 0x26, duke@435: FS_segment = 0x64, duke@435: GS_segment = 0x65, duke@435: duke@435: REX = 0x40, duke@435: duke@435: REX_B = 0x41, duke@435: REX_X = 0x42, duke@435: REX_XB = 0x43, duke@435: REX_R = 0x44, duke@435: REX_RB = 0x45, duke@435: REX_RX = 0x46, duke@435: REX_RXB = 0x47, duke@435: duke@435: REX_W = 0x48, duke@435: duke@435: REX_WB = 0x49, duke@435: REX_WX = 0x4A, duke@435: REX_WXB = 0x4B, duke@435: REX_WR = 0x4C, duke@435: REX_WRB = 0x4D, duke@435: REX_WRX = 0x4E, duke@435: REX_WRXB = 0x4F duke@435: }; duke@435: duke@435: enum WhichOperand { duke@435: // input to locate_operand, and format code for relocations duke@435: imm64_operand = 0, // embedded 64-bit immediate operand duke@435: disp32_operand = 1, // embedded 32-bit displacement duke@435: call32_operand = 2, // embedded 32-bit self-relative displacement duke@435: _WhichOperand_limit = 3 duke@435: }; duke@435: duke@435: public: duke@435: duke@435: // Creation duke@435: Assembler(CodeBuffer* code) duke@435: : AbstractAssembler(code) { duke@435: } duke@435: duke@435: // Decoding duke@435: static address locate_operand(address inst, WhichOperand which); duke@435: static address locate_next_instruction(address inst); duke@435: duke@435: // Utilities duke@435: duke@435: static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } duke@435: static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; } duke@435: duke@435: duke@435: // Stack duke@435: void pushaq(); duke@435: void popaq(); duke@435: duke@435: void pushfq(); duke@435: void popfq(); duke@435: duke@435: void pushq(int imm32); duke@435: duke@435: void pushq(Register src); duke@435: void pushq(Address src); duke@435: duke@435: void popq(Register dst); duke@435: void popq(Address dst); duke@435: duke@435: // Instruction prefixes duke@435: void prefix(Prefix p); duke@435: duke@435: int prefix_and_encode(int reg_enc, bool byteinst = false); duke@435: int prefixq_and_encode(int reg_enc); duke@435: duke@435: int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); duke@435: int prefixq_and_encode(int dst_enc, int src_enc); duke@435: duke@435: void prefix(Register reg); duke@435: void prefix(Address adr); duke@435: void prefixq(Address adr); duke@435: duke@435: void prefix(Address adr, Register reg, bool byteinst = false); duke@435: void prefixq(Address adr, Register reg); duke@435: duke@435: void prefix(Address adr, XMMRegister reg); duke@435: duke@435: // Moves duke@435: void movb(Register dst, Address src); duke@435: void movb(Address dst, int imm8); duke@435: void movb(Address dst, Register src); duke@435: duke@435: void movw(Address dst, int imm16); duke@435: void movw(Register dst, Address src); duke@435: void movw(Address dst, Register src); duke@435: duke@435: void movl(Register dst, int imm32); duke@435: void movl(Register dst, Register src); duke@435: void movl(Register dst, Address src); duke@435: void movl(Address dst, int imm32); duke@435: void movl(Address dst, Register src); duke@435: duke@435: void movq(Register dst, Register src); duke@435: void movq(Register dst, Address src); duke@435: void movq(Address dst, Register src); duke@435: // These prevent using movq from converting a zero (like NULL) into Register duke@435: // by giving the compiler two choices it can't resolve duke@435: void movq(Address dst, void* dummy); duke@435: void movq(Register dst, void* dummy); duke@435: duke@435: void mov64(Register dst, intptr_t imm64); duke@435: void mov64(Address dst, intptr_t imm64); duke@435: duke@435: void movsbl(Register dst, Address src); duke@435: void movsbl(Register dst, Register src); duke@435: void movswl(Register dst, Address src); duke@435: void movswl(Register dst, Register src); duke@435: void movslq(Register dst, Address src); duke@435: void movslq(Register dst, Register src); duke@435: duke@435: void movzbl(Register dst, Address src); duke@435: void movzbl(Register dst, Register src); duke@435: void movzwl(Register dst, Address src); duke@435: void movzwl(Register dst, Register src); duke@435: duke@435: protected: // Avoid using the next instructions directly. duke@435: // New cpus require use of movsd and movss to avoid partial register stall duke@435: // when loading from memory. But for old Opteron use movlpd instead of movsd. duke@435: // The selection is done in MacroAssembler::movdbl() and movflt(). duke@435: void movss(XMMRegister dst, XMMRegister src); duke@435: void movss(XMMRegister dst, Address src); duke@435: void movss(Address dst, XMMRegister src); duke@435: void movsd(XMMRegister dst, XMMRegister src); duke@435: void movsd(Address dst, XMMRegister src); duke@435: void movsd(XMMRegister dst, Address src); duke@435: void movlpd(XMMRegister dst, Address src); duke@435: // New cpus require use of movaps and movapd to avoid partial register stall duke@435: // when moving between registers. duke@435: void movapd(XMMRegister dst, XMMRegister src); duke@435: void movaps(XMMRegister dst, XMMRegister src); duke@435: public: duke@435: duke@435: void movdl(XMMRegister dst, Register src); duke@435: void movdl(Register dst, XMMRegister src); duke@435: void movdq(XMMRegister dst, Register src); duke@435: void movdq(Register dst, XMMRegister src); duke@435: duke@435: void cmovl(Condition cc, Register dst, Register src); duke@435: void cmovl(Condition cc, Register dst, Address src); duke@435: void cmovq(Condition cc, Register dst, Register src); duke@435: void cmovq(Condition cc, Register dst, Address src); duke@435: duke@435: // Prefetches duke@435: private: duke@435: void prefetch_prefix(Address src); duke@435: public: duke@435: void prefetcht0(Address src); duke@435: void prefetcht1(Address src); duke@435: void prefetcht2(Address src); duke@435: void prefetchnta(Address src); duke@435: void prefetchw(Address src); duke@435: duke@435: // Arithmetics duke@435: void adcl(Register dst, int imm32); duke@435: void adcl(Register dst, Address src); duke@435: void adcl(Register dst, Register src); duke@435: void adcq(Register dst, int imm32); duke@435: void adcq(Register dst, Address src); duke@435: void adcq(Register dst, Register src); duke@435: duke@435: void addl(Address dst, int imm32); duke@435: void addl(Address dst, Register src); duke@435: void addl(Register dst, int imm32); duke@435: void addl(Register dst, Address src); duke@435: void addl(Register dst, Register src); duke@435: void addq(Address dst, int imm32); duke@435: void addq(Address dst, Register src); duke@435: void addq(Register dst, int imm32); duke@435: void addq(Register dst, Address src); duke@435: void addq(Register dst, Register src); duke@435: duke@435: void andl(Register dst, int imm32); duke@435: void andl(Register dst, Address src); duke@435: void andl(Register dst, Register src); duke@435: void andq(Register dst, int imm32); duke@435: void andq(Register dst, Address src); duke@435: void andq(Register dst, Register src); duke@435: duke@435: void cmpb(Address dst, int imm8); duke@435: void cmpl(Address dst, int imm32); duke@435: void cmpl(Register dst, int imm32); duke@435: void cmpl(Register dst, Register src); duke@435: void cmpl(Register dst, Address src); duke@435: void cmpq(Address dst, int imm32); duke@435: void cmpq(Address dst, Register src); duke@435: void cmpq(Register dst, int imm32); duke@435: void cmpq(Register dst, Register src); duke@435: void cmpq(Register dst, Address src); duke@435: duke@435: void ucomiss(XMMRegister dst, XMMRegister src); duke@435: void ucomisd(XMMRegister dst, XMMRegister src); duke@435: duke@435: protected: duke@435: // Don't use next inc() and dec() methods directly. INC & DEC instructions duke@435: // could cause a partial flag stall since they don't set CF flag. duke@435: // Use MacroAssembler::decrement() & MacroAssembler::increment() methods duke@435: // which call inc() & dec() or add() & sub() in accordance with duke@435: // the product flag UseIncDec value. duke@435: duke@435: void decl(Register dst); duke@435: void decl(Address dst); duke@435: void decq(Register dst); duke@435: void decq(Address dst); duke@435: duke@435: void incl(Register dst); duke@435: void incl(Address dst); duke@435: void incq(Register dst); duke@435: void incq(Address dst); duke@435: duke@435: public: duke@435: void idivl(Register src); duke@435: void idivq(Register src); duke@435: void cdql(); duke@435: void cdqq(); duke@435: duke@435: void imull(Register dst, Register src); duke@435: void imull(Register dst, Register src, int value); duke@435: void imulq(Register dst, Register src); duke@435: void imulq(Register dst, Register src, int value); duke@435: duke@435: void leal(Register dst, Address src); duke@435: void leaq(Register dst, Address src); duke@435: duke@435: void mull(Address src); duke@435: void mull(Register src); duke@435: duke@435: void negl(Register dst); duke@435: void negq(Register dst); duke@435: duke@435: void notl(Register dst); duke@435: void notq(Register dst); duke@435: duke@435: void orl(Address dst, int imm32); duke@435: void orl(Register dst, int imm32); duke@435: void orl(Register dst, Address src); duke@435: void orl(Register dst, Register src); duke@435: void orq(Address dst, int imm32); duke@435: void orq(Register dst, int imm32); duke@435: void orq(Register dst, Address src); duke@435: void orq(Register dst, Register src); duke@435: duke@435: void rcll(Register dst, int imm8); duke@435: void rclq(Register dst, int imm8); duke@435: duke@435: void sarl(Register dst, int imm8); duke@435: void sarl(Register dst); duke@435: void sarq(Register dst, int imm8); duke@435: void sarq(Register dst); duke@435: duke@435: void sbbl(Address dst, int imm32); duke@435: void sbbl(Register dst, int imm32); duke@435: void sbbl(Register dst, Address src); duke@435: void sbbl(Register dst, Register src); duke@435: void sbbq(Address dst, int imm32); duke@435: void sbbq(Register dst, int imm32); duke@435: void sbbq(Register dst, Address src); duke@435: void sbbq(Register dst, Register src); duke@435: duke@435: void shll(Register dst, int imm8); duke@435: void shll(Register dst); duke@435: void shlq(Register dst, int imm8); duke@435: void shlq(Register dst); duke@435: duke@435: void shrl(Register dst, int imm8); duke@435: void shrl(Register dst); duke@435: void shrq(Register dst, int imm8); duke@435: void shrq(Register dst); duke@435: duke@435: void subl(Address dst, int imm32); duke@435: void subl(Address dst, Register src); duke@435: void subl(Register dst, int imm32); duke@435: void subl(Register dst, Address src); duke@435: void subl(Register dst, Register src); duke@435: void subq(Address dst, int imm32); duke@435: void subq(Address dst, Register src); duke@435: void subq(Register dst, int imm32); duke@435: void subq(Register dst, Address src); duke@435: void subq(Register dst, Register src); duke@435: duke@435: void testb(Register dst, int imm8); duke@435: void testl(Register dst, int imm32); duke@435: void testl(Register dst, Register src); duke@435: void testq(Register dst, int imm32); duke@435: void testq(Register dst, Register src); duke@435: duke@435: void xaddl(Address dst, Register src); duke@435: void xaddq(Address dst, Register src); duke@435: duke@435: void xorl(Register dst, int imm32); duke@435: void xorl(Register dst, Address src); duke@435: void xorl(Register dst, Register src); duke@435: void xorq(Register dst, int imm32); duke@435: void xorq(Register dst, Address src); duke@435: void xorq(Register dst, Register src); duke@435: duke@435: // Miscellaneous duke@435: void bswapl(Register reg); duke@435: void bswapq(Register reg); duke@435: void lock(); duke@435: duke@435: void xchgl(Register reg, Address adr); duke@435: void xchgl(Register dst, Register src); duke@435: void xchgq(Register reg, Address adr); duke@435: void xchgq(Register dst, Register src); duke@435: duke@435: void cmpxchgl(Register reg, Address adr); duke@435: void cmpxchgq(Register reg, Address adr); duke@435: duke@435: void nop(int i = 1); duke@435: void addr_nop_4(); duke@435: void addr_nop_5(); duke@435: void addr_nop_7(); duke@435: void addr_nop_8(); duke@435: duke@435: void hlt(); duke@435: void ret(int imm16); duke@435: void smovl(); duke@435: void rep_movl(); duke@435: void rep_movq(); duke@435: void rep_set(); coleenp@548: void repne_scanl(); coleenp@548: void repne_scanq(); duke@435: void setb(Condition cc, Register dst); duke@435: duke@435: void clflush(Address adr); duke@435: duke@435: enum Membar_mask_bits { duke@435: StoreStore = 1 << 3, duke@435: LoadStore = 1 << 2, duke@435: StoreLoad = 1 << 1, duke@435: LoadLoad = 1 << 0 duke@435: }; duke@435: duke@435: // Serializes memory. duke@435: void membar(Membar_mask_bits order_constraint) { duke@435: // We only have to handle StoreLoad and LoadLoad duke@435: if (order_constraint & StoreLoad) { duke@435: // MFENCE subsumes LFENCE duke@435: mfence(); duke@435: } /* [jk] not needed currently: else if (order_constraint & LoadLoad) { duke@435: lfence(); duke@435: } */ duke@435: } duke@435: duke@435: void lfence() { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAE); duke@435: emit_byte(0xE8); duke@435: } duke@435: duke@435: void mfence() { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAE); duke@435: emit_byte(0xF0); duke@435: } duke@435: duke@435: // Identify processor type and features duke@435: void cpuid() { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xA2); duke@435: } duke@435: duke@435: void cld() { emit_byte(0xfc); duke@435: } duke@435: duke@435: void std() { emit_byte(0xfd); duke@435: } duke@435: duke@435: duke@435: // Calls duke@435: duke@435: void call(Label& L, relocInfo::relocType rtype); duke@435: void call(Register reg); duke@435: void call(Address adr); duke@435: duke@435: // Jumps duke@435: duke@435: void jmp(Register reg); duke@435: void jmp(Address adr); duke@435: duke@435: // Label operations & relative jumps (PPUM Appendix D) duke@435: // unconditional jump to L duke@435: void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); duke@435: duke@435: duke@435: // Unconditional 8-bit offset jump to L. duke@435: // WARNING: be very careful using this for forward jumps. If the label is duke@435: // not bound within an 8-bit offset of this instruction, a run-time error duke@435: // will occur. duke@435: void jmpb(Label& L); duke@435: duke@435: // jcc is the generic conditional branch generator to run- time duke@435: // routines, jcc is used for branches to labels. jcc takes a branch duke@435: // opcode (cc) and a label (L) and generates either a backward duke@435: // branch or a forward branch and links it to the label fixup duke@435: // chain. Usage: duke@435: // duke@435: // Label L; // unbound label duke@435: // jcc(cc, L); // forward branch to unbound label duke@435: // bind(L); // bind label to the current pc duke@435: // jcc(cc, L); // backward branch to bound label duke@435: // bind(L); // illegal: a label may be bound only once duke@435: // duke@435: // Note: The same Label can be used for forward and backward branches duke@435: // but it may be bound only once. duke@435: duke@435: void jcc(Condition cc, Label& L, duke@435: relocInfo::relocType rtype = relocInfo::none); duke@435: duke@435: // Conditional jump to a 8-bit offset to L. duke@435: // WARNING: be very careful using this for forward jumps. If the label is duke@435: // not bound within an 8-bit offset of this instruction, a run-time error duke@435: // will occur. duke@435: void jccb(Condition cc, Label& L); duke@435: duke@435: // Floating-point operations duke@435: duke@435: void fxsave(Address dst); duke@435: void fxrstor(Address src); duke@435: void ldmxcsr(Address src); duke@435: void stmxcsr(Address dst); duke@435: duke@435: void addss(XMMRegister dst, XMMRegister src); duke@435: void addss(XMMRegister dst, Address src); duke@435: void subss(XMMRegister dst, XMMRegister src); duke@435: void subss(XMMRegister dst, Address src); duke@435: void mulss(XMMRegister dst, XMMRegister src); duke@435: void mulss(XMMRegister dst, Address src); duke@435: void divss(XMMRegister dst, XMMRegister src); duke@435: void divss(XMMRegister dst, Address src); duke@435: void addsd(XMMRegister dst, XMMRegister src); duke@435: void addsd(XMMRegister dst, Address src); duke@435: void subsd(XMMRegister dst, XMMRegister src); duke@435: void subsd(XMMRegister dst, Address src); duke@435: void mulsd(XMMRegister dst, XMMRegister src); duke@435: void mulsd(XMMRegister dst, Address src); duke@435: void divsd(XMMRegister dst, XMMRegister src); duke@435: void divsd(XMMRegister dst, Address src); duke@435: duke@435: // We only need the double form duke@435: void sqrtsd(XMMRegister dst, XMMRegister src); duke@435: void sqrtsd(XMMRegister dst, Address src); duke@435: duke@435: void xorps(XMMRegister dst, XMMRegister src); duke@435: void xorps(XMMRegister dst, Address src); duke@435: void xorpd(XMMRegister dst, XMMRegister src); duke@435: void xorpd(XMMRegister dst, Address src); duke@435: duke@435: void cvtsi2ssl(XMMRegister dst, Register src); duke@435: void cvtsi2ssq(XMMRegister dst, Register src); duke@435: void cvtsi2sdl(XMMRegister dst, Register src); duke@435: void cvtsi2sdq(XMMRegister dst, Register src); duke@435: void cvttss2sil(Register dst, XMMRegister src); // truncates duke@435: void cvttss2siq(Register dst, XMMRegister src); // truncates duke@435: void cvttsd2sil(Register dst, XMMRegister src); // truncates duke@435: void cvttsd2siq(Register dst, XMMRegister src); // truncates duke@435: void cvtss2sd(XMMRegister dst, XMMRegister src); duke@435: void cvtsd2ss(XMMRegister dst, XMMRegister src); kvn@506: void cvtdq2pd(XMMRegister dst, XMMRegister src); kvn@506: void cvtdq2ps(XMMRegister dst, XMMRegister src); duke@435: duke@435: void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values duke@435: void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values duke@435: duke@435: void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword duke@435: void movdqa(XMMRegister dst, XMMRegister src); duke@435: void movdqa(Address dst, XMMRegister src); duke@435: duke@435: void movq(XMMRegister dst, Address src); duke@435: void movq(Address dst, XMMRegister src); duke@435: duke@435: void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords duke@435: void pshufd(XMMRegister dst, Address src, int mode); duke@435: void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words duke@435: void pshuflw(XMMRegister dst, Address src, int mode); duke@435: duke@435: void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate duke@435: duke@435: void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes duke@435: void punpcklbw(XMMRegister dst, Address src); duke@435: }; duke@435: duke@435: duke@435: // MacroAssembler extends Assembler by frequently used macros. duke@435: // duke@435: // Instructions for which a 'better' code sequence exists depending duke@435: // on arguments should also go in here. duke@435: duke@435: class MacroAssembler : public Assembler { duke@435: friend class LIR_Assembler; duke@435: protected: duke@435: duke@435: Address as_Address(AddressLiteral adr); duke@435: Address as_Address(ArrayAddress adr); duke@435: duke@435: // Support for VM calls duke@435: // duke@435: // This is the base routine called by the different versions of duke@435: // call_VM_leaf. The interpreter may customize this version by duke@435: // overriding it for its purposes (e.g., to save/restore additional duke@435: // registers when doing a VM call). duke@435: duke@435: virtual void call_VM_leaf_base( duke@435: address entry_point, // the entry point duke@435: int number_of_arguments // the number of arguments to duke@435: // pop after the call duke@435: ); duke@435: duke@435: // This is the base routine called by the different versions of duke@435: // call_VM. The interpreter may customize this version by overriding duke@435: // it for its purposes (e.g., to save/restore additional registers duke@435: // when doing a VM call). duke@435: // duke@435: // If no java_thread register is specified (noreg) than rdi will be duke@435: // used instead. call_VM_base returns the register which contains duke@435: // the thread upon return. If a thread register has been specified, duke@435: // the return value will correspond to that register. If no duke@435: // last_java_sp is specified (noreg) than rsp will be used instead. duke@435: virtual void call_VM_base( // returns the register duke@435: // containing the thread upon duke@435: // return duke@435: Register oop_result, // where an oop-result ends up duke@435: // if any; use noreg otherwise duke@435: Register java_thread, // the thread if computed duke@435: // before ; use noreg otherwise duke@435: Register last_java_sp, // to set up last_Java_frame in duke@435: // stubs; use noreg otherwise duke@435: address entry_point, // the entry point duke@435: int number_of_arguments, // the number of arguments (w/o duke@435: // thread) to pop after the duke@435: // call duke@435: bool check_exceptions // whether to check for pending duke@435: // exceptions after return duke@435: ); duke@435: duke@435: // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code. duke@435: // The implementation is only non-empty for the InterpreterMacroAssembler, duke@435: // as only the interpreter handles PopFrame and ForceEarlyReturn requests. duke@435: virtual void check_and_handle_popframe(Register java_thread); duke@435: virtual void check_and_handle_earlyret(Register java_thread); duke@435: duke@435: void call_VM_helper(Register oop_result, duke@435: address entry_point, duke@435: int number_of_arguments, duke@435: bool check_exceptions = true); duke@435: duke@435: public: duke@435: MacroAssembler(CodeBuffer* code) : Assembler(code) {} duke@435: duke@435: // Support for NULL-checks duke@435: // duke@435: // Generates code that causes a NULL OS exception if the content of duke@435: // reg is NULL. If the accessed location is M[reg + offset] and the duke@435: // offset is known, provide the offset. No explicit code generation duke@435: // is needed if the offset is within a certain range (0 <= offset <= duke@435: // page_size). duke@435: void null_check(Register reg, int offset = -1); duke@435: static bool needs_explicit_null_check(int offset); duke@435: duke@435: // Required platform-specific helpers for Label::patch_instructions. duke@435: // They _shadow_ the declarations in AbstractAssembler, which are undefined. duke@435: void pd_patch_instruction(address branch, address target); duke@435: #ifndef PRODUCT duke@435: static void pd_print_patched_instruction(address branch); duke@435: #endif duke@435: duke@435: duke@435: // The following 4 methods return the offset of the appropriate move duke@435: // instruction. Note: these are 32 bit instructions duke@435: duke@435: // Support for fast byte/word loading with zero extension (depending duke@435: // on particular CPU) duke@435: int load_unsigned_byte(Register dst, Address src); duke@435: int load_unsigned_word(Register dst, Address src); duke@435: duke@435: // Support for fast byte/word loading with sign extension (depending duke@435: // on particular CPU) duke@435: int load_signed_byte(Register dst, Address src); duke@435: int load_signed_word(Register dst, Address src); duke@435: duke@435: // Support for inc/dec with optimal instruction selection depending duke@435: // on value duke@435: void incrementl(Register reg, int value = 1); duke@435: void decrementl(Register reg, int value = 1); duke@435: void incrementq(Register reg, int value = 1); duke@435: void decrementq(Register reg, int value = 1); duke@435: duke@435: void incrementl(Address dst, int value = 1); duke@435: void decrementl(Address dst, int value = 1); duke@435: void incrementq(Address dst, int value = 1); duke@435: void decrementq(Address dst, int value = 1); duke@435: duke@435: // Support optimal SSE move instructions. duke@435: void movflt(XMMRegister dst, XMMRegister src) { duke@435: if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } duke@435: else { movss (dst, src); return; } duke@435: } duke@435: duke@435: void movflt(XMMRegister dst, Address src) { movss(dst, src); } duke@435: duke@435: void movflt(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void movflt(Address dst, XMMRegister src) { movss(dst, src); } duke@435: duke@435: void movdbl(XMMRegister dst, XMMRegister src) { duke@435: if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } duke@435: else { movsd (dst, src); return; } duke@435: } duke@435: duke@435: void movdbl(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void movdbl(XMMRegister dst, Address src) { duke@435: if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } duke@435: else { movlpd(dst, src); return; } duke@435: } duke@435: duke@435: void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } duke@435: duke@435: void incrementl(AddressLiteral dst); duke@435: void incrementl(ArrayAddress dst); duke@435: duke@435: // Alignment duke@435: void align(int modulus); duke@435: duke@435: // Misc duke@435: void fat_nop(); // 5 byte nop duke@435: duke@435: duke@435: // C++ bool manipulation duke@435: duke@435: void movbool(Register dst, Address src); duke@435: void movbool(Address dst, bool boolconst); duke@435: void movbool(Address dst, Register src); duke@435: void testbool(Register dst); duke@435: coleenp@548: // oop manipulations coleenp@548: void load_klass(Register dst, Register src); coleenp@548: void store_klass(Register dst, Register src); coleenp@548: coleenp@548: void load_heap_oop(Register dst, Address src); coleenp@548: void store_heap_oop(Address dst, Register src); coleenp@548: void encode_heap_oop(Register r); coleenp@548: void decode_heap_oop(Register r); coleenp@548: void encode_heap_oop_not_null(Register r); coleenp@548: void decode_heap_oop_not_null(Register r); coleenp@548: duke@435: // Stack frame creation/removal duke@435: void enter(); duke@435: void leave(); duke@435: duke@435: // Support for getting the JavaThread pointer (i.e.; a reference to duke@435: // thread-local information) The pointer will be loaded into the duke@435: // thread register. duke@435: void get_thread(Register thread); duke@435: duke@435: void int3(); duke@435: duke@435: // Support for VM calls duke@435: // duke@435: // It is imperative that all calls into the VM are handled via the duke@435: // call_VM macros. They make sure that the stack linkage is setup duke@435: // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points duke@435: // while call_VM_leaf's correspond to LEAF entry points. duke@435: void call_VM(Register oop_result, duke@435: address entry_point, duke@435: bool check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: address entry_point, duke@435: Register arg_1, duke@435: bool check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: address entry_point, duke@435: Register arg_1, Register arg_2, duke@435: bool check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: address entry_point, duke@435: Register arg_1, Register arg_2, Register arg_3, duke@435: bool check_exceptions = true); duke@435: duke@435: // Overloadings with last_Java_sp duke@435: void call_VM(Register oop_result, duke@435: Register last_java_sp, duke@435: address entry_point, duke@435: int number_of_arguments = 0, duke@435: bool check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: Register last_java_sp, duke@435: address entry_point, duke@435: Register arg_1, bool duke@435: check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: Register last_java_sp, duke@435: address entry_point, duke@435: Register arg_1, Register arg_2, duke@435: bool check_exceptions = true); duke@435: void call_VM(Register oop_result, duke@435: Register last_java_sp, duke@435: address entry_point, duke@435: Register arg_1, Register arg_2, Register arg_3, duke@435: bool check_exceptions = true); duke@435: duke@435: void call_VM_leaf(address entry_point, duke@435: int number_of_arguments = 0); duke@435: void call_VM_leaf(address entry_point, duke@435: Register arg_1); duke@435: void call_VM_leaf(address entry_point, duke@435: Register arg_1, Register arg_2); duke@435: void call_VM_leaf(address entry_point, duke@435: Register arg_1, Register arg_2, Register arg_3); duke@435: duke@435: // last Java Frame (fills frame anchor) duke@435: void set_last_Java_frame(Register last_java_sp, duke@435: Register last_java_fp, duke@435: address last_java_pc); duke@435: void reset_last_Java_frame(bool clear_fp, bool clear_pc); duke@435: duke@435: // Stores duke@435: void store_check(Register obj); // store check for duke@435: // obj - register is duke@435: // destroyed duke@435: // afterwards duke@435: void store_check(Register obj, Address dst); // same as above, dst duke@435: // is exact store duke@435: // location (reg. is duke@435: // destroyed) duke@435: duke@435: // split store_check(Register obj) to enhance instruction interleaving duke@435: void store_check_part_1(Register obj); duke@435: void store_check_part_2(Register obj); duke@435: duke@435: // C 'boolean' to Java boolean: x == 0 ? 0 : 1 duke@435: void c2bool(Register x); duke@435: duke@435: // Int division/reminder for Java duke@435: // (as idivl, but checks for special case as described in JVM spec.) duke@435: // returns idivl instruction offset for implicit exception handling duke@435: int corrected_idivl(Register reg); duke@435: // Long division/reminder for Java duke@435: // (as idivq, but checks for special case as described in JVM spec.) duke@435: // returns idivq instruction offset for implicit exception handling duke@435: int corrected_idivq(Register reg); duke@435: duke@435: // Push and pop integer/fpu/cpu state duke@435: void push_IU_state(); duke@435: void pop_IU_state(); duke@435: duke@435: void push_FPU_state(); duke@435: void pop_FPU_state(); duke@435: duke@435: void push_CPU_state(); duke@435: void pop_CPU_state(); duke@435: duke@435: // Sign extension duke@435: void sign_extend_short(Register reg); duke@435: void sign_extend_byte(Register reg); duke@435: duke@435: // Division by power of 2, rounding towards 0 duke@435: void division_with_shift(Register reg, int shift_value); duke@435: duke@435: // Round up to a power of two duke@435: void round_to_l(Register reg, int modulus); duke@435: void round_to_q(Register reg, int modulus); duke@435: duke@435: // allocation duke@435: void eden_allocate( duke@435: Register obj, // result: pointer to object after duke@435: // successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at duke@435: // compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at duke@435: // compile time duke@435: Register t1, // temp register duke@435: Label& slow_case // continuation point if fast duke@435: // allocation fails duke@435: ); duke@435: void tlab_allocate( duke@435: Register obj, // result: pointer to object after duke@435: // successful allocation duke@435: Register var_size_in_bytes, // object size in bytes if unknown at duke@435: // compile time; invalid otherwise duke@435: int con_size_in_bytes, // object size in bytes if known at duke@435: // compile time duke@435: Register t1, // temp register duke@435: Register t2, // temp register duke@435: Label& slow_case // continuation point if fast duke@435: // allocation fails duke@435: ); duke@435: void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); duke@435: duke@435: //---- duke@435: duke@435: // Debugging duke@435: duke@435: // only if +VerifyOops duke@435: void verify_oop(Register reg, const char* s = "broken oop"); duke@435: void verify_oop_addr(Address addr, const char * s = "broken oop addr"); duke@435: coleenp@548: // if heap base register is used - reinit it with the correct value coleenp@548: void reinit_heapbase(); coleenp@548: duke@435: // only if +VerifyFPU duke@435: void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {} duke@435: duke@435: // prints msg, dumps registers and stops execution duke@435: void stop(const char* msg); duke@435: duke@435: // prints message and continues duke@435: void warn(const char* msg); duke@435: duke@435: static void debug(char* msg, int64_t pc, int64_t regs[]); duke@435: duke@435: void os_breakpoint(); duke@435: duke@435: void untested() duke@435: { duke@435: stop("untested"); duke@435: } duke@435: duke@435: void unimplemented(const char* what = "") duke@435: { duke@435: char* b = new char[1024]; duke@435: sprintf(b, "unimplemented: %s", what); duke@435: stop(b); duke@435: } duke@435: duke@435: void should_not_reach_here() duke@435: { duke@435: stop("should not reach here"); duke@435: } duke@435: duke@435: // Stack overflow checking duke@435: void bang_stack_with_offset(int offset) duke@435: { duke@435: // stack grows down, caller passes positive offset duke@435: assert(offset > 0, "must bang with negative offset"); duke@435: movl(Address(rsp, (-offset)), rax); duke@435: } duke@435: duke@435: // Writes to stack successive pages until offset reached to check for duke@435: // stack overflow + shadow pages. Also, clobbers tmp duke@435: void bang_stack_size(Register offset, Register tmp); duke@435: duke@435: // Support for serializing memory accesses between threads. duke@435: void serialize_memory(Register thread, Register tmp); duke@435: duke@435: void verify_tlab(); duke@435: duke@435: // Biased locking support duke@435: // lock_reg and obj_reg must be loaded up with the appropriate values. duke@435: // swap_reg must be rax and is killed. duke@435: // tmp_reg must be supplied and is killed. duke@435: // If swap_reg_contains_mark is true then the code assumes that the duke@435: // mark word of the object has already been loaded into swap_reg. duke@435: // Optional slow case is for implementations (interpreter and C1) which branch to duke@435: // slow case directly. Leaves condition codes set for C2's Fast_Lock node. duke@435: // Returns offset of first potentially-faulting instruction for null duke@435: // check info (currently consumed only by C1). If duke@435: // swap_reg_contains_mark is true then returns -1 as it is assumed duke@435: // the calling code has already passed any potential faults. duke@435: int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, duke@435: bool swap_reg_contains_mark, duke@435: Label& done, Label* slow_case = NULL, duke@435: BiasedLockingCounters* counters = NULL); duke@435: void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); duke@435: duke@435: Condition negate_condition(Condition cond); duke@435: duke@435: // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit duke@435: // operands. In general the names are modified to avoid hiding the instruction in Assembler duke@435: // so that we don't need to implement all the varieties in the Assembler with trivial wrappers duke@435: // here in MacroAssembler. The major exception to this rule is call duke@435: duke@435: // Arithmetics duke@435: duke@435: void cmp8(AddressLiteral src1, int8_t imm32); duke@435: duke@435: void cmp32(AddressLiteral src1, int32_t src2); duke@435: // compare reg - mem, or reg - &mem duke@435: void cmp32(Register src1, AddressLiteral src2); duke@435: duke@435: void cmp32(Register src1, Address src2); duke@435: duke@435: #ifndef _LP64 duke@435: void cmpoop(Address dst, jobject obj); duke@435: void cmpoop(Register dst, jobject obj); duke@435: #endif // _LP64 duke@435: duke@435: // NOTE src2 must be the lval. This is NOT an mem-mem compare duke@435: void cmpptr(Address src1, AddressLiteral src2); duke@435: duke@435: void cmpptr(Register src1, AddressLiteral src); duke@435: duke@435: // will be cmpreg(?) duke@435: void cmp64(Register src1, AddressLiteral src); duke@435: duke@435: void cmpxchgptr(Register reg, Address adr); duke@435: void cmpxchgptr(Register reg, AddressLiteral adr); duke@435: duke@435: // Helper functions for statistics gathering. duke@435: // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. duke@435: void cond_inc32(Condition cond, AddressLiteral counter_addr); duke@435: // Unconditional atomic increment. duke@435: void atomic_incl(AddressLiteral counter_addr); duke@435: duke@435: duke@435: void lea(Register dst, AddressLiteral src); duke@435: void lea(Register dst, Address src); duke@435: duke@435: duke@435: // Calls duke@435: void call(Label& L, relocInfo::relocType rtype); duke@435: void call(Register entry); duke@435: void call(AddressLiteral entry); duke@435: duke@435: // Jumps duke@435: duke@435: // 32bit can do a case table jump in one instruction but we no longer allow the base duke@435: // to be installed in the Address class duke@435: void jump(ArrayAddress entry); duke@435: duke@435: void jump(AddressLiteral entry); duke@435: void jump_cc(Condition cc, AddressLiteral dst); duke@435: duke@435: // Floating duke@435: duke@435: void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } duke@435: void ldmxcsr(AddressLiteral src); duke@435: duke@435: private: duke@435: // these are private because users should be doing movflt/movdbl duke@435: duke@435: void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } duke@435: void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } duke@435: void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } duke@435: void movss(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } duke@435: void movlpd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: public: duke@435: duke@435: duke@435: void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); } duke@435: void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); } duke@435: void xorpd(XMMRegister dst, AddressLiteral src); duke@435: duke@435: void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); } duke@435: void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); } duke@435: void xorps(XMMRegister dst, AddressLiteral src); duke@435: duke@435: duke@435: // Data duke@435: duke@435: void movoop(Register dst, jobject obj); duke@435: void movoop(Address dst, jobject obj); duke@435: duke@435: void movptr(ArrayAddress dst, Register src); duke@435: void movptr(Register dst, AddressLiteral src); duke@435: duke@435: void movptr(Register dst, intptr_t src); duke@435: void movptr(Address dst, intptr_t src); duke@435: duke@435: void movptr(Register dst, ArrayAddress src); duke@435: duke@435: // to avoid hiding movl duke@435: void mov32(AddressLiteral dst, Register src); duke@435: void mov32(Register dst, AddressLiteral src); duke@435: duke@435: void pushoop(jobject obj); duke@435: duke@435: // Can push value or effective address duke@435: void pushptr(AddressLiteral src); duke@435: duke@435: }; duke@435: duke@435: /** duke@435: * class SkipIfEqual: duke@435: * duke@435: * Instantiating this class will result in assembly code being output that will duke@435: * jump around any code emitted between the creation of the instance and it's duke@435: * automatic destruction at the end of a scope block, depending on the value of duke@435: * the flag passed to the constructor, which will be checked at run-time. duke@435: */ duke@435: class SkipIfEqual { duke@435: private: duke@435: MacroAssembler* _masm; duke@435: Label _label; duke@435: duke@435: public: duke@435: SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); duke@435: ~SkipIfEqual(); duke@435: }; duke@435: duke@435: duke@435: #ifdef ASSERT duke@435: inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } duke@435: #endif