duke@435: /* duke@435: * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: #include "incls/_precompiled.incl" duke@435: #include "incls/_assembler_x86_32.cpp.incl" duke@435: duke@435: // Implementation of AddressLiteral duke@435: duke@435: AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { duke@435: _is_lval = false; duke@435: _target = target; duke@435: switch (rtype) { duke@435: case relocInfo::oop_type: duke@435: // Oops are a special case. Normally they would be their own section duke@435: // but in cases like icBuffer they are literals in the code stream that duke@435: // we don't have a section for. We use none so that we get a literal address duke@435: // which is always patchable. duke@435: break; duke@435: case relocInfo::external_word_type: duke@435: _rspec = external_word_Relocation::spec(target); duke@435: break; duke@435: case relocInfo::internal_word_type: duke@435: _rspec = internal_word_Relocation::spec(target); duke@435: break; duke@435: case relocInfo::opt_virtual_call_type: duke@435: _rspec = opt_virtual_call_Relocation::spec(); duke@435: break; duke@435: case relocInfo::static_call_type: duke@435: _rspec = static_call_Relocation::spec(); duke@435: break; duke@435: case relocInfo::runtime_call_type: duke@435: _rspec = runtime_call_Relocation::spec(); duke@435: break; duke@435: case relocInfo::poll_type: duke@435: case relocInfo::poll_return_type: duke@435: _rspec = Relocation::spec_simple(rtype); duke@435: break; duke@435: case relocInfo::none: duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: break; duke@435: } duke@435: } duke@435: duke@435: // Implementation of Address duke@435: duke@435: Address Address::make_array(ArrayAddress adr) { duke@435: #ifdef _LP64 duke@435: // Not implementable on 64bit machines duke@435: // Should have been handled higher up the call chain. duke@435: ShouldNotReachHere(); duke@435: #else duke@435: AddressLiteral base = adr.base(); duke@435: Address index = adr.index(); duke@435: assert(index._disp == 0, "must not have disp"); // maybe it can? duke@435: Address array(index._base, index._index, index._scale, (intptr_t) base.target()); duke@435: array._rspec = base._rspec; duke@435: return array; duke@435: #endif // _LP64 duke@435: } duke@435: duke@435: #ifndef _LP64 duke@435: duke@435: // exceedingly dangerous constructor duke@435: Address::Address(address loc, RelocationHolder spec) { duke@435: _base = noreg; duke@435: _index = noreg; duke@435: _scale = no_scale; duke@435: _disp = (intptr_t) loc; duke@435: _rspec = spec; duke@435: } duke@435: #endif // _LP64 duke@435: duke@435: // Convert the raw encoding form into the form expected by the constructor for duke@435: // Address. An index of 4 (rsp) corresponds to having no index, so convert duke@435: // that to noreg for the Address constructor. duke@435: Address Address::make_raw(int base, int index, int scale, int disp) { duke@435: bool valid_index = index != rsp->encoding(); duke@435: if (valid_index) { duke@435: Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); duke@435: return madr; duke@435: } else { duke@435: Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); duke@435: return madr; duke@435: } duke@435: } duke@435: duke@435: // Implementation of Assembler duke@435: duke@435: int AbstractAssembler::code_fill_byte() { duke@435: return (u_char)'\xF4'; // hlt duke@435: } duke@435: duke@435: // make this go away someday duke@435: void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { duke@435: if (rtype == relocInfo::none) duke@435: emit_long(data); duke@435: else emit_data(data, Relocation::spec_simple(rtype), format); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { duke@435: assert(imm32_operand == 0, "default format must be imm32 in this file"); duke@435: assert(inst_mark() != NULL, "must be inside InstructionMark"); duke@435: if (rspec.type() != relocInfo::none) { duke@435: #ifdef ASSERT duke@435: check_relocation(rspec, format); duke@435: #endif duke@435: // Do not use AbstractAssembler::relocate, which is not intended for duke@435: // embedded words. Instead, relocate to the enclosing instruction. duke@435: duke@435: // hack. call32 is too wide for mask so use disp32 duke@435: if (format == call32_operand) duke@435: code_section()->relocate(inst_mark(), rspec, disp32_operand); duke@435: else duke@435: code_section()->relocate(inst_mark(), rspec, format); duke@435: } duke@435: emit_long(data); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { duke@435: assert(dst->has_byte_register(), "must have byte register"); duke@435: assert(isByte(op1) && isByte(op2), "wrong opcode"); duke@435: assert(isByte(imm8), "not a byte"); duke@435: assert((op1 & 0x01) == 0, "should be 8bit operation"); duke@435: emit_byte(op1); duke@435: emit_byte(op2 | dst->encoding()); duke@435: emit_byte(imm8); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) { duke@435: assert(isByte(op1) && isByte(op2), "wrong opcode"); duke@435: assert((op1 & 0x01) == 1, "should be 32bit operation"); duke@435: assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); duke@435: if (is8bit(imm32)) { duke@435: emit_byte(op1 | 0x02); // set sign bit duke@435: emit_byte(op2 | dst->encoding()); duke@435: emit_byte(imm32 & 0xFF); duke@435: } else { duke@435: emit_byte(op1); duke@435: emit_byte(op2 | dst->encoding()); duke@435: emit_long(imm32); duke@435: } duke@435: } duke@435: duke@435: // immediate-to-memory forms duke@435: void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) { duke@435: assert((op1 & 0x01) == 1, "should be 32bit operation"); duke@435: assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); duke@435: if (is8bit(imm32)) { duke@435: emit_byte(op1 | 0x02); // set sign bit duke@435: emit_operand(rm,adr); duke@435: emit_byte(imm32 & 0xFF); duke@435: } else { duke@435: emit_byte(op1); duke@435: emit_operand(rm,adr); duke@435: emit_long(imm32); duke@435: } duke@435: } duke@435: duke@435: void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { duke@435: assert(isByte(op1) && isByte(op2), "wrong opcode"); duke@435: assert((op1 & 0x01) == 1, "should be 32bit operation"); duke@435: assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); duke@435: InstructionMark im(this); duke@435: emit_byte(op1); duke@435: emit_byte(op2 | dst->encoding()); duke@435: emit_data((int)obj, relocInfo::oop_type, 0); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { duke@435: assert(isByte(op1) && isByte(op2), "wrong opcode"); duke@435: emit_byte(op1); duke@435: emit_byte(op2 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_operand(Register reg, duke@435: Register base, duke@435: Register index, duke@435: Address::ScaleFactor scale, duke@435: int disp, duke@435: RelocationHolder const& rspec) { duke@435: duke@435: relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); duke@435: if (base->is_valid()) { duke@435: if (index->is_valid()) { duke@435: assert(scale != Address::no_scale, "inconsistent address"); duke@435: // [base + index*scale + disp] duke@435: if (disp == 0 && rtype == relocInfo::none && base != rbp) { duke@435: // [base + index*scale] duke@435: // [00 reg 100][ss index base] duke@435: assert(index != rsp, "illegal addressing mode"); duke@435: emit_byte(0x04 | reg->encoding() << 3); duke@435: emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); duke@435: } else if (is8bit(disp) && rtype == relocInfo::none) { duke@435: // [base + index*scale + imm8] duke@435: // [01 reg 100][ss index base] imm8 duke@435: assert(index != rsp, "illegal addressing mode"); duke@435: emit_byte(0x44 | reg->encoding() << 3); duke@435: emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); duke@435: emit_byte(disp & 0xFF); duke@435: } else { duke@435: // [base + index*scale + imm32] duke@435: // [10 reg 100][ss index base] imm32 duke@435: assert(index != rsp, "illegal addressing mode"); duke@435: emit_byte(0x84 | reg->encoding() << 3); duke@435: emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); duke@435: emit_data(disp, rspec, disp32_operand); duke@435: } duke@435: } else if (base == rsp) { duke@435: // [esp + disp] duke@435: if (disp == 0 && rtype == relocInfo::none) { duke@435: // [esp] duke@435: // [00 reg 100][00 100 100] duke@435: emit_byte(0x04 | reg->encoding() << 3); duke@435: emit_byte(0x24); duke@435: } else if (is8bit(disp) && rtype == relocInfo::none) { duke@435: // [esp + imm8] duke@435: // [01 reg 100][00 100 100] imm8 duke@435: emit_byte(0x44 | reg->encoding() << 3); duke@435: emit_byte(0x24); duke@435: emit_byte(disp & 0xFF); duke@435: } else { duke@435: // [esp + imm32] duke@435: // [10 reg 100][00 100 100] imm32 duke@435: emit_byte(0x84 | reg->encoding() << 3); duke@435: emit_byte(0x24); duke@435: emit_data(disp, rspec, disp32_operand); duke@435: } duke@435: } else { duke@435: // [base + disp] duke@435: assert(base != rsp, "illegal addressing mode"); duke@435: if (disp == 0 && rtype == relocInfo::none && base != rbp) { duke@435: // [base] duke@435: // [00 reg base] duke@435: assert(base != rbp, "illegal addressing mode"); duke@435: emit_byte(0x00 | reg->encoding() << 3 | base->encoding()); duke@435: } else if (is8bit(disp) && rtype == relocInfo::none) { duke@435: // [base + imm8] duke@435: // [01 reg base] imm8 duke@435: emit_byte(0x40 | reg->encoding() << 3 | base->encoding()); duke@435: emit_byte(disp & 0xFF); duke@435: } else { duke@435: // [base + imm32] duke@435: // [10 reg base] imm32 duke@435: emit_byte(0x80 | reg->encoding() << 3 | base->encoding()); duke@435: emit_data(disp, rspec, disp32_operand); duke@435: } duke@435: } duke@435: } else { duke@435: if (index->is_valid()) { duke@435: assert(scale != Address::no_scale, "inconsistent address"); duke@435: // [index*scale + disp] duke@435: // [00 reg 100][ss index 101] imm32 duke@435: assert(index != rsp, "illegal addressing mode"); duke@435: emit_byte(0x04 | reg->encoding() << 3); duke@435: emit_byte(scale << 6 | index->encoding() << 3 | 0x05); duke@435: emit_data(disp, rspec, disp32_operand); duke@435: } else { duke@435: // [disp] duke@435: // [00 reg 101] imm32 duke@435: emit_byte(0x05 | reg->encoding() << 3); duke@435: emit_data(disp, rspec, disp32_operand); duke@435: } duke@435: } duke@435: } duke@435: duke@435: // Secret local extension to Assembler::WhichOperand: duke@435: #define end_pc_operand (_WhichOperand_limit) duke@435: duke@435: address Assembler::locate_operand(address inst, WhichOperand which) { duke@435: // Decode the given instruction, and return the address of duke@435: // an embedded 32-bit operand word. duke@435: duke@435: // If "which" is disp32_operand, selects the displacement portion duke@435: // of an effective address specifier. duke@435: // If "which" is imm32_operand, selects the trailing immediate constant. duke@435: // If "which" is call32_operand, selects the displacement of a call or jump. duke@435: // Caller is responsible for ensuring that there is such an operand, duke@435: // and that it is 32 bits wide. duke@435: duke@435: // If "which" is end_pc_operand, find the end of the instruction. duke@435: duke@435: address ip = inst; duke@435: duke@435: debug_only(bool has_imm32 = false); duke@435: int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn duke@435: duke@435: again_after_prefix: duke@435: switch (0xFF & *ip++) { duke@435: duke@435: // These convenience macros generate groups of "case" labels for the switch. duke@435: #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 duke@435: #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ duke@435: case (x)+4: case (x)+5: case (x)+6: case (x)+7 duke@435: #define REP16(x) REP8((x)+0): \ duke@435: case REP8((x)+8) duke@435: duke@435: case CS_segment: duke@435: case SS_segment: duke@435: case DS_segment: duke@435: case ES_segment: duke@435: case FS_segment: duke@435: case GS_segment: duke@435: assert(ip == inst+1, "only one prefix allowed"); duke@435: goto again_after_prefix; duke@435: duke@435: case 0xFF: // pushl a; decl a; incl a; call a; jmp a duke@435: case 0x88: // movb a, r duke@435: case 0x89: // movl a, r duke@435: case 0x8A: // movb r, a duke@435: case 0x8B: // movl r, a duke@435: case 0x8F: // popl a duke@435: break; duke@435: duke@435: case 0x68: // pushl #32(oop?) duke@435: if (which == end_pc_operand) return ip + 4; duke@435: assert(which == imm32_operand, "pushl has no disp32"); duke@435: return ip; // not produced by emit_operand duke@435: duke@435: case 0x66: // movw ... (size prefix) duke@435: switch (0xFF & *ip++) { duke@435: case 0x8B: // movw r, a duke@435: case 0x89: // movw a, r duke@435: break; duke@435: case 0xC7: // movw a, #16 duke@435: tail_size = 2; // the imm16 duke@435: break; duke@435: case 0x0F: // several SSE/SSE2 variants duke@435: ip--; // reparse the 0x0F duke@435: goto again_after_prefix; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: break; duke@435: duke@435: case REP8(0xB8): // movl r, #32(oop?) duke@435: if (which == end_pc_operand) return ip + 4; duke@435: assert(which == imm32_operand || which == disp32_operand, ""); duke@435: return ip; duke@435: duke@435: case 0x69: // imul r, a, #32 duke@435: case 0xC7: // movl a, #32(oop?) duke@435: tail_size = 4; duke@435: debug_only(has_imm32 = true); // has both kinds of operands! duke@435: break; duke@435: duke@435: case 0x0F: // movx..., etc. duke@435: switch (0xFF & *ip++) { duke@435: case 0x12: // movlps duke@435: case 0x28: // movaps duke@435: case 0x2E: // ucomiss duke@435: case 0x2F: // comiss duke@435: case 0x54: // andps duke@435: case 0x55: // andnps duke@435: case 0x56: // orps duke@435: case 0x57: // xorps duke@435: case 0x6E: // movd duke@435: case 0x7E: // movd duke@435: case 0xAE: // ldmxcsr a duke@435: // amd side says it these have both operands but that doesn't duke@435: // appear to be true. duke@435: // debug_only(has_imm32 = true); // has both kinds of operands! duke@435: break; duke@435: duke@435: case 0xAD: // shrd r, a, %cl duke@435: case 0xAF: // imul r, a duke@435: case 0xBE: // movsxb r, a duke@435: case 0xBF: // movsxw r, a duke@435: case 0xB6: // movzxb r, a duke@435: case 0xB7: // movzxw r, a duke@435: case REP16(0x40): // cmovl cc, r, a duke@435: case 0xB0: // cmpxchgb duke@435: case 0xB1: // cmpxchg duke@435: case 0xC1: // xaddl duke@435: case 0xC7: // cmpxchg8 duke@435: case REP16(0x90): // setcc a duke@435: // fall out of the switch to decode the address duke@435: break; duke@435: case 0xAC: // shrd r, a, #8 duke@435: tail_size = 1; // the imm8 duke@435: break; duke@435: case REP16(0x80): // jcc rdisp32 duke@435: if (which == end_pc_operand) return ip + 4; duke@435: assert(which == call32_operand, "jcc has no disp32 or imm32"); duke@435: return ip; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: break; duke@435: duke@435: case 0x81: // addl a, #32; addl r, #32 duke@435: // also: orl, adcl, sbbl, andl, subl, xorl, cmpl duke@435: // in the case of cmpl, the imm32 might be an oop duke@435: tail_size = 4; duke@435: debug_only(has_imm32 = true); // has both kinds of operands! duke@435: break; duke@435: duke@435: case 0x85: // test r/m, r duke@435: break; duke@435: duke@435: case 0x83: // addl a, #8; addl r, #8 duke@435: // also: orl, adcl, sbbl, andl, subl, xorl, cmpl duke@435: tail_size = 1; duke@435: break; duke@435: duke@435: case 0x9B: duke@435: switch (0xFF & *ip++) { duke@435: case 0xD9: // fnstcw a duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: break; duke@435: duke@435: case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a duke@435: case REP4(0x10): // adc... duke@435: case REP4(0x20): // and... duke@435: case REP4(0x30): // xor... duke@435: case REP4(0x08): // or... duke@435: case REP4(0x18): // sbb... duke@435: case REP4(0x28): // sub... duke@435: case REP4(0x38): // cmp... duke@435: case 0xF7: // mull a duke@435: case 0x8D: // leal r, a duke@435: case 0x87: // xchg r, a duke@435: break; duke@435: duke@435: case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 duke@435: case 0xC6: // movb a, #8 duke@435: case 0x80: // cmpb a, #8 duke@435: case 0x6B: // imul r, a, #8 duke@435: tail_size = 1; // the imm8 duke@435: break; duke@435: duke@435: case 0xE8: // call rdisp32 duke@435: case 0xE9: // jmp rdisp32 duke@435: if (which == end_pc_operand) return ip + 4; duke@435: assert(which == call32_operand, "call has no disp32 or imm32"); duke@435: return ip; duke@435: duke@435: case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 duke@435: case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl duke@435: case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a duke@435: case 0xDD: // fld_d a; fst_d a; fstp_d a duke@435: case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a duke@435: case 0xDF: // fild_d a; fistp_d a duke@435: case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a duke@435: case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a duke@435: case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a duke@435: break; duke@435: duke@435: case 0xF3: // For SSE duke@435: case 0xF2: // For SSE2 duke@435: ip++; ip++; duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: duke@435: #undef REP8 duke@435: #undef REP16 duke@435: } duke@435: duke@435: assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); duke@435: assert(which != imm32_operand || has_imm32, "instruction has no imm32 field"); duke@435: duke@435: // parse the output of emit_operand duke@435: int op2 = 0xFF & *ip++; duke@435: int base = op2 & 0x07; duke@435: int op3 = -1; duke@435: const int b100 = 4; duke@435: const int b101 = 5; duke@435: if (base == b100 && (op2 >> 6) != 3) { duke@435: op3 = 0xFF & *ip++; duke@435: base = op3 & 0x07; // refetch the base duke@435: } duke@435: // now ip points at the disp (if any) duke@435: duke@435: switch (op2 >> 6) { duke@435: case 0: duke@435: // [00 reg 100][ss index base] duke@435: // [00 reg 100][00 100 rsp] duke@435: // [00 reg base] duke@435: // [00 reg 100][ss index 101][disp32] duke@435: // [00 reg 101] [disp32] duke@435: duke@435: if (base == b101) { duke@435: if (which == disp32_operand) duke@435: return ip; // caller wants the disp32 duke@435: ip += 4; // skip the disp32 duke@435: } duke@435: break; duke@435: duke@435: case 1: duke@435: // [01 reg 100][ss index base][disp8] duke@435: // [01 reg 100][00 100 rsp][disp8] duke@435: // [01 reg base] [disp8] duke@435: ip += 1; // skip the disp8 duke@435: break; duke@435: duke@435: case 2: duke@435: // [10 reg 100][ss index base][disp32] duke@435: // [10 reg 100][00 100 rsp][disp32] duke@435: // [10 reg base] [disp32] duke@435: if (which == disp32_operand) duke@435: return ip; // caller wants the disp32 duke@435: ip += 4; // skip the disp32 duke@435: break; duke@435: duke@435: case 3: duke@435: // [11 reg base] (not a memory addressing mode) duke@435: break; duke@435: } duke@435: duke@435: if (which == end_pc_operand) { duke@435: return ip + tail_size; duke@435: } duke@435: duke@435: assert(which == imm32_operand, "instruction has only an imm32 field"); duke@435: return ip; duke@435: } duke@435: duke@435: address Assembler::locate_next_instruction(address inst) { duke@435: // Secretly share code with locate_operand: duke@435: return locate_operand(inst, end_pc_operand); duke@435: } duke@435: duke@435: duke@435: #ifdef ASSERT duke@435: void Assembler::check_relocation(RelocationHolder const& rspec, int format) { duke@435: address inst = inst_mark(); duke@435: assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); duke@435: address opnd; duke@435: duke@435: Relocation* r = rspec.reloc(); duke@435: if (r->type() == relocInfo::none) { duke@435: return; duke@435: } else if (r->is_call() || format == call32_operand) { duke@435: // assert(format == imm32_operand, "cannot specify a nonzero format"); duke@435: opnd = locate_operand(inst, call32_operand); duke@435: } else if (r->is_data()) { duke@435: assert(format == imm32_operand || format == disp32_operand, "format ok"); duke@435: opnd = locate_operand(inst, (WhichOperand)format); duke@435: } else { duke@435: assert(format == imm32_operand, "cannot specify a format"); duke@435: return; duke@435: } duke@435: assert(opnd == pc(), "must put operand where relocs can find it"); duke@435: } duke@435: #endif duke@435: duke@435: duke@435: duke@435: void Assembler::emit_operand(Register reg, Address adr) { duke@435: emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); duke@435: } duke@435: duke@435: duke@435: void Assembler::emit_farith(int b1, int b2, int i) { duke@435: assert(isByte(b1) && isByte(b2), "wrong opcode"); duke@435: assert(0 <= i && i < 8, "illegal stack offset"); duke@435: emit_byte(b1); duke@435: emit_byte(b2 + i); duke@435: } duke@435: duke@435: duke@435: void Assembler::pushad() { duke@435: emit_byte(0x60); duke@435: } duke@435: duke@435: void Assembler::popad() { duke@435: emit_byte(0x61); duke@435: } duke@435: duke@435: void Assembler::pushfd() { duke@435: emit_byte(0x9C); duke@435: } duke@435: duke@435: void Assembler::popfd() { duke@435: emit_byte(0x9D); duke@435: } duke@435: duke@435: void Assembler::pushl(int imm32) { duke@435: emit_byte(0x68); duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: #ifndef _LP64 duke@435: void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x68); duke@435: emit_data(imm32, rspec, 0); duke@435: } duke@435: #endif // _LP64 duke@435: duke@435: void Assembler::pushl(Register src) { duke@435: emit_byte(0x50 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::pushl(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xFF); duke@435: emit_operand(rsi, src); duke@435: } duke@435: duke@435: void Assembler::popl(Register dst) { duke@435: emit_byte(0x58 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::popl(Address dst) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x8F); duke@435: emit_operand(rax, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::prefix(Prefix p) { duke@435: a_byte(p); duke@435: } duke@435: duke@435: duke@435: void Assembler::movb(Register dst, Address src) { duke@435: assert(dst->has_byte_register(), "must have byte register"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x8A); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movb(Address dst, int imm8) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xC6); duke@435: emit_operand(rax, dst); duke@435: emit_byte(imm8); duke@435: } duke@435: duke@435: duke@435: void Assembler::movb(Address dst, Register src) { duke@435: assert(src->has_byte_register(), "must have byte register"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x88); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::movw(Address dst, int imm16) { duke@435: InstructionMark im(this); duke@435: duke@435: emit_byte(0x66); // switch to 16-bit mode duke@435: emit_byte(0xC7); duke@435: emit_operand(rax, dst); duke@435: emit_word(imm16); duke@435: } duke@435: duke@435: duke@435: void Assembler::movw(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x8B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movw(Address dst, Register src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x89); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::movl(Register dst, int imm32) { duke@435: emit_byte(0xB8 | dst->encoding()); duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: #ifndef _LP64 duke@435: void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0xB8 | dst->encoding()); duke@435: emit_data((int)imm32, rspec, 0); duke@435: } duke@435: #endif // _LP64 duke@435: duke@435: void Assembler::movl(Register dst, Register src) { duke@435: emit_byte(0x8B); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::movl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x8B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movl(Address dst, int imm32) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xC7); duke@435: emit_operand(rax, dst); duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: #ifndef _LP64 duke@435: void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xC7); duke@435: emit_operand(rax, dst); duke@435: emit_data((int)imm32, rspec, 0); duke@435: } duke@435: #endif // _LP64 duke@435: duke@435: void Assembler::movl(Address dst, Register src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x89); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::movsxb(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xBE); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: void Assembler::movsxb(Register dst, Register src) { duke@435: assert(src->has_byte_register(), "must have byte register"); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xBE); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::movsxw(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xBF); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movsxw(Register dst, Register src) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xBF); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::movzxb(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xB6); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movzxb(Register dst, Register src) { duke@435: assert(src->has_byte_register(), "must have byte register"); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xB6); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::movzxw(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xB7); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::movzxw(Register dst, Register src) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xB7); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::cmovl(Condition cc, Register dst, Register src) { duke@435: guarantee(VM_Version::supports_cmov(), "illegal instruction"); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x40 | cc); duke@435: emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::cmovl(Condition cc, Register dst, Address src) { duke@435: guarantee(VM_Version::supports_cmov(), "illegal instruction"); duke@435: // The code below seems to be wrong - however the manual is inconclusive duke@435: // do not use for now (remember to enable all callers when fixing this) duke@435: Unimplemented(); duke@435: // wrong bytes? duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x40 | cc); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetcht0(Address src) { duke@435: assert(VM_Version::supports_sse(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x18); duke@435: emit_operand(rcx, src); // 1, src duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetcht1(Address src) { duke@435: assert(VM_Version::supports_sse(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x18); duke@435: emit_operand(rdx, src); // 2, src duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetcht2(Address src) { duke@435: assert(VM_Version::supports_sse(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x18); duke@435: emit_operand(rbx, src); // 3, src duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetchnta(Address src) { duke@435: assert(VM_Version::supports_sse2(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x18); duke@435: emit_operand(rax, src); // 0, src duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetchw(Address src) { duke@435: assert(VM_Version::supports_3dnow(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x0D); duke@435: emit_operand(rcx, src); // 1, src duke@435: } duke@435: duke@435: duke@435: void Assembler::prefetchr(Address src) { duke@435: assert(VM_Version::supports_3dnow(), "must support"); duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x0D); duke@435: emit_operand(rax, src); // 0, src duke@435: } duke@435: duke@435: duke@435: void Assembler::adcl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xD0, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::adcl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x13); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::adcl(Register dst, Register src) { duke@435: emit_arith(0x13, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::addl(Address dst, int imm32) { duke@435: InstructionMark im(this); duke@435: emit_arith_operand(0x81,rax,dst,imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::addl(Address dst, Register src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x01); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::addl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xC0, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::addl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x03); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::addl(Register dst, Register src) { duke@435: emit_arith(0x03, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::andl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xE0, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::andl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x23); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::andl(Register dst, Register src) { duke@435: emit_arith(0x23, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::cmpb(Address dst, int imm8) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x80); duke@435: emit_operand(rdi, dst); duke@435: emit_byte(imm8); duke@435: } duke@435: duke@435: void Assembler::cmpw(Address dst, int imm16) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x81); duke@435: emit_operand(rdi, dst); duke@435: emit_word(imm16); duke@435: } duke@435: duke@435: void Assembler::cmpl(Address dst, int imm32) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x81); duke@435: emit_operand(rdi, dst); duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: #ifndef _LP64 duke@435: void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x81); duke@435: emit_byte(0xF8 | src1->encoding()); duke@435: emit_data(imm32, rspec, 0); duke@435: } duke@435: duke@435: void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x81); duke@435: emit_operand(rdi, src1); duke@435: emit_data(imm32, rspec, 0); duke@435: } duke@435: #endif // _LP64 duke@435: duke@435: duke@435: void Assembler::cmpl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xF8, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::cmpl(Register dst, Register src) { duke@435: emit_arith(0x3B, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::cmpl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x3B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::decl(Register dst) { duke@435: // Don't use it directly. Use MacroAssembler::decrement() instead. duke@435: emit_byte(0x48 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::decl(Address dst) { duke@435: // Don't use it directly. Use MacroAssembler::decrement() instead. duke@435: InstructionMark im(this); duke@435: emit_byte(0xFF); duke@435: emit_operand(rcx, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::idivl(Register src) { duke@435: emit_byte(0xF7); duke@435: emit_byte(0xF8 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::cdql() { duke@435: emit_byte(0x99); duke@435: } duke@435: duke@435: duke@435: void Assembler::imull(Register dst, Register src) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAF); duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::imull(Register dst, Register src, int value) { duke@435: if (is8bit(value)) { duke@435: emit_byte(0x6B); duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: emit_byte(value); duke@435: } else { duke@435: emit_byte(0x69); duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: emit_long(value); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::incl(Register dst) { duke@435: // Don't use it directly. Use MacroAssembler::increment() instead. duke@435: emit_byte(0x40 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::incl(Address dst) { duke@435: // Don't use it directly. Use MacroAssembler::increment() instead. duke@435: InstructionMark im(this); duke@435: emit_byte(0xFF); duke@435: emit_operand(rax, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::leal(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x8D); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: void Assembler::mull(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xF7); duke@435: emit_operand(rsp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::mull(Register src) { duke@435: emit_byte(0xF7); duke@435: emit_byte(0xE0 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::negl(Register dst) { duke@435: emit_byte(0xF7); duke@435: emit_byte(0xD8 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::notl(Register dst) { duke@435: emit_byte(0xF7); duke@435: emit_byte(0xD0 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::orl(Address dst, int imm32) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x81); duke@435: emit_operand(rcx, dst); duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: void Assembler::orl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xC8, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::orl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::orl(Register dst, Register src) { duke@435: emit_arith(0x0B, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::rcll(Register dst, int imm8) { duke@435: assert(isShiftCount(imm8), "illegal shift count"); duke@435: if (imm8 == 1) { duke@435: emit_byte(0xD1); duke@435: emit_byte(0xD0 | dst->encoding()); duke@435: } else { duke@435: emit_byte(0xC1); duke@435: emit_byte(0xD0 | dst->encoding()); duke@435: emit_byte(imm8); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::sarl(Register dst, int imm8) { duke@435: assert(isShiftCount(imm8), "illegal shift count"); duke@435: if (imm8 == 1) { duke@435: emit_byte(0xD1); duke@435: emit_byte(0xF8 | dst->encoding()); duke@435: } else { duke@435: emit_byte(0xC1); duke@435: emit_byte(0xF8 | dst->encoding()); duke@435: emit_byte(imm8); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::sarl(Register dst) { duke@435: emit_byte(0xD3); duke@435: emit_byte(0xF8 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::sbbl(Address dst, int imm32) { duke@435: InstructionMark im(this); duke@435: emit_arith_operand(0x81,rbx,dst,imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::sbbl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xD8, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::sbbl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x1B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::sbbl(Register dst, Register src) { duke@435: emit_arith(0x1B, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::shldl(Register dst, Register src) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xA5); duke@435: emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::shll(Register dst, int imm8) { duke@435: assert(isShiftCount(imm8), "illegal shift count"); duke@435: if (imm8 == 1 ) { duke@435: emit_byte(0xD1); duke@435: emit_byte(0xE0 | dst->encoding()); duke@435: } else { duke@435: emit_byte(0xC1); duke@435: emit_byte(0xE0 | dst->encoding()); duke@435: emit_byte(imm8); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::shll(Register dst) { duke@435: emit_byte(0xD3); duke@435: emit_byte(0xE0 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::shrdl(Register dst, Register src) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAD); duke@435: emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::shrl(Register dst, int imm8) { duke@435: assert(isShiftCount(imm8), "illegal shift count"); duke@435: emit_byte(0xC1); duke@435: emit_byte(0xE8 | dst->encoding()); duke@435: emit_byte(imm8); duke@435: } duke@435: duke@435: duke@435: void Assembler::shrl(Register dst) { duke@435: emit_byte(0xD3); duke@435: emit_byte(0xE8 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::subl(Address dst, int imm32) { duke@435: if (is8bit(imm32)) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x83); duke@435: emit_operand(rbp, dst); duke@435: emit_byte(imm32 & 0xFF); duke@435: } else { duke@435: InstructionMark im(this); duke@435: emit_byte(0x81); duke@435: emit_operand(rbp, dst); duke@435: emit_long(imm32); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::subl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xE8, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::subl(Address dst, Register src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x29); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::subl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x2B); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::subl(Register dst, Register src) { duke@435: emit_arith(0x2B, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::testb(Register dst, int imm8) { duke@435: assert(dst->has_byte_register(), "must have byte register"); duke@435: emit_arith_b(0xF6, 0xC0, dst, imm8); duke@435: } duke@435: duke@435: duke@435: void Assembler::testl(Register dst, int imm32) { duke@435: // not using emit_arith because test duke@435: // doesn't support sign-extension of duke@435: // 8bit operands duke@435: if (dst->encoding() == 0) { duke@435: emit_byte(0xA9); duke@435: } else { duke@435: emit_byte(0xF7); duke@435: emit_byte(0xC0 | dst->encoding()); duke@435: } duke@435: emit_long(imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::testl(Register dst, Register src) { duke@435: emit_arith(0x85, 0xC0, dst, src); duke@435: } duke@435: duke@435: void Assembler::testl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x85); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: void Assembler::xaddl(Address dst, Register src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xC1); duke@435: emit_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::xorl(Register dst, int imm32) { duke@435: emit_arith(0x81, 0xF0, dst, imm32); duke@435: } duke@435: duke@435: duke@435: void Assembler::xorl(Register dst, Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x33); duke@435: emit_operand(dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::xorl(Register dst, Register src) { duke@435: emit_arith(0x33, 0xC0, dst, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::bswap(Register reg) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0xC8 | reg->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::lock() { duke@435: if (Atomics & 1) { duke@435: // Emit either nothing, a NOP, or a NOP: prefix duke@435: emit_byte(0x90) ; duke@435: } else { duke@435: emit_byte(0xF0); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::xchg(Register reg, Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x87); duke@435: emit_operand(reg, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::xchgl(Register dst, Register src) { duke@435: emit_byte(0x87); duke@435: emit_byte(0xc0 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: // The 32-bit cmpxchg compares the value at adr with the contents of rax, duke@435: // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. duke@435: // The ZF is set if the compared values were equal, and cleared otherwise. duke@435: void Assembler::cmpxchg(Register reg, Address adr) { duke@435: if (Atomics & 2) { duke@435: // caveat: no instructionmark, so this isn't relocatable. duke@435: // Emit a synthetic, non-atomic, CAS equivalent. duke@435: // Beware. The synthetic form sets all ICCs, not just ZF. duke@435: // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) duke@435: cmpl (rax, adr) ; duke@435: movl (rax, adr) ; duke@435: if (reg != rax) { duke@435: Label L ; duke@435: jcc (Assembler::notEqual, L) ; duke@435: movl (adr, reg) ; duke@435: bind (L) ; duke@435: } duke@435: } else { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xB1); duke@435: emit_operand(reg, adr); duke@435: } duke@435: } duke@435: duke@435: // The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax, duke@435: // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded duke@435: // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. duke@435: void Assembler::cmpxchg8(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xc7); duke@435: emit_operand(rcx, adr); duke@435: } duke@435: duke@435: void Assembler::hlt() { duke@435: emit_byte(0xF4); duke@435: } duke@435: duke@435: duke@435: void Assembler::addr_nop_4() { duke@435: // 4 bytes: NOP DWORD PTR [EAX+0] duke@435: emit_byte(0x0F); duke@435: emit_byte(0x1F); duke@435: emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); duke@435: emit_byte(0); // 8-bits offset (1 byte) duke@435: } duke@435: duke@435: void Assembler::addr_nop_5() { duke@435: // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset duke@435: emit_byte(0x0F); duke@435: emit_byte(0x1F); duke@435: emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); duke@435: emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); duke@435: emit_byte(0); // 8-bits offset (1 byte) duke@435: } duke@435: duke@435: void Assembler::addr_nop_7() { duke@435: // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset duke@435: emit_byte(0x0F); duke@435: emit_byte(0x1F); duke@435: emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); duke@435: emit_long(0); // 32-bits offset (4 bytes) duke@435: } duke@435: duke@435: void Assembler::addr_nop_8() { duke@435: // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset duke@435: emit_byte(0x0F); duke@435: emit_byte(0x1F); duke@435: emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); duke@435: emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); duke@435: emit_long(0); // 32-bits offset (4 bytes) duke@435: } duke@435: duke@435: void Assembler::nop(int i) { duke@435: assert(i > 0, " "); duke@435: if (UseAddressNop && VM_Version::is_intel()) { duke@435: // duke@435: // Using multi-bytes nops "0x0F 0x1F [address]" for Intel duke@435: // 1: 0x90 duke@435: // 2: 0x66 0x90 duke@435: // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) duke@435: // 4: 0x0F 0x1F 0x40 0x00 duke@435: // 5: 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 duke@435: // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: duke@435: // The rest coding is Intel specific - don't use consecutive address nops duke@435: duke@435: // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 duke@435: // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 duke@435: // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 duke@435: // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 duke@435: duke@435: while(i >= 15) { duke@435: // For Intel don't generate consecutive addess nops (mix with regular nops) duke@435: i -= 15; duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: addr_nop_8(); duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x90); // nop duke@435: } duke@435: switch (i) { duke@435: case 14: duke@435: emit_byte(0x66); // size prefix duke@435: case 13: duke@435: emit_byte(0x66); // size prefix duke@435: case 12: duke@435: addr_nop_8(); duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x90); // nop duke@435: break; duke@435: case 11: duke@435: emit_byte(0x66); // size prefix duke@435: case 10: duke@435: emit_byte(0x66); // size prefix duke@435: case 9: duke@435: emit_byte(0x66); // size prefix duke@435: case 8: duke@435: addr_nop_8(); duke@435: break; duke@435: case 7: duke@435: addr_nop_7(); duke@435: break; duke@435: case 6: duke@435: emit_byte(0x66); // size prefix duke@435: case 5: duke@435: addr_nop_5(); duke@435: break; duke@435: case 4: duke@435: addr_nop_4(); duke@435: break; duke@435: case 3: duke@435: // Don't use "0x0F 0x1F 0x00" - need patching safe padding duke@435: emit_byte(0x66); // size prefix duke@435: case 2: duke@435: emit_byte(0x66); // size prefix duke@435: case 1: duke@435: emit_byte(0x90); // nop duke@435: break; duke@435: default: duke@435: assert(i == 0, " "); duke@435: } duke@435: return; duke@435: } duke@435: if (UseAddressNop && VM_Version::is_amd()) { duke@435: // duke@435: // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. duke@435: // 1: 0x90 duke@435: // 2: 0x66 0x90 duke@435: // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) duke@435: // 4: 0x0F 0x1F 0x40 0x00 duke@435: // 5: 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 duke@435: // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: duke@435: // The rest coding is AMD specific - use consecutive address nops duke@435: duke@435: // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 duke@435: // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 duke@435: // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 duke@435: // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 duke@435: // Size prefixes (0x66) are added for larger sizes duke@435: duke@435: while(i >= 22) { duke@435: i -= 11; duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); // size prefix duke@435: addr_nop_8(); duke@435: } duke@435: // Generate first nop for size between 21-12 duke@435: switch (i) { duke@435: case 21: duke@435: i -= 1; duke@435: emit_byte(0x66); // size prefix duke@435: case 20: duke@435: case 19: duke@435: i -= 1; duke@435: emit_byte(0x66); // size prefix duke@435: case 18: duke@435: case 17: duke@435: i -= 1; duke@435: emit_byte(0x66); // size prefix duke@435: case 16: duke@435: case 15: duke@435: i -= 8; duke@435: addr_nop_8(); duke@435: break; duke@435: case 14: duke@435: case 13: duke@435: i -= 7; duke@435: addr_nop_7(); duke@435: break; duke@435: case 12: duke@435: i -= 6; duke@435: emit_byte(0x66); // size prefix duke@435: addr_nop_5(); duke@435: break; duke@435: default: duke@435: assert(i < 12, " "); duke@435: } duke@435: duke@435: // Generate second nop for size between 11-1 duke@435: switch (i) { duke@435: case 11: duke@435: emit_byte(0x66); // size prefix duke@435: case 10: duke@435: emit_byte(0x66); // size prefix duke@435: case 9: duke@435: emit_byte(0x66); // size prefix duke@435: case 8: duke@435: addr_nop_8(); duke@435: break; duke@435: case 7: duke@435: addr_nop_7(); duke@435: break; duke@435: case 6: duke@435: emit_byte(0x66); // size prefix duke@435: case 5: duke@435: addr_nop_5(); duke@435: break; duke@435: case 4: duke@435: addr_nop_4(); duke@435: break; duke@435: case 3: duke@435: // Don't use "0x0F 0x1F 0x00" - need patching safe padding duke@435: emit_byte(0x66); // size prefix duke@435: case 2: duke@435: emit_byte(0x66); // size prefix duke@435: case 1: duke@435: emit_byte(0x90); // nop duke@435: break; duke@435: default: duke@435: assert(i == 0, " "); duke@435: } duke@435: return; duke@435: } duke@435: duke@435: // Using nops with size prefixes "0x66 0x90". duke@435: // From AMD Optimization Guide: duke@435: // 1: 0x90 duke@435: // 2: 0x66 0x90 duke@435: // 3: 0x66 0x66 0x90 duke@435: // 4: 0x66 0x66 0x66 0x90 duke@435: // 5: 0x66 0x66 0x90 0x66 0x90 duke@435: // 6: 0x66 0x66 0x90 0x66 0x66 0x90 duke@435: // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 duke@435: // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 duke@435: // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 duke@435: // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 duke@435: // duke@435: while(i > 12) { duke@435: i -= 4; duke@435: emit_byte(0x66); // size prefix duke@435: emit_byte(0x66); duke@435: emit_byte(0x66); duke@435: emit_byte(0x90); // nop duke@435: } duke@435: // 1 - 12 nops duke@435: if(i > 8) { duke@435: if(i > 9) { duke@435: i -= 1; duke@435: emit_byte(0x66); duke@435: } duke@435: i -= 3; duke@435: emit_byte(0x66); duke@435: emit_byte(0x66); duke@435: emit_byte(0x90); duke@435: } duke@435: // 1 - 8 nops duke@435: if(i > 4) { duke@435: if(i > 6) { duke@435: i -= 1; duke@435: emit_byte(0x66); duke@435: } duke@435: i -= 3; duke@435: emit_byte(0x66); duke@435: emit_byte(0x66); duke@435: emit_byte(0x90); duke@435: } duke@435: switch (i) { duke@435: case 4: duke@435: emit_byte(0x66); duke@435: case 3: duke@435: emit_byte(0x66); duke@435: case 2: duke@435: emit_byte(0x66); duke@435: case 1: duke@435: emit_byte(0x90); duke@435: break; duke@435: default: duke@435: assert(i == 0, " "); duke@435: } duke@435: } duke@435: duke@435: void Assembler::ret(int imm16) { duke@435: if (imm16 == 0) { duke@435: emit_byte(0xC3); duke@435: } else { duke@435: emit_byte(0xC2); duke@435: emit_word(imm16); duke@435: } duke@435: } duke@435: duke@435: duke@435: void Assembler::set_byte_if_not_zero(Register dst) { duke@435: emit_byte(0x0F); duke@435: emit_byte(0x95); duke@435: emit_byte(0xE0 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: // copies a single word from [esi] to [edi] duke@435: void Assembler::smovl() { duke@435: emit_byte(0xA5); duke@435: } duke@435: duke@435: // copies data from [esi] to [edi] using rcx double words (m32) duke@435: void Assembler::rep_movl() { duke@435: emit_byte(0xF3); duke@435: emit_byte(0xA5); duke@435: } duke@435: duke@435: duke@435: // sets rcx double words (m32) with rax, value at [edi] duke@435: void Assembler::rep_set() { duke@435: emit_byte(0xF3); duke@435: emit_byte(0xAB); duke@435: } duke@435: duke@435: // scans rcx double words (m32) at [edi] for occurance of rax, duke@435: void Assembler::repne_scan() { duke@435: emit_byte(0xF2); duke@435: emit_byte(0xAF); duke@435: } duke@435: duke@435: duke@435: void Assembler::setb(Condition cc, Register dst) { duke@435: assert(0 <= cc && cc < 16, "illegal cc"); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x90 | cc); duke@435: emit_byte(0xC0 | dst->encoding()); duke@435: } duke@435: duke@435: void Assembler::cld() { duke@435: emit_byte(0xfc); duke@435: } duke@435: duke@435: void Assembler::std() { duke@435: emit_byte(0xfd); duke@435: } duke@435: duke@435: void Assembler::emit_raw (unsigned char b) { duke@435: emit_byte (b) ; duke@435: } duke@435: duke@435: // Serializes memory. duke@435: void Assembler::membar() { duke@435: // Memory barriers are only needed on multiprocessors duke@435: if (os::is_MP()) { duke@435: if( VM_Version::supports_sse2() ) { duke@435: emit_byte( 0x0F ); // MFENCE; faster blows no regs duke@435: emit_byte( 0xAE ); duke@435: emit_byte( 0xF0 ); duke@435: } else { duke@435: // All usable chips support "locked" instructions which suffice duke@435: // as barriers, and are much faster than the alternative of duke@435: // using cpuid instruction. We use here a locked add [esp],0. duke@435: // This is conveniently otherwise a no-op except for blowing duke@435: // flags (which we save and restore.) duke@435: pushfd(); // Save eflags register duke@435: lock(); duke@435: addl(Address(rsp, 0), 0);// Assert the lock# signal here duke@435: popfd(); // Restore eflags register duke@435: } duke@435: } duke@435: } duke@435: duke@435: // Identify processor type and features duke@435: void Assembler::cpuid() { duke@435: // Note: we can't assert VM_Version::supports_cpuid() here duke@435: // because this instruction is used in the processor duke@435: // identification code. duke@435: emit_byte( 0x0F ); duke@435: emit_byte( 0xA2 ); duke@435: } duke@435: duke@435: void Assembler::call(Label& L, relocInfo::relocType rtype) { duke@435: if (L.is_bound()) { duke@435: const int long_size = 5; duke@435: int offs = target(L) - pc(); duke@435: assert(offs <= 0, "assembler error"); duke@435: InstructionMark im(this); duke@435: // 1110 1000 #32-bit disp duke@435: emit_byte(0xE8); duke@435: emit_data(offs - long_size, rtype, 0); duke@435: } else { duke@435: InstructionMark im(this); duke@435: // 1110 1000 #32-bit disp duke@435: L.add_patch_at(code(), locator()); duke@435: emit_byte(0xE8); duke@435: emit_data(int(0), rtype, 0); duke@435: } duke@435: } duke@435: duke@435: void Assembler::call(Register dst) { duke@435: emit_byte(0xFF); duke@435: emit_byte(0xD0 | dst->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::call(Address adr) { duke@435: InstructionMark im(this); duke@435: relocInfo::relocType rtype = adr.reloc(); duke@435: if (rtype != relocInfo::runtime_call_type) { duke@435: emit_byte(0xFF); duke@435: emit_operand(rdx, adr); duke@435: } else { duke@435: assert(false, "ack"); duke@435: } duke@435: duke@435: } duke@435: duke@435: void Assembler::call_literal(address dest, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xE8); duke@435: intptr_t disp = dest - (_code_pos + sizeof(int32_t)); duke@435: assert(dest != NULL, "must have a target"); duke@435: emit_data(disp, rspec, call32_operand); duke@435: duke@435: } duke@435: duke@435: void Assembler::jmp(Register entry) { duke@435: emit_byte(0xFF); duke@435: emit_byte(0xE0 | entry->encoding()); duke@435: } duke@435: duke@435: duke@435: void Assembler::jmp(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xFF); duke@435: emit_operand(rsp, adr); duke@435: } duke@435: duke@435: void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xE9); duke@435: assert(dest != NULL, "must have a target"); duke@435: intptr_t disp = dest - (_code_pos + sizeof(int32_t)); duke@435: emit_data(disp, rspec.reloc(), call32_operand); duke@435: } duke@435: duke@435: void Assembler::jmp(Label& L, relocInfo::relocType rtype) { duke@435: if (L.is_bound()) { duke@435: address entry = target(L); duke@435: assert(entry != NULL, "jmp most probably wrong"); duke@435: InstructionMark im(this); duke@435: const int short_size = 2; duke@435: const int long_size = 5; duke@435: intptr_t offs = entry - _code_pos; duke@435: if (rtype == relocInfo::none && is8bit(offs - short_size)) { duke@435: emit_byte(0xEB); duke@435: emit_byte((offs - short_size) & 0xFF); duke@435: } else { duke@435: emit_byte(0xE9); duke@435: emit_long(offs - long_size); duke@435: } duke@435: } else { duke@435: // By default, forward jumps are always 32-bit displacements, since duke@435: // we can't yet know where the label will be bound. If you're sure that duke@435: // the forward jump will not run beyond 256 bytes, use jmpb to duke@435: // force an 8-bit displacement. duke@435: InstructionMark im(this); duke@435: relocate(rtype); duke@435: L.add_patch_at(code(), locator()); duke@435: emit_byte(0xE9); duke@435: emit_long(0); duke@435: } duke@435: } duke@435: duke@435: void Assembler::jmpb(Label& L) { duke@435: if (L.is_bound()) { duke@435: const int short_size = 2; duke@435: address entry = target(L); duke@435: assert(is8bit((entry - _code_pos) + short_size), duke@435: "Dispacement too large for a short jmp"); duke@435: assert(entry != NULL, "jmp most probably wrong"); duke@435: intptr_t offs = entry - _code_pos; duke@435: emit_byte(0xEB); duke@435: emit_byte((offs - short_size) & 0xFF); duke@435: } else { duke@435: InstructionMark im(this); duke@435: L.add_patch_at(code(), locator()); duke@435: emit_byte(0xEB); duke@435: emit_byte(0); duke@435: } duke@435: } duke@435: duke@435: void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { duke@435: InstructionMark im(this); duke@435: relocate(rtype); duke@435: assert((0 <= cc) && (cc < 16), "illegal cc"); duke@435: if (L.is_bound()) { duke@435: address dst = target(L); duke@435: assert(dst != NULL, "jcc most probably wrong"); duke@435: duke@435: const int short_size = 2; duke@435: const int long_size = 6; duke@435: int offs = (int)dst - ((int)_code_pos); duke@435: if (rtype == relocInfo::none && is8bit(offs - short_size)) { duke@435: // 0111 tttn #8-bit disp duke@435: emit_byte(0x70 | cc); duke@435: emit_byte((offs - short_size) & 0xFF); duke@435: } else { duke@435: // 0000 1111 1000 tttn #32-bit disp duke@435: emit_byte(0x0F); duke@435: emit_byte(0x80 | cc); duke@435: emit_long(offs - long_size); duke@435: } duke@435: } else { duke@435: // Note: could eliminate cond. jumps to this jump if condition duke@435: // is the same however, seems to be rather unlikely case. duke@435: // Note: use jccb() if label to be bound is very close to get duke@435: // an 8-bit displacement duke@435: L.add_patch_at(code(), locator()); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x80 | cc); duke@435: emit_long(0); duke@435: } duke@435: } duke@435: duke@435: void Assembler::jccb(Condition cc, Label& L) { duke@435: if (L.is_bound()) { duke@435: const int short_size = 2; duke@435: address entry = target(L); duke@435: assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), duke@435: "Dispacement too large for a short jmp"); duke@435: intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; duke@435: // 0111 tttn #8-bit disp duke@435: emit_byte(0x70 | cc); duke@435: emit_byte((offs - short_size) & 0xFF); duke@435: jcc(cc, L); duke@435: } else { duke@435: InstructionMark im(this); duke@435: L.add_patch_at(code(), locator()); duke@435: emit_byte(0x70 | cc); duke@435: emit_byte(0); duke@435: } duke@435: } duke@435: duke@435: // FPU instructions duke@435: duke@435: void Assembler::fld1() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xE8); duke@435: } duke@435: duke@435: duke@435: void Assembler::fldz() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xEE); duke@435: } duke@435: duke@435: duke@435: void Assembler::fld_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD9); duke@435: emit_operand(rax, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fld_s (int index) { duke@435: emit_farith(0xD9, 0xC0, index); duke@435: } duke@435: duke@435: duke@435: void Assembler::fld_d(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDD); duke@435: emit_operand(rax, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fld_x(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDB); duke@435: emit_operand(rbp, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fst_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD9); duke@435: emit_operand(rdx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fst_d(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDD); duke@435: emit_operand(rdx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fstp_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD9); duke@435: emit_operand(rbx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fstp_d(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDD); duke@435: emit_operand(rbx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fstp_x(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDB); duke@435: emit_operand(rdi, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fstp_d(int index) { duke@435: emit_farith(0xDD, 0xD8, index); duke@435: } duke@435: duke@435: duke@435: void Assembler::fild_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDB); duke@435: emit_operand(rax, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fild_d(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDF); duke@435: emit_operand(rbp, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fistp_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDB); duke@435: emit_operand(rbx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fistp_d(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDF); duke@435: emit_operand(rdi, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fist_s(Address adr) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDB); duke@435: emit_operand(rdx, adr); duke@435: } duke@435: duke@435: duke@435: void Assembler::fabs() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xE1); duke@435: } duke@435: duke@435: duke@435: void Assembler::fldln2() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xED); duke@435: } duke@435: duke@435: void Assembler::fyl2x() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF1); duke@435: } duke@435: duke@435: duke@435: void Assembler::fldlg2() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xEC); duke@435: } duke@435: duke@435: duke@435: void Assembler::flog() { duke@435: fldln2(); duke@435: fxch(); duke@435: fyl2x(); duke@435: } duke@435: duke@435: duke@435: void Assembler::flog10() { duke@435: fldlg2(); duke@435: fxch(); duke@435: fyl2x(); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsin() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xFE); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcos() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xFF); duke@435: } duke@435: duke@435: void Assembler::ftan() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF2); duke@435: emit_byte(0xDD); duke@435: emit_byte(0xD8); duke@435: } duke@435: duke@435: void Assembler::fsqrt() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xFA); duke@435: } duke@435: duke@435: duke@435: void Assembler::fchs() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xE0); duke@435: } duke@435: duke@435: duke@435: void Assembler::fadd_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rax, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fadd_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rax, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fadd(int i) { duke@435: emit_farith(0xD8, 0xC0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fadda(int i) { duke@435: emit_farith(0xDC, 0xC0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsub_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rsp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsub_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rsp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubr_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rbp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubr_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rbp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fmul_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rcx, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fmul_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rcx, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fmul(int i) { duke@435: emit_farith(0xD8, 0xC8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fmula(int i) { duke@435: emit_farith(0xDC, 0xC8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdiv_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rsi, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdiv_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rsi, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdivr_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rdi, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdivr_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rdi, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsub(int i) { duke@435: emit_farith(0xD8, 0xE0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsuba(int i) { duke@435: emit_farith(0xDC, 0xE8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubr(int i) { duke@435: emit_farith(0xD8, 0xE8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubra(int i) { duke@435: emit_farith(0xDC, 0xE0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdiv(int i) { duke@435: emit_farith(0xD8, 0xF0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdiva(int i) { duke@435: emit_farith(0xDC, 0xF8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdivr(int i) { duke@435: emit_farith(0xD8, 0xF8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdivra(int i) { duke@435: emit_farith(0xDC, 0xF0, i); duke@435: } duke@435: duke@435: duke@435: // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) duke@435: // is erroneous for some of the floating-point instructions below. duke@435: duke@435: void Assembler::fdivp(int i) { duke@435: emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) duke@435: } duke@435: duke@435: duke@435: void Assembler::fdivrp(int i) { duke@435: emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubp(int i) { duke@435: emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) duke@435: } duke@435: duke@435: duke@435: void Assembler::fsubrp(int i) { duke@435: emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) duke@435: } duke@435: duke@435: duke@435: void Assembler::faddp(int i) { duke@435: emit_farith(0xDE, 0xC0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fmulp(int i) { duke@435: emit_farith(0xDE, 0xC8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fprem() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF8); duke@435: } duke@435: duke@435: duke@435: void Assembler::fprem1() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF5); duke@435: } duke@435: duke@435: duke@435: void Assembler::fxch(int i) { duke@435: emit_farith(0xD9, 0xC8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fincstp() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF7); duke@435: } duke@435: duke@435: duke@435: void Assembler::fdecstp() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xF6); duke@435: } duke@435: duke@435: duke@435: void Assembler::ffree(int i) { duke@435: emit_farith(0xDD, 0xC0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcomp_s(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD8); duke@435: emit_operand(rbx, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcomp_d(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDC); duke@435: emit_operand(rbx, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcom(int i) { duke@435: emit_farith(0xD8, 0xD0, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcomp(int i) { duke@435: emit_farith(0xD8, 0xD8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fcompp() { duke@435: emit_byte(0xDE); duke@435: emit_byte(0xD9); duke@435: } duke@435: duke@435: duke@435: void Assembler::fucomi(int i) { duke@435: // make sure the instruction is supported (introduced for P6, together with cmov) duke@435: guarantee(VM_Version::supports_cmov(), "illegal instruction"); duke@435: emit_farith(0xDB, 0xE8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::fucomip(int i) { duke@435: // make sure the instruction is supported (introduced for P6, together with cmov) duke@435: guarantee(VM_Version::supports_cmov(), "illegal instruction"); duke@435: emit_farith(0xDF, 0xE8, i); duke@435: } duke@435: duke@435: duke@435: void Assembler::ftst() { duke@435: emit_byte(0xD9); duke@435: emit_byte(0xE4); duke@435: } duke@435: duke@435: duke@435: void Assembler::fnstsw_ax() { duke@435: emit_byte(0xdF); duke@435: emit_byte(0xE0); duke@435: } duke@435: duke@435: duke@435: void Assembler::fwait() { duke@435: emit_byte(0x9B); duke@435: } duke@435: duke@435: duke@435: void Assembler::finit() { duke@435: emit_byte(0x9B); duke@435: emit_byte(0xDB); duke@435: emit_byte(0xE3); duke@435: } duke@435: duke@435: duke@435: void Assembler::fldcw(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xd9); duke@435: emit_operand(rbp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fnstcw(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x9B); duke@435: emit_byte(0xD9); duke@435: emit_operand(rdi, src); duke@435: } duke@435: duke@435: void Assembler::fnsave(Address dst) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDD); duke@435: emit_operand(rsi, dst); duke@435: } duke@435: duke@435: duke@435: void Assembler::frstor(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xDD); duke@435: emit_operand(rsp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::fldenv(Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0xD9); duke@435: emit_operand(rsp, src); duke@435: } duke@435: duke@435: duke@435: void Assembler::sahf() { duke@435: emit_byte(0x9E); duke@435: } duke@435: duke@435: // MMX operations duke@435: void Assembler::emit_operand(MMXRegister reg, Address adr) { duke@435: emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); duke@435: } duke@435: duke@435: void Assembler::movq( MMXRegister dst, Address src ) { duke@435: assert( VM_Version::supports_mmx(), "" ); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x6F); duke@435: emit_operand(dst,src); duke@435: } duke@435: duke@435: void Assembler::movq( Address dst, MMXRegister src ) { duke@435: assert( VM_Version::supports_mmx(), "" ); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x7F); duke@435: emit_operand(src,dst); duke@435: } duke@435: duke@435: void Assembler::emms() { duke@435: emit_byte(0x0F); duke@435: emit_byte(0x77); duke@435: } duke@435: duke@435: duke@435: duke@435: duke@435: // SSE and SSE2 instructions duke@435: inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) { duke@435: assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid"); duke@435: emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); duke@435: } duke@435: inline void Assembler::emit_sse_operand(Register reg, Address adr) { duke@435: emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); duke@435: } duke@435: duke@435: inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) { duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) { duke@435: emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); duke@435: } duke@435: duke@435: duke@435: // Macro for creation of SSE2 instructions duke@435: // The SSE2 instricution set is highly regular, so this macro saves duke@435: // a lot of cut&paste duke@435: // Each macro expansion creates two methods (same name with different duke@435: // parameter list) duke@435: // duke@435: // Macro parameters: duke@435: // * name: name of the created methods duke@435: // * sse_version: either sse or sse2 for the assertion if instruction supported by processor duke@435: // * prefix: first opcode byte of the instruction (or 0 if no prefix byte) duke@435: // * opcode: last opcode byte of the instruction duke@435: // * conversion instruction have parameters of type Register instead of XMMRegister, duke@435: // so this can also configured with macro parameters duke@435: #define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type) \ duke@435: \ duke@435: void Assembler:: name (dst_register_type dst, Address src) { \ duke@435: assert(VM_Version::supports_##sse_version(), ""); \ duke@435: \ duke@435: InstructionMark im(this); \ duke@435: if (prefix != 0) emit_byte(prefix); \ duke@435: emit_byte(0x0F); \ duke@435: emit_byte(opcode); \ duke@435: emit_sse_operand(dst, src); \ duke@435: } \ duke@435: \ duke@435: void Assembler:: name (dst_register_type dst, src_register_type src) { \ duke@435: assert(VM_Version::supports_##sse_version(), ""); \ duke@435: \ duke@435: if (prefix != 0) emit_byte(prefix); \ duke@435: emit_byte(0x0F); \ duke@435: emit_byte(opcode); \ duke@435: emit_sse_operand(dst, src); \ duke@435: } \ duke@435: duke@435: emit_sse_instruction(addss, sse, 0xF3, 0x58, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(addsd, sse2, 0xF2, 0x58, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(subss, sse, 0xF3, 0x5C, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(subsd, sse2, 0xF2, 0x5C, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(mulss, sse, 0xF3, 0x59, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(mulsd, sse2, 0xF2, 0x59, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(divss, sse, 0xF3, 0x5E, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(divsd, sse2, 0xF2, 0x5E, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(sqrtss, sse, 0xF3, 0x51, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister) duke@435: duke@435: emit_sse_instruction(pxor, sse2, 0x66, 0xEF, XMMRegister, XMMRegister) duke@435: duke@435: emit_sse_instruction(comiss, sse, 0, 0x2F, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(comisd, sse2, 0x66, 0x2F, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(ucomiss, sse, 0, 0x2E, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister) duke@435: duke@435: emit_sse_instruction(cvtss2sd, sse2, 0xF3, 0x5A, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(cvtsd2ss, sse2, 0xF2, 0x5A, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(cvtsi2ss, sse, 0xF3, 0x2A, XMMRegister, Register); duke@435: emit_sse_instruction(cvtsi2sd, sse2, 0xF2, 0x2A, XMMRegister, Register) duke@435: emit_sse_instruction(cvtss2si, sse, 0xF3, 0x2D, Register, XMMRegister); duke@435: emit_sse_instruction(cvtsd2si, sse2, 0xF2, 0x2D, Register, XMMRegister) duke@435: emit_sse_instruction(cvttss2si, sse, 0xF3, 0x2C, Register, XMMRegister); duke@435: emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister) duke@435: duke@435: emit_sse_instruction(movss, sse, 0xF3, 0x10, XMMRegister, XMMRegister) duke@435: emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister) duke@435: duke@435: emit_sse_instruction(movq, sse2, 0xF3, 0x7E, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(movd, sse2, 0x66, 0x6E, XMMRegister, Register); duke@435: emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister); duke@435: duke@435: emit_sse_instruction(punpcklbw, sse2, 0x66, 0x60, XMMRegister, XMMRegister); duke@435: duke@435: duke@435: // Instruction not covered by macro duke@435: void Assembler::movq(Address dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xD6); duke@435: emit_sse_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::movd(Address dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x7E); duke@435: emit_sse_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::movd(Register dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x7E); duke@435: emit_sse_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::movdqa(Address dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x7F); duke@435: emit_sse_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { duke@435: assert(isByte(mode), "invalid value"); duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x70); duke@435: emit_sse_operand(dst, src); duke@435: emit_byte(mode & 0xFF); duke@435: } duke@435: duke@435: void Assembler::pshufd(XMMRegister dst, Address src, int mode) { duke@435: assert(isByte(mode), "invalid value"); duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x70); duke@435: emit_sse_operand(dst, src); duke@435: emit_byte(mode & 0xFF); duke@435: } duke@435: duke@435: void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { duke@435: assert(isByte(mode), "invalid value"); duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: emit_byte(0xF2); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x70); duke@435: emit_sse_operand(dst, src); duke@435: emit_byte(mode & 0xFF); duke@435: } duke@435: duke@435: void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { duke@435: assert(isByte(mode), "invalid value"); duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0xF2); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x70); duke@435: emit_sse_operand(dst, src); duke@435: emit_byte(mode & 0xFF); duke@435: } duke@435: duke@435: void Assembler::psrlq(XMMRegister dst, int shift) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x73); duke@435: emit_sse_operand(xmm2, dst); duke@435: emit_byte(shift); duke@435: } duke@435: duke@435: void Assembler::movss( Address dst, XMMRegister src ) { duke@435: assert(VM_Version::supports_sse(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0xF3); // single duke@435: emit_byte(0x0F); duke@435: emit_byte(0x11); // store duke@435: emit_sse_operand(src, dst); duke@435: } duke@435: duke@435: void Assembler::movsd( Address dst, XMMRegister src ) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0xF2); // double duke@435: emit_byte(0x0F); duke@435: emit_byte(0x11); // store duke@435: emit_sse_operand(src,dst); duke@435: } duke@435: duke@435: // New cpus require to use movaps and movapd to avoid partial register stall duke@435: // when moving between registers. duke@435: void Assembler::movaps(XMMRegister dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse(), ""); duke@435: duke@435: emit_byte(0x0F); duke@435: emit_byte(0x28); duke@435: emit_sse_operand(dst, src); duke@435: } duke@435: void Assembler::movapd(XMMRegister dst, XMMRegister src) { duke@435: assert(VM_Version::supports_sse2(), ""); duke@435: duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x28); duke@435: emit_sse_operand(dst, src); duke@435: } duke@435: duke@435: // New cpus require to use movsd and movss to avoid partial register stall duke@435: // when loading from memory. But for old Opteron use movlpd instead of movsd. duke@435: // The selection is done in MacroAssembler::movdbl() and movflt(). duke@435: void Assembler::movlpd(XMMRegister dst, Address src) { duke@435: assert(VM_Version::supports_sse(), ""); duke@435: duke@435: InstructionMark im(this); duke@435: emit_byte(0x66); duke@435: emit_byte(0x0F); duke@435: emit_byte(0x12); duke@435: emit_sse_operand(dst, src); duke@435: } duke@435: kvn@506: void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { kvn@506: assert(VM_Version::supports_sse2(), ""); kvn@506: kvn@506: emit_byte(0xF3); kvn@506: emit_byte(0x0F); kvn@506: emit_byte(0xE6); kvn@506: emit_sse_operand(dst, src); kvn@506: } kvn@506: kvn@506: void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { kvn@506: assert(VM_Version::supports_sse2(), ""); kvn@506: kvn@506: emit_byte(0x0F); kvn@506: emit_byte(0x5B); kvn@506: emit_sse_operand(dst, src); kvn@506: } duke@435: duke@435: emit_sse_instruction(andps, sse, 0, 0x54, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(andpd, sse2, 0x66, 0x54, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(andnps, sse, 0, 0x55, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(orps, sse, 0, 0x56, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(orpd, sse2, 0x66, 0x56, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(xorps, sse, 0, 0x57, XMMRegister, XMMRegister); duke@435: emit_sse_instruction(xorpd, sse2, 0x66, 0x57, XMMRegister, XMMRegister); duke@435: duke@435: duke@435: void Assembler::ldmxcsr( Address src) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAE); duke@435: emit_operand(rdx /* 2 */, src); duke@435: } duke@435: duke@435: void Assembler::stmxcsr( Address dst) { duke@435: InstructionMark im(this); duke@435: emit_byte(0x0F); duke@435: emit_byte(0xAE); duke@435: emit_operand(rbx /* 3 */, dst); duke@435: } duke@435: duke@435: // Implementation of MacroAssembler duke@435: duke@435: Address MacroAssembler::as_Address(AddressLiteral adr) { duke@435: // amd64 always does this as a pc-rel duke@435: // we can be absolute or disp based on the instruction type duke@435: // jmp/call are displacements others are absolute duke@435: assert(!adr.is_lval(), "must be rval"); duke@435: duke@435: return Address(adr.target(), adr.rspec()); duke@435: } duke@435: duke@435: Address MacroAssembler::as_Address(ArrayAddress adr) { duke@435: return Address::make_array(adr); duke@435: } duke@435: duke@435: void MacroAssembler::fat_nop() { duke@435: // A 5 byte nop that is safe for patching (see patch_verified_entry) duke@435: emit_byte(0x26); // es: duke@435: emit_byte(0x2e); // cs: duke@435: emit_byte(0x64); // fs: duke@435: emit_byte(0x65); // gs: duke@435: emit_byte(0x90); duke@435: } duke@435: duke@435: // 32bit can do a case table jump in one instruction but we no longer allow the base duke@435: // to be installed in the Address class duke@435: void MacroAssembler::jump(ArrayAddress entry) { duke@435: jmp(as_Address(entry)); duke@435: } duke@435: duke@435: void MacroAssembler::jump(AddressLiteral dst) { duke@435: jmp_literal(dst.target(), dst.rspec()); duke@435: } duke@435: duke@435: void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { duke@435: assert((0 <= cc) && (cc < 16), "illegal cc"); duke@435: duke@435: InstructionMark im(this); duke@435: duke@435: relocInfo::relocType rtype = dst.reloc(); duke@435: relocate(rtype); duke@435: const int short_size = 2; duke@435: const int long_size = 6; duke@435: int offs = (int)dst.target() - ((int)_code_pos); duke@435: if (rtype == relocInfo::none && is8bit(offs - short_size)) { duke@435: // 0111 tttn #8-bit disp duke@435: emit_byte(0x70 | cc); duke@435: emit_byte((offs - short_size) & 0xFF); duke@435: } else { duke@435: // 0000 1111 1000 tttn #32-bit disp duke@435: emit_byte(0x0F); duke@435: emit_byte(0x80 | cc); duke@435: emit_long(offs - long_size); duke@435: } duke@435: } duke@435: duke@435: // Calls duke@435: void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { duke@435: Assembler::call(L, rtype); duke@435: } duke@435: duke@435: void MacroAssembler::call(Register entry) { duke@435: Assembler::call(entry); duke@435: } duke@435: duke@435: void MacroAssembler::call(AddressLiteral entry) { duke@435: Assembler::call_literal(entry.target(), entry.rspec()); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) { duke@435: Assembler::cmpb(as_Address(src1), imm); duke@435: } duke@435: duke@435: void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { duke@435: Assembler::cmpl(as_Address(src1), imm); duke@435: } duke@435: duke@435: void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { duke@435: if (src2.is_lval()) { duke@435: cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); duke@435: } else { duke@435: Assembler::cmpl(src1, as_Address(src2)); duke@435: } duke@435: } duke@435: duke@435: void MacroAssembler::cmp32(Register src1, int32_t imm) { duke@435: Assembler::cmpl(src1, imm); duke@435: } duke@435: duke@435: void MacroAssembler::cmp32(Register src1, Address src2) { duke@435: Assembler::cmpl(src1, src2); duke@435: } duke@435: duke@435: void MacroAssembler::cmpoop(Address src1, jobject obj) { duke@435: cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); duke@435: } duke@435: duke@435: void MacroAssembler::cmpoop(Register src1, jobject obj) { duke@435: cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); duke@435: } duke@435: duke@435: void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { duke@435: if (src2.is_lval()) { duke@435: // compare the effect address of src2 to src1 duke@435: cmp_literal32(src1, (int32_t)src2.target(), src2.rspec()); duke@435: } else { duke@435: Assembler::cmpl(src1, as_Address(src2)); duke@435: } duke@435: } duke@435: duke@435: void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { duke@435: assert(src2.is_lval(), "not a mem-mem compare"); duke@435: cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) { duke@435: cmpxchg(reg, as_Address(adr)); duke@435: } duke@435: duke@435: void MacroAssembler::increment(AddressLiteral dst) { duke@435: increment(as_Address(dst)); duke@435: } duke@435: duke@435: void MacroAssembler::increment(ArrayAddress dst) { duke@435: increment(as_Address(dst)); duke@435: } duke@435: duke@435: void MacroAssembler::lea(Register dst, AddressLiteral adr) { duke@435: // leal(dst, as_Address(adr)); duke@435: // see note in movl as to why we musr use a move duke@435: mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); duke@435: } duke@435: duke@435: void MacroAssembler::lea(Address dst, AddressLiteral adr) { duke@435: // leal(dst, as_Address(adr)); duke@435: // see note in movl as to why we musr use a move duke@435: mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); duke@435: } duke@435: duke@435: void MacroAssembler::mov32(AddressLiteral dst, Register src) { duke@435: Assembler::movl(as_Address(dst), src); duke@435: } duke@435: duke@435: void MacroAssembler::mov32(Register dst, AddressLiteral src) { duke@435: Assembler::movl(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::movbyte(ArrayAddress dst, int src) { duke@435: movb(as_Address(dst), src); duke@435: } duke@435: duke@435: void MacroAssembler::movoop(Address dst, jobject obj) { duke@435: mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); duke@435: } duke@435: duke@435: void MacroAssembler::movoop(Register dst, jobject obj) { duke@435: mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); duke@435: } duke@435: duke@435: void MacroAssembler::movptr(Register dst, AddressLiteral src) { duke@435: if (src.is_lval()) { duke@435: // essentially an lea duke@435: mov_literal32(dst, (int32_t) src.target(), src.rspec()); duke@435: } else { duke@435: // mov 32bits from an absolute address duke@435: movl(dst, as_Address(src)); duke@435: } duke@435: } duke@435: duke@435: void MacroAssembler::movptr(ArrayAddress dst, Register src) { duke@435: movl(as_Address(dst), src); duke@435: } duke@435: duke@435: void MacroAssembler::movptr(Register dst, ArrayAddress src) { duke@435: movl(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { duke@435: movss(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { duke@435: if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; } duke@435: else { movlpd(dst, as_Address(src)); return; } duke@435: } duke@435: duke@435: void Assembler::pushoop(jobject obj) { duke@435: push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pushptr(AddressLiteral src) { duke@435: if (src.is_lval()) { duke@435: push_literal32((int32_t)src.target(), src.rspec()); duke@435: } else { duke@435: pushl(as_Address(src)); duke@435: } duke@435: } duke@435: duke@435: void MacroAssembler::test32(Register src1, AddressLiteral src2) { duke@435: // src2 must be rval duke@435: testl(src1, as_Address(src2)); duke@435: } duke@435: duke@435: // FPU duke@435: duke@435: void MacroAssembler::fld_x(AddressLiteral src) { duke@435: Assembler::fld_x(as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::fld_d(AddressLiteral src) { duke@435: fld_d(as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::fld_s(AddressLiteral src) { duke@435: fld_s(as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::fldcw(AddressLiteral src) { duke@435: Assembler::fldcw(as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::ldmxcsr(AddressLiteral src) { duke@435: Assembler::ldmxcsr(as_Address(src)); duke@435: } duke@435: duke@435: // SSE duke@435: duke@435: void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { duke@435: andpd(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { duke@435: comisd(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { duke@435: comiss(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { duke@435: movsd(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { duke@435: movss(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { duke@435: xorpd(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { duke@435: xorps(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { duke@435: ucomisd(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { duke@435: ucomiss(dst, as_Address(src)); duke@435: } duke@435: duke@435: void MacroAssembler::null_check(Register reg, int offset) { duke@435: if (needs_explicit_null_check(offset)) { duke@435: // provoke OS NULL exception if reg = NULL by duke@435: // accessing M[reg] w/o changing any (non-CC) registers duke@435: cmpl(rax, Address(reg, 0)); duke@435: // Note: should probably use testl(rax, Address(reg, 0)); duke@435: // may be shorter code (however, this version of duke@435: // testl needs to be implemented first) duke@435: } else { duke@435: // nothing to do, (later) access of M[reg + offset] duke@435: // will provoke OS NULL exception if reg = NULL duke@435: } duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::load_unsigned_byte(Register dst, Address src) { duke@435: // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, duke@435: // and "3.9 Partial Register Penalties", p. 22). duke@435: int off; duke@435: if (VM_Version::is_P6() || src.uses(dst)) { duke@435: off = offset(); duke@435: movzxb(dst, src); duke@435: } else { duke@435: xorl(dst, dst); duke@435: off = offset(); duke@435: movb(dst, src); duke@435: } duke@435: return off; duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::load_unsigned_word(Register dst, Address src) { duke@435: // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, duke@435: // and "3.9 Partial Register Penalties", p. 22). duke@435: int off; duke@435: if (VM_Version::is_P6() || src.uses(dst)) { duke@435: off = offset(); duke@435: movzxw(dst, src); duke@435: } else { duke@435: xorl(dst, dst); duke@435: off = offset(); duke@435: movw(dst, src); duke@435: } duke@435: return off; duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::load_signed_byte(Register dst, Address src) { duke@435: int off; duke@435: if (VM_Version::is_P6()) { duke@435: off = offset(); duke@435: movsxb(dst, src); duke@435: } else { duke@435: off = load_unsigned_byte(dst, src); duke@435: shll(dst, 24); duke@435: sarl(dst, 24); duke@435: } duke@435: return off; duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::load_signed_word(Register dst, Address src) { duke@435: int off; duke@435: if (VM_Version::is_P6()) { duke@435: off = offset(); duke@435: movsxw(dst, src); duke@435: } else { duke@435: off = load_unsigned_word(dst, src); duke@435: shll(dst, 16); duke@435: sarl(dst, 16); duke@435: } duke@435: return off; duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::extend_sign(Register hi, Register lo) { duke@435: // According to Intel Doc. AP-526, "Integer Divide", p.18. duke@435: if (VM_Version::is_P6() && hi == rdx && lo == rax) { duke@435: cdql(); duke@435: } else { duke@435: movl(hi, lo); duke@435: sarl(hi, 31); duke@435: } duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::increment(Register reg, int value) { duke@435: if (value == min_jint) {addl(reg, value); return; } duke@435: if (value < 0) { decrement(reg, -value); return; } duke@435: if (value == 0) { ; return; } duke@435: if (value == 1 && UseIncDec) { incl(reg); return; } duke@435: /* else */ { addl(reg, value) ; return; } duke@435: } duke@435: duke@435: void MacroAssembler::increment(Address dst, int value) { duke@435: if (value == min_jint) {addl(dst, value); return; } duke@435: if (value < 0) { decrement(dst, -value); return; } duke@435: if (value == 0) { ; return; } duke@435: if (value == 1 && UseIncDec) { incl(dst); return; } duke@435: /* else */ { addl(dst, value) ; return; } duke@435: } duke@435: duke@435: void MacroAssembler::decrement(Register reg, int value) { duke@435: if (value == min_jint) {subl(reg, value); return; } duke@435: if (value < 0) { increment(reg, -value); return; } duke@435: if (value == 0) { ; return; } duke@435: if (value == 1 && UseIncDec) { decl(reg); return; } duke@435: /* else */ { subl(reg, value) ; return; } duke@435: } duke@435: duke@435: void MacroAssembler::decrement(Address dst, int value) { duke@435: if (value == min_jint) {subl(dst, value); return; } duke@435: if (value < 0) { increment(dst, -value); return; } duke@435: if (value == 0) { ; return; } duke@435: if (value == 1 && UseIncDec) { decl(dst); return; } duke@435: /* else */ { subl(dst, value) ; return; } duke@435: } duke@435: duke@435: void MacroAssembler::align(int modulus) { duke@435: if (offset() % modulus != 0) nop(modulus - (offset() % modulus)); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::enter() { duke@435: pushl(rbp); duke@435: movl(rbp, rsp); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::leave() { duke@435: movl(rsp, rbp); duke@435: popl(rbp); duke@435: } duke@435: duke@435: void MacroAssembler::set_last_Java_frame(Register java_thread, duke@435: Register last_java_sp, duke@435: Register last_java_fp, duke@435: address last_java_pc) { duke@435: // determine java_thread register duke@435: if (!java_thread->is_valid()) { duke@435: java_thread = rdi; duke@435: get_thread(java_thread); duke@435: } duke@435: // determine last_java_sp register duke@435: if (!last_java_sp->is_valid()) { duke@435: last_java_sp = rsp; duke@435: } duke@435: duke@435: // last_java_fp is optional duke@435: duke@435: if (last_java_fp->is_valid()) { duke@435: movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); duke@435: } duke@435: duke@435: // last_java_pc is optional duke@435: duke@435: if (last_java_pc != NULL) { duke@435: lea(Address(java_thread, duke@435: JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), duke@435: InternalAddress(last_java_pc)); duke@435: duke@435: } duke@435: movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); duke@435: } duke@435: duke@435: void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { duke@435: // determine java_thread register duke@435: if (!java_thread->is_valid()) { duke@435: java_thread = rdi; duke@435: get_thread(java_thread); duke@435: } duke@435: // we must set sp to zero to clear frame duke@435: movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0); duke@435: if (clear_fp) { duke@435: movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0); duke@435: } duke@435: duke@435: if (clear_pc) duke@435: movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0); duke@435: duke@435: } duke@435: duke@435: duke@435: duke@435: // Implementation of call_VM versions duke@435: duke@435: void MacroAssembler::call_VM_leaf_base( duke@435: address entry_point, duke@435: int number_of_arguments duke@435: ) { duke@435: call(RuntimeAddress(entry_point)); duke@435: increment(rsp, number_of_arguments * wordSize); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM_base( duke@435: Register oop_result, duke@435: Register java_thread, duke@435: Register last_java_sp, duke@435: address entry_point, duke@435: int number_of_arguments, duke@435: bool check_exceptions duke@435: ) { duke@435: // determine java_thread register duke@435: if (!java_thread->is_valid()) { duke@435: java_thread = rdi; duke@435: get_thread(java_thread); duke@435: } duke@435: // determine last_java_sp register duke@435: if (!last_java_sp->is_valid()) { duke@435: last_java_sp = rsp; duke@435: } duke@435: // debugging support duke@435: assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); duke@435: assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); duke@435: assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); duke@435: // push java thread (becomes first argument of C function) duke@435: pushl(java_thread); duke@435: // set last Java frame before call duke@435: assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,"); duke@435: // Only interpreter should have to set fp duke@435: set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); duke@435: // do the call duke@435: call(RuntimeAddress(entry_point)); duke@435: // restore the thread (cannot use the pushed argument since arguments duke@435: // may be overwritten by C code generated by an optimizing compiler); duke@435: // however can use the register value directly if it is callee saved. duke@435: if (java_thread == rdi || java_thread == rsi) { duke@435: // rdi & rsi are callee saved -> nothing to do duke@435: #ifdef ASSERT duke@435: guarantee(java_thread != rax, "change this code"); duke@435: pushl(rax); duke@435: { Label L; duke@435: get_thread(rax); duke@435: cmpl(java_thread, rax); duke@435: jcc(Assembler::equal, L); duke@435: stop("MacroAssembler::call_VM_base: rdi not callee saved?"); duke@435: bind(L); duke@435: } duke@435: popl(rax); duke@435: #endif duke@435: } else { duke@435: get_thread(java_thread); duke@435: } duke@435: // reset last Java frame duke@435: // Only interpreter should have to clear fp duke@435: reset_last_Java_frame(java_thread, true, false); duke@435: // discard thread and arguments duke@435: addl(rsp, (1 + number_of_arguments)*wordSize); duke@435: duke@435: #ifndef CC_INTERP duke@435: // C++ interp handles this in the interpreter duke@435: check_and_handle_popframe(java_thread); duke@435: check_and_handle_earlyret(java_thread); duke@435: #endif /* CC_INTERP */ duke@435: duke@435: if (check_exceptions) { duke@435: // check for pending exceptions (java_thread is set upon return) duke@435: cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD); duke@435: jump_cc(Assembler::notEqual, duke@435: RuntimeAddress(StubRoutines::forward_exception_entry())); duke@435: } duke@435: duke@435: // get oop result if there is one and reset the value in the thread duke@435: if (oop_result->is_valid()) { duke@435: movl(oop_result, Address(java_thread, JavaThread::vm_result_offset())); duke@435: movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); duke@435: verify_oop(oop_result); duke@435: } duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::check_and_handle_popframe(Register java_thread) { duke@435: } duke@435: duke@435: void MacroAssembler::check_and_handle_earlyret(Register java_thread) { duke@435: } duke@435: duke@435: void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { duke@435: leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); duke@435: call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) { duke@435: Label C, E; duke@435: call(C, relocInfo::none); duke@435: jmp(E); duke@435: duke@435: bind(C); duke@435: call_VM_helper(oop_result, entry_point, 0, check_exceptions); duke@435: ret(0); duke@435: duke@435: bind(E); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { duke@435: Label C, E; duke@435: call(C, relocInfo::none); duke@435: jmp(E); duke@435: duke@435: bind(C); duke@435: pushl(arg_1); duke@435: call_VM_helper(oop_result, entry_point, 1, check_exceptions); duke@435: ret(0); duke@435: duke@435: bind(E); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { duke@435: Label C, E; duke@435: call(C, relocInfo::none); duke@435: jmp(E); duke@435: duke@435: bind(C); duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM_helper(oop_result, entry_point, 2, check_exceptions); duke@435: ret(0); duke@435: duke@435: bind(E); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { duke@435: Label C, E; duke@435: call(C, relocInfo::none); duke@435: jmp(E); duke@435: duke@435: bind(C); duke@435: pushl(arg_3); duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM_helper(oop_result, entry_point, 3, check_exceptions); duke@435: ret(0); duke@435: duke@435: bind(E); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { duke@435: call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { duke@435: pushl(arg_1); duke@435: call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { duke@435: pushl(arg_3); duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { duke@435: call_VM_leaf_base(entry_point, number_of_arguments); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) { duke@435: pushl(arg_1); duke@435: call_VM_leaf(entry_point, 1); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) { duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM_leaf(entry_point, 2); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) { duke@435: pushl(arg_3); duke@435: pushl(arg_2); duke@435: pushl(arg_1); duke@435: call_VM_leaf(entry_point, 3); duke@435: } duke@435: duke@435: duke@435: // Calls to C land duke@435: // duke@435: // When entering C land, the rbp, & rsp of the last Java frame have to be recorded duke@435: // in the (thread-local) JavaThread object. When leaving C land, the last Java fp duke@435: // has to be reset to 0. This is required to allow proper stack traversal. duke@435: duke@435: void MacroAssembler::store_check(Register obj) { duke@435: // Does a store check for the oop in register obj. The content of duke@435: // register obj is destroyed afterwards. duke@435: store_check_part_1(obj); duke@435: store_check_part_2(obj); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::store_check(Register obj, Address dst) { duke@435: store_check(obj); duke@435: } duke@435: duke@435: duke@435: // split the store check operation so that other instructions can be scheduled inbetween duke@435: void MacroAssembler::store_check_part_1(Register obj) { duke@435: BarrierSet* bs = Universe::heap()->barrier_set(); duke@435: assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); duke@435: shrl(obj, CardTableModRefBS::card_shift); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::store_check_part_2(Register obj) { duke@435: BarrierSet* bs = Universe::heap()->barrier_set(); duke@435: assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); duke@435: CardTableModRefBS* ct = (CardTableModRefBS*)bs; duke@435: assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); duke@435: ExternalAddress cardtable((address)ct->byte_map_base); duke@435: Address index(noreg, obj, Address::times_1); duke@435: duke@435: movb(as_Address(ArrayAddress(cardtable, index)), 0); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::c2bool(Register x) { duke@435: // implements x == 0 ? 0 : 1 duke@435: // note: must only look at least-significant byte of x duke@435: // since C-style booleans are stored in one byte duke@435: // only! (was bug) duke@435: andl(x, 0xFF); duke@435: setb(Assembler::notZero, x); duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::corrected_idivl(Register reg) { duke@435: // Full implementation of Java idiv and irem; checks for duke@435: // special case as described in JVM spec., p.243 & p.271. duke@435: // The function returns the (pc) offset of the idivl duke@435: // instruction - may be needed for implicit exceptions. duke@435: // duke@435: // normal case special case duke@435: // duke@435: // input : rax,: dividend min_int duke@435: // reg: divisor (may not be rax,/rdx) -1 duke@435: // duke@435: // output: rax,: quotient (= rax, idiv reg) min_int duke@435: // rdx: remainder (= rax, irem reg) 0 duke@435: assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); duke@435: const int min_int = 0x80000000; duke@435: Label normal_case, special_case; duke@435: duke@435: // check for special case duke@435: cmpl(rax, min_int); duke@435: jcc(Assembler::notEqual, normal_case); duke@435: xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) duke@435: cmpl(reg, -1); duke@435: jcc(Assembler::equal, special_case); duke@435: duke@435: // handle normal case duke@435: bind(normal_case); duke@435: cdql(); duke@435: int idivl_offset = offset(); duke@435: idivl(reg); duke@435: duke@435: // normal and special case exit duke@435: bind(special_case); duke@435: duke@435: return idivl_offset; duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::lneg(Register hi, Register lo) { duke@435: negl(lo); duke@435: adcl(hi, 0); duke@435: negl(hi); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { duke@435: // Multiplication of two Java long values stored on the stack duke@435: // as illustrated below. Result is in rdx:rax. duke@435: // duke@435: // rsp ---> [ ?? ] \ \ duke@435: // .... | y_rsp_offset | duke@435: // [ y_lo ] / (in bytes) | x_rsp_offset duke@435: // [ y_hi ] | (in bytes) duke@435: // .... | duke@435: // [ x_lo ] / duke@435: // [ x_hi ] duke@435: // .... duke@435: // duke@435: // Basic idea: lo(result) = lo(x_lo * y_lo) duke@435: // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) duke@435: Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); duke@435: Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); duke@435: Label quick; duke@435: // load x_hi, y_hi and check if quick duke@435: // multiplication is possible duke@435: movl(rbx, x_hi); duke@435: movl(rcx, y_hi); duke@435: movl(rax, rbx); duke@435: orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 duke@435: jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply duke@435: // do full multiplication duke@435: // 1st step duke@435: mull(y_lo); // x_hi * y_lo duke@435: movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, duke@435: // 2nd step duke@435: movl(rax, x_lo); duke@435: mull(rcx); // x_lo * y_hi duke@435: addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, duke@435: // 3rd step duke@435: bind(quick); // note: rbx, = 0 if quick multiply! duke@435: movl(rax, x_lo); duke@435: mull(y_lo); // x_lo * y_lo duke@435: addl(rdx, rbx); // correct hi(x_lo * y_lo) duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::lshl(Register hi, Register lo) { duke@435: // Java shift left long support (semantics as described in JVM spec., p.305) duke@435: // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) duke@435: // shift value is in rcx ! duke@435: assert(hi != rcx, "must not use rcx"); duke@435: assert(lo != rcx, "must not use rcx"); duke@435: const Register s = rcx; // shift count duke@435: const int n = BitsPerWord; duke@435: Label L; duke@435: andl(s, 0x3f); // s := s & 0x3f (s < 0x40) duke@435: cmpl(s, n); // if (s < n) duke@435: jcc(Assembler::less, L); // else (s >= n) duke@435: movl(hi, lo); // x := x << n duke@435: xorl(lo, lo); duke@435: // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! duke@435: bind(L); // s (mod n) < n duke@435: shldl(hi, lo); // x := x << s duke@435: shll(lo); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { duke@435: // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) duke@435: // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) duke@435: assert(hi != rcx, "must not use rcx"); duke@435: assert(lo != rcx, "must not use rcx"); duke@435: const Register s = rcx; // shift count duke@435: const int n = BitsPerWord; duke@435: Label L; duke@435: andl(s, 0x3f); // s := s & 0x3f (s < 0x40) duke@435: cmpl(s, n); // if (s < n) duke@435: jcc(Assembler::less, L); // else (s >= n) duke@435: movl(lo, hi); // x := x >> n duke@435: if (sign_extension) sarl(hi, 31); duke@435: else xorl(hi, hi); duke@435: // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! duke@435: bind(L); // s (mod n) < n duke@435: shrdl(lo, hi); // x := x >> s duke@435: if (sign_extension) sarl(hi); duke@435: else shrl(hi); duke@435: } duke@435: duke@435: duke@435: // Note: y_lo will be destroyed duke@435: void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { duke@435: // Long compare for Java (semantics as described in JVM spec.) duke@435: Label high, low, done; duke@435: duke@435: cmpl(x_hi, y_hi); duke@435: jcc(Assembler::less, low); duke@435: jcc(Assembler::greater, high); duke@435: // x_hi is the return register duke@435: xorl(x_hi, x_hi); duke@435: cmpl(x_lo, y_lo); duke@435: jcc(Assembler::below, low); duke@435: jcc(Assembler::equal, done); duke@435: duke@435: bind(high); duke@435: xorl(x_hi, x_hi); duke@435: increment(x_hi); duke@435: jmp(done); duke@435: duke@435: bind(low); duke@435: xorl(x_hi, x_hi); duke@435: decrement(x_hi); duke@435: duke@435: bind(done); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::save_rax(Register tmp) { duke@435: if (tmp == noreg) pushl(rax); duke@435: else if (tmp != rax) movl(tmp, rax); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::restore_rax(Register tmp) { duke@435: if (tmp == noreg) popl(rax); duke@435: else if (tmp != rax) movl(rax, tmp); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::fremr(Register tmp) { duke@435: save_rax(tmp); duke@435: { Label L; duke@435: bind(L); duke@435: fprem(); duke@435: fwait(); fnstsw_ax(); duke@435: sahf(); duke@435: jcc(Assembler::parity, L); duke@435: } duke@435: restore_rax(tmp); duke@435: // Result is in ST0. duke@435: // Note: fxch & fpop to get rid of ST1 duke@435: // (otherwise FPU stack could overflow eventually) duke@435: fxch(1); duke@435: fpop(); duke@435: } duke@435: duke@435: duke@435: static const double pi_4 = 0.7853981633974483; duke@435: duke@435: void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { duke@435: // A hand-coded argument reduction for values in fabs(pi/4, pi/2) duke@435: // was attempted in this code; unfortunately it appears that the duke@435: // switch to 80-bit precision and back causes this to be duke@435: // unprofitable compared with simply performing a runtime call if duke@435: // the argument is out of the (-pi/4, pi/4) range. duke@435: duke@435: Register tmp = noreg; duke@435: if (!VM_Version::supports_cmov()) { duke@435: // fcmp needs a temporary so preserve rbx, duke@435: tmp = rbx; duke@435: pushl(tmp); duke@435: } duke@435: duke@435: Label slow_case, done; duke@435: duke@435: // x ?<= pi/4 duke@435: fld_d(ExternalAddress((address)&pi_4)); duke@435: fld_s(1); // Stack: X PI/4 X duke@435: fabs(); // Stack: |X| PI/4 X duke@435: fcmp(tmp); duke@435: jcc(Assembler::above, slow_case); duke@435: duke@435: // fastest case: -pi/4 <= x <= pi/4 duke@435: switch(trig) { duke@435: case 's': duke@435: fsin(); duke@435: break; duke@435: case 'c': duke@435: fcos(); duke@435: break; duke@435: case 't': duke@435: ftan(); duke@435: break; duke@435: default: duke@435: assert(false, "bad intrinsic"); duke@435: break; duke@435: } duke@435: jmp(done); duke@435: duke@435: // slow case: runtime call duke@435: bind(slow_case); duke@435: // Preserve registers across runtime call duke@435: pushad(); duke@435: int incoming_argument_and_return_value_offset = -1; duke@435: if (num_fpu_regs_in_use > 1) { duke@435: // Must preserve all other FPU regs (could alternatively convert duke@435: // SharedRuntime::dsin and dcos into assembly routines known not to trash duke@435: // FPU state, but can not trust C compiler) duke@435: NEEDS_CLEANUP; duke@435: // NOTE that in this case we also push the incoming argument to duke@435: // the stack and restore it later; we also use this stack slot to duke@435: // hold the return value from dsin or dcos. duke@435: for (int i = 0; i < num_fpu_regs_in_use; i++) { duke@435: subl(rsp, wordSize*2); duke@435: fstp_d(Address(rsp, 0)); duke@435: } duke@435: incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1); duke@435: fld_d(Address(rsp, incoming_argument_and_return_value_offset)); duke@435: } duke@435: subl(rsp, wordSize*2); duke@435: fstp_d(Address(rsp, 0)); duke@435: // NOTE: we must not use call_VM_leaf here because that requires a duke@435: // complete interpreter frame in debug mode -- same bug as 4387334 duke@435: NEEDS_CLEANUP; duke@435: // Need to add stack banging before this runtime call if it needs to duke@435: // be taken; however, there is no generic stack banging routine at duke@435: // the MacroAssembler level duke@435: switch(trig) { duke@435: case 's': duke@435: { duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin))); duke@435: } duke@435: break; duke@435: case 'c': duke@435: { duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos))); duke@435: } duke@435: break; duke@435: case 't': duke@435: { duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan))); duke@435: } duke@435: break; duke@435: default: duke@435: assert(false, "bad intrinsic"); duke@435: break; duke@435: } duke@435: addl(rsp, wordSize * 2); duke@435: if (num_fpu_regs_in_use > 1) { duke@435: // Must save return value to stack and then restore entire FPU stack duke@435: fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); duke@435: for (int i = 0; i < num_fpu_regs_in_use; i++) { duke@435: fld_d(Address(rsp, 0)); duke@435: addl(rsp, wordSize*2); duke@435: } duke@435: } duke@435: popad(); duke@435: duke@435: // Come here with result in F-TOS duke@435: bind(done); duke@435: duke@435: if (tmp != noreg) { duke@435: popl(tmp); duke@435: } duke@435: } duke@435: duke@435: void MacroAssembler::jC2(Register tmp, Label& L) { duke@435: // set parity bit if FPU flag C2 is set (via rax) duke@435: save_rax(tmp); duke@435: fwait(); fnstsw_ax(); duke@435: sahf(); duke@435: restore_rax(tmp); duke@435: // branch duke@435: jcc(Assembler::parity, L); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::jnC2(Register tmp, Label& L) { duke@435: // set parity bit if FPU flag C2 is set (via rax) duke@435: save_rax(tmp); duke@435: fwait(); fnstsw_ax(); duke@435: sahf(); duke@435: restore_rax(tmp); duke@435: // branch duke@435: jcc(Assembler::noParity, L); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::fcmp(Register tmp) { duke@435: fcmp(tmp, 1, true, true); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { duke@435: assert(!pop_right || pop_left, "usage error"); duke@435: if (VM_Version::supports_cmov()) { duke@435: assert(tmp == noreg, "unneeded temp"); duke@435: if (pop_left) { duke@435: fucomip(index); duke@435: } else { duke@435: fucomi(index); duke@435: } duke@435: if (pop_right) { duke@435: fpop(); duke@435: } duke@435: } else { duke@435: assert(tmp != noreg, "need temp"); duke@435: if (pop_left) { duke@435: if (pop_right) { duke@435: fcompp(); duke@435: } else { duke@435: fcomp(index); duke@435: } duke@435: } else { duke@435: fcom(index); duke@435: } duke@435: // convert FPU condition into eflags condition via rax, duke@435: save_rax(tmp); duke@435: fwait(); fnstsw_ax(); duke@435: sahf(); duke@435: restore_rax(tmp); duke@435: } duke@435: // condition codes set as follows: duke@435: // duke@435: // CF (corresponds to C0) if x < y duke@435: // PF (corresponds to C2) if unordered duke@435: // ZF (corresponds to C3) if x = y duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { duke@435: fcmp2int(dst, unordered_is_less, 1, true, true); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { duke@435: fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); duke@435: Label L; duke@435: if (unordered_is_less) { duke@435: movl(dst, -1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::below , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: increment(dst); duke@435: } else { // unordered is greater duke@435: movl(dst, 1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::above , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: decrement(dst); duke@435: } duke@435: bind(L); duke@435: } duke@435: duke@435: void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { duke@435: ucomiss(opr1, opr2); duke@435: duke@435: Label L; duke@435: if (unordered_is_less) { duke@435: movl(dst, -1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::below , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: increment(dst); duke@435: } else { // unordered is greater duke@435: movl(dst, 1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::above , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: decrement(dst); duke@435: } duke@435: bind(L); duke@435: } duke@435: duke@435: void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { duke@435: ucomisd(opr1, opr2); duke@435: duke@435: Label L; duke@435: if (unordered_is_less) { duke@435: movl(dst, -1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::below , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: increment(dst); duke@435: } else { // unordered is greater duke@435: movl(dst, 1); duke@435: jcc(Assembler::parity, L); duke@435: jcc(Assembler::above , L); duke@435: movl(dst, 0); duke@435: jcc(Assembler::equal , L); duke@435: decrement(dst); duke@435: } duke@435: bind(L); duke@435: } duke@435: duke@435: duke@435: duke@435: void MacroAssembler::fpop() { duke@435: ffree(); duke@435: fincstp(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::sign_extend_short(Register reg) { duke@435: if (VM_Version::is_P6()) { duke@435: movsxw(reg, reg); duke@435: } else { duke@435: shll(reg, 16); duke@435: sarl(reg, 16); duke@435: } duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::sign_extend_byte(Register reg) { duke@435: if (VM_Version::is_P6() && reg->has_byte_register()) { duke@435: movsxb(reg, reg); duke@435: } else { duke@435: shll(reg, 24); duke@435: sarl(reg, 24); duke@435: } duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::division_with_shift (Register reg, int shift_value) { duke@435: assert (shift_value > 0, "illegal shift value"); duke@435: Label _is_positive; duke@435: testl (reg, reg); duke@435: jcc (Assembler::positive, _is_positive); duke@435: int offset = (1 << shift_value) - 1 ; duke@435: duke@435: increment(reg, offset); duke@435: duke@435: bind (_is_positive); duke@435: sarl(reg, shift_value); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::round_to(Register reg, int modulus) { duke@435: addl(reg, modulus - 1); duke@435: andl(reg, -modulus); duke@435: } duke@435: duke@435: // C++ bool manipulation duke@435: duke@435: void MacroAssembler::movbool(Register dst, Address src) { duke@435: if(sizeof(bool) == 1) duke@435: movb(dst, src); duke@435: else if(sizeof(bool) == 2) duke@435: movw(dst, src); duke@435: else if(sizeof(bool) == 4) duke@435: movl(dst, src); duke@435: else duke@435: // unsupported duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: void MacroAssembler::movbool(Address dst, bool boolconst) { duke@435: if(sizeof(bool) == 1) duke@435: movb(dst, (int) boolconst); duke@435: else if(sizeof(bool) == 2) duke@435: movw(dst, (int) boolconst); duke@435: else if(sizeof(bool) == 4) duke@435: movl(dst, (int) boolconst); duke@435: else duke@435: // unsupported duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: void MacroAssembler::movbool(Address dst, Register src) { duke@435: if(sizeof(bool) == 1) duke@435: movb(dst, src); duke@435: else if(sizeof(bool) == 2) duke@435: movw(dst, src); duke@435: else if(sizeof(bool) == 4) duke@435: movl(dst, src); duke@435: else duke@435: // unsupported duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: void MacroAssembler::testbool(Register dst) { duke@435: if(sizeof(bool) == 1) duke@435: testb(dst, (int) 0xff); duke@435: else if(sizeof(bool) == 2) { duke@435: // testw implementation needed for two byte bools duke@435: ShouldNotReachHere(); duke@435: } else if(sizeof(bool) == 4) duke@435: testl(dst, dst); duke@435: else duke@435: // unsupported duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: void MacroAssembler::verify_oop(Register reg, const char* s) { duke@435: if (!VerifyOops) return; duke@435: // Pass register number to verify_oop_subroutine duke@435: char* b = new char[strlen(s) + 50]; duke@435: sprintf(b, "verify_oop: %s: %s", reg->name(), s); duke@435: pushl(rax); // save rax, duke@435: pushl(reg); // pass register argument duke@435: ExternalAddress buffer((address) b); duke@435: pushptr(buffer.addr()); duke@435: // call indirectly to solve generation ordering problem duke@435: movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); duke@435: call(rax); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::verify_oop_addr(Address addr, const char* s) { duke@435: if (!VerifyOops) return; duke@435: // QQQ fix this duke@435: // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); duke@435: // Pass register number to verify_oop_subroutine duke@435: char* b = new char[strlen(s) + 50]; duke@435: sprintf(b, "verify_oop_addr: %s", s); duke@435: pushl(rax); // save rax, duke@435: // addr may contain rsp so we will have to adjust it based on the push duke@435: // we just did duke@435: if (addr.uses(rsp)) { duke@435: leal(rax, addr); duke@435: pushl(Address(rax, BytesPerWord)); duke@435: } else { duke@435: pushl(addr); duke@435: } duke@435: ExternalAddress buffer((address) b); duke@435: // pass msg argument duke@435: pushptr(buffer.addr()); duke@435: // call indirectly to solve generation ordering problem duke@435: movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); duke@435: call(rax); duke@435: // Caller pops the arguments and restores rax, from the stack duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::stop(const char* msg) { duke@435: ExternalAddress message((address)msg); duke@435: // push address of message duke@435: pushptr(message.addr()); duke@435: { Label L; call(L, relocInfo::none); bind(L); } // push eip duke@435: pushad(); // push registers duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug))); duke@435: hlt(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::warn(const char* msg) { duke@435: push_CPU_state(); duke@435: duke@435: ExternalAddress message((address) msg); duke@435: // push address of message duke@435: pushptr(message.addr()); duke@435: duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); duke@435: addl(rsp, wordSize); // discard argument duke@435: pop_CPU_state(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { duke@435: // In order to get locks to work, we need to fake a in_VM state duke@435: JavaThread* thread = JavaThread::current(); duke@435: JavaThreadState saved_state = thread->thread_state(); duke@435: thread->set_thread_state(_thread_in_vm); duke@435: if (ShowMessageBoxOnError) { duke@435: JavaThread* thread = JavaThread::current(); duke@435: JavaThreadState saved_state = thread->thread_state(); duke@435: thread->set_thread_state(_thread_in_vm); duke@435: ttyLocker ttyl; duke@435: if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { duke@435: BytecodeCounter::print(); duke@435: } duke@435: // To see where a verify_oop failed, get $ebx+40/X for this frame. duke@435: // This is the value of eip which points to where verify_oop will return. duke@435: if (os::message_box(msg, "Execution stopped, print registers?")) { duke@435: tty->print_cr("eip = 0x%08x", eip); duke@435: tty->print_cr("rax, = 0x%08x", rax); duke@435: tty->print_cr("rbx, = 0x%08x", rbx); duke@435: tty->print_cr("rcx = 0x%08x", rcx); duke@435: tty->print_cr("rdx = 0x%08x", rdx); duke@435: tty->print_cr("rdi = 0x%08x", rdi); duke@435: tty->print_cr("rsi = 0x%08x", rsi); duke@435: tty->print_cr("rbp, = 0x%08x", rbp); duke@435: tty->print_cr("rsp = 0x%08x", rsp); duke@435: BREAKPOINT; duke@435: } duke@435: } else { duke@435: ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); duke@435: assert(false, "DEBUG MESSAGE"); duke@435: } duke@435: ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); duke@435: } duke@435: duke@435: duke@435: duke@435: void MacroAssembler::os_breakpoint() { duke@435: // instead of directly emitting a breakpoint, call os:breakpoint for better debugability duke@435: // (e.g., MSVC can't call ps() otherwise) duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::push_fTOS() { duke@435: subl(rsp, 2 * wordSize); duke@435: fstp_d(Address(rsp, 0)); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pop_fTOS() { duke@435: fld_d(Address(rsp, 0)); duke@435: addl(rsp, 2 * wordSize); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::empty_FPU_stack() { duke@435: if (VM_Version::supports_mmx()) { duke@435: emms(); duke@435: } else { duke@435: for (int i = 8; i-- > 0; ) ffree(i); duke@435: } duke@435: } duke@435: duke@435: duke@435: class ControlWord { duke@435: public: duke@435: int32_t _value; duke@435: duke@435: int rounding_control() const { return (_value >> 10) & 3 ; } duke@435: int precision_control() const { return (_value >> 8) & 3 ; } duke@435: bool precision() const { return ((_value >> 5) & 1) != 0; } duke@435: bool underflow() const { return ((_value >> 4) & 1) != 0; } duke@435: bool overflow() const { return ((_value >> 3) & 1) != 0; } duke@435: bool zero_divide() const { return ((_value >> 2) & 1) != 0; } duke@435: bool denormalized() const { return ((_value >> 1) & 1) != 0; } duke@435: bool invalid() const { return ((_value >> 0) & 1) != 0; } duke@435: duke@435: void print() const { duke@435: // rounding control duke@435: const char* rc; duke@435: switch (rounding_control()) { duke@435: case 0: rc = "round near"; break; duke@435: case 1: rc = "round down"; break; duke@435: case 2: rc = "round up "; break; duke@435: case 3: rc = "chop "; break; duke@435: }; duke@435: // precision control duke@435: const char* pc; duke@435: switch (precision_control()) { duke@435: case 0: pc = "24 bits "; break; duke@435: case 1: pc = "reserved"; break; duke@435: case 2: pc = "53 bits "; break; duke@435: case 3: pc = "64 bits "; break; duke@435: }; duke@435: // flags duke@435: char f[9]; duke@435: f[0] = ' '; duke@435: f[1] = ' '; duke@435: f[2] = (precision ()) ? 'P' : 'p'; duke@435: f[3] = (underflow ()) ? 'U' : 'u'; duke@435: f[4] = (overflow ()) ? 'O' : 'o'; duke@435: f[5] = (zero_divide ()) ? 'Z' : 'z'; duke@435: f[6] = (denormalized()) ? 'D' : 'd'; duke@435: f[7] = (invalid ()) ? 'I' : 'i'; duke@435: f[8] = '\x0'; duke@435: // output duke@435: printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class StatusWord { duke@435: public: duke@435: int32_t _value; duke@435: duke@435: bool busy() const { return ((_value >> 15) & 1) != 0; } duke@435: bool C3() const { return ((_value >> 14) & 1) != 0; } duke@435: bool C2() const { return ((_value >> 10) & 1) != 0; } duke@435: bool C1() const { return ((_value >> 9) & 1) != 0; } duke@435: bool C0() const { return ((_value >> 8) & 1) != 0; } duke@435: int top() const { return (_value >> 11) & 7 ; } duke@435: bool error_status() const { return ((_value >> 7) & 1) != 0; } duke@435: bool stack_fault() const { return ((_value >> 6) & 1) != 0; } duke@435: bool precision() const { return ((_value >> 5) & 1) != 0; } duke@435: bool underflow() const { return ((_value >> 4) & 1) != 0; } duke@435: bool overflow() const { return ((_value >> 3) & 1) != 0; } duke@435: bool zero_divide() const { return ((_value >> 2) & 1) != 0; } duke@435: bool denormalized() const { return ((_value >> 1) & 1) != 0; } duke@435: bool invalid() const { return ((_value >> 0) & 1) != 0; } duke@435: duke@435: void print() const { duke@435: // condition codes duke@435: char c[5]; duke@435: c[0] = (C3()) ? '3' : '-'; duke@435: c[1] = (C2()) ? '2' : '-'; duke@435: c[2] = (C1()) ? '1' : '-'; duke@435: c[3] = (C0()) ? '0' : '-'; duke@435: c[4] = '\x0'; duke@435: // flags duke@435: char f[9]; duke@435: f[0] = (error_status()) ? 'E' : '-'; duke@435: f[1] = (stack_fault ()) ? 'S' : '-'; duke@435: f[2] = (precision ()) ? 'P' : '-'; duke@435: f[3] = (underflow ()) ? 'U' : '-'; duke@435: f[4] = (overflow ()) ? 'O' : '-'; duke@435: f[5] = (zero_divide ()) ? 'Z' : '-'; duke@435: f[6] = (denormalized()) ? 'D' : '-'; duke@435: f[7] = (invalid ()) ? 'I' : '-'; duke@435: f[8] = '\x0'; duke@435: // output duke@435: printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class TagWord { duke@435: public: duke@435: int32_t _value; duke@435: duke@435: int tag_at(int i) const { return (_value >> (i*2)) & 3; } duke@435: duke@435: void print() const { duke@435: printf("%04x", _value & 0xFFFF); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class FPU_Register { duke@435: public: duke@435: int32_t _m0; duke@435: int32_t _m1; duke@435: int16_t _ex; duke@435: duke@435: bool is_indefinite() const { duke@435: return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; duke@435: } duke@435: duke@435: void print() const { duke@435: char sign = (_ex < 0) ? '-' : '+'; duke@435: const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; duke@435: printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); duke@435: }; duke@435: duke@435: }; duke@435: duke@435: duke@435: class FPU_State { duke@435: public: duke@435: enum { duke@435: register_size = 10, duke@435: number_of_registers = 8, duke@435: register_mask = 7 duke@435: }; duke@435: duke@435: ControlWord _control_word; duke@435: StatusWord _status_word; duke@435: TagWord _tag_word; duke@435: int32_t _error_offset; duke@435: int32_t _error_selector; duke@435: int32_t _data_offset; duke@435: int32_t _data_selector; duke@435: int8_t _register[register_size * number_of_registers]; duke@435: duke@435: int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } duke@435: FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } duke@435: duke@435: const char* tag_as_string(int tag) const { duke@435: switch (tag) { duke@435: case 0: return "valid"; duke@435: case 1: return "zero"; duke@435: case 2: return "special"; duke@435: case 3: return "empty"; duke@435: } duke@435: ShouldNotReachHere() duke@435: return NULL; duke@435: } duke@435: duke@435: void print() const { duke@435: // print computation registers duke@435: { int t = _status_word.top(); duke@435: for (int i = 0; i < number_of_registers; i++) { duke@435: int j = (i - t) & register_mask; duke@435: printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); duke@435: st(j)->print(); duke@435: printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); duke@435: } duke@435: } duke@435: printf("\n"); duke@435: // print control registers duke@435: printf("ctrl = "); _control_word.print(); printf("\n"); duke@435: printf("stat = "); _status_word .print(); printf("\n"); duke@435: printf("tags = "); _tag_word .print(); printf("\n"); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class Flag_Register { duke@435: public: duke@435: int32_t _value; duke@435: duke@435: bool overflow() const { return ((_value >> 11) & 1) != 0; } duke@435: bool direction() const { return ((_value >> 10) & 1) != 0; } duke@435: bool sign() const { return ((_value >> 7) & 1) != 0; } duke@435: bool zero() const { return ((_value >> 6) & 1) != 0; } duke@435: bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } duke@435: bool parity() const { return ((_value >> 2) & 1) != 0; } duke@435: bool carry() const { return ((_value >> 0) & 1) != 0; } duke@435: duke@435: void print() const { duke@435: // flags duke@435: char f[8]; duke@435: f[0] = (overflow ()) ? 'O' : '-'; duke@435: f[1] = (direction ()) ? 'D' : '-'; duke@435: f[2] = (sign ()) ? 'S' : '-'; duke@435: f[3] = (zero ()) ? 'Z' : '-'; duke@435: f[4] = (auxiliary_carry()) ? 'A' : '-'; duke@435: f[5] = (parity ()) ? 'P' : '-'; duke@435: f[6] = (carry ()) ? 'C' : '-'; duke@435: f[7] = '\x0'; duke@435: // output duke@435: printf("%08x flags = %s", _value, f); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class IU_Register { duke@435: public: duke@435: int32_t _value; duke@435: duke@435: void print() const { duke@435: printf("%08x %11d", _value, _value); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: class IU_State { duke@435: public: duke@435: Flag_Register _eflags; duke@435: IU_Register _rdi; duke@435: IU_Register _rsi; duke@435: IU_Register _rbp; duke@435: IU_Register _rsp; duke@435: IU_Register _rbx; duke@435: IU_Register _rdx; duke@435: IU_Register _rcx; duke@435: IU_Register _rax; duke@435: duke@435: void print() const { duke@435: // computation registers duke@435: printf("rax, = "); _rax.print(); printf("\n"); duke@435: printf("rbx, = "); _rbx.print(); printf("\n"); duke@435: printf("rcx = "); _rcx.print(); printf("\n"); duke@435: printf("rdx = "); _rdx.print(); printf("\n"); duke@435: printf("rdi = "); _rdi.print(); printf("\n"); duke@435: printf("rsi = "); _rsi.print(); printf("\n"); duke@435: printf("rbp, = "); _rbp.print(); printf("\n"); duke@435: printf("rsp = "); _rsp.print(); printf("\n"); duke@435: printf("\n"); duke@435: // control registers duke@435: printf("flgs = "); _eflags.print(); printf("\n"); duke@435: } duke@435: }; duke@435: duke@435: duke@435: class CPU_State { duke@435: public: duke@435: FPU_State _fpu_state; duke@435: IU_State _iu_state; duke@435: duke@435: void print() const { duke@435: printf("--------------------------------------------------\n"); duke@435: _iu_state .print(); duke@435: printf("\n"); duke@435: _fpu_state.print(); duke@435: printf("--------------------------------------------------\n"); duke@435: } duke@435: duke@435: }; duke@435: duke@435: duke@435: static void _print_CPU_state(CPU_State* state) { duke@435: state->print(); duke@435: }; duke@435: duke@435: duke@435: void MacroAssembler::print_CPU_state() { duke@435: push_CPU_state(); duke@435: pushl(rsp); // pass CPU state duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); duke@435: addl(rsp, wordSize); // discard argument duke@435: pop_CPU_state(); duke@435: } duke@435: duke@435: duke@435: static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { duke@435: static int counter = 0; duke@435: FPU_State* fs = &state->_fpu_state; duke@435: counter++; duke@435: // For leaf calls, only verify that the top few elements remain empty. duke@435: // We only need 1 empty at the top for C2 code. duke@435: if( stack_depth < 0 ) { duke@435: if( fs->tag_for_st(7) != 3 ) { duke@435: printf("FPR7 not empty\n"); duke@435: state->print(); duke@435: assert(false, "error"); duke@435: return false; duke@435: } duke@435: return true; // All other stack states do not matter duke@435: } duke@435: duke@435: assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, duke@435: "bad FPU control word"); duke@435: duke@435: // compute stack depth duke@435: int i = 0; duke@435: while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; duke@435: int d = i; duke@435: while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; duke@435: // verify findings duke@435: if (i != FPU_State::number_of_registers) { duke@435: // stack not contiguous duke@435: printf("%s: stack not contiguous at ST%d\n", s, i); duke@435: state->print(); duke@435: assert(false, "error"); duke@435: return false; duke@435: } duke@435: // check if computed stack depth corresponds to expected stack depth duke@435: if (stack_depth < 0) { duke@435: // expected stack depth is -stack_depth or less duke@435: if (d > -stack_depth) { duke@435: // too many elements on the stack duke@435: printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); duke@435: state->print(); duke@435: assert(false, "error"); duke@435: return false; duke@435: } duke@435: } else { duke@435: // expected stack depth is stack_depth duke@435: if (d != stack_depth) { duke@435: // wrong stack depth duke@435: printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); duke@435: state->print(); duke@435: assert(false, "error"); duke@435: return false; duke@435: } duke@435: } duke@435: // everything is cool duke@435: return true; duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::verify_FPU(int stack_depth, const char* s) { duke@435: if (!VerifyFPU) return; duke@435: push_CPU_state(); duke@435: pushl(rsp); // pass CPU state duke@435: ExternalAddress msg((address) s); duke@435: // pass message string s duke@435: pushptr(msg.addr()); duke@435: pushl(stack_depth); // pass stack depth duke@435: call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); duke@435: addl(rsp, 3 * wordSize); // discard arguments duke@435: // check for error duke@435: { Label L; duke@435: testl(rax, rax); duke@435: jcc(Assembler::notZero, L); duke@435: int3(); // break if error condition duke@435: bind(L); duke@435: } duke@435: pop_CPU_state(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::push_IU_state() { duke@435: pushad(); duke@435: pushfd(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pop_IU_state() { duke@435: popfd(); duke@435: popad(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::push_FPU_state() { duke@435: subl(rsp, FPUStateSizeInWords * wordSize); duke@435: fnsave(Address(rsp, 0)); duke@435: fwait(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pop_FPU_state() { duke@435: frstor(Address(rsp, 0)); duke@435: addl(rsp, FPUStateSizeInWords * wordSize); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::push_CPU_state() { duke@435: push_IU_state(); duke@435: push_FPU_state(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pop_CPU_state() { duke@435: pop_FPU_state(); duke@435: pop_IU_state(); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::push_callee_saved_registers() { duke@435: pushl(rsi); duke@435: pushl(rdi); duke@435: pushl(rdx); duke@435: pushl(rcx); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::pop_callee_saved_registers() { duke@435: popl(rcx); duke@435: popl(rdx); duke@435: popl(rdi); duke@435: popl(rsi); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::set_word_if_not_zero(Register dst) { duke@435: xorl(dst, dst); duke@435: set_byte_if_not_zero(dst); duke@435: } duke@435: duke@435: // Write serialization page so VM thread can do a pseudo remote membar. duke@435: // We use the current thread pointer to calculate a thread specific duke@435: // offset to write to within the page. This minimizes bus traffic duke@435: // due to cache line collision. duke@435: void MacroAssembler::serialize_memory(Register thread, Register tmp) { duke@435: movl(tmp, thread); duke@435: shrl(tmp, os::get_serialize_page_shift_count()); duke@435: andl(tmp, (os::vm_page_size() - sizeof(int))); duke@435: duke@435: Address index(noreg, tmp, Address::times_1); duke@435: ExternalAddress page(os::get_memory_serialize_page()); duke@435: duke@435: movptr(ArrayAddress(page, index), tmp); duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::verify_tlab() { duke@435: #ifdef ASSERT duke@435: if (UseTLAB && VerifyOops) { duke@435: Label next, ok; duke@435: Register t1 = rsi; duke@435: Register thread_reg = rbx; duke@435: duke@435: pushl(t1); duke@435: pushl(thread_reg); duke@435: get_thread(thread_reg); duke@435: duke@435: movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); duke@435: cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); duke@435: jcc(Assembler::aboveEqual, next); duke@435: stop("assert(top >= start)"); duke@435: should_not_reach_here(); duke@435: duke@435: bind(next); duke@435: movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); duke@435: cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); duke@435: jcc(Assembler::aboveEqual, ok); duke@435: stop("assert(top <= end)"); duke@435: should_not_reach_here(); duke@435: duke@435: bind(ok); duke@435: popl(thread_reg); duke@435: popl(t1); duke@435: } duke@435: #endif duke@435: } duke@435: duke@435: duke@435: // Defines obj, preserves var_size_in_bytes duke@435: void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, duke@435: Register t1, Label& slow_case) { duke@435: assert(obj == rax, "obj must be in rax, for cmpxchg"); duke@435: assert_different_registers(obj, var_size_in_bytes, t1); duke@435: Register end = t1; duke@435: Label retry; duke@435: bind(retry); duke@435: ExternalAddress heap_top((address) Universe::heap()->top_addr()); duke@435: movptr(obj, heap_top); duke@435: if (var_size_in_bytes == noreg) { duke@435: leal(end, Address(obj, con_size_in_bytes)); duke@435: } else { duke@435: leal(end, Address(obj, var_size_in_bytes, Address::times_1)); duke@435: } duke@435: // if end < obj then we wrapped around => object too long => slow case duke@435: cmpl(end, obj); duke@435: jcc(Assembler::below, slow_case); duke@435: cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); duke@435: jcc(Assembler::above, slow_case); duke@435: // Compare obj with the top addr, and if still equal, store the new top addr in duke@435: // end at the address of the top addr pointer. Sets ZF if was equal, and clears duke@435: // it otherwise. Use lock prefix for atomicity on MPs. duke@435: if (os::is_MP()) { duke@435: lock(); duke@435: } duke@435: cmpxchgptr(end, heap_top); duke@435: jcc(Assembler::notEqual, retry); duke@435: } duke@435: duke@435: duke@435: // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. duke@435: void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, duke@435: Register t1, Register t2, Label& slow_case) { duke@435: assert_different_registers(obj, t1, t2); duke@435: assert_different_registers(obj, var_size_in_bytes, t1); duke@435: Register end = t2; duke@435: Register thread = t1; duke@435: duke@435: verify_tlab(); duke@435: duke@435: get_thread(thread); duke@435: duke@435: movl(obj, Address(thread, JavaThread::tlab_top_offset())); duke@435: if (var_size_in_bytes == noreg) { duke@435: leal(end, Address(obj, con_size_in_bytes)); duke@435: } else { duke@435: leal(end, Address(obj, var_size_in_bytes, Address::times_1)); duke@435: } duke@435: cmpl(end, Address(thread, JavaThread::tlab_end_offset())); duke@435: jcc(Assembler::above, slow_case); duke@435: duke@435: // update the tlab top pointer duke@435: movl(Address(thread, JavaThread::tlab_top_offset()), end); duke@435: duke@435: // recover var_size_in_bytes if necessary duke@435: if (var_size_in_bytes == end) { duke@435: subl(var_size_in_bytes, obj); duke@435: } duke@435: verify_tlab(); duke@435: } duke@435: duke@435: // Preserves rbx, and rdx. duke@435: void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { duke@435: Register top = rax; duke@435: Register t1 = rcx; duke@435: Register t2 = rsi; duke@435: Register thread_reg = rdi; duke@435: assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); duke@435: Label do_refill, discard_tlab; duke@435: duke@435: if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { duke@435: // No allocation in the shared eden. duke@435: jmp(slow_case); duke@435: } duke@435: duke@435: get_thread(thread_reg); duke@435: duke@435: movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); duke@435: movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); duke@435: duke@435: // calculate amount of free space duke@435: subl(t1, top); duke@435: shrl(t1, LogHeapWordSize); duke@435: duke@435: // Retain tlab and allocate object in shared space if duke@435: // the amount free in the tlab is too large to discard. duke@435: cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); duke@435: jcc(Assembler::lessEqual, discard_tlab); duke@435: duke@435: // Retain duke@435: movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment()); duke@435: addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); duke@435: if (TLABStats) { duke@435: // increment number of slow_allocations duke@435: addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); duke@435: } duke@435: jmp(try_eden); duke@435: duke@435: bind(discard_tlab); duke@435: if (TLABStats) { duke@435: // increment number of refills duke@435: addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); duke@435: // accumulate wastage -- t1 is amount free in tlab duke@435: addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); duke@435: } duke@435: duke@435: // if tlab is currently allocated (top or end != null) then duke@435: // fill [top, end + alignment_reserve) with array object duke@435: testl (top, top); duke@435: jcc(Assembler::zero, do_refill); duke@435: duke@435: // set up the mark word duke@435: movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2)); duke@435: // set the length to the remaining space duke@435: subl(t1, typeArrayOopDesc::header_size(T_INT)); duke@435: addl(t1, ThreadLocalAllocBuffer::alignment_reserve()); duke@435: shll(t1, log2_intptr(HeapWordSize/sizeof(jint))); duke@435: movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); duke@435: // set klass to intArrayKlass duke@435: // dubious reloc why not an oop reloc? duke@435: movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); duke@435: movl(Address(top, oopDesc::klass_offset_in_bytes()), t1); duke@435: duke@435: // refill the tlab with an eden allocation duke@435: bind(do_refill); duke@435: movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); duke@435: shll(t1, LogHeapWordSize); duke@435: // add object_size ?? duke@435: eden_allocate(top, t1, 0, t2, slow_case); duke@435: duke@435: // Check that t1 was preserved in eden_allocate. duke@435: #ifdef ASSERT duke@435: if (UseTLAB) { duke@435: Label ok; duke@435: Register tsize = rsi; duke@435: assert_different_registers(tsize, thread_reg, t1); duke@435: pushl(tsize); duke@435: movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); duke@435: shll(tsize, LogHeapWordSize); duke@435: cmpl(t1, tsize); duke@435: jcc(Assembler::equal, ok); duke@435: stop("assert(t1 != tlab size)"); duke@435: should_not_reach_here(); duke@435: duke@435: bind(ok); duke@435: popl(tsize); duke@435: } duke@435: #endif duke@435: movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); duke@435: movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); duke@435: addl(top, t1); duke@435: subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); duke@435: movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); duke@435: verify_tlab(); duke@435: jmp(retry); duke@435: } duke@435: duke@435: duke@435: int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, duke@435: bool swap_reg_contains_mark, duke@435: Label& done, Label* slow_case, duke@435: BiasedLockingCounters* counters) { duke@435: assert(UseBiasedLocking, "why call this otherwise?"); duke@435: assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); duke@435: assert_different_registers(lock_reg, obj_reg, swap_reg); duke@435: duke@435: if (PrintBiasedLockingStatistics && counters == NULL) duke@435: counters = BiasedLocking::counters(); duke@435: duke@435: bool need_tmp_reg = false; duke@435: if (tmp_reg == noreg) { duke@435: need_tmp_reg = true; duke@435: tmp_reg = lock_reg; duke@435: } else { duke@435: assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); duke@435: } duke@435: assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); duke@435: Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); duke@435: Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); duke@435: Address saved_mark_addr(lock_reg, 0); duke@435: duke@435: // Biased locking duke@435: // See whether the lock is currently biased toward our thread and duke@435: // whether the epoch is still valid duke@435: // Note that the runtime guarantees sufficient alignment of JavaThread duke@435: // pointers to allow age to be placed into low bits duke@435: // First check to see whether biasing is even enabled for this object duke@435: Label cas_label; duke@435: int null_check_offset = -1; duke@435: if (!swap_reg_contains_mark) { duke@435: null_check_offset = offset(); duke@435: movl(swap_reg, mark_addr); duke@435: } duke@435: if (need_tmp_reg) { duke@435: pushl(tmp_reg); duke@435: } duke@435: movl(tmp_reg, swap_reg); duke@435: andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); duke@435: cmpl(tmp_reg, markOopDesc::biased_lock_pattern); duke@435: if (need_tmp_reg) { duke@435: popl(tmp_reg); duke@435: } duke@435: jcc(Assembler::notEqual, cas_label); duke@435: // The bias pattern is present in the object's header. Need to check duke@435: // whether the bias owner and the epoch are both still current. duke@435: // Note that because there is no current thread register on x86 we duke@435: // need to store off the mark word we read out of the object to duke@435: // avoid reloading it and needing to recheck invariants below. This duke@435: // store is unfortunate but it makes the overall code shorter and duke@435: // simpler. duke@435: movl(saved_mark_addr, swap_reg); duke@435: if (need_tmp_reg) { duke@435: pushl(tmp_reg); duke@435: } duke@435: get_thread(tmp_reg); duke@435: xorl(swap_reg, tmp_reg); duke@435: if (swap_reg_contains_mark) { duke@435: null_check_offset = offset(); duke@435: } duke@435: movl(tmp_reg, klass_addr); duke@435: xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); duke@435: andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); duke@435: if (need_tmp_reg) { duke@435: popl(tmp_reg); duke@435: } duke@435: if (counters != NULL) { duke@435: cond_inc32(Assembler::zero, duke@435: ExternalAddress((address)counters->biased_lock_entry_count_addr())); duke@435: } duke@435: jcc(Assembler::equal, done); duke@435: duke@435: Label try_revoke_bias; duke@435: Label try_rebias; duke@435: duke@435: // At this point we know that the header has the bias pattern and duke@435: // that we are not the bias owner in the current epoch. We need to duke@435: // figure out more details about the state of the header in order to duke@435: // know what operations can be legally performed on the object's duke@435: // header. duke@435: duke@435: // If the low three bits in the xor result aren't clear, that means duke@435: // the prototype header is no longer biased and we have to revoke duke@435: // the bias on this object. duke@435: testl(swap_reg, markOopDesc::biased_lock_mask_in_place); duke@435: jcc(Assembler::notZero, try_revoke_bias); duke@435: duke@435: // Biasing is still enabled for this data type. See whether the duke@435: // epoch of the current bias is still valid, meaning that the epoch duke@435: // bits of the mark word are equal to the epoch bits of the duke@435: // prototype header. (Note that the prototype header's epoch bits duke@435: // only change at a safepoint.) If not, attempt to rebias the object duke@435: // toward the current thread. Note that we must be absolutely sure duke@435: // that the current epoch is invalid in order to do this because duke@435: // otherwise the manipulations it performs on the mark word are duke@435: // illegal. duke@435: testl(swap_reg, markOopDesc::epoch_mask_in_place); duke@435: jcc(Assembler::notZero, try_rebias); duke@435: duke@435: // The epoch of the current bias is still valid but we know nothing duke@435: // about the owner; it might be set or it might be clear. Try to duke@435: // acquire the bias of the object using an atomic operation. If this duke@435: // fails we will go in to the runtime to revoke the object's bias. duke@435: // Note that we first construct the presumed unbiased header so we duke@435: // don't accidentally blow away another thread's valid bias. duke@435: movl(swap_reg, saved_mark_addr); duke@435: andl(swap_reg, duke@435: markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); duke@435: if (need_tmp_reg) { duke@435: pushl(tmp_reg); duke@435: } duke@435: get_thread(tmp_reg); duke@435: orl(tmp_reg, swap_reg); duke@435: if (os::is_MP()) { duke@435: lock(); duke@435: } duke@435: cmpxchg(tmp_reg, Address(obj_reg, 0)); duke@435: if (need_tmp_reg) { duke@435: popl(tmp_reg); duke@435: } duke@435: // If the biasing toward our thread failed, this means that duke@435: // another thread succeeded in biasing it toward itself and we duke@435: // need to revoke that bias. The revocation will occur in the duke@435: // interpreter runtime in the slow case. duke@435: if (counters != NULL) { duke@435: cond_inc32(Assembler::zero, duke@435: ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); duke@435: } duke@435: if (slow_case != NULL) { duke@435: jcc(Assembler::notZero, *slow_case); duke@435: } duke@435: jmp(done); duke@435: duke@435: bind(try_rebias); duke@435: // At this point we know the epoch has expired, meaning that the duke@435: // current "bias owner", if any, is actually invalid. Under these duke@435: // circumstances _only_, we are allowed to use the current header's duke@435: // value as the comparison value when doing the cas to acquire the duke@435: // bias in the current epoch. In other words, we allow transfer of duke@435: // the bias from one thread to another directly in this situation. duke@435: // duke@435: // FIXME: due to a lack of registers we currently blow away the age duke@435: // bits in this situation. Should attempt to preserve them. duke@435: if (need_tmp_reg) { duke@435: pushl(tmp_reg); duke@435: } duke@435: get_thread(tmp_reg); duke@435: movl(swap_reg, klass_addr); duke@435: orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); duke@435: movl(swap_reg, saved_mark_addr); duke@435: if (os::is_MP()) { duke@435: lock(); duke@435: } duke@435: cmpxchg(tmp_reg, Address(obj_reg, 0)); duke@435: if (need_tmp_reg) { duke@435: popl(tmp_reg); duke@435: } duke@435: // If the biasing toward our thread failed, then another thread duke@435: // succeeded in biasing it toward itself and we need to revoke that duke@435: // bias. The revocation will occur in the runtime in the slow case. duke@435: if (counters != NULL) { duke@435: cond_inc32(Assembler::zero, duke@435: ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); duke@435: } duke@435: if (slow_case != NULL) { duke@435: jcc(Assembler::notZero, *slow_case); duke@435: } duke@435: jmp(done); duke@435: duke@435: bind(try_revoke_bias); duke@435: // The prototype mark in the klass doesn't have the bias bit set any duke@435: // more, indicating that objects of this data type are not supposed duke@435: // to be biased any more. We are going to try to reset the mark of duke@435: // this object to the prototype value and fall through to the duke@435: // CAS-based locking scheme. Note that if our CAS fails, it means duke@435: // that another thread raced us for the privilege of revoking the duke@435: // bias of this particular object, so it's okay to continue in the duke@435: // normal locking code. duke@435: // duke@435: // FIXME: due to a lack of registers we currently blow away the age duke@435: // bits in this situation. Should attempt to preserve them. duke@435: movl(swap_reg, saved_mark_addr); duke@435: if (need_tmp_reg) { duke@435: pushl(tmp_reg); duke@435: } duke@435: movl(tmp_reg, klass_addr); duke@435: movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); duke@435: if (os::is_MP()) { duke@435: lock(); duke@435: } duke@435: cmpxchg(tmp_reg, Address(obj_reg, 0)); duke@435: if (need_tmp_reg) { duke@435: popl(tmp_reg); duke@435: } duke@435: // Fall through to the normal CAS-based lock, because no matter what duke@435: // the result of the above CAS, some thread must have succeeded in duke@435: // removing the bias bit from the object's header. duke@435: if (counters != NULL) { duke@435: cond_inc32(Assembler::zero, duke@435: ExternalAddress((address)counters->revoked_lock_entry_count_addr())); duke@435: } duke@435: duke@435: bind(cas_label); duke@435: duke@435: return null_check_offset; duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { duke@435: assert(UseBiasedLocking, "why call this otherwise?"); duke@435: duke@435: // Check for biased locking unlock case, which is a no-op duke@435: // Note: we do not have to check the thread ID for two reasons. duke@435: // First, the interpreter checks for IllegalMonitorStateException at duke@435: // a higher level. Second, if the bias was revoked while we held the duke@435: // lock, the object could not be rebiased toward another thread, so duke@435: // the bias bit would be clear. duke@435: movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); duke@435: andl(temp_reg, markOopDesc::biased_lock_mask_in_place); duke@435: cmpl(temp_reg, markOopDesc::biased_lock_pattern); duke@435: jcc(Assembler::equal, done); duke@435: } duke@435: duke@435: duke@435: Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { duke@435: switch (cond) { duke@435: // Note some conditions are synonyms for others duke@435: case Assembler::zero: return Assembler::notZero; duke@435: case Assembler::notZero: return Assembler::zero; duke@435: case Assembler::less: return Assembler::greaterEqual; duke@435: case Assembler::lessEqual: return Assembler::greater; duke@435: case Assembler::greater: return Assembler::lessEqual; duke@435: case Assembler::greaterEqual: return Assembler::less; duke@435: case Assembler::below: return Assembler::aboveEqual; duke@435: case Assembler::belowEqual: return Assembler::above; duke@435: case Assembler::above: return Assembler::belowEqual; duke@435: case Assembler::aboveEqual: return Assembler::below; duke@435: case Assembler::overflow: return Assembler::noOverflow; duke@435: case Assembler::noOverflow: return Assembler::overflow; duke@435: case Assembler::negative: return Assembler::positive; duke@435: case Assembler::positive: return Assembler::negative; duke@435: case Assembler::parity: return Assembler::noParity; duke@435: case Assembler::noParity: return Assembler::parity; duke@435: } duke@435: ShouldNotReachHere(); return Assembler::overflow; duke@435: } duke@435: duke@435: duke@435: void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { duke@435: Condition negated_cond = negate_condition(cond); duke@435: Label L; duke@435: jcc(negated_cond, L); duke@435: atomic_incl(counter_addr); duke@435: bind(L); duke@435: } duke@435: duke@435: void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { duke@435: pushfd(); duke@435: if (os::is_MP()) duke@435: lock(); duke@435: increment(counter_addr); duke@435: popfd(); duke@435: } duke@435: duke@435: SkipIfEqual::SkipIfEqual( duke@435: MacroAssembler* masm, const bool* flag_addr, bool value) { duke@435: _masm = masm; duke@435: _masm->cmp8(ExternalAddress((address)flag_addr), value); duke@435: _masm->jcc(Assembler::equal, _label); duke@435: } duke@435: duke@435: SkipIfEqual::~SkipIfEqual() { duke@435: _masm->bind(_label); duke@435: } duke@435: duke@435: duke@435: // Writes to stack successive pages until offset reached to check for duke@435: // stack overflow + shadow pages. This clobbers tmp. duke@435: void MacroAssembler::bang_stack_size(Register size, Register tmp) { duke@435: movl(tmp, rsp); duke@435: // Bang stack for total size given plus shadow page size. duke@435: // Bang one page at a time because large size can bang beyond yellow and duke@435: // red zones. duke@435: Label loop; duke@435: bind(loop); duke@435: movl(Address(tmp, (-os::vm_page_size())), size ); duke@435: subl(tmp, os::vm_page_size()); duke@435: subl(size, os::vm_page_size()); duke@435: jcc(Assembler::greater, loop); duke@435: duke@435: // Bang down shadow pages too. duke@435: // The -1 because we already subtracted 1 page. duke@435: for (int i = 0; i< StackShadowPages-1; i++) { duke@435: movl(Address(tmp, (-i*os::vm_page_size())), size ); duke@435: } duke@435: }