duke@435: /* kvn@3882: * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * trims@1907: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA trims@1907: * or visit www.oracle.com if you need additional information or have any trims@1907: * questions. duke@435: * duke@435: */ duke@435: stefank@2314: #include "precompiled.hpp" stefank@2314: #include "libadt/vectset.hpp" stefank@2314: #include "memory/allocation.inline.hpp" stefank@2314: #include "opto/addnode.hpp" stefank@2314: #include "opto/c2compiler.hpp" stefank@2314: #include "opto/callnode.hpp" stefank@2314: #include "opto/cfgnode.hpp" stefank@2314: #include "opto/chaitin.hpp" stefank@2314: #include "opto/loopnode.hpp" stefank@2314: #include "opto/machnode.hpp" duke@435: duke@435: //------------------------------Split-------------------------------------- twisti@1040: // Walk the graph in RPO and for each lrg which spills, propagate reaching twisti@1040: // definitions. During propagation, split the live range around regions of duke@435: // High Register Pressure (HRP). If a Def is in a region of Low Register duke@435: // Pressure (LRP), it will not get spilled until we encounter a region of duke@435: // HRP between it and one of its uses. We will spill at the transition duke@435: // point between LRP and HRP. Uses in the HRP region will use the spilled duke@435: // Def. The first Use outside the HRP region will generate a SpillCopy to duke@435: // hoist the live range back up into a register, and all subsequent uses duke@435: // will use that new Def until another HRP region is encountered. Defs in duke@435: // HRP regions will get trailing SpillCopies to push the LRG down into the duke@435: // stack immediately. duke@435: // duke@435: // As a side effect, unlink from (hence make dead) coalesced copies. duke@435: // duke@435: duke@435: static const char out_of_nodes[] = "out of nodes during split"; duke@435: adlertz@5227: static bool contains_no_live_range_input(const Node* def) { adlertz@5227: for (uint i = 1; i < def->req(); ++i) { adlertz@5227: if (def->in(i) != NULL && def->in_RegMask(i).is_NotEmpty()) { adlertz@5227: return false; adlertz@5227: } adlertz@5227: } adlertz@5227: return true; adlertz@5227: } adlertz@5227: duke@435: //------------------------------get_spillcopy_wide----------------------------- duke@435: // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the duke@435: // wide ideal-register spill-mask if possible. If the 'wide-mask' does duke@435: // not cover the input (or output), use the input (or output) mask instead. duke@435: Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { duke@435: // If ideal reg doesn't exist we've got a bad schedule happening duke@435: // that is forcing us to spill something that isn't spillable. duke@435: // Bail rather than abort duke@435: int ireg = def->ideal_reg(); duke@435: if( ireg == 0 || ireg == Op_RegFlags ) { never@850: assert(false, "attempted to spill a non-spillable item"); duke@435: C->record_method_not_compilable("attempted to spill a non-spillable item"); duke@435: return NULL; duke@435: } duke@435: if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { duke@435: return NULL; duke@435: } duke@435: const RegMask *i_mask = &def->out_RegMask(); duke@435: const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg]; duke@435: const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask; duke@435: const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask; duke@435: const RegMask *w_o_mask; duke@435: kvn@3882: int num_regs = RegMask::num_registers(ireg); kvn@3882: bool is_vect = RegMask::is_vector(ireg); duke@435: if( w_mask->overlap( *o_mask ) && // Overlap AND kvn@3882: ((num_regs == 1) // Single use or aligned kvn@3882: || is_vect // or vector kvn@3882: || !is_vect && o_mask->is_aligned_pairs()) ) { kvn@3882: assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned"); duke@435: // Don't come here for mis-aligned doubles duke@435: w_o_mask = w_mask; duke@435: } else { // wide ideal mask does not overlap with o_mask duke@435: // Mis-aligned doubles come here and XMM->FPR moves on x86. duke@435: w_o_mask = o_mask; // Must target desired registers duke@435: // Does the ideal-reg-mask overlap with o_mask? I.e., can I use duke@435: // a reg-reg move or do I need a trip across register classes duke@435: // (and thus through memory)? duke@435: if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() ) duke@435: // Here we assume a trip through memory is required. duke@435: w_i_mask = &C->FIRST_STACK_mask(); duke@435: } duke@435: return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); duke@435: } duke@435: duke@435: //------------------------------insert_proj------------------------------------ twisti@1040: // Insert the spill at chosen location. Skip over any intervening Proj's or duke@435: // Phis. Skip over a CatchNode and projs, inserting in the fall-through block duke@435: // instead. Update high-pressure indices. Create a new live range. duke@435: void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) { duke@435: // Skip intervening ProjNodes. Do not insert between a ProjNode and duke@435: // its definer. duke@435: while( i < b->_nodes.size() && duke@435: (b->_nodes[i]->is_Proj() || kvn@1001: b->_nodes[i]->is_Phi() ) ) duke@435: i++; duke@435: duke@435: // Do not insert between a call and his Catch duke@435: if( b->_nodes[i]->is_Catch() ) { duke@435: // Put the instruction at the top of the fall-thru block. duke@435: // Find the fall-thru projection duke@435: while( 1 ) { duke@435: const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj(); duke@435: if( cp->_con == CatchProjNode::fall_through_index ) duke@435: break; duke@435: } duke@435: int sidx = i - b->end_idx()-1; duke@435: b = b->_succs[sidx]; // Switch to successor block duke@435: i = 1; // Right at start of block duke@435: } duke@435: duke@435: b->_nodes.insert(i,spill); // Insert node in block duke@435: _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect duke@435: // Adjust the point where we go hi-pressure duke@435: if( i <= b->_ihrp_index ) b->_ihrp_index++; duke@435: if( i <= b->_fhrp_index ) b->_fhrp_index++; duke@435: duke@435: // Assign a new Live Range Number to the SpillCopy and grow duke@435: // the node->live range mapping. duke@435: new_lrg(spill,maxlrg); duke@435: } duke@435: duke@435: //------------------------------split_DEF-------------------------------------- twisti@1040: // There are four categories of Split; UP/DOWN x DEF/USE duke@435: // Only three of these really occur as DOWN/USE will always color duke@435: // Any Split with a DEF cannot CISC-Spill now. Thus we need duke@435: // two helper routines, one for Split DEFS (insert after instruction), duke@435: // one for Split USES (insert before instruction). DEF insertion duke@435: // happens inside Split, where the Leaveblock array is updated. duke@435: uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray splits, int slidx ) { duke@435: #ifdef ASSERT duke@435: // Increment the counter for this lrg duke@435: splits.at_put(slidx, splits.at(slidx)+1); duke@435: #endif duke@435: // If we are spilling the memory op for an implicit null check, at the duke@435: // null check location (ie - null check is in HRP block) we need to do duke@435: // the null-check first, then spill-down in the following block. duke@435: // (The implicit_null_check function ensures the use is also dominated duke@435: // by the branch-not-taken block.) duke@435: Node *be = b->end(); duke@435: if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) { duke@435: // Spill goes in the branch-not-taken block duke@435: b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue]; duke@435: loc = 0; // Just past the Region duke@435: } duke@435: assert( loc >= 0, "must insert past block head" ); duke@435: duke@435: // Get a def-side SpillCopy duke@435: Node *spill = get_spillcopy_wide(def,NULL,0); duke@435: // Did we fail to split?, then bail duke@435: if (!spill) { duke@435: return 0; duke@435: } duke@435: duke@435: // Insert the spill at chosen location duke@435: insert_proj( b, loc+1, spill, maxlrg++); duke@435: duke@435: // Insert new node into Reaches array duke@435: Reachblock[slidx] = spill; duke@435: // Update debug list of reaching down definitions by adding this one duke@435: debug_defs[slidx] = spill; duke@435: duke@435: // return updated count of live ranges duke@435: return maxlrg; duke@435: } duke@435: duke@435: //------------------------------split_USE-------------------------------------- duke@435: // Splits at uses can involve redeffing the LRG, so no CISC Spilling there. duke@435: // Debug uses want to know if def is already stack enabled. duke@435: uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray splits, int slidx ) { duke@435: #ifdef ASSERT duke@435: // Increment the counter for this lrg duke@435: splits.at_put(slidx, splits.at(slidx)+1); duke@435: #endif duke@435: duke@435: // Some setup stuff for handling debug node uses duke@435: JVMState* jvms = use->jvms(); duke@435: uint debug_start = jvms ? jvms->debug_start() : 999999; duke@435: uint debug_end = jvms ? jvms->debug_end() : 999999; duke@435: duke@435: //------------------------------------------- duke@435: // Check for use of debug info duke@435: if (useidx >= debug_start && useidx < debug_end) { duke@435: // Actually it's perfectly legal for constant debug info to appear duke@435: // just unlikely. In this case the optimizer left a ConI of a 4 duke@435: // as both inputs to a Phi with only a debug use. It's a single-def duke@435: // live range of a rematerializable value. The live range spills, duke@435: // rematerializes and now the ConI directly feeds into the debug info. duke@435: // assert(!def->is_Con(), "constant debug info already constructed directly"); duke@435: duke@435: // Special split handling for Debug Info duke@435: // If DEF is DOWN, just hook the edge and return duke@435: // If DEF is UP, Split it DOWN for this USE. duke@435: if( def->is_Mach() ) { duke@435: if( def_down ) { duke@435: // DEF is DOWN, so connect USE directly to the DEF duke@435: use->set_req(useidx, def); duke@435: } else { duke@435: // Block and index where the use occurs. duke@435: Block *b = _cfg._bbs[use->_idx]; duke@435: // Put the clone just prior to use duke@435: int bindex = b->find_node(use); duke@435: // DEF is UP, so must copy it DOWN and hook in USE duke@435: // Insert SpillCopy before the USE, which uses DEF as its input, duke@435: // and defs a new live range, which is used by this node. duke@435: Node *spill = get_spillcopy_wide(def,use,useidx); duke@435: // did we fail to split? duke@435: if (!spill) { duke@435: // Bail duke@435: return 0; duke@435: } duke@435: // insert into basic block duke@435: insert_proj( b, bindex, spill, maxlrg++ ); duke@435: // Use the new split duke@435: use->set_req(useidx,spill); duke@435: } duke@435: // No further split handling needed for this use duke@435: return maxlrg; duke@435: } // End special splitting for debug info live range duke@435: } // If debug info duke@435: duke@435: // CISC-SPILLING duke@435: // Finally, check to see if USE is CISC-Spillable, and if so, duke@435: // gather_lrg_masks will add the flags bit to its mask, and duke@435: // no use side copy is needed. This frees up the live range duke@435: // register choices without causing copy coalescing, etc. duke@435: if( UseCISCSpill && cisc_sp ) { duke@435: int inp = use->cisc_operand(); duke@435: if( inp != AdlcVMDeps::Not_cisc_spillable ) duke@435: // Convert operand number to edge index number duke@435: inp = use->as_Mach()->operand_index(inp); duke@435: if( inp == (int)useidx ) { duke@435: use->set_req(useidx, def); duke@435: #ifndef PRODUCT duke@435: if( TraceCISCSpill ) { duke@435: tty->print(" set_split: "); duke@435: use->dump(); duke@435: } duke@435: #endif duke@435: return maxlrg; duke@435: } duke@435: } duke@435: duke@435: //------------------------------------------- duke@435: // Insert a Copy before the use duke@435: duke@435: // Block and index where the use occurs. duke@435: int bindex; duke@435: // Phi input spill-copys belong at the end of the prior block duke@435: if( use->is_Phi() ) { duke@435: b = _cfg._bbs[b->pred(useidx)->_idx]; duke@435: bindex = b->end_idx(); duke@435: } else { duke@435: // Put the clone just prior to use duke@435: bindex = b->find_node(use); duke@435: } duke@435: duke@435: Node *spill = get_spillcopy_wide( def, use, useidx ); duke@435: if( !spill ) return 0; // Bailed out duke@435: // Insert SpillCopy before the USE, which uses the reaching DEF as duke@435: // its input, and defs a new live range, which is used by this node. duke@435: insert_proj( b, bindex, spill, maxlrg++ ); duke@435: // Use the spill/clone duke@435: use->set_req(useidx,spill); duke@435: duke@435: // return updated live range count duke@435: return maxlrg; duke@435: } duke@435: kvn@2048: //------------------------------clone_node---------------------------- kvn@2048: // Clone node with anti dependence check. kvn@2048: Node* clone_node(Node* def, Block *b, Compile* C) { kvn@2048: if (def->needs_anti_dependence_check()) { kvn@2048: #ifdef ASSERT kvn@2048: if (Verbose) { kvn@2048: tty->print_cr("RA attempts to clone node with anti_dependence:"); kvn@2048: def->dump(-1); tty->cr(); kvn@2048: tty->print_cr("into block:"); kvn@2048: b->dump(); kvn@2048: } kvn@2048: #endif kvn@2048: if (C->subsume_loads() == true && !C->failing()) { kvn@2048: // Retry with subsume_loads == false kvn@2048: // If this is the first failure, the sentinel string will "stick" kvn@2048: // to the Compile object, and the C2Compiler will see it and retry. kvn@2048: C->record_failure(C2Compiler::retry_no_subsuming_loads()); kvn@2048: } else { kvn@2048: // Bailout without retry kvn@2048: C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence"); kvn@2048: } kvn@2048: return 0; kvn@2048: } kvn@2048: return def->clone(); kvn@2048: } kvn@2048: duke@435: //------------------------------split_Rematerialize---------------------------- duke@435: // Clone a local copy of the def. duke@435: Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) { duke@435: // The input live ranges will be stretched to the site of the new duke@435: // instruction. They might be stretched past a def and will thus duke@435: // have the old and new values of the same live range alive at the duke@435: // same time - a definite no-no. Split out private copies of duke@435: // the inputs. duke@435: if( def->req() > 1 ) { duke@435: for( uint i = 1; i < def->req(); i++ ) { duke@435: Node *in = def->in(i); duke@435: // Check for single-def (LRG cannot redefined) neliasso@4949: uint lidx = _lrg_map.live_range_id(in); neliasso@4949: if (lidx >= _lrg_map.max_lrg_id()) { neliasso@4949: continue; // Value is a recent spill-copy neliasso@4949: } neliasso@4949: if (lrgs(lidx).is_singledef()) { neliasso@4949: continue; neliasso@4949: } duke@435: duke@435: Block *b_def = _cfg._bbs[def->_idx]; duke@435: int idx_def = b_def->find_node(def); duke@435: Node *in_spill = get_spillcopy_wide( in, def, i ); duke@435: if( !in_spill ) return 0; // Bailed out duke@435: insert_proj(b_def,idx_def,in_spill,maxlrg++); duke@435: if( b_def == b ) duke@435: insidx++; duke@435: def->set_req(i,in_spill); duke@435: } duke@435: } duke@435: kvn@2048: Node *spill = clone_node(def, b, C); kvn@2048: if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { duke@435: // Check when generating nodes duke@435: return 0; duke@435: } duke@435: duke@435: // See if any inputs are currently being spilled, and take the duke@435: // latest copy of spilled inputs. duke@435: if( spill->req() > 1 ) { duke@435: for( uint i = 1; i < spill->req(); i++ ) { duke@435: Node *in = spill->in(i); neliasso@4949: uint lidx = _lrg_map.find_id(in); duke@435: duke@435: // Walk backwards thru spill copy node intermediates never@730: if (walkThru) { neliasso@4949: while (in->is_SpillCopy() && lidx >= _lrg_map.max_lrg_id()) { duke@435: in = in->in(1); neliasso@4949: lidx = _lrg_map.find_id(in); duke@435: } duke@435: neliasso@4949: if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_multidef()) { never@730: // walkThru found a multidef LRG, which is unsafe to use, so never@730: // just keep the original def used in the clone. never@730: in = spill->in(i); neliasso@4949: lidx = _lrg_map.find_id(in); never@730: } never@730: } never@730: neliasso@4949: if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).reg() >= LRG::SPILL_REG) { duke@435: Node *rdef = Reachblock[lrg2reach[lidx]]; neliasso@4949: if (rdef) { neliasso@4949: spill->set_req(i, rdef); neliasso@4949: } duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" ); duke@435: // Rematerialized op is def->spilled+1 duke@435: set_was_spilled(spill); duke@435: if( _spilled_once.test(def->_idx) ) duke@435: set_was_spilled(spill); duke@435: duke@435: insert_proj( b, insidx, spill, maxlrg++ ); duke@435: #ifdef ASSERT duke@435: // Increment the counter for this lrg duke@435: splits.at_put(slidx, splits.at(slidx)+1); duke@435: #endif duke@435: // See if the cloned def kills any flags, and copy those kills as well duke@435: uint i = insidx+1; neliasso@4949: if( clone_projs( b, i, def, spill, maxlrg) ) { duke@435: // Adjust the point where we go hi-pressure duke@435: if( i <= b->_ihrp_index ) b->_ihrp_index++; duke@435: if( i <= b->_fhrp_index ) b->_fhrp_index++; duke@435: } duke@435: duke@435: return spill; duke@435: } duke@435: duke@435: //------------------------------is_high_pressure------------------------------- duke@435: // Function to compute whether or not this live range is "high pressure" duke@435: // in this block - whether it spills eagerly or not. duke@435: bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) { duke@435: if( lrg->_was_spilled1 ) return true; duke@435: // Forced spilling due to conflict? Then split only at binding uses duke@435: // or defs, not for supposed capacity problems. duke@435: // CNC - Turned off 7/8/99, causes too much spilling duke@435: // if( lrg->_is_bound ) return false; duke@435: kvn@3882: // Use float pressure numbers for vectors. kvn@3882: bool is_float_or_vector = lrg->_is_float || lrg->_is_vector; duke@435: // Not yet reached the high-pressure cutoff point, so low pressure kvn@3882: uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index; duke@435: if( insidx < hrp_idx ) return false; duke@435: // Register pressure for the block as a whole depends on reg class kvn@3882: int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure; duke@435: // Bound live ranges will split at the binding points first; duke@435: // Intermediate splits should assume the live range's register set duke@435: // got "freed up" and that num_regs will become INT_PRESSURE. kvn@3882: int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE; duke@435: // Effective register pressure limit. duke@435: int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs()) duke@435: ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres; duke@435: // High pressure if block pressure requires more register freedom duke@435: // than live range has. duke@435: return block_pres >= lrg_pres; duke@435: } duke@435: duke@435: duke@435: //------------------------------prompt_use--------------------------------- duke@435: // True if lidx is used before any real register is def'd in the block duke@435: bool PhaseChaitin::prompt_use( Block *b, uint lidx ) { neliasso@4949: if (lrgs(lidx)._was_spilled2) { neliasso@4949: return false; neliasso@4949: } duke@435: duke@435: // Scan block for 1st use. duke@435: for( uint i = 1; i <= b->end_idx(); i++ ) { duke@435: Node *n = b->_nodes[i]; duke@435: // Ignore PHI use, these can be up or down neliasso@4949: if (n->is_Phi()) { neliasso@4949: continue; neliasso@4949: } neliasso@4949: for (uint j = 1; j < n->req(); j++) { neliasso@4949: if (_lrg_map.find_id(n->in(j)) == lidx) { duke@435: return true; // Found 1st use! neliasso@4949: } neliasso@4949: } neliasso@4949: if (n->out_RegMask().is_NotEmpty()) { neliasso@4949: return false; neliasso@4949: } duke@435: } duke@435: return false; duke@435: } duke@435: duke@435: //------------------------------Split-------------------------------------- duke@435: //----------Split Routine---------- duke@435: // ***** NEW SPLITTING HEURISTIC ***** duke@435: // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there. duke@435: // Else, no split unless there is a HRP block between a DEF and duke@435: // one of its uses, and then split at the HRP block. duke@435: // duke@435: // USES: If USE is in HRP, split at use to leave main LRG on stack. duke@435: // Else, hoist LRG back up to register only (ie - split is also DEF) duke@435: // We will compute a new maxlrg as we go kvn@4019: uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) { duke@435: NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); ) duke@435: kvn@4019: // Free thread local resources used by this method on exit. kvn@4019: ResourceMark rm(split_arena); kvn@4019: duke@435: uint bidx, pidx, slidx, insidx, inpidx, twoidx; duke@435: uint non_phi = 1, spill_cnt = 0; duke@435: Node **Reachblock; duke@435: Node *n1, *n2, *n3; duke@435: Node_List *defs,*phis; duke@435: bool *UPblock; duke@435: bool u1, u2, u3; duke@435: Block *b, *pred; duke@435: PhiNode *phi; neliasso@4949: GrowableArray lidxs(split_arena, maxlrg, 0, 0); duke@435: duke@435: // Array of counters to count splits per live range neliasso@4949: GrowableArray splits(split_arena, maxlrg, 0, 0); kvn@4019: kvn@4019: #define NEW_SPLIT_ARRAY(type, size)\ kvn@4019: (type*) split_arena->allocate_bytes((size) * sizeof(type)) duke@435: duke@435: //----------Setup Code---------- duke@435: // Create a convenient mapping from lrg numbers to reaches/leaves indices neliasso@4949: uint *lrg2reach = NEW_SPLIT_ARRAY(uint, maxlrg); duke@435: // Keep track of DEFS & Phis for later passes duke@435: defs = new Node_List(); duke@435: phis = new Node_List(); duke@435: // Gather info on which LRG's are spilling, and build maps neliasso@4949: for (bidx = 1; bidx < maxlrg; bidx++) { neliasso@4949: if (lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG) { duke@435: assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color"); duke@435: lrg2reach[bidx] = spill_cnt; duke@435: spill_cnt++; duke@435: lidxs.append(bidx); duke@435: #ifdef ASSERT duke@435: // Initialize the split counts to zero duke@435: splits.append(0); duke@435: #endif duke@435: #ifndef PRODUCT duke@435: if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 ) duke@435: tty->print_cr("Warning, 2nd spill of L%d",bidx); duke@435: #endif duke@435: } duke@435: } duke@435: duke@435: // Create side arrays for propagating reaching defs info. duke@435: // Each block needs a node pointer for each spilling live range for the duke@435: // Def which is live into the block. Phi nodes handle multiple input duke@435: // Defs by querying the output of their predecessor blocks and resolving duke@435: // them to a single Def at the phi. The pointer is updated for each duke@435: // Def in the block, and then becomes the output for the block when duke@435: // processing of the block is complete. We also need to track whether duke@435: // a Def is UP or DOWN. UP means that it should get a register (ie - duke@435: // it is always in LRP regions), and DOWN means that it is probably duke@435: // on the stack (ie - it crosses HRP regions). kvn@4019: Node ***Reaches = NEW_SPLIT_ARRAY( Node**, _cfg._num_blocks+1 ); kvn@4019: bool **UP = NEW_SPLIT_ARRAY( bool*, _cfg._num_blocks+1 ); kvn@4019: Node **debug_defs = NEW_SPLIT_ARRAY( Node*, spill_cnt ); kvn@4019: VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt ); duke@435: duke@435: // Initialize Reaches & UP duke@435: for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) { kvn@4019: Reaches[bidx] = NEW_SPLIT_ARRAY( Node*, spill_cnt ); kvn@4019: UP[bidx] = NEW_SPLIT_ARRAY( bool, spill_cnt ); duke@435: Node **Reachblock = Reaches[bidx]; duke@435: bool *UPblock = UP[bidx]; duke@435: for( slidx = 0; slidx < spill_cnt; slidx++ ) { duke@435: UPblock[slidx] = true; // Assume they start in registers duke@435: Reachblock[slidx] = NULL; // Assume that no def is present duke@435: } duke@435: } duke@435: kvn@4019: #undef NEW_SPLIT_ARRAY kvn@4019: duke@435: // Initialize to array of empty vectorsets duke@435: for( slidx = 0; slidx < spill_cnt; slidx++ ) kvn@4019: UP_entry[slidx] = new VectorSet(split_arena); duke@435: duke@435: //----------PASS 1---------- duke@435: //----------Propagation & Node Insertion Code---------- duke@435: // Walk the Blocks in RPO for DEF & USE info duke@435: for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { duke@435: duke@435: if (C->check_node_count(spill_cnt, out_of_nodes)) { duke@435: return 0; duke@435: } duke@435: duke@435: b = _cfg._blocks[bidx]; duke@435: // Reaches & UP arrays for this block duke@435: Reachblock = Reaches[b->_pre_order]; duke@435: UPblock = UP[b->_pre_order]; duke@435: // Reset counter of start of non-Phi nodes in block duke@435: non_phi = 1; duke@435: //----------Block Entry Handling---------- duke@435: // Check for need to insert a new phi duke@435: // Cycle through this block's predecessors, collecting Reaches duke@435: // info for each spilled LRG. If they are identical, no phi is duke@435: // needed. If they differ, check for a phi, and insert if missing, duke@435: // or update edges if present. Set current block's Reaches set to duke@435: // be either the phi's or the reaching def, as appropriate. duke@435: // If no Phi is needed, check if the LRG needs to spill on entry duke@435: // to the block due to HRP. duke@435: for( slidx = 0; slidx < spill_cnt; slidx++ ) { duke@435: // Grab the live range number duke@435: uint lidx = lidxs.at(slidx); duke@435: // Do not bother splitting or putting in Phis for single-def duke@435: // rematerialized live ranges. This happens alot to constants duke@435: // with long live ranges. never@730: if( lrgs(lidx).is_singledef() && duke@435: lrgs(lidx)._def->rematerialize() ) { duke@435: // reset the Reaches & UP entries duke@435: Reachblock[slidx] = lrgs(lidx)._def; duke@435: UPblock[slidx] = true; duke@435: // Record following instruction in case 'n' rematerializes and duke@435: // kills flags duke@435: Block *pred1 = _cfg._bbs[b->pred(1)->_idx]; duke@435: continue; duke@435: } duke@435: duke@435: // Initialize needs_phi and needs_split duke@435: bool needs_phi = false; duke@435: bool needs_split = false; kvn@765: bool has_phi = false; duke@435: // Walk the predecessor blocks to check inputs for that live range duke@435: // Grab predecessor block header duke@435: n1 = b->pred(1); duke@435: // Grab the appropriate reaching def info for inpidx duke@435: pred = _cfg._bbs[n1->_idx]; duke@435: pidx = pred->_pre_order; duke@435: Node **Ltmp = Reaches[pidx]; duke@435: bool *Utmp = UP[pidx]; duke@435: n1 = Ltmp[slidx]; duke@435: u1 = Utmp[slidx]; duke@435: // Initialize node for saving type info duke@435: n3 = n1; duke@435: u3 = u1; duke@435: duke@435: // Compare inputs to see if a Phi is needed duke@435: for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) { duke@435: // Grab predecessor block headers duke@435: n2 = b->pred(inpidx); duke@435: // Grab the appropriate reaching def info for inpidx duke@435: pred = _cfg._bbs[n2->_idx]; duke@435: pidx = pred->_pre_order; duke@435: Ltmp = Reaches[pidx]; duke@435: Utmp = UP[pidx]; duke@435: n2 = Ltmp[slidx]; duke@435: u2 = Utmp[slidx]; duke@435: // For each LRG, decide if a phi is necessary duke@435: if( n1 != n2 ) { duke@435: needs_phi = true; duke@435: } duke@435: // See if the phi has mismatched inputs, UP vs. DOWN duke@435: if( n1 && n2 && (u1 != u2) ) { duke@435: needs_split = true; duke@435: } duke@435: // Move n2/u2 to n1/u1 for next iteration duke@435: n1 = n2; duke@435: u1 = u2; duke@435: // Preserve a non-NULL predecessor for later type referencing duke@435: if( (n3 == NULL) && (n2 != NULL) ){ duke@435: n3 = n2; duke@435: u3 = u2; duke@435: } duke@435: } // End for all potential Phi inputs duke@435: kvn@765: // check block for appropriate phinode & update edges kvn@765: for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { kvn@765: n1 = b->_nodes[insidx]; kvn@765: // bail if this is not a phi kvn@765: phi = n1->is_Phi() ? n1->as_Phi() : NULL; kvn@765: if( phi == NULL ) { kvn@765: // Keep track of index of first non-PhiNode instruction in block kvn@765: non_phi = insidx; kvn@765: // break out of the for loop as we have handled all phi nodes kvn@765: break; kvn@765: } kvn@765: // must be looking at a phi neliasso@4949: if (_lrg_map.find_id(n1) == lidxs.at(slidx)) { kvn@765: // found the necessary phi kvn@765: needs_phi = false; kvn@765: has_phi = true; kvn@765: // initialize the Reaches entry for this LRG kvn@765: Reachblock[slidx] = phi; kvn@765: break; kvn@765: } // end if found correct phi kvn@765: } // end for all phi's kvn@765: kvn@765: // If a phi is needed or exist, check for it kvn@765: if( needs_phi || has_phi ) { duke@435: // add new phinode if one not already found duke@435: if( needs_phi ) { duke@435: // create a new phi node and insert it into the block duke@435: // type is taken from left over pointer to a predecessor duke@435: assert(n3,"No non-NULL reaching DEF for a Phi"); kvn@4115: phi = new (C) PhiNode(b->head(), n3->bottom_type()); duke@435: // initialize the Reaches entry for this LRG duke@435: Reachblock[slidx] = phi; duke@435: duke@435: // add node to block & node_to_block mapping neliasso@4949: insert_proj(b, insidx++, phi, maxlrg++); duke@435: non_phi++; duke@435: // Reset new phi's mapping to be the spilling live range neliasso@4949: _lrg_map.map(phi->_idx, lidx); neliasso@4949: assert(_lrg_map.find_id(phi) == lidx, "Bad update on Union-Find mapping"); duke@435: } // end if not found correct phi duke@435: // Here you have either found or created the Phi, so record it duke@435: assert(phi != NULL,"Must have a Phi Node here"); duke@435: phis->push(phi); duke@435: // PhiNodes should either force the LRG UP or DOWN depending duke@435: // on its inputs and the register pressure in the Phi's block. duke@435: UPblock[slidx] = true; // Assume new DEF is UP duke@435: // If entering a high-pressure area with no immediate use, duke@435: // assume Phi is DOWN duke@435: if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) ) duke@435: UPblock[slidx] = false; duke@435: // If we are not split up/down and all inputs are down, then we duke@435: // are down duke@435: if( !needs_split && !u3 ) duke@435: UPblock[slidx] = false; duke@435: } // end if phi is needed duke@435: duke@435: // Do not need a phi, so grab the reaching DEF duke@435: else { duke@435: // Grab predecessor block header duke@435: n1 = b->pred(1); duke@435: // Grab the appropriate reaching def info for k duke@435: pred = _cfg._bbs[n1->_idx]; duke@435: pidx = pred->_pre_order; duke@435: Node **Ltmp = Reaches[pidx]; duke@435: bool *Utmp = UP[pidx]; duke@435: // reset the Reaches & UP entries duke@435: Reachblock[slidx] = Ltmp[slidx]; duke@435: UPblock[slidx] = Utmp[slidx]; duke@435: } // end else no Phi is needed duke@435: } // end for all spilling live ranges duke@435: // DEBUG duke@435: #ifndef PRODUCT duke@435: if(trace_spilling()) { duke@435: tty->print("/`\nBlock %d: ", b->_pre_order); duke@435: tty->print("Reaching Definitions after Phi handling\n"); duke@435: for( uint x = 0; x < spill_cnt; x++ ) { duke@435: tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]); duke@435: if( Reachblock[x] ) duke@435: Reachblock[x]->dump(); duke@435: else duke@435: tty->print("Undefined\n"); duke@435: } duke@435: } duke@435: #endif duke@435: duke@435: //----------Non-Phi Node Splitting---------- duke@435: // Since phi-nodes have now been handled, the Reachblock array for this duke@435: // block is initialized with the correct starting value for the defs which duke@435: // reach non-phi instructions in this block. Thus, process non-phi duke@435: // instructions normally, inserting SpillCopy nodes for all spill duke@435: // locations. duke@435: duke@435: // Memoize any DOWN reaching definitions for use as DEBUG info duke@435: for( insidx = 0; insidx < spill_cnt; insidx++ ) { duke@435: debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx]; duke@435: if( UPblock[insidx] ) // Memoize UP decision at block start duke@435: UP_entry[insidx]->set( b->_pre_order ); duke@435: } duke@435: duke@435: //----------Walk Instructions in the Block and Split---------- duke@435: // For all non-phi instructions in the block duke@435: for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { duke@435: Node *n = b->_nodes[insidx]; duke@435: // Find the defining Node's live range index neliasso@4949: uint defidx = _lrg_map.find_id(n); duke@435: uint cnt = n->req(); duke@435: neliasso@4949: if (n->is_Phi()) { duke@435: // Skip phi nodes after removing dead copies. neliasso@4949: if (defidx < _lrg_map.max_lrg_id()) { duke@435: // Check for useless Phis. These appear if we spill, then duke@435: // coalesce away copies. Dont touch Phis in spilling live duke@435: // ranges; they are busy getting modifed in this pass. duke@435: if( lrgs(defidx).reg() < LRG::SPILL_REG ) { duke@435: uint i; duke@435: Node *u = NULL; duke@435: // Look for the Phi merging 2 unique inputs duke@435: for( i = 1; i < cnt; i++ ) { duke@435: // Ignore repeats and self duke@435: if( n->in(i) != u && n->in(i) != n ) { duke@435: // Found a unique input duke@435: if( u != NULL ) // If it's the 2nd, bail out duke@435: break; duke@435: u = n->in(i); // Else record it duke@435: } duke@435: } duke@435: assert( u, "at least 1 valid input expected" ); neliasso@4949: if (i >= cnt) { // Found one unique input neliasso@4949: assert(_lrg_map.find_id(n) == _lrg_map.find_id(u), "should be the same lrg"); duke@435: n->replace_by(u); // Then replace with unique input bharadwaj@4315: n->disconnect_inputs(NULL, C); duke@435: b->_nodes.remove(insidx); duke@435: insidx--; duke@435: b->_ihrp_index--; duke@435: b->_fhrp_index--; duke@435: } duke@435: } duke@435: } duke@435: continue; duke@435: } duke@435: assert( insidx > b->_ihrp_index || duke@435: (b->_reg_pressure < (uint)INTPRESSURE) || duke@435: b->_ihrp_index > 4000000 || duke@435: b->_ihrp_index >= b->end_idx() || duke@435: !b->_nodes[b->_ihrp_index]->is_Proj(), "" ); duke@435: assert( insidx > b->_fhrp_index || duke@435: (b->_freg_pressure < (uint)FLOATPRESSURE) || duke@435: b->_fhrp_index > 4000000 || duke@435: b->_fhrp_index >= b->end_idx() || duke@435: !b->_nodes[b->_fhrp_index]->is_Proj(), "" ); duke@435: duke@435: // ********** Handle Crossing HRP Boundry ********** duke@435: if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) { duke@435: for( slidx = 0; slidx < spill_cnt; slidx++ ) { twisti@1040: // Check for need to split at HRP boundary - split if UP duke@435: n1 = Reachblock[slidx]; duke@435: // bail out if no reaching DEF duke@435: if( n1 == NULL ) continue; duke@435: // bail out if live range is 'isolated' around inner loop duke@435: uint lidx = lidxs.at(slidx); duke@435: // If live range is currently UP duke@435: if( UPblock[slidx] ) { duke@435: // set location to insert spills at duke@435: // SPLIT DOWN HERE - NO CISC SPILL duke@435: if( is_high_pressure( b, &lrgs(lidx), insidx ) && duke@435: !n1->rematerialize() ) { duke@435: // If there is already a valid stack definition available, use it duke@435: if( debug_defs[slidx] != NULL ) { duke@435: Reachblock[slidx] = debug_defs[slidx]; duke@435: } duke@435: else { duke@435: // Insert point is just past last use or def in the block duke@435: int insert_point = insidx-1; duke@435: while( insert_point > 0 ) { duke@435: Node *n = b->_nodes[insert_point]; duke@435: // Hit top of block? Quit going backwards neliasso@4949: if (n->is_Phi()) { neliasso@4949: break; neliasso@4949: } duke@435: // Found a def? Better split after it. neliasso@4949: if (_lrg_map.live_range_id(n) == lidx) { neliasso@4949: break; neliasso@4949: } duke@435: // Look for a use duke@435: uint i; neliasso@4949: for( i = 1; i < n->req(); i++ ) { neliasso@4949: if (_lrg_map.live_range_id(n->in(i)) == lidx) { duke@435: break; neliasso@4949: } neliasso@4949: } duke@435: // Found a use? Better split after it. neliasso@4949: if (i < n->req()) { neliasso@4949: break; neliasso@4949: } duke@435: insert_point--; duke@435: } kvn@3882: uint orig_eidx = b->end_idx(); duke@435: maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } kvn@3882: // Spill of NULL check mem op goes into the following block. neliasso@4949: if (b->end_idx() > orig_eidx) { kvn@3882: insidx++; neliasso@4949: } duke@435: } duke@435: // This is a new DEF, so update UP duke@435: UPblock[slidx] = false; duke@435: #ifndef PRODUCT duke@435: // DEBUG duke@435: if( trace_spilling() ) { duke@435: tty->print("\nNew Split DOWN DEF of Spill Idx "); duke@435: tty->print("%d, UP %d:\n",slidx,false); duke@435: n1->dump(); duke@435: } duke@435: #endif duke@435: } duke@435: } // end if LRG is UP duke@435: } // end for all spilling live ranges duke@435: assert( b->_nodes[insidx] == n, "got insidx set incorrectly" ); duke@435: } // end if crossing HRP Boundry duke@435: duke@435: // If the LRG index is oob, then this is a new spillcopy, skip it. neliasso@4949: if (defidx >= _lrg_map.max_lrg_id()) { duke@435: continue; duke@435: } duke@435: LRG &deflrg = lrgs(defidx); duke@435: uint copyidx = n->is_Copy(); duke@435: // Remove coalesced copy from CFG neliasso@4949: if (copyidx && defidx == _lrg_map.live_range_id(n->in(copyidx))) { duke@435: n->replace_by( n->in(copyidx) ); duke@435: n->set_req( copyidx, NULL ); duke@435: b->_nodes.remove(insidx--); duke@435: b->_ihrp_index--; // Adjust the point where we go hi-pressure duke@435: b->_fhrp_index--; duke@435: continue; duke@435: } duke@435: duke@435: #define DERIVED 0 duke@435: duke@435: // ********** Handle USES ********** duke@435: bool nullcheck = false; duke@435: // Implicit null checks never use the spilled value duke@435: if( n->is_MachNullCheck() ) duke@435: nullcheck = true; duke@435: if( !nullcheck ) { duke@435: // Search all inputs for a Spill-USE duke@435: JVMState* jvms = n->jvms(); duke@435: uint oopoff = jvms ? jvms->oopoff() : cnt; duke@435: uint old_last = cnt - 1; duke@435: for( inpidx = 1; inpidx < cnt; inpidx++ ) { duke@435: // Derived/base pairs may be added to our inputs during this loop. duke@435: // If inpidx > old_last, then one of these new inputs is being duke@435: // handled. Skip the derived part of the pair, but process duke@435: // the base like any other input. neliasso@4949: if (inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED) { duke@435: continue; // skip derived_debug added below duke@435: } duke@435: // Get lidx of input neliasso@4949: uint useidx = _lrg_map.find_id(n->in(inpidx)); duke@435: // Not a brand-new split, and it is a spill use neliasso@4949: if (useidx < _lrg_map.max_lrg_id() && lrgs(useidx).reg() >= LRG::SPILL_REG) { duke@435: // Check for valid reaching DEF duke@435: slidx = lrg2reach[useidx]; duke@435: Node *def = Reachblock[slidx]; duke@435: assert( def != NULL, "Using Undefined Value in Split()\n"); duke@435: duke@435: // (+++) %%%% remove this in favor of pre-pass in matcher.cpp duke@435: // monitor references do not care where they live, so just hook duke@435: if ( jvms && jvms->is_monitor_use(inpidx) ) { duke@435: // The effect of this clone is to drop the node out of the block, duke@435: // so that the allocator does not see it anymore, and therefore duke@435: // does not attempt to assign it a register. kvn@2048: def = clone_node(def, b, C); kvn@2048: if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { kvn@2048: return 0; kvn@2048: } neliasso@4949: _lrg_map.extend(def->_idx, 0); duke@435: _cfg._bbs.map(def->_idx,b); duke@435: n->set_req(inpidx, def); duke@435: continue; duke@435: } duke@435: duke@435: // Rematerializable? Then clone def at use site instead duke@435: // of store/load duke@435: if( def->rematerialize() ) { duke@435: int old_size = b->_nodes.size(); duke@435: def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true ); duke@435: if( !def ) return 0; // Bail out duke@435: insidx += b->_nodes.size()-old_size; duke@435: } duke@435: duke@435: MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL; duke@435: // Base pointers and oopmap references do not care where they live. duke@435: if ((inpidx >= oopoff) || duke@435: (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) { duke@435: if (def->rematerialize() && lrgs(useidx)._was_spilled2) { duke@435: // This def has been rematerialized a couple of times without duke@435: // progress. It doesn't care if it lives UP or DOWN, so duke@435: // spill it down now. duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx++; // Reset iterator to skip USE side split duke@435: } else { duke@435: // Just hook the def edge duke@435: n->set_req(inpidx, def); duke@435: } duke@435: duke@435: if (inpidx >= oopoff) { duke@435: // After oopoff, we have derived/base pairs. We must mention all duke@435: // derived pointers here as derived/base pairs for GC. If the duke@435: // derived value is spilling and we have a copy both in Reachblock duke@435: // (called here 'def') and debug_defs[slidx] we need to mention duke@435: // both in derived/base pairs or kill one. duke@435: Node *derived_debug = debug_defs[slidx]; duke@435: if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base? duke@435: mach && mach->ideal_Opcode() != Op_Halt && duke@435: derived_debug != NULL && duke@435: derived_debug != def ) { // Actual 2nd value appears duke@435: // We have already set 'def' as a derived value. duke@435: // Also set debug_defs[slidx] as a derived value. duke@435: uint k; duke@435: for( k = oopoff; k < cnt; k += 2 ) duke@435: if( n->in(k) == derived_debug ) duke@435: break; // Found an instance of debug derived duke@435: if( k == cnt ) {// No instance of debug_defs[slidx] duke@435: // Add a derived/base pair to cover the debug info. duke@435: // We have to process the added base later since it is not duke@435: // handled yet at this point but skip derived part. duke@435: assert(((n->req() - oopoff) & 1) == DERIVED, duke@435: "must match skip condition above"); duke@435: n->add_req( derived_debug ); // this will be skipped above duke@435: n->add_req( n->in(inpidx+1) ); // this will be processed duke@435: // Increment cnt to handle added input edges on duke@435: // subsequent iterations. duke@435: cnt += 2; duke@435: } duke@435: } duke@435: } duke@435: continue; duke@435: } duke@435: // Special logic for DEBUG info duke@435: if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) { duke@435: uint debug_start = jvms->debug_start(); duke@435: // If this is debug info use & there is a reaching DOWN def duke@435: if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) { duke@435: assert(inpidx < oopoff, "handle only debug info here"); duke@435: // Just hook it in & move on duke@435: n->set_req(inpidx, debug_defs[slidx]); duke@435: // (Note that this can make two sides of a split live at the duke@435: // same time: The debug def on stack, and another def in a duke@435: // register. The GC needs to know about both of them, but any duke@435: // derived pointers after oopoff will refer to only one of the duke@435: // two defs and the GC would therefore miss the other. Thus duke@435: // this hack is only allowed for debug info which is Java state duke@435: // and therefore never a derived pointer.) duke@435: continue; duke@435: } duke@435: } duke@435: // Grab register mask info duke@435: const RegMask &dmask = def->out_RegMask(); duke@435: const RegMask &umask = n->in_RegMask(inpidx); kvn@3882: bool is_vect = RegMask::is_vector(def->ideal_reg()); duke@435: assert(inpidx < oopoff, "cannot use-split oop map info"); duke@435: duke@435: bool dup = UPblock[slidx]; duke@435: bool uup = umask.is_UP(); duke@435: duke@435: // Need special logic to handle bound USES. Insert a split at this duke@435: // bound use if we can't rematerialize the def, or if we need the duke@435: // split to form a misaligned pair. duke@435: if( !umask.is_AllStack() && duke@435: (int)umask.Size() <= lrgs(useidx).num_regs() && duke@435: (!def->rematerialize() || kvn@3882: !is_vect && umask.is_misaligned_pair())) { duke@435: // These need a Split regardless of overlap or pressure duke@435: // SPLIT - NO DEF - NO CISC SPILL duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx++; // Reset iterator to skip USE side split duke@435: continue; duke@435: } never@2085: kvn@3040: if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) { never@2085: // The use at the call can force the def down so insert never@2085: // a split before the use to allow the def more freedom. never@2085: maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); never@2085: // If it wasn't split bail never@2085: if (!maxlrg) { never@2085: return 0; never@2085: } never@2085: insidx++; // Reset iterator to skip USE side split never@2085: continue; never@2085: } never@2085: duke@435: // Here is the logic chart which describes USE Splitting: duke@435: // 0 = false or DOWN, 1 = true or UP duke@435: // duke@435: // Overlap | DEF | USE | Action duke@435: //------------------------------------------------------- duke@435: // 0 | 0 | 0 | Copy - mem -> mem duke@435: // 0 | 0 | 1 | Split-UP - Check HRP duke@435: // 0 | 1 | 0 | Split-DOWN - Debug Info? duke@435: // 0 | 1 | 1 | Copy - reg -> reg duke@435: // 1 | 0 | 0 | Reset Input Edge (no Split) duke@435: // 1 | 0 | 1 | Split-UP - Check HRP duke@435: // 1 | 1 | 0 | Split-DOWN - Debug Info? duke@435: // 1 | 1 | 1 | Reset Input Edge (no Split) duke@435: // duke@435: // So, if (dup == uup), then overlap test determines action, duke@435: // with true being no split, and false being copy. Else, duke@435: // if DEF is DOWN, Split-UP, and check HRP to decide on duke@435: // resetting DEF. Finally if DEF is UP, Split-DOWN, with duke@435: // special handling for Debug Info. duke@435: if( dup == uup ) { duke@435: if( dmask.overlap(umask) ) { duke@435: // Both are either up or down, and there is overlap, No Split duke@435: n->set_req(inpidx, def); duke@435: } duke@435: else { // Both are either up or down, and there is no overlap duke@435: if( dup ) { // If UP, reg->reg copy duke@435: // COPY ACROSS HERE - NO DEF - NO CISC SPILL duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx++; // Reset iterator to skip USE side split duke@435: } duke@435: else { // DOWN, mem->mem copy duke@435: // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL duke@435: // First Split-UP to move value into Register duke@435: uint def_ideal = def->ideal_reg(); duke@435: const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; duke@435: Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); duke@435: insert_proj( b, insidx, spill, maxlrg ); duke@435: // Then Split-DOWN as if previous Split was DEF duke@435: maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx += 2; // Reset iterator to skip USE side splits duke@435: } duke@435: } // End else no overlap duke@435: } // End if dup == uup duke@435: // dup != uup, so check dup for direction of Split duke@435: else { duke@435: if( dup ) { // If UP, Split-DOWN and check Debug Info duke@435: // If this node is already a SpillCopy, just patch the edge duke@435: // except the case of spilling to stack. duke@435: if( n->is_SpillCopy() ) { duke@435: RegMask tmp_rm(umask); duke@435: tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask); duke@435: if( dmask.overlap(tmp_rm) ) { duke@435: if( def != n->in(inpidx) ) { duke@435: n->set_req(inpidx, def); duke@435: } duke@435: continue; duke@435: } duke@435: } duke@435: // COPY DOWN HERE - NO DEF - NO CISC SPILL duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx++; // Reset iterator to skip USE side split duke@435: // Check for debug-info split. Capture it for later duke@435: // debug splits of the same value duke@435: if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff) duke@435: debug_defs[slidx] = n->in(inpidx); duke@435: duke@435: } duke@435: else { // DOWN, Split-UP and check register pressure duke@435: if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { duke@435: // COPY UP HERE - NO DEF - CISC SPILL duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: insidx++; // Reset iterator to skip USE side split duke@435: } else { // LRP duke@435: // COPY UP HERE - WITH DEF - NO CISC SPILL duke@435: maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: // Flag this lift-up in a low-pressure block as duke@435: // already-spilled, so if it spills again it will duke@435: // spill hard (instead of not spilling hard and duke@435: // coalescing away). duke@435: set_was_spilled(n->in(inpidx)); duke@435: // Since this is a new DEF, update Reachblock & UP duke@435: Reachblock[slidx] = n->in(inpidx); duke@435: UPblock[slidx] = true; duke@435: insidx++; // Reset iterator to skip USE side split duke@435: } duke@435: } // End else DOWN duke@435: } // End dup != uup duke@435: } // End if Spill USE duke@435: } // End For All Inputs duke@435: } // End If not nullcheck duke@435: duke@435: // ********** Handle DEFS ********** duke@435: // DEFS either Split DOWN in HRP regions or when the LRG is bound, or duke@435: // just reset the Reaches info in LRP regions. DEFS must always update duke@435: // UP info. duke@435: if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled? duke@435: uint slidx = lrg2reach[defidx]; duke@435: // Add to defs list for later assignment of new live range number duke@435: defs->push(n); duke@435: // Set a flag on the Node indicating it has already spilled. duke@435: // Only do it for capacity spills not conflict spills. duke@435: if( !deflrg._direct_conflict ) duke@435: set_was_spilled(n); duke@435: assert(!n->is_Phi(),"Cannot insert Phi into DEFS list"); duke@435: // Grab UP info for DEF duke@435: const RegMask &dmask = n->out_RegMask(); duke@435: bool defup = dmask.is_UP(); kvn@3882: int ireg = n->ideal_reg(); kvn@3882: bool is_vect = RegMask::is_vector(ireg); duke@435: // Only split at Def if this is a HRP block or bound (and spilled once) duke@435: if( !n->rematerialize() && kvn@3882: (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) && kvn@3882: (deflrg._direct_conflict || deflrg._must_spill)) || duke@435: // Check for LRG being up in a register and we are inside a high duke@435: // pressure area. Spill it down immediately. duke@435: (defup && is_high_pressure(b,&deflrg,insidx))) ) { duke@435: assert( !n->rematerialize(), "" ); duke@435: assert( !n->is_SpillCopy(), "" ); duke@435: // Do a split at the def site. duke@435: maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx ); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: // Split DEF's Down duke@435: UPblock[slidx] = 0; duke@435: #ifndef PRODUCT duke@435: // DEBUG duke@435: if( trace_spilling() ) { duke@435: tty->print("\nNew Split DOWN DEF of Spill Idx "); duke@435: tty->print("%d, UP %d:\n",slidx,false); duke@435: n->dump(); duke@435: } duke@435: #endif duke@435: } duke@435: else { // Neither bound nor HRP, must be LRP duke@435: // otherwise, just record the def duke@435: Reachblock[slidx] = n; duke@435: // UP should come from the outRegmask() of the DEF duke@435: UPblock[slidx] = defup; duke@435: // Update debug list of reaching down definitions, kill if DEF is UP duke@435: debug_defs[slidx] = defup ? NULL : n; duke@435: #ifndef PRODUCT duke@435: // DEBUG duke@435: if( trace_spilling() ) { duke@435: tty->print("\nNew DEF of Spill Idx "); duke@435: tty->print("%d, UP %d:\n",slidx,defup); duke@435: n->dump(); duke@435: } duke@435: #endif duke@435: } // End else LRP duke@435: } // End if spill def duke@435: duke@435: // ********** Split Left Over Mem-Mem Moves ********** duke@435: // Check for mem-mem copies and split them now. Do not do this duke@435: // to copies about to be spilled; they will be Split shortly. neliasso@4949: if (copyidx) { duke@435: Node *use = n->in(copyidx); neliasso@4949: uint useidx = _lrg_map.find_id(use); neliasso@4949: if (useidx < _lrg_map.max_lrg_id() && // This is not a new split duke@435: OptoReg::is_stack(deflrg.reg()) && duke@435: deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack duke@435: LRG &uselrg = lrgs(useidx); duke@435: if( OptoReg::is_stack(uselrg.reg()) && duke@435: uselrg.reg() < LRG::SPILL_REG && // USE is from stack duke@435: deflrg.reg() != uselrg.reg() ) { // Not trivially removed coleenp@4037: uint def_ideal_reg = n->bottom_type()->ideal_reg(); duke@435: const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg]; duke@435: const RegMask &use_rm = n->in_RegMask(copyidx); duke@435: if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL duke@435: if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes duke@435: return 0; duke@435: } duke@435: Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); duke@435: n->set_req(copyidx,spill); duke@435: n->as_MachSpillCopy()->set_in_RegMask(def_rm); duke@435: // Put the spill just before the copy duke@435: insert_proj( b, insidx++, spill, maxlrg++ ); duke@435: } duke@435: } duke@435: } duke@435: } duke@435: } // End For All Instructions in Block - Non-PHI Pass duke@435: duke@435: // Check if each LRG is live out of this block so as not to propagate duke@435: // beyond the last use of a LRG. duke@435: for( slidx = 0; slidx < spill_cnt; slidx++ ) { duke@435: uint defidx = lidxs.at(slidx); duke@435: IndexSet *liveout = _live->live(b); duke@435: if( !liveout->member(defidx) ) { duke@435: #ifdef ASSERT duke@435: // The index defidx is not live. Check the liveout array to ensure that duke@435: // it contains no members which compress to defidx. Finding such an duke@435: // instance may be a case to add liveout adjustment in compress_uf_map(). duke@435: // See 5063219. duke@435: uint member; duke@435: IndexSetIterator isi(liveout); duke@435: while ((member = isi.next()) != 0) { neliasso@4949: assert(defidx != _lrg_map.find_const(member), "Live out member has not been compressed"); duke@435: } duke@435: #endif duke@435: Reachblock[slidx] = NULL; duke@435: } else { duke@435: assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value"); duke@435: } duke@435: } duke@435: #ifndef PRODUCT duke@435: if( trace_spilling() ) duke@435: b->dump(); duke@435: #endif duke@435: } // End For All Blocks duke@435: duke@435: //----------PASS 2---------- duke@435: // Reset all DEF live range numbers here duke@435: for( insidx = 0; insidx < defs->size(); insidx++ ) { duke@435: // Grab the def duke@435: n1 = defs->at(insidx); duke@435: // Set new lidx for DEF duke@435: new_lrg(n1, maxlrg++); duke@435: } duke@435: //----------Phi Node Splitting---------- duke@435: // Clean up a phi here, and assign a new live range number duke@435: // Cycle through this block's predecessors, collecting Reaches duke@435: // info for each spilled LRG and update edges. duke@435: // Walk the phis list to patch inputs, split phis, and name phis never@2358: uint lrgs_before_phi_split = maxlrg; duke@435: for( insidx = 0; insidx < phis->size(); insidx++ ) { duke@435: Node *phi = phis->at(insidx); duke@435: assert(phi->is_Phi(),"This list must only contain Phi Nodes"); duke@435: Block *b = _cfg._bbs[phi->_idx]; duke@435: // Grab the live range number neliasso@4949: uint lidx = _lrg_map.find_id(phi); duke@435: uint slidx = lrg2reach[lidx]; duke@435: // Update node to lidx map duke@435: new_lrg(phi, maxlrg++); duke@435: // Get PASS1's up/down decision for the block. duke@435: int phi_up = !!UP_entry[slidx]->test(b->_pre_order); duke@435: duke@435: // Force down if double-spilling live range duke@435: if( lrgs(lidx)._was_spilled1 ) duke@435: phi_up = false; duke@435: duke@435: // When splitting a Phi we an split it normal or "inverted". duke@435: // An inverted split makes the splits target the Phi's UP/DOWN duke@435: // sense inverted; then the Phi is followed by a final def-side duke@435: // split to invert back. It changes which blocks the spill code duke@435: // goes in. duke@435: duke@435: // Walk the predecessor blocks and assign the reaching def to the Phi. duke@435: // Split Phi nodes by placing USE side splits wherever the reaching duke@435: // DEF has the wrong UP/DOWN value. duke@435: for( uint i = 1; i < b->num_preds(); i++ ) { duke@435: // Get predecessor block pre-order number duke@435: Block *pred = _cfg._bbs[b->pred(i)->_idx]; duke@435: pidx = pred->_pre_order; duke@435: // Grab reaching def duke@435: Node *def = Reaches[pidx][slidx]; duke@435: assert( def, "must have reaching def" ); duke@435: // If input up/down sense and reg-pressure DISagree adlertz@5227: if (def->rematerialize() && contains_no_live_range_input(def)) { never@2358: // Place the rematerialized node above any MSCs created during never@2358: // phi node splitting. end_idx points at the insertion point never@2358: // so look at the node before it. never@2358: int insert = pred->end_idx(); never@2358: while (insert >= 1 && never@2358: pred->_nodes[insert - 1]->is_SpillCopy() && neliasso@4949: _lrg_map.find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) { never@2358: insert--; never@2358: } neliasso@4949: def = split_Rematerialize(def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false); neliasso@4949: if (!def) { neliasso@4949: return 0; // Bail out neliasso@4949: } duke@435: } duke@435: // Update the Phi's input edge array duke@435: phi->set_req(i,def); duke@435: // Grab the UP/DOWN sense for the input duke@435: u1 = UP[pidx][slidx]; duke@435: if( u1 != (phi_up != 0)) { duke@435: maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); duke@435: // If it wasn't split bail duke@435: if (!maxlrg) { duke@435: return 0; duke@435: } duke@435: } duke@435: } // End for all inputs to the Phi duke@435: } // End for all Phi Nodes duke@435: // Update _maxlrg to save Union asserts neliasso@4949: _lrg_map.set_max_lrg_id(maxlrg); duke@435: duke@435: duke@435: //----------PASS 3---------- duke@435: // Pass over all Phi's to union the live ranges duke@435: for( insidx = 0; insidx < phis->size(); insidx++ ) { duke@435: Node *phi = phis->at(insidx); duke@435: assert(phi->is_Phi(),"This list must only contain Phi Nodes"); duke@435: // Walk all inputs to Phi and Union input live range with Phi live range duke@435: for( uint i = 1; i < phi->req(); i++ ) { duke@435: // Grab the input node duke@435: Node *n = phi->in(i); neliasso@4949: assert(n, "node should exist"); neliasso@4949: uint lidx = _lrg_map.find(n); neliasso@4949: uint pidx = _lrg_map.find(phi); neliasso@4949: if (lidx < pidx) { duke@435: Union(n, phi); neliasso@4949: } neliasso@4949: else if(lidx > pidx) { duke@435: Union(phi, n); neliasso@4949: } duke@435: } // End for all inputs to the Phi Node duke@435: } // End for all Phi Nodes duke@435: // Now union all two address instructions neliasso@4949: for (insidx = 0; insidx < defs->size(); insidx++) { duke@435: // Grab the def duke@435: n1 = defs->at(insidx); duke@435: // Set new lidx for DEF & handle 2-addr instructions neliasso@4949: if (n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0)) { neliasso@4949: assert(_lrg_map.find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index"); duke@435: // Union the input and output live ranges neliasso@4949: uint lr1 = _lrg_map.find(n1); neliasso@4949: uint lr2 = _lrg_map.find(n1->in(twoidx)); neliasso@4949: if (lr1 < lr2) { duke@435: Union(n1, n1->in(twoidx)); neliasso@4949: } neliasso@4949: else if (lr1 > lr2) { duke@435: Union(n1->in(twoidx), n1); neliasso@4949: } duke@435: } // End if two address duke@435: } // End for all defs duke@435: // DEBUG duke@435: #ifdef ASSERT duke@435: // Validate all live range index assignments neliasso@4949: for (bidx = 0; bidx < _cfg._num_blocks; bidx++) { duke@435: b = _cfg._blocks[bidx]; neliasso@4949: for (insidx = 0; insidx <= b->end_idx(); insidx++) { duke@435: Node *n = b->_nodes[insidx]; neliasso@4949: uint defidx = _lrg_map.find(n); neliasso@4949: assert(defidx < _lrg_map.max_lrg_id(), "Bad live range index in Split"); duke@435: assert(defidx < maxlrg,"Bad live range index in Split"); duke@435: } duke@435: } duke@435: // Issue a warning if splitting made no progress duke@435: int noprogress = 0; neliasso@4949: for (slidx = 0; slidx < spill_cnt; slidx++) { neliasso@4949: if (PrintOpto && WizardMode && splits.at(slidx) == 0) { duke@435: tty->print_cr("Failed to split live range %d", lidxs.at(slidx)); duke@435: //BREAKPOINT; duke@435: } duke@435: else { duke@435: noprogress++; duke@435: } duke@435: } duke@435: if(!noprogress) { duke@435: tty->print_cr("Failed to make progress in Split"); duke@435: //BREAKPOINT; duke@435: } duke@435: #endif duke@435: // Return updated count of live ranges duke@435: return maxlrg; duke@435: }