duke@435: /*
duke@435:  * Copyright 2003-2007 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: # include "incls/_precompiled.incl"
duke@435: # include "incls/_vm_version_x86_64.cpp.incl"
duke@435: 
duke@435: int VM_Version::_cpu;
duke@435: int VM_Version::_model;
duke@435: int VM_Version::_stepping;
duke@435: int VM_Version::_cpuFeatures;
duke@435: const char*           VM_Version::_features_str = "";
duke@435: VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
duke@435: 
duke@435: static BufferBlob* stub_blob;
duke@435: static const int stub_size = 300;
duke@435: 
duke@435: extern "C" {
duke@435:   typedef void (*getPsrInfo_stub_t)(void*);
duke@435: }
duke@435: static getPsrInfo_stub_t getPsrInfo_stub = NULL;
duke@435: 
duke@435: 
duke@435: class VM_Version_StubGenerator: public StubCodeGenerator {
duke@435:  public:
duke@435: 
duke@435:   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
duke@435: 
duke@435:   address generate_getPsrInfo() {
duke@435: 
duke@435:     Label std_cpuid1, ext_cpuid1, ext_cpuid5, done;
duke@435: 
duke@435:     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
duke@435: #   define __ _masm->
duke@435: 
duke@435:     address start = __ pc();
duke@435: 
duke@435:     //
duke@435:     // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
duke@435:     //
duke@435:     // rcx and rdx are first and second argument registers on windows
duke@435: 
duke@435:     __ pushq(rbp);
duke@435:     __ movq(rbp, c_rarg0); // cpuid_info address
duke@435:     __ pushq(rbx);
duke@435:     __ pushq(rsi);
duke@435: 
duke@435:     //
duke@435:     // we have a chip which supports the "cpuid" instruction
duke@435:     //
duke@435:     __ xorl(rax, rax);
duke@435:     __ cpuid();
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     __ cmpl(rax, 3);     // Is cpuid(0x4) supported?
duke@435:     __ jccb(Assembler::belowEqual, std_cpuid1);
duke@435: 
duke@435:     //
duke@435:     // cpuid(0x4) Deterministic cache params
duke@435:     //
duke@435:     __ movl(rax, 4);
duke@435:     __ xorl(rcx, rcx);   // L1 cache
duke@435:     __ cpuid();
duke@435:     __ pushq(rax);
duke@435:     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
duke@435:     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
duke@435:     __ popq(rax);
duke@435:     __ jccb(Assembler::equal, std_cpuid1);
duke@435: 
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     //
duke@435:     // Standard cpuid(0x1)
duke@435:     //
duke@435:     __ bind(std_cpuid1);
duke@435:     __ movl(rax, 1);
duke@435:     __ cpuid();
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     __ movl(rax, 0x80000000);
duke@435:     __ cpuid();
duke@435:     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
duke@435:     __ jcc(Assembler::belowEqual, done);
duke@435:     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
duke@435:     __ jccb(Assembler::belowEqual, ext_cpuid1);
duke@435:     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
duke@435:     __ jccb(Assembler::belowEqual, ext_cpuid5);
duke@435:     //
duke@435:     // Extended cpuid(0x80000008)
duke@435:     //
duke@435:     __ movl(rax, 0x80000008);
duke@435:     __ cpuid();
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     //
duke@435:     // Extended cpuid(0x80000005)
duke@435:     //
duke@435:     __ bind(ext_cpuid5);
duke@435:     __ movl(rax, 0x80000005);
duke@435:     __ cpuid();
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     //
duke@435:     // Extended cpuid(0x80000001)
duke@435:     //
duke@435:     __ bind(ext_cpuid1);
duke@435:     __ movl(rax, 0x80000001);
duke@435:     __ cpuid();
duke@435:     __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
duke@435:     __ movl(Address(rsi, 0), rax);
duke@435:     __ movl(Address(rsi, 4), rbx);
duke@435:     __ movl(Address(rsi, 8), rcx);
duke@435:     __ movl(Address(rsi,12), rdx);
duke@435: 
duke@435:     //
duke@435:     // return
duke@435:     //
duke@435:     __ bind(done);
duke@435:     __ popq(rsi);
duke@435:     __ popq(rbx);
duke@435:     __ popq(rbp);
duke@435:     __ ret(0);
duke@435: 
duke@435: #   undef __
duke@435: 
duke@435:     return start;
duke@435:   };
duke@435: };
duke@435: 
duke@435: 
duke@435: void VM_Version::get_processor_features() {
duke@435: 
duke@435:   _logical_processors_per_package = 1;
duke@435:   // Get raw processor info
duke@435:   getPsrInfo_stub(&_cpuid_info);
duke@435:   assert_is_initialized();
duke@435:   _cpu = extended_cpu_family();
duke@435:   _model = extended_cpu_model();
duke@435:   _stepping = cpu_stepping();
duke@435:   _cpuFeatures = feature_flags();
duke@435:   // Logical processors are only available on P4s and above,
duke@435:   // and only if hyperthreading is available.
duke@435:   _logical_processors_per_package = logical_processor_count();
duke@435:   _supports_cx8    = supports_cmpxchg8();
duke@435:   // OS should support SSE for x64 and hardware should support at least SSE2.
duke@435:   if (!VM_Version::supports_sse2()) {
duke@435:     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
duke@435:   }
duke@435:   if (UseSSE < 4)
duke@435:     _cpuFeatures &= ~CPU_SSE4;
duke@435:   if (UseSSE < 3) {
duke@435:     _cpuFeatures &= ~CPU_SSE3;
duke@435:     _cpuFeatures &= ~CPU_SSSE3;
duke@435:     _cpuFeatures &= ~CPU_SSE4A;
duke@435:   }
duke@435:   if (UseSSE < 2)
duke@435:     _cpuFeatures &= ~CPU_SSE2;
duke@435:   if (UseSSE < 1)
duke@435:     _cpuFeatures &= ~CPU_SSE;
duke@435: 
duke@435:   if (logical_processors_per_package() == 1) {
duke@435:     // HT processor could be installed on a system which doesn't support HT.
duke@435:     _cpuFeatures &= ~CPU_HT;
duke@435:   }
duke@435: 
duke@435:   char buf[256];
duke@435:   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
duke@435:                cores_per_cpu(), threads_per_core(),
duke@435:                cpu_family(), _model, _stepping,
duke@435:                (supports_cmov() ? ", cmov" : ""),
duke@435:                (supports_cmpxchg8() ? ", cx8" : ""),
duke@435:                (supports_fxsr() ? ", fxsr" : ""),
duke@435:                (supports_mmx()  ? ", mmx"  : ""),
duke@435:                (supports_sse()  ? ", sse"  : ""),
duke@435:                (supports_sse2() ? ", sse2" : ""),
duke@435:                (supports_sse3() ? ", sse3" : ""),
duke@435:                (supports_ssse3()? ", ssse3": ""),
duke@435:                (supports_sse4() ? ", sse4" : ""),
duke@435:                (supports_mmx_ext() ? ", mmxext" : ""),
duke@435:                (supports_3dnow()   ? ", 3dnow"  : ""),
duke@435:                (supports_3dnow2()  ? ", 3dnowext" : ""),
duke@435:                (supports_sse4a()   ? ", sse4a": ""),
duke@435:                (supports_ht() ? ", ht": ""));
duke@435:   _features_str = strdup(buf);
duke@435: 
duke@435:   // UseSSE is set to the smaller of what hardware supports and what
duke@435:   // the command line requires.  I.e., you cannot set UseSSE to 2 on
duke@435:   // older Pentiums which do not support it.
duke@435:   if( UseSSE > 4 ) UseSSE=4;
duke@435:   if( UseSSE < 0 ) UseSSE=0;
duke@435:   if( !supports_sse4() ) // Drop to 3 if no SSE4 support
duke@435:     UseSSE = MIN2((intx)3,UseSSE);
duke@435:   if( !supports_sse3() ) // Drop to 2 if no SSE3 support
duke@435:     UseSSE = MIN2((intx)2,UseSSE);
duke@435:   if( !supports_sse2() ) // Drop to 1 if no SSE2 support
duke@435:     UseSSE = MIN2((intx)1,UseSSE);
duke@435:   if( !supports_sse () ) // Drop to 0 if no SSE  support
duke@435:     UseSSE = 0;
duke@435: 
duke@435:   // On new cpus instructions which update whole XMM register should be used
duke@435:   // to prevent partial register stall due to dependencies on high half.
duke@435:   //
duke@435:   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
duke@435:   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
duke@435:   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
duke@435:   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
duke@435: 
duke@435:   if( is_amd() ) { // AMD cpus specific settings
duke@435:     if( FLAG_IS_DEFAULT(UseAddressNop) ) {
duke@435:       // Use it on all AMD cpus starting from Opteron (don't need
duke@435:       // a cpu check since only Opteron and new cpus support 64-bits mode).
duke@435:       UseAddressNop = true;
duke@435:     }
duke@435:     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
duke@435:       if( supports_sse4a() ) {
duke@435:         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
duke@435:       } else {
duke@435:         UseXmmLoadAndClearUpper = false;
duke@435:       }
duke@435:     }
duke@435:     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
duke@435:       if( supports_sse4a() ) {
duke@435:         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
duke@435:       } else {
duke@435:         UseXmmRegToRegMoveAll = false;
duke@435:       }
duke@435:     }
duke@435:   }
duke@435: 
duke@435:   if( is_intel() ) { // Intel cpus specific settings
duke@435:     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
duke@435:       UseStoreImmI16 = false; // don't use it on Intel cpus
duke@435:     }
duke@435:     if( FLAG_IS_DEFAULT(UseAddressNop) ) {
duke@435:       // Use it on all Intel cpus starting from PentiumPro
duke@435:       // (don't need a cpu check since only new cpus support 64-bits mode).
duke@435:       UseAddressNop = true;
duke@435:     }
duke@435:     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
duke@435:       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
duke@435:     }
duke@435:     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
duke@435:       if( supports_sse3() ) {
duke@435:         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
duke@435:       } else {
duke@435:         UseXmmRegToRegMoveAll = false;
duke@435:       }
duke@435:     }
duke@435:     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
duke@435: #ifdef COMPILER2
duke@435:       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
duke@435:         // For new Intel cpus do the next optimization:
duke@435:         // don't align the beginning of a loop if there are enough instructions
duke@435:         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
duke@435:         // in current fetch line (OptoLoopAlignment) or the padding
duke@435:         // is big (> MaxLoopPad).
duke@435:         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
duke@435:         // generated NOP instructions. 11 is the largest size of one
duke@435:         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
duke@435:         MaxLoopPad = 11;
duke@435:       }
duke@435: #endif // COMPILER2
duke@435:     }
duke@435:   }
duke@435: 
duke@435:   assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
duke@435:   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
duke@435: 
duke@435:   // set valid Prefetch instruction
duke@435:   if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
duke@435:   if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
duke@435:   if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
duke@435: 
duke@435:   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
duke@435:   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
duke@435:   if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
duke@435: 
duke@435:   // Allocation prefetch settings
duke@435:   intx cache_line_size = L1_data_cache_line_size();
duke@435:   if( cache_line_size > AllocatePrefetchStepSize )
duke@435:     AllocatePrefetchStepSize = cache_line_size;
duke@435:   if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
duke@435:     AllocatePrefetchLines = 3; // Optimistic value
duke@435:   assert(AllocatePrefetchLines > 0, "invalid value");
duke@435:   if( AllocatePrefetchLines < 1 ) // set valid value in product VM
duke@435:     AllocatePrefetchLines = 1; // Conservative value
duke@435: 
duke@435:   AllocatePrefetchDistance = allocate_prefetch_distance();
duke@435:   AllocatePrefetchStyle    = allocate_prefetch_style();
duke@435: 
duke@435:   if( AllocatePrefetchStyle == 2 && is_intel() &&
duke@435:       cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
duke@435:     AllocatePrefetchDistance = 384;
duke@435:   }
duke@435:   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
duke@435: 
duke@435:   // Prefetch settings
duke@435:   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
duke@435:   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
duke@435:   PrefetchFieldsAhead         = prefetch_fields_ahead();
duke@435: 
duke@435: #ifndef PRODUCT
duke@435:   if (PrintMiscellaneous && Verbose) {
duke@435:     tty->print_cr("Logical CPUs per package: %u",
duke@435:                   logical_processors_per_package());
duke@435:     tty->print_cr("UseSSE=%d",UseSSE);
duke@435:     tty->print("Allocation: ");
duke@435:     if (AllocatePrefetchStyle <= 0) {
duke@435:       tty->print_cr("no prefetching");
duke@435:     } else {
duke@435:       if (AllocatePrefetchInstr == 0) {
duke@435:         tty->print("PREFETCHNTA");
duke@435:       } else if (AllocatePrefetchInstr == 1) {
duke@435:         tty->print("PREFETCHT0");
duke@435:       } else if (AllocatePrefetchInstr == 2) {
duke@435:         tty->print("PREFETCHT2");
duke@435:       } else if (AllocatePrefetchInstr == 3) {
duke@435:         tty->print("PREFETCHW");
duke@435:       }
duke@435:       if (AllocatePrefetchLines > 1) {
duke@435:         tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
duke@435:       } else {
duke@435:         tty->print_cr(" %d, one line", AllocatePrefetchDistance);
duke@435:       }
duke@435:     }
duke@435:     if (PrefetchCopyIntervalInBytes > 0) {
duke@435:       tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
duke@435:     }
duke@435:     if (PrefetchScanIntervalInBytes > 0) {
duke@435:       tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
duke@435:     }
duke@435:     if (PrefetchFieldsAhead > 0) {
duke@435:       tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
duke@435:     }
duke@435:   }
duke@435: #endif // !PRODUCT
duke@435: }
duke@435: 
duke@435: void VM_Version::initialize() {
duke@435:   ResourceMark rm;
duke@435:   // Making this stub must be FIRST use of assembler
duke@435: 
duke@435:   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
duke@435:   if (stub_blob == NULL) {
duke@435:     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
duke@435:   }
duke@435:   CodeBuffer c(stub_blob->instructions_begin(),
duke@435:                stub_blob->instructions_size());
duke@435:   VM_Version_StubGenerator g(&c);
duke@435:   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
duke@435:                                    g.generate_getPsrInfo());
duke@435: 
duke@435:   get_processor_features();
duke@435: }