duke@435: /* duke@435: * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: # include "incls/_precompiled.incl" duke@435: # include "incls/_c1_LIRAssembler_sparc.cpp.incl" duke@435: duke@435: #define __ _masm-> duke@435: duke@435: duke@435: //------------------------------------------------------------ duke@435: duke@435: duke@435: bool LIR_Assembler::is_small_constant(LIR_Opr opr) { duke@435: if (opr->is_constant()) { duke@435: LIR_Const* constant = opr->as_constant_ptr(); duke@435: switch (constant->type()) { duke@435: case T_INT: { duke@435: jint value = constant->as_jint(); duke@435: return Assembler::is_simm13(value); duke@435: } duke@435: duke@435: default: duke@435: return false; duke@435: } duke@435: } duke@435: return false; duke@435: } duke@435: duke@435: duke@435: bool LIR_Assembler::is_single_instruction(LIR_Op* op) { duke@435: switch (op->code()) { duke@435: case lir_null_check: duke@435: return true; duke@435: duke@435: duke@435: case lir_add: duke@435: case lir_ushr: duke@435: case lir_shr: duke@435: case lir_shl: duke@435: // integer shifts and adds are always one instruction duke@435: return op->result_opr()->is_single_cpu(); duke@435: duke@435: duke@435: case lir_move: { duke@435: LIR_Op1* op1 = op->as_Op1(); duke@435: LIR_Opr src = op1->in_opr(); duke@435: LIR_Opr dst = op1->result_opr(); duke@435: duke@435: if (src == dst) { duke@435: NEEDS_CLEANUP; duke@435: // this works around a problem where moves with the same src and dst duke@435: // end up in the delay slot and then the assembler swallows the mov duke@435: // since it has no effect and then it complains because the delay slot duke@435: // is empty. returning false stops the optimizer from putting this in duke@435: // the delay slot duke@435: return false; duke@435: } duke@435: duke@435: // don't put moves involving oops into the delay slot since the VerifyOops code duke@435: // will make it much larger than a single instruction. duke@435: if (VerifyOops) { duke@435: return false; duke@435: } duke@435: duke@435: if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || duke@435: ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { duke@435: return false; duke@435: } duke@435: duke@435: if (dst->is_register()) { duke@435: if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { duke@435: return !PatchALot; duke@435: } else if (src->is_single_stack()) { duke@435: return true; duke@435: } duke@435: } duke@435: duke@435: if (src->is_register()) { duke@435: if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { duke@435: return !PatchALot; duke@435: } else if (dst->is_single_stack()) { duke@435: return true; duke@435: } duke@435: } duke@435: duke@435: if (dst->is_register() && duke@435: ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || duke@435: (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { duke@435: return true; duke@435: } duke@435: duke@435: return false; duke@435: } duke@435: duke@435: default: duke@435: return false; duke@435: } duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: duke@435: LIR_Opr LIR_Assembler::receiverOpr() { duke@435: return FrameMap::O0_oop_opr; duke@435: } duke@435: duke@435: duke@435: LIR_Opr LIR_Assembler::incomingReceiverOpr() { duke@435: return FrameMap::I0_oop_opr; duke@435: } duke@435: duke@435: duke@435: LIR_Opr LIR_Assembler::osrBufferPointer() { duke@435: return FrameMap::I0_opr; duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::initial_frame_size_in_bytes() { duke@435: return in_bytes(frame_map()->framesize_in_bytes()); duke@435: } duke@435: duke@435: duke@435: // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); duke@435: // we fetch the class of the receiver (O0) and compare it with the cached class. duke@435: // If they do not match we jump to slow case. duke@435: int LIR_Assembler::check_icache() { duke@435: int offset = __ offset(); duke@435: __ inline_cache_check(O0, G5_inline_cache_reg); duke@435: return offset; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::osr_entry() { duke@435: // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): duke@435: // duke@435: // 1. Create a new compiled activation. duke@435: // 2. Initialize local variables in the compiled activation. The expression stack must be empty duke@435: // at the osr_bci; it is not initialized. duke@435: // 3. Jump to the continuation address in compiled code to resume execution. duke@435: duke@435: // OSR entry point duke@435: offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); duke@435: BlockBegin* osr_entry = compilation()->hir()->osr_entry(); duke@435: ValueStack* entry_state = osr_entry->end()->state(); duke@435: int number_of_locks = entry_state->locks_size(); duke@435: duke@435: // Create a frame for the compiled activation. duke@435: __ build_frame(initial_frame_size_in_bytes()); duke@435: duke@435: // OSR buffer is duke@435: // duke@435: // locals[nlocals-1..0] duke@435: // monitors[number_of_locks-1..0] duke@435: // duke@435: // locals is a direct copy of the interpreter frame so in the osr buffer duke@435: // so first slot in the local array is the last local from the interpreter duke@435: // and last slot is local[0] (receiver) from the interpreter duke@435: // duke@435: // Similarly with locks. The first lock slot in the osr buffer is the nth lock duke@435: // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock duke@435: // in the interpreter frame (the method lock if a sync method) duke@435: duke@435: // Initialize monitors in the compiled activation. duke@435: // I0: pointer to osr buffer duke@435: // duke@435: // All other registers are dead at this point and the locals will be duke@435: // copied into place by code emitted in the IR. duke@435: duke@435: Register OSR_buf = osrBufferPointer()->as_register(); duke@435: { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); duke@435: int monitor_offset = BytesPerWord * method()->max_locals() + duke@435: (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); duke@435: for (int i = 0; i < number_of_locks; i++) { duke@435: int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); duke@435: #ifdef ASSERT duke@435: // verify the interpreter's monitor has a non-null object duke@435: { duke@435: Label L; duke@435: __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); duke@435: __ cmp(G0, O7); duke@435: __ br(Assembler::notEqual, false, Assembler::pt, L); duke@435: __ delayed()->nop(); duke@435: __ stop("locked object is NULL"); duke@435: __ bind(L); duke@435: } duke@435: #endif // ASSERT duke@435: // Copy the lock field into the compiled activation. duke@435: __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::lock_offset_in_bytes()), O7); duke@435: __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); duke@435: __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); duke@435: __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: // Optimized Library calls duke@435: // This is the fast version of java.lang.String.compare; it has not duke@435: // OSR-entry and therefore, we generate a slow version for OSR's duke@435: void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { duke@435: Register str0 = left->as_register(); duke@435: Register str1 = right->as_register(); duke@435: duke@435: Label Ldone; duke@435: duke@435: Register result = dst->as_register(); duke@435: { duke@435: // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 duke@435: // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 duke@435: // Also, get string0.count-string1.count in o7 and get the condition code set duke@435: // Note: some instructions have been hoisted for better instruction scheduling duke@435: duke@435: Register tmp0 = L0; duke@435: Register tmp1 = L1; duke@435: Register tmp2 = L2; duke@435: duke@435: int value_offset = java_lang_String:: value_offset_in_bytes(); // char array duke@435: int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position duke@435: int count_offset = java_lang_String:: count_offset_in_bytes(); duke@435: duke@435: __ ld_ptr(Address(str0, 0, value_offset), tmp0); duke@435: __ ld(Address(str0, 0, offset_offset), tmp2); duke@435: __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); duke@435: __ ld(Address(str0, 0, count_offset), str0); duke@435: __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); duke@435: duke@435: // str1 may be null duke@435: add_debug_info_for_null_check_here(info); duke@435: duke@435: __ ld_ptr(Address(str1, 0, value_offset), tmp1); duke@435: __ add(tmp0, tmp2, tmp0); duke@435: duke@435: __ ld(Address(str1, 0, offset_offset), tmp2); duke@435: __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); duke@435: __ ld(Address(str1, 0, count_offset), str1); duke@435: __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); duke@435: __ subcc(str0, str1, O7); duke@435: __ add(tmp1, tmp2, tmp1); duke@435: } duke@435: duke@435: { duke@435: // Compute the minimum of the string lengths, scale it and store it in limit duke@435: Register count0 = I0; duke@435: Register count1 = I1; duke@435: Register limit = L3; duke@435: duke@435: Label Lskip; duke@435: __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter duke@435: __ br(Assembler::greater, true, Assembler::pt, Lskip); duke@435: __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter duke@435: __ bind(Lskip); duke@435: duke@435: // If either string is empty (or both of them) the result is the difference in lengths duke@435: __ cmp(limit, 0); duke@435: __ br(Assembler::equal, true, Assembler::pn, Ldone); duke@435: __ delayed()->mov(O7, result); // result is difference in lengths duke@435: } duke@435: duke@435: { duke@435: // Neither string is empty duke@435: Label Lloop; duke@435: duke@435: Register base0 = L0; duke@435: Register base1 = L1; duke@435: Register chr0 = I0; duke@435: Register chr1 = I1; duke@435: Register limit = L3; duke@435: duke@435: // Shift base0 and base1 to the end of the arrays, negate limit duke@435: __ add(base0, limit, base0); duke@435: __ add(base1, limit, base1); duke@435: __ neg(limit); // limit = -min{string0.count, strin1.count} duke@435: duke@435: __ lduh(base0, limit, chr0); duke@435: __ bind(Lloop); duke@435: __ lduh(base1, limit, chr1); duke@435: __ subcc(chr0, chr1, chr0); duke@435: __ br(Assembler::notZero, false, Assembler::pn, Ldone); duke@435: assert(chr0 == result, "result must be pre-placed"); duke@435: __ delayed()->inccc(limit, sizeof(jchar)); duke@435: __ br(Assembler::notZero, true, Assembler::pt, Lloop); duke@435: __ delayed()->lduh(base0, limit, chr0); duke@435: } duke@435: duke@435: // If strings are equal up to min length, return the length difference. duke@435: __ mov(O7, result); duke@435: duke@435: // Otherwise, return the difference between the first mismatched chars. duke@435: __ bind(Ldone); duke@435: } duke@435: duke@435: duke@435: // -------------------------------------------------------------------------------------------- duke@435: duke@435: void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { duke@435: if (!GenerateSynchronizationCode) return; duke@435: duke@435: Register obj_reg = obj_opr->as_register(); duke@435: Register lock_reg = lock_opr->as_register(); duke@435: duke@435: Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); duke@435: Register reg = mon_addr.base(); duke@435: int offset = mon_addr.disp(); duke@435: // compute pointer to BasicLock duke@435: if (mon_addr.is_simm13()) { duke@435: __ add(reg, offset, lock_reg); duke@435: } duke@435: else { duke@435: __ set(offset, lock_reg); duke@435: __ add(reg, lock_reg, lock_reg); duke@435: } duke@435: // unlock object duke@435: MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); duke@435: // _slow_case_stubs->append(slow_case); duke@435: // temporary fix: must be created after exceptionhandler, therefore as call stub duke@435: _slow_case_stubs->append(slow_case); duke@435: if (UseFastLocking) { duke@435: // try inlined fast unlocking first, revert to slow locking if it fails duke@435: // note: lock_reg points to the displaced header since the displaced header offset is 0! duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); duke@435: } else { duke@435: // always do slow unlocking duke@435: // note: the slow unlocking code could be inlined here, however if we use duke@435: // slow unlocking, speed doesn't matter anyway and this solution is duke@435: // simpler and requires less duplicated code - additionally, the duke@435: // slow unlocking code is the same in either case which simplifies duke@435: // debugging duke@435: __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: // done duke@435: __ bind(*slow_case->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_exception_handler() { duke@435: // if the last instruction is a call (typically to do a throw which duke@435: // is coming at the end after block reordering) the return address duke@435: // must still point into the code area in order to avoid assertion duke@435: // failures when searching for the corresponding bci => add a nop duke@435: // (was bug 5/14/1999 - gri) duke@435: __ nop(); duke@435: duke@435: // generate code for exception handler duke@435: ciMethod* method = compilation()->method(); duke@435: duke@435: address handler_base = __ start_a_stub(exception_handler_size); duke@435: duke@435: if (handler_base == NULL) { duke@435: // not enough space left for the handler duke@435: bailout("exception handler overflow"); duke@435: return; duke@435: } duke@435: #ifdef ASSERT duke@435: int offset = code_offset(); duke@435: #endif // ASSERT duke@435: compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); duke@435: duke@435: duke@435: if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { duke@435: __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: debug_only(__ stop("should have gone to the caller");) duke@435: assert(code_offset() - offset <= exception_handler_size, "overflow"); duke@435: duke@435: __ end_a_stub(); duke@435: } duke@435: duke@435: void LIR_Assembler::emit_deopt_handler() { duke@435: // if the last instruction is a call (typically to do a throw which duke@435: // is coming at the end after block reordering) the return address duke@435: // must still point into the code area in order to avoid assertion duke@435: // failures when searching for the corresponding bci => add a nop duke@435: // (was bug 5/14/1999 - gri) duke@435: __ nop(); duke@435: duke@435: // generate code for deopt handler duke@435: ciMethod* method = compilation()->method(); duke@435: address handler_base = __ start_a_stub(deopt_handler_size); duke@435: if (handler_base == NULL) { duke@435: // not enough space left for the handler duke@435: bailout("deopt handler overflow"); duke@435: return; duke@435: } duke@435: #ifdef ASSERT duke@435: int offset = code_offset(); duke@435: #endif // ASSERT duke@435: compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); duke@435: duke@435: Address deopt_blob(G3_scratch, SharedRuntime::deopt_blob()->unpack()); duke@435: duke@435: __ JUMP(deopt_blob, 0); // sethi;jmp duke@435: __ delayed()->nop(); duke@435: duke@435: assert(code_offset() - offset <= deopt_handler_size, "overflow"); duke@435: duke@435: debug_only(__ stop("should have gone to the caller");) duke@435: duke@435: __ end_a_stub(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::jobject2reg(jobject o, Register reg) { duke@435: if (o == NULL) { duke@435: __ set(NULL_WORD, reg); duke@435: } else { duke@435: int oop_index = __ oop_recorder()->find_index(o); duke@435: RelocationHolder rspec = oop_Relocation::spec(oop_index); duke@435: __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { duke@435: // Allocate a new index in oop table to hold the oop once it's been patched duke@435: int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); duke@435: PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); duke@435: duke@435: Address addr = Address(reg, address(NULL), oop_Relocation::spec(oop_index)); duke@435: assert(addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); duke@435: // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the duke@435: // NULL will be dynamically patched later and the patched value may be large. We must duke@435: // therefore generate the sethi/add as a placeholders duke@435: __ sethi(addr, true); duke@435: __ add(addr, reg, 0); duke@435: duke@435: patching_epilog(patch, lir_patch_normal, reg, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_op3(LIR_Op3* op) { duke@435: Register Rdividend = op->in_opr1()->as_register(); duke@435: Register Rdivisor = noreg; duke@435: Register Rscratch = op->in_opr3()->as_register(); duke@435: Register Rresult = op->result_opr()->as_register(); duke@435: int divisor = -1; duke@435: duke@435: if (op->in_opr2()->is_register()) { duke@435: Rdivisor = op->in_opr2()->as_register(); duke@435: } else { duke@435: divisor = op->in_opr2()->as_constant_ptr()->as_jint(); duke@435: assert(Assembler::is_simm13(divisor), "can only handle simm13"); duke@435: } duke@435: duke@435: assert(Rdividend != Rscratch, ""); duke@435: assert(Rdivisor != Rscratch, ""); duke@435: assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); duke@435: duke@435: if (Rdivisor == noreg && is_power_of_2(divisor)) { duke@435: // convert division by a power of two into some shifts and logical operations duke@435: if (op->code() == lir_idiv) { duke@435: if (divisor == 2) { duke@435: __ srl(Rdividend, 31, Rscratch); duke@435: } else { duke@435: __ sra(Rdividend, 31, Rscratch); duke@435: __ and3(Rscratch, divisor - 1, Rscratch); duke@435: } duke@435: __ add(Rdividend, Rscratch, Rscratch); duke@435: __ sra(Rscratch, log2_intptr(divisor), Rresult); duke@435: return; duke@435: } else { duke@435: if (divisor == 2) { duke@435: __ srl(Rdividend, 31, Rscratch); duke@435: } else { duke@435: __ sra(Rdividend, 31, Rscratch); duke@435: __ and3(Rscratch, divisor - 1,Rscratch); duke@435: } duke@435: __ add(Rdividend, Rscratch, Rscratch); duke@435: __ andn(Rscratch, divisor - 1,Rscratch); duke@435: __ sub(Rdividend, Rscratch, Rresult); duke@435: return; duke@435: } duke@435: } duke@435: duke@435: __ sra(Rdividend, 31, Rscratch); duke@435: __ wry(Rscratch); duke@435: if (!VM_Version::v9_instructions_work()) { duke@435: // v9 doesn't require these nops duke@435: __ nop(); duke@435: __ nop(); duke@435: __ nop(); duke@435: __ nop(); duke@435: } duke@435: duke@435: add_debug_info_for_div0_here(op->info()); duke@435: duke@435: if (Rdivisor != noreg) { duke@435: __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); duke@435: } else { duke@435: assert(Assembler::is_simm13(divisor), "can only handle simm13"); duke@435: __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); duke@435: } duke@435: duke@435: Label skip; duke@435: __ br(Assembler::overflowSet, true, Assembler::pn, skip); duke@435: __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); duke@435: __ bind(skip); duke@435: duke@435: if (op->code() == lir_irem) { duke@435: if (Rdivisor != noreg) { duke@435: __ smul(Rscratch, Rdivisor, Rscratch); duke@435: } else { duke@435: __ smul(Rscratch, divisor, Rscratch); duke@435: } duke@435: __ sub(Rdividend, Rscratch, Rresult); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { duke@435: #ifdef ASSERT duke@435: assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); duke@435: if (op->block() != NULL) _branch_target_blocks.append(op->block()); duke@435: if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); duke@435: #endif duke@435: assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); duke@435: duke@435: if (op->cond() == lir_cond_always) { duke@435: __ br(Assembler::always, false, Assembler::pt, *(op->label())); duke@435: } else if (op->code() == lir_cond_float_branch) { duke@435: assert(op->ublock() != NULL, "must have unordered successor"); duke@435: bool is_unordered = (op->ublock() == op->block()); duke@435: Assembler::Condition acond; duke@435: switch (op->cond()) { duke@435: case lir_cond_equal: acond = Assembler::f_equal; break; duke@435: case lir_cond_notEqual: acond = Assembler::f_notEqual; break; duke@435: case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; duke@435: case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; duke@435: case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; duke@435: case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; duke@435: default : ShouldNotReachHere(); duke@435: }; duke@435: duke@435: if (!VM_Version::v9_instructions_work()) { duke@435: __ nop(); duke@435: } duke@435: __ fb( acond, false, Assembler::pn, *(op->label())); duke@435: } else { duke@435: assert (op->code() == lir_branch, "just checking"); duke@435: duke@435: Assembler::Condition acond; duke@435: switch (op->cond()) { duke@435: case lir_cond_equal: acond = Assembler::equal; break; duke@435: case lir_cond_notEqual: acond = Assembler::notEqual; break; duke@435: case lir_cond_less: acond = Assembler::less; break; duke@435: case lir_cond_lessEqual: acond = Assembler::lessEqual; break; duke@435: case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; duke@435: case lir_cond_greater: acond = Assembler::greater; break; duke@435: case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; duke@435: case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; duke@435: default: ShouldNotReachHere(); duke@435: }; duke@435: duke@435: // sparc has different condition codes for testing 32-bit duke@435: // vs. 64-bit values. We could always test xcc is we could duke@435: // guarantee that 32-bit loads always sign extended but that isn't duke@435: // true and since sign extension isn't free, it would impose a duke@435: // slight cost. duke@435: #ifdef _LP64 duke@435: if (op->type() == T_INT) { duke@435: __ br(acond, false, Assembler::pn, *(op->label())); duke@435: } else duke@435: #endif duke@435: __ brx(acond, false, Assembler::pn, *(op->label())); duke@435: } duke@435: // The peephole pass fills the delay slot duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { duke@435: Bytecodes::Code code = op->bytecode(); duke@435: LIR_Opr dst = op->result_opr(); duke@435: duke@435: switch(code) { duke@435: case Bytecodes::_i2l: { duke@435: Register rlo = dst->as_register_lo(); duke@435: Register rhi = dst->as_register_hi(); duke@435: Register rval = op->in_opr()->as_register(); duke@435: #ifdef _LP64 duke@435: __ sra(rval, 0, rlo); duke@435: #else duke@435: __ mov(rval, rlo); duke@435: __ sra(rval, BitsPerInt-1, rhi); duke@435: #endif duke@435: break; duke@435: } duke@435: case Bytecodes::_i2d: duke@435: case Bytecodes::_i2f: { duke@435: bool is_double = (code == Bytecodes::_i2d); duke@435: FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); duke@435: FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; duke@435: FloatRegister rsrc = op->in_opr()->as_float_reg(); duke@435: if (rsrc != rdst) { duke@435: __ fmov(FloatRegisterImpl::S, rsrc, rdst); duke@435: } duke@435: __ fitof(w, rdst, rdst); duke@435: break; duke@435: } duke@435: case Bytecodes::_f2i:{ duke@435: FloatRegister rsrc = op->in_opr()->as_float_reg(); duke@435: Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); duke@435: Label L; duke@435: // result must be 0 if value is NaN; test by comparing value to itself duke@435: __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); duke@435: if (!VM_Version::v9_instructions_work()) { duke@435: __ nop(); duke@435: } duke@435: __ fb(Assembler::f_unordered, true, Assembler::pn, L); duke@435: __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN duke@435: __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); duke@435: // move integer result from float register to int register duke@435: __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); duke@435: __ bind (L); duke@435: break; duke@435: } duke@435: case Bytecodes::_l2i: { duke@435: Register rlo = op->in_opr()->as_register_lo(); duke@435: Register rhi = op->in_opr()->as_register_hi(); duke@435: Register rdst = dst->as_register(); duke@435: #ifdef _LP64 duke@435: __ sra(rlo, 0, rdst); duke@435: #else duke@435: __ mov(rlo, rdst); duke@435: #endif duke@435: break; duke@435: } duke@435: case Bytecodes::_d2f: duke@435: case Bytecodes::_f2d: { duke@435: bool is_double = (code == Bytecodes::_f2d); duke@435: assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); duke@435: LIR_Opr val = op->in_opr(); duke@435: FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); duke@435: FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); duke@435: FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; duke@435: FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; duke@435: __ ftof(vw, dw, rval, rdst); duke@435: break; duke@435: } duke@435: case Bytecodes::_i2s: duke@435: case Bytecodes::_i2b: { duke@435: Register rval = op->in_opr()->as_register(); duke@435: Register rdst = dst->as_register(); duke@435: int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); duke@435: __ sll (rval, shift, rdst); duke@435: __ sra (rdst, shift, rdst); duke@435: break; duke@435: } duke@435: case Bytecodes::_i2c: { duke@435: Register rval = op->in_opr()->as_register(); duke@435: Register rdst = dst->as_register(); duke@435: int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; duke@435: __ sll (rval, shift, rdst); duke@435: __ srl (rdst, shift, rdst); duke@435: break; duke@435: } duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::align_call(LIR_Code) { duke@435: // do nothing since all instructions are word aligned on sparc duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { duke@435: __ call(entry, rtype); duke@435: // the peephole pass fills the delay slot duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { duke@435: RelocationHolder rspec = virtual_call_Relocation::spec(pc()); duke@435: __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); duke@435: __ relocate(rspec); duke@435: __ call(entry, relocInfo::none); duke@435: // the peephole pass fills the delay slot duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { duke@435: add_debug_info_for_null_check_here(info); duke@435: __ ld_ptr(Address(O0, 0, oopDesc::klass_offset_in_bytes()), G3_scratch); duke@435: if (__ is_simm13(vtable_offset) ) { duke@435: __ ld_ptr(G3_scratch, vtable_offset, G5_method); duke@435: } else { duke@435: // This will generate 2 instructions duke@435: __ set(vtable_offset, G5_method); duke@435: // ld_ptr, set_hi, set duke@435: __ ld_ptr(G3_scratch, G5_method, G5_method); duke@435: } duke@435: __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); duke@435: __ callr(G3_scratch, G0); duke@435: // the peephole pass fills the delay slot duke@435: } duke@435: duke@435: duke@435: // load with 32-bit displacement duke@435: int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { duke@435: int load_offset = code_offset(); duke@435: if (Assembler::is_simm13(disp)) { duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: switch(ld_type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ ldsb(s, disp, d); break; duke@435: case T_CHAR : __ lduh(s, disp, d); break; duke@435: case T_SHORT : __ ldsh(s, disp, d); break; duke@435: case T_INT : __ ld(s, disp, d); break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ ld_ptr(s, disp, d); break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: __ sethi(disp & ~0x3ff, O7, true); duke@435: __ add(O7, disp & 0x3ff, O7); duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: load_offset = code_offset(); duke@435: switch(ld_type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ ldsb(s, O7, d); break; duke@435: case T_CHAR : __ lduh(s, O7, d); break; duke@435: case T_SHORT : __ ldsh(s, O7, d); break; duke@435: case T_INT : __ ld(s, O7, d); break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ ld_ptr(s, O7, d); break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } duke@435: if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); duke@435: return load_offset; duke@435: } duke@435: duke@435: duke@435: // store with 32-bit displacement duke@435: void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { duke@435: if (Assembler::is_simm13(offset)) { duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: switch (type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ stb(value, base, offset); break; duke@435: case T_CHAR : __ sth(value, base, offset); break; duke@435: case T_SHORT : __ sth(value, base, offset); break; duke@435: case T_INT : __ stw(value, base, offset); break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ st_ptr(value, base, offset); break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: __ sethi(offset & ~0x3ff, O7, true); duke@435: __ add(O7, offset & 0x3ff, O7); duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: switch (type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ stb(value, base, O7); break; duke@435: case T_CHAR : __ sth(value, base, O7); break; duke@435: case T_SHORT : __ sth(value, base, O7); break; duke@435: case T_INT : __ stw(value, base, O7); break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : //fall through duke@435: case T_OBJECT: __ st_ptr(value, base, O7); break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } duke@435: // Note: Do the store before verification as the code might be patched! duke@435: if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); duke@435: } duke@435: duke@435: duke@435: // load float with 32-bit displacement duke@435: void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { duke@435: FloatRegisterImpl::Width w; duke@435: switch(ld_type) { duke@435: case T_FLOAT : w = FloatRegisterImpl::S; break; duke@435: case T_DOUBLE: w = FloatRegisterImpl::D; break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (Assembler::is_simm13(disp)) { duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { duke@435: __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); duke@435: __ ldf(FloatRegisterImpl::S, s, disp , d); duke@435: } else { duke@435: __ ldf(w, s, disp, d); duke@435: } duke@435: } else { duke@435: __ sethi(disp & ~0x3ff, O7, true); duke@435: __ add(O7, disp & 0x3ff, O7); duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: __ ldf(w, s, O7, d); duke@435: } duke@435: } duke@435: duke@435: duke@435: // store float with 32-bit displacement duke@435: void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { duke@435: FloatRegisterImpl::Width w; duke@435: switch(type) { duke@435: case T_FLOAT : w = FloatRegisterImpl::S; break; duke@435: case T_DOUBLE: w = FloatRegisterImpl::D; break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (Assembler::is_simm13(offset)) { duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { duke@435: __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); duke@435: __ stf(FloatRegisterImpl::S, value , base, offset); duke@435: } else { duke@435: __ stf(w, value, base, offset); duke@435: } duke@435: } else { duke@435: __ sethi(offset & ~0x3ff, O7, true); duke@435: __ add(O7, offset & 0x3ff, O7); duke@435: if (info != NULL) add_debug_info_for_null_check_here(info); duke@435: __ stf(w, value, O7, base); duke@435: } duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { duke@435: int store_offset; duke@435: if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { duke@435: assert(!unaligned, "can't handle this"); duke@435: // for offsets larger than a simm13 we setup the offset in O7 duke@435: __ sethi(offset & ~0x3ff, O7, true); duke@435: __ add(O7, offset & 0x3ff, O7); duke@435: store_offset = store(from_reg, base, O7, type); duke@435: } else { duke@435: if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); duke@435: store_offset = code_offset(); duke@435: switch (type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; duke@435: case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; duke@435: case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; duke@435: case T_INT : __ stw(from_reg->as_register(), base, offset); break; duke@435: case T_LONG : duke@435: #ifdef _LP64 duke@435: if (unaligned || PatchALot) { duke@435: __ srax(from_reg->as_register_lo(), 32, O7); duke@435: __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); duke@435: __ stw(O7, base, offset + hi_word_offset_in_bytes); duke@435: } else { duke@435: __ stx(from_reg->as_register_lo(), base, offset); duke@435: } duke@435: #else duke@435: assert(Assembler::is_simm13(offset + 4), "must be"); duke@435: __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); duke@435: __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); duke@435: #endif duke@435: break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; duke@435: case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; duke@435: case T_DOUBLE: duke@435: { duke@435: FloatRegister reg = from_reg->as_double_reg(); duke@435: // split unaligned stores duke@435: if (unaligned || PatchALot) { duke@435: assert(Assembler::is_simm13(offset + 4), "must be"); duke@435: __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); duke@435: __ stf(FloatRegisterImpl::S, reg, base, offset); duke@435: } else { duke@435: __ stf(FloatRegisterImpl::D, reg, base, offset); duke@435: } duke@435: break; duke@435: } duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } duke@435: return store_offset; duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { duke@435: if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); duke@435: int store_offset = code_offset(); duke@435: switch (type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; duke@435: case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; duke@435: case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; duke@435: case T_INT : __ stw(from_reg->as_register(), base, disp); break; duke@435: case T_LONG : duke@435: #ifdef _LP64 duke@435: __ stx(from_reg->as_register_lo(), base, disp); duke@435: #else duke@435: assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); duke@435: __ std(from_reg->as_register_hi(), base, disp); duke@435: #endif duke@435: break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; duke@435: case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; duke@435: case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: return store_offset; duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { duke@435: int load_offset; duke@435: if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { duke@435: assert(base != O7, "destroying register"); duke@435: assert(!unaligned, "can't handle this"); duke@435: // for offsets larger than a simm13 we setup the offset in O7 duke@435: __ sethi(offset & ~0x3ff, O7, true); duke@435: __ add(O7, offset & 0x3ff, O7); duke@435: load_offset = load(base, O7, to_reg, type); duke@435: } else { duke@435: load_offset = code_offset(); duke@435: switch(type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; duke@435: case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; duke@435: case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; duke@435: case T_INT : __ ld(base, offset, to_reg->as_register()); break; duke@435: case T_LONG : duke@435: if (!unaligned) { duke@435: #ifdef _LP64 duke@435: __ ldx(base, offset, to_reg->as_register_lo()); duke@435: #else duke@435: assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), duke@435: "must be sequential"); duke@435: __ ldd(base, offset, to_reg->as_register_hi()); duke@435: #endif duke@435: } else { duke@435: #ifdef _LP64 duke@435: assert(base != to_reg->as_register_lo(), "can't handle this"); duke@435: __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); duke@435: __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); duke@435: __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); duke@435: #else duke@435: if (base == to_reg->as_register_lo()) { duke@435: __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); duke@435: __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); duke@435: } else { duke@435: __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); duke@435: __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); duke@435: } duke@435: #endif duke@435: } duke@435: break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; duke@435: case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; duke@435: case T_DOUBLE: duke@435: { duke@435: FloatRegister reg = to_reg->as_double_reg(); duke@435: // split unaligned loads duke@435: if (unaligned || PatchALot) { duke@435: __ ldf(FloatRegisterImpl::S, base, offset + BytesPerWord, reg->successor()); duke@435: __ ldf(FloatRegisterImpl::S, base, offset, reg); duke@435: } else { duke@435: __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); duke@435: } duke@435: break; duke@435: } duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); duke@435: } duke@435: return load_offset; duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { duke@435: int load_offset = code_offset(); duke@435: switch(type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; duke@435: case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; duke@435: case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; duke@435: case T_INT : __ ld(base, disp, to_reg->as_register()); break; duke@435: case T_ADDRESS:// fall through duke@435: case T_ARRAY : // fall through duke@435: case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; duke@435: case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; duke@435: case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; duke@435: case T_LONG : duke@435: #ifdef _LP64 duke@435: __ ldx(base, disp, to_reg->as_register_lo()); duke@435: #else duke@435: assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), duke@435: "must be sequential"); duke@435: __ ldd(base, disp, to_reg->as_register_hi()); duke@435: #endif duke@435: break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); duke@435: return load_offset; duke@435: } duke@435: duke@435: duke@435: // load/store with an Address duke@435: void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { duke@435: load(a.base(), a.disp() + offset, d, ld_type, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { duke@435: store(value, dest.base(), dest.disp() + offset, type, info); duke@435: } duke@435: duke@435: duke@435: // loadf/storef with an Address duke@435: void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { duke@435: load(a.base(), a.disp() + offset, d, ld_type, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { duke@435: store(value, dest.base(), dest.disp() + offset, type, info); duke@435: } duke@435: duke@435: duke@435: // load/store with an Address duke@435: void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { duke@435: load(as_Address(a), d, ld_type, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { duke@435: store(value, as_Address(dest), type, info); duke@435: } duke@435: duke@435: duke@435: // loadf/storef with an Address duke@435: void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { duke@435: load(as_Address(a), d, ld_type, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { duke@435: store(value, as_Address(dest), type, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: switch (c->type()) { duke@435: case T_INT: duke@435: case T_FLOAT: { duke@435: Register src_reg = O7; duke@435: int value = c->as_jint_bits(); duke@435: if (value == 0) { duke@435: src_reg = G0; duke@435: } else { duke@435: __ set(value, O7); duke@435: } duke@435: Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: __ stw(src_reg, addr.base(), addr.disp()); duke@435: break; duke@435: } duke@435: case T_OBJECT: { duke@435: Register src_reg = O7; duke@435: jobject2reg(c->as_jobject(), src_reg); duke@435: Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: __ st_ptr(src_reg, addr.base(), addr.disp()); duke@435: break; duke@435: } duke@435: case T_LONG: duke@435: case T_DOUBLE: { duke@435: Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); duke@435: duke@435: Register tmp = O7; duke@435: int value_lo = c->as_jint_lo_bits(); duke@435: if (value_lo == 0) { duke@435: tmp = G0; duke@435: } else { duke@435: __ set(value_lo, O7); duke@435: } duke@435: __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); duke@435: int value_hi = c->as_jint_hi_bits(); duke@435: if (value_hi == 0) { duke@435: tmp = G0; duke@435: } else { duke@435: __ set(value_hi, O7); duke@435: } duke@435: __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); duke@435: break; duke@435: } duke@435: default: duke@435: Unimplemented(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: LIR_Address* addr = dest->as_address_ptr(); duke@435: Register base = addr->base()->as_pointer_register(); duke@435: duke@435: if (info != NULL) { duke@435: add_debug_info_for_null_check_here(info); duke@435: } duke@435: switch (c->type()) { duke@435: case T_INT: duke@435: case T_FLOAT: { duke@435: LIR_Opr tmp = FrameMap::O7_opr; duke@435: int value = c->as_jint_bits(); duke@435: if (value == 0) { duke@435: tmp = FrameMap::G0_opr; duke@435: } else if (Assembler::is_simm13(value)) { duke@435: __ set(value, O7); duke@435: } duke@435: if (addr->index()->is_valid()) { duke@435: assert(addr->disp() == 0, "must be zero"); duke@435: store(tmp, base, addr->index()->as_pointer_register(), type); duke@435: } else { duke@435: assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); duke@435: store(tmp, base, addr->disp(), type); duke@435: } duke@435: break; duke@435: } duke@435: case T_LONG: duke@435: case T_DOUBLE: { duke@435: assert(!addr->index()->is_valid(), "can't handle reg reg address here"); duke@435: assert(Assembler::is_simm13(addr->disp()) && duke@435: Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); duke@435: duke@435: Register tmp = O7; duke@435: int value_lo = c->as_jint_lo_bits(); duke@435: if (value_lo == 0) { duke@435: tmp = G0; duke@435: } else { duke@435: __ set(value_lo, O7); duke@435: } duke@435: store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); duke@435: int value_hi = c->as_jint_hi_bits(); duke@435: if (value_hi == 0) { duke@435: tmp = G0; duke@435: } else { duke@435: __ set(value_hi, O7); duke@435: } duke@435: store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); duke@435: break; duke@435: } duke@435: case T_OBJECT: { duke@435: jobject obj = c->as_jobject(); duke@435: LIR_Opr tmp; duke@435: if (obj == NULL) { duke@435: tmp = FrameMap::G0_opr; duke@435: } else { duke@435: tmp = FrameMap::O7_opr; duke@435: jobject2reg(c->as_jobject(), O7); duke@435: } duke@435: // handle either reg+reg or reg+disp address duke@435: if (addr->index()->is_valid()) { duke@435: assert(addr->disp() == 0, "must be zero"); duke@435: store(tmp, base, addr->index()->as_pointer_register(), type); duke@435: } else { duke@435: assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); duke@435: store(tmp, base, addr->disp(), type); duke@435: } duke@435: duke@435: break; duke@435: } duke@435: default: duke@435: Unimplemented(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: LIR_Opr to_reg = dest; duke@435: duke@435: switch (c->type()) { duke@435: case T_INT: duke@435: { duke@435: jint con = c->as_jint(); duke@435: if (to_reg->is_single_cpu()) { duke@435: assert(patch_code == lir_patch_none, "no patching handled here"); duke@435: __ set(con, to_reg->as_register()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: assert(to_reg->is_single_fpu(), "wrong register kind"); duke@435: duke@435: __ set(con, O7); duke@435: Address temp_slot(SP, 0, (frame::register_save_words * wordSize) + STACK_BIAS); duke@435: __ st(O7, temp_slot); duke@435: __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: case T_LONG: duke@435: { duke@435: jlong con = c->as_jlong(); duke@435: duke@435: if (to_reg->is_double_cpu()) { duke@435: #ifdef _LP64 duke@435: __ set(con, to_reg->as_register_lo()); duke@435: #else duke@435: __ set(low(con), to_reg->as_register_lo()); duke@435: __ set(high(con), to_reg->as_register_hi()); duke@435: #endif duke@435: #ifdef _LP64 duke@435: } else if (to_reg->is_single_cpu()) { duke@435: __ set(con, to_reg->as_register()); duke@435: #endif duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: assert(to_reg->is_double_fpu(), "wrong register kind"); duke@435: Address temp_slot_lo(SP, 0, ((frame::register_save_words ) * wordSize) + STACK_BIAS); duke@435: Address temp_slot_hi(SP, 0, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); duke@435: __ set(low(con), O7); duke@435: __ st(O7, temp_slot_lo); duke@435: __ set(high(con), O7); duke@435: __ st(O7, temp_slot_hi); duke@435: __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: case T_OBJECT: duke@435: { duke@435: if (patch_code == lir_patch_none) { duke@435: jobject2reg(c->as_jobject(), to_reg->as_register()); duke@435: } else { duke@435: jobject2reg_with_patching(to_reg->as_register(), info); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: case T_FLOAT: duke@435: { duke@435: address const_addr = __ float_constant(c->as_jfloat()); duke@435: if (const_addr == NULL) { duke@435: bailout("const section overflow"); duke@435: break; duke@435: } duke@435: RelocationHolder rspec = internal_word_Relocation::spec(const_addr); duke@435: if (to_reg->is_single_fpu()) { duke@435: __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); duke@435: __ relocate(rspec); duke@435: duke@435: int offset = (intx)const_addr & 0x3ff; duke@435: __ ldf (FloatRegisterImpl::S, O7, offset, to_reg->as_float_reg()); duke@435: duke@435: } else { duke@435: assert(to_reg->is_single_cpu(), "Must be a cpu register."); duke@435: duke@435: __ set((intx)const_addr, O7, rspec); duke@435: load(O7, 0, to_reg->as_register(), T_INT); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: case T_DOUBLE: duke@435: { duke@435: address const_addr = __ double_constant(c->as_jdouble()); duke@435: if (const_addr == NULL) { duke@435: bailout("const section overflow"); duke@435: break; duke@435: } duke@435: RelocationHolder rspec = internal_word_Relocation::spec(const_addr); duke@435: duke@435: if (to_reg->is_double_fpu()) { duke@435: __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); duke@435: int offset = (intx)const_addr & 0x3ff; duke@435: __ relocate(rspec); duke@435: __ ldf (FloatRegisterImpl::D, O7, offset, to_reg->as_double_reg()); duke@435: } else { duke@435: assert(to_reg->is_double_cpu(), "Must be a long register."); duke@435: #ifdef _LP64 duke@435: __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); duke@435: #else duke@435: __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); duke@435: __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); duke@435: #endif duke@435: } duke@435: duke@435: } duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: Address LIR_Assembler::as_Address(LIR_Address* addr) { duke@435: Register reg = addr->base()->as_register(); duke@435: return Address(reg, 0, addr->disp()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { duke@435: switch (type) { duke@435: case T_INT: duke@435: case T_FLOAT: { duke@435: Register tmp = O7; duke@435: Address from = frame_map()->address_for_slot(src->single_stack_ix()); duke@435: Address to = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: __ lduw(from.base(), from.disp(), tmp); duke@435: __ stw(tmp, to.base(), to.disp()); duke@435: break; duke@435: } duke@435: case T_OBJECT: { duke@435: Register tmp = O7; duke@435: Address from = frame_map()->address_for_slot(src->single_stack_ix()); duke@435: Address to = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: __ ld_ptr(from.base(), from.disp(), tmp); duke@435: __ st_ptr(tmp, to.base(), to.disp()); duke@435: break; duke@435: } duke@435: case T_LONG: duke@435: case T_DOUBLE: { duke@435: Register tmp = O7; duke@435: Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); duke@435: Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); duke@435: __ lduw(from.base(), from.disp(), tmp); duke@435: __ stw(tmp, to.base(), to.disp()); duke@435: __ lduw(from.base(), from.disp() + 4, tmp); duke@435: __ stw(tmp, to.base(), to.disp() + 4); duke@435: break; duke@435: } duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { duke@435: Address base = as_Address(addr); duke@435: return Address(base.base(), 0, base.disp() + hi_word_offset_in_bytes); duke@435: } duke@435: duke@435: duke@435: Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { duke@435: Address base = as_Address(addr); duke@435: return Address(base.base(), 0, base.disp() + lo_word_offset_in_bytes); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, duke@435: LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { duke@435: duke@435: LIR_Address* addr = src_opr->as_address_ptr(); duke@435: LIR_Opr to_reg = dest; duke@435: duke@435: Register src = addr->base()->as_pointer_register(); duke@435: Register disp_reg = noreg; duke@435: int disp_value = addr->disp(); duke@435: bool needs_patching = (patch_code != lir_patch_none); duke@435: duke@435: if (addr->base()->type() == T_OBJECT) { duke@435: __ verify_oop(src); duke@435: } duke@435: duke@435: PatchingStub* patch = NULL; duke@435: if (needs_patching) { duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: assert(!to_reg->is_double_cpu() || duke@435: patch_code == lir_patch_none || duke@435: patch_code == lir_patch_normal, "patching doesn't match register"); duke@435: } duke@435: duke@435: if (addr->index()->is_illegal()) { duke@435: if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { duke@435: if (needs_patching) { duke@435: __ sethi(0, O7, true); duke@435: __ add(O7, 0, O7); duke@435: } else { duke@435: __ set(disp_value, O7); duke@435: } duke@435: disp_reg = O7; duke@435: } duke@435: } else if (unaligned || PatchALot) { duke@435: __ add(src, addr->index()->as_register(), O7); duke@435: src = O7; duke@435: } else { duke@435: disp_reg = addr->index()->as_pointer_register(); duke@435: assert(disp_value == 0, "can't handle 3 operand addresses"); duke@435: } duke@435: duke@435: // remember the offset of the load. The patching_epilog must be done duke@435: // before the call to add_debug_info, otherwise the PcDescs don't get duke@435: // entered in increasing order. duke@435: int offset = code_offset(); duke@435: duke@435: assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); duke@435: if (disp_reg == noreg) { duke@435: offset = load(src, disp_value, to_reg, type, unaligned); duke@435: } else { duke@435: assert(!unaligned, "can't handle this"); duke@435: offset = load(src, disp_reg, to_reg, type); duke@435: } duke@435: duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, patch_code, src, info); duke@435: } duke@435: duke@435: if (info != NULL) add_debug_info_for_null_check(offset, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::prefetchr(LIR_Opr src) { duke@435: LIR_Address* addr = src->as_address_ptr(); duke@435: Address from_addr = as_Address(addr); duke@435: duke@435: if (VM_Version::has_v9()) { duke@435: __ prefetch(from_addr, Assembler::severalReads); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::prefetchw(LIR_Opr src) { duke@435: LIR_Address* addr = src->as_address_ptr(); duke@435: Address from_addr = as_Address(addr); duke@435: duke@435: if (VM_Version::has_v9()) { duke@435: __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { duke@435: Address addr; duke@435: if (src->is_single_word()) { duke@435: addr = frame_map()->address_for_slot(src->single_stack_ix()); duke@435: } else if (src->is_double_word()) { duke@435: addr = frame_map()->address_for_double_slot(src->double_stack_ix()); duke@435: } duke@435: duke@435: bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; duke@435: load(addr.base(), addr.disp(), dest, dest->type(), unaligned); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { duke@435: Address addr; duke@435: if (dest->is_single_word()) { duke@435: addr = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: } else if (dest->is_double_word()) { duke@435: addr = frame_map()->address_for_slot(dest->double_stack_ix()); duke@435: } duke@435: bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; duke@435: store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { duke@435: if (from_reg->is_float_kind() && to_reg->is_float_kind()) { duke@435: if (from_reg->is_double_fpu()) { duke@435: // double to double moves duke@435: assert(to_reg->is_double_fpu(), "should match"); duke@435: __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); duke@435: } else { duke@435: // float to float moves duke@435: assert(to_reg->is_single_fpu(), "should match"); duke@435: __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); duke@435: } duke@435: } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { duke@435: if (from_reg->is_double_cpu()) { duke@435: #ifdef _LP64 duke@435: __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); duke@435: #else duke@435: assert(to_reg->is_double_cpu() && duke@435: from_reg->as_register_hi() != to_reg->as_register_lo() && duke@435: from_reg->as_register_lo() != to_reg->as_register_hi(), duke@435: "should both be long and not overlap"); duke@435: // long to long moves duke@435: __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); duke@435: __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); duke@435: #endif duke@435: #ifdef _LP64 duke@435: } else if (to_reg->is_double_cpu()) { duke@435: // int to int moves duke@435: __ mov(from_reg->as_register(), to_reg->as_register_lo()); duke@435: #endif duke@435: } else { duke@435: // int to int moves duke@435: __ mov(from_reg->as_register(), to_reg->as_register()); duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { duke@435: __ verify_oop(to_reg->as_register()); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, duke@435: LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, duke@435: bool unaligned) { duke@435: LIR_Address* addr = dest->as_address_ptr(); duke@435: duke@435: Register src = addr->base()->as_pointer_register(); duke@435: Register disp_reg = noreg; duke@435: int disp_value = addr->disp(); duke@435: bool needs_patching = (patch_code != lir_patch_none); duke@435: duke@435: if (addr->base()->is_oop_register()) { duke@435: __ verify_oop(src); duke@435: } duke@435: duke@435: PatchingStub* patch = NULL; duke@435: if (needs_patching) { duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: assert(!from_reg->is_double_cpu() || duke@435: patch_code == lir_patch_none || duke@435: patch_code == lir_patch_normal, "patching doesn't match register"); duke@435: } duke@435: duke@435: if (addr->index()->is_illegal()) { duke@435: if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { duke@435: if (needs_patching) { duke@435: __ sethi(0, O7, true); duke@435: __ add(O7, 0, O7); duke@435: } else { duke@435: __ set(disp_value, O7); duke@435: } duke@435: disp_reg = O7; duke@435: } duke@435: } else if (unaligned || PatchALot) { duke@435: __ add(src, addr->index()->as_register(), O7); duke@435: src = O7; duke@435: } else { duke@435: disp_reg = addr->index()->as_pointer_register(); duke@435: assert(disp_value == 0, "can't handle 3 operand addresses"); duke@435: } duke@435: duke@435: // remember the offset of the store. The patching_epilog must be done duke@435: // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get duke@435: // entered in increasing order. duke@435: int offset; duke@435: duke@435: assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); duke@435: if (disp_reg == noreg) { duke@435: offset = store(from_reg, src, disp_value, type, unaligned); duke@435: } else { duke@435: assert(!unaligned, "can't handle this"); duke@435: offset = store(from_reg, src, disp_reg, type); duke@435: } duke@435: duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, patch_code, src, info); duke@435: } duke@435: duke@435: if (info != NULL) add_debug_info_for_null_check(offset, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::return_op(LIR_Opr result) { duke@435: // the poll may need a register so just pick one that isn't the return register duke@435: #ifdef TIERED duke@435: if (result->type_field() == LIR_OprDesc::long_type) { duke@435: // Must move the result to G1 duke@435: // Must leave proper result in O0,O1 and G1 (TIERED only) duke@435: __ sllx(I0, 32, G1); // Shift bits into high G1 duke@435: __ srl (I1, 0, I1); // Zero extend O1 (harmless?) duke@435: __ or3 (I1, G1, G1); // OR 64 bits into G1 duke@435: } duke@435: #endif // TIERED duke@435: __ set((intptr_t)os::get_polling_page(), L0); duke@435: __ relocate(relocInfo::poll_return_type); duke@435: __ ld_ptr(L0, 0, G0); duke@435: __ ret(); duke@435: __ delayed()->restore(); duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { duke@435: __ set((intptr_t)os::get_polling_page(), tmp->as_register()); duke@435: if (info != NULL) { duke@435: add_debug_info_for_branch(info); duke@435: } else { duke@435: __ relocate(relocInfo::poll_type); duke@435: } duke@435: duke@435: int offset = __ offset(); duke@435: __ ld_ptr(tmp->as_register(), 0, G0); duke@435: duke@435: return offset; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_static_call_stub() { duke@435: address call_pc = __ pc(); duke@435: address stub = __ start_a_stub(call_stub_size); duke@435: if (stub == NULL) { duke@435: bailout("static call stub overflow"); duke@435: return; duke@435: } duke@435: duke@435: int start = __ offset(); duke@435: __ relocate(static_stub_Relocation::spec(call_pc)); duke@435: duke@435: __ set_oop(NULL, G5); duke@435: // must be set to -1 at code generation time duke@435: Address a(G3, (address)-1); duke@435: __ jump_to(a, 0); duke@435: __ delayed()->nop(); duke@435: duke@435: assert(__ offset() - start <= call_stub_size, "stub too big"); duke@435: __ end_a_stub(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { duke@435: if (opr1->is_single_fpu()) { duke@435: __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); duke@435: } else if (opr1->is_double_fpu()) { duke@435: __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); duke@435: } else if (opr1->is_single_cpu()) { duke@435: if (opr2->is_constant()) { duke@435: switch (opr2->as_constant_ptr()->type()) { duke@435: case T_INT: duke@435: { jint con = opr2->as_constant_ptr()->as_jint(); duke@435: if (Assembler::is_simm13(con)) { duke@435: __ cmp(opr1->as_register(), con); duke@435: } else { duke@435: __ set(con, O7); duke@435: __ cmp(opr1->as_register(), O7); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: case T_OBJECT: duke@435: // there are only equal/notequal comparisions on objects duke@435: { jobject con = opr2->as_constant_ptr()->as_jobject(); duke@435: if (con == NULL) { duke@435: __ cmp(opr1->as_register(), 0); duke@435: } else { duke@435: jobject2reg(con, O7); duke@435: __ cmp(opr1->as_register(), O7); duke@435: } duke@435: } duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: break; duke@435: } duke@435: } else { duke@435: if (opr2->is_address()) { duke@435: LIR_Address * addr = opr2->as_address_ptr(); duke@435: BasicType type = addr->type(); duke@435: if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); duke@435: else __ ld(as_Address(addr), O7); duke@435: __ cmp(opr1->as_register(), O7); duke@435: } else { duke@435: __ cmp(opr1->as_register(), opr2->as_register()); duke@435: } duke@435: } duke@435: } else if (opr1->is_double_cpu()) { duke@435: Register xlo = opr1->as_register_lo(); duke@435: Register xhi = opr1->as_register_hi(); duke@435: if (opr2->is_constant() && opr2->as_jlong() == 0) { duke@435: assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); duke@435: #ifdef _LP64 duke@435: __ orcc(xhi, G0, G0); duke@435: #else duke@435: __ orcc(xhi, xlo, G0); duke@435: #endif duke@435: } else if (opr2->is_register()) { duke@435: Register ylo = opr2->as_register_lo(); duke@435: Register yhi = opr2->as_register_hi(); duke@435: #ifdef _LP64 duke@435: __ cmp(xlo, ylo); duke@435: #else duke@435: __ subcc(xlo, ylo, xlo); duke@435: __ subccc(xhi, yhi, xhi); duke@435: if (condition == lir_cond_equal || condition == lir_cond_notEqual) { duke@435: __ orcc(xhi, xlo, G0); duke@435: } duke@435: #endif duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } else if (opr1->is_address()) { duke@435: LIR_Address * addr = opr1->as_address_ptr(); duke@435: BasicType type = addr->type(); duke@435: assert (opr2->is_constant(), "Checking"); duke@435: if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); duke@435: else __ ld(as_Address(addr), O7); duke@435: __ cmp(O7, opr2->as_constant_ptr()->as_jint()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ duke@435: if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { duke@435: bool is_unordered_less = (code == lir_ucmp_fd2i); duke@435: if (left->is_single_fpu()) { duke@435: __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); duke@435: } else if (left->is_double_fpu()) { duke@435: __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } else if (code == lir_cmp_l2i) { duke@435: __ lcmp(left->as_register_hi(), left->as_register_lo(), duke@435: right->as_register_hi(), right->as_register_lo(), duke@435: dst->as_register()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { duke@435: duke@435: Assembler::Condition acond; duke@435: switch (condition) { duke@435: case lir_cond_equal: acond = Assembler::equal; break; duke@435: case lir_cond_notEqual: acond = Assembler::notEqual; break; duke@435: case lir_cond_less: acond = Assembler::less; break; duke@435: case lir_cond_lessEqual: acond = Assembler::lessEqual; break; duke@435: case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; duke@435: case lir_cond_greater: acond = Assembler::greater; break; duke@435: case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; duke@435: case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; duke@435: default: ShouldNotReachHere(); duke@435: }; duke@435: duke@435: if (opr1->is_constant() && opr1->type() == T_INT) { duke@435: Register dest = result->as_register(); duke@435: // load up first part of constant before branch duke@435: // and do the rest in the delay slot. duke@435: if (!Assembler::is_simm13(opr1->as_jint())) { duke@435: __ sethi(opr1->as_jint(), dest); duke@435: } duke@435: } else if (opr1->is_constant()) { duke@435: const2reg(opr1, result, lir_patch_none, NULL); duke@435: } else if (opr1->is_register()) { duke@435: reg2reg(opr1, result); duke@435: } else if (opr1->is_stack()) { duke@435: stack2reg(opr1, result, result->type()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: Label skip; duke@435: __ br(acond, false, Assembler::pt, skip); duke@435: if (opr1->is_constant() && opr1->type() == T_INT) { duke@435: Register dest = result->as_register(); duke@435: if (Assembler::is_simm13(opr1->as_jint())) { duke@435: __ delayed()->or3(G0, opr1->as_jint(), dest); duke@435: } else { duke@435: // the sethi has been done above, so just put in the low 10 bits duke@435: __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); duke@435: } duke@435: } else { duke@435: // can't do anything useful in the delay slot duke@435: __ delayed()->nop(); duke@435: } duke@435: if (opr2->is_constant()) { duke@435: const2reg(opr2, result, lir_patch_none, NULL); duke@435: } else if (opr2->is_register()) { duke@435: reg2reg(opr2, result); duke@435: } else if (opr2->is_stack()) { duke@435: stack2reg(opr2, result, result->type()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: __ bind(skip); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { duke@435: assert(info == NULL, "unused on this code path"); duke@435: assert(left->is_register(), "wrong items state"); duke@435: assert(dest->is_register(), "wrong items state"); duke@435: duke@435: if (right->is_register()) { duke@435: if (dest->is_float_kind()) { duke@435: duke@435: FloatRegister lreg, rreg, res; duke@435: FloatRegisterImpl::Width w; duke@435: if (right->is_single_fpu()) { duke@435: w = FloatRegisterImpl::S; duke@435: lreg = left->as_float_reg(); duke@435: rreg = right->as_float_reg(); duke@435: res = dest->as_float_reg(); duke@435: } else { duke@435: w = FloatRegisterImpl::D; duke@435: lreg = left->as_double_reg(); duke@435: rreg = right->as_double_reg(); duke@435: res = dest->as_double_reg(); duke@435: } duke@435: duke@435: switch (code) { duke@435: case lir_add: __ fadd(w, lreg, rreg, res); break; duke@435: case lir_sub: __ fsub(w, lreg, rreg, res); break; duke@435: case lir_mul: // fall through duke@435: case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; duke@435: case lir_div: // fall through duke@435: case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (dest->is_double_cpu()) { duke@435: #ifdef _LP64 duke@435: Register dst_lo = dest->as_register_lo(); duke@435: Register op1_lo = left->as_pointer_register(); duke@435: Register op2_lo = right->as_pointer_register(); duke@435: duke@435: switch (code) { duke@435: case lir_add: duke@435: __ add(op1_lo, op2_lo, dst_lo); duke@435: break; duke@435: duke@435: case lir_sub: duke@435: __ sub(op1_lo, op2_lo, dst_lo); duke@435: break; duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #else duke@435: Register op1_lo = left->as_register_lo(); duke@435: Register op1_hi = left->as_register_hi(); duke@435: Register op2_lo = right->as_register_lo(); duke@435: Register op2_hi = right->as_register_hi(); duke@435: Register dst_lo = dest->as_register_lo(); duke@435: Register dst_hi = dest->as_register_hi(); duke@435: duke@435: switch (code) { duke@435: case lir_add: duke@435: __ addcc(op1_lo, op2_lo, dst_lo); duke@435: __ addc (op1_hi, op2_hi, dst_hi); duke@435: break; duke@435: duke@435: case lir_sub: duke@435: __ subcc(op1_lo, op2_lo, dst_lo); duke@435: __ subc (op1_hi, op2_hi, dst_hi); duke@435: break; duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #endif duke@435: } else { duke@435: assert (right->is_single_cpu(), "Just Checking"); duke@435: duke@435: Register lreg = left->as_register(); duke@435: Register res = dest->as_register(); duke@435: Register rreg = right->as_register(); duke@435: switch (code) { duke@435: case lir_add: __ add (lreg, rreg, res); break; duke@435: case lir_sub: __ sub (lreg, rreg, res); break; duke@435: case lir_mul: __ mult (lreg, rreg, res); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: } else { duke@435: assert (right->is_constant(), "must be constant"); duke@435: duke@435: if (dest->is_single_cpu()) { duke@435: Register lreg = left->as_register(); duke@435: Register res = dest->as_register(); duke@435: int simm13 = right->as_constant_ptr()->as_jint(); duke@435: duke@435: switch (code) { duke@435: case lir_add: __ add (lreg, simm13, res); break; duke@435: case lir_sub: __ sub (lreg, simm13, res); break; duke@435: case lir_mul: __ mult (lreg, simm13, res); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Register lreg = left->as_pointer_register(); duke@435: Register res = dest->as_register_lo(); duke@435: long con = right->as_constant_ptr()->as_jlong(); duke@435: assert(Assembler::is_simm13(con), "must be simm13"); duke@435: duke@435: switch (code) { duke@435: case lir_add: __ add (lreg, (int)con, res); break; duke@435: case lir_sub: __ sub (lreg, (int)con, res); break; duke@435: case lir_mul: __ mult (lreg, (int)con, res); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::fpop() { duke@435: // do nothing duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { duke@435: switch (code) { duke@435: case lir_sin: duke@435: case lir_tan: duke@435: case lir_cos: { duke@435: assert(thread->is_valid(), "preserve the thread object for performance reasons"); duke@435: assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); duke@435: break; duke@435: } duke@435: case lir_sqrt: { duke@435: assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); duke@435: FloatRegister src_reg = value->as_double_reg(); duke@435: FloatRegister dst_reg = dest->as_double_reg(); duke@435: __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); duke@435: break; duke@435: } duke@435: case lir_abs: { duke@435: assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); duke@435: FloatRegister src_reg = value->as_double_reg(); duke@435: FloatRegister dst_reg = dest->as_double_reg(); duke@435: __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); duke@435: break; duke@435: } duke@435: default: { duke@435: ShouldNotReachHere(); duke@435: break; duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { duke@435: if (right->is_constant()) { duke@435: if (dest->is_single_cpu()) { duke@435: int simm13 = right->as_constant_ptr()->as_jint(); duke@435: switch (code) { duke@435: case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; duke@435: case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; duke@435: case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: long c = right->as_constant_ptr()->as_jlong(); duke@435: assert(c == (int)c && Assembler::is_simm13(c), "out of range"); duke@435: int simm13 = (int)c; duke@435: switch (code) { duke@435: case lir_logic_and: duke@435: #ifndef _LP64 duke@435: __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); duke@435: #endif duke@435: __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); duke@435: break; duke@435: duke@435: case lir_logic_or: duke@435: #ifndef _LP64 duke@435: __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); duke@435: #endif duke@435: __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); duke@435: break; duke@435: duke@435: case lir_logic_xor: duke@435: #ifndef _LP64 duke@435: __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); duke@435: #endif duke@435: __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); duke@435: break; duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: } else { duke@435: assert(right->is_register(), "right should be in register"); duke@435: duke@435: if (dest->is_single_cpu()) { duke@435: switch (code) { duke@435: case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; duke@435: case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; duke@435: case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: #ifdef _LP64 duke@435: Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : duke@435: left->as_register_lo(); duke@435: Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : duke@435: right->as_register_lo(); duke@435: duke@435: switch (code) { duke@435: case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; duke@435: case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; duke@435: case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #else duke@435: switch (code) { duke@435: case lir_logic_and: duke@435: __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); duke@435: __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); duke@435: break; duke@435: duke@435: case lir_logic_or: duke@435: __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); duke@435: __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); duke@435: break; duke@435: duke@435: case lir_logic_xor: duke@435: __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); duke@435: __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); duke@435: break; duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #endif duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::shift_amount(BasicType t) { duke@435: int elem_size = type2aelembytes[t]; duke@435: switch (elem_size) { duke@435: case 1 : return 0; duke@435: case 2 : return 1; duke@435: case 4 : return 2; duke@435: case 8 : return 3; duke@435: } duke@435: ShouldNotReachHere(); duke@435: return -1; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { duke@435: assert(exceptionOop->as_register() == Oexception, "should match"); duke@435: assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match"); duke@435: duke@435: info->add_register_oop(exceptionOop); duke@435: duke@435: if (unwind) { duke@435: __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: } else { duke@435: // reuse the debug info from the safepoint poll for the throw op itself duke@435: address pc_for_athrow = __ pc(); duke@435: int pc_for_athrow_offset = __ offset(); duke@435: RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); duke@435: __ set((intptr_t)pc_for_athrow, Oissuing_pc, rspec); duke@435: add_call_info(pc_for_athrow_offset, info); // for exception handler duke@435: duke@435: __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { duke@435: Register src = op->src()->as_register(); duke@435: Register dst = op->dst()->as_register(); duke@435: Register src_pos = op->src_pos()->as_register(); duke@435: Register dst_pos = op->dst_pos()->as_register(); duke@435: Register length = op->length()->as_register(); duke@435: Register tmp = op->tmp()->as_register(); duke@435: Register tmp2 = O7; duke@435: duke@435: int flags = op->flags(); duke@435: ciArrayKlass* default_type = op->expected_type(); duke@435: BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; duke@435: if (basic_type == T_ARRAY) basic_type = T_OBJECT; duke@435: duke@435: // set up the arraycopy stub information duke@435: ArrayCopyStub* stub = op->stub(); duke@435: duke@435: // always do stub if no type information is available. it's ok if duke@435: // the known type isn't loaded since the code sanity checks duke@435: // in debug mode and the type isn't required when we know the exact type duke@435: // also check that the type is an array type. duke@435: if (op->expected_type() == NULL) { duke@435: __ mov(src, O0); duke@435: __ mov(src_pos, O1); duke@435: __ mov(dst, O2); duke@435: __ mov(dst_pos, O3); duke@435: __ mov(length, O4); duke@435: __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); duke@435: duke@435: __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: __ bind(*stub->continuation()); duke@435: return; duke@435: } duke@435: duke@435: assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); duke@435: duke@435: // make sure src and dst are non-null and load array length duke@435: if (flags & LIR_OpArrayCopy::src_null_check) { duke@435: __ tst(src); duke@435: __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::dst_null_check) { duke@435: __ tst(dst); duke@435: __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::src_pos_positive_check) { duke@435: // test src_pos register duke@435: __ tst(src_pos); duke@435: __ br(Assembler::less, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { duke@435: // test dst_pos register duke@435: __ tst(dst_pos); duke@435: __ br(Assembler::less, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::length_positive_check) { duke@435: // make sure length isn't negative duke@435: __ tst(length); duke@435: __ br(Assembler::less, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::src_range_check) { duke@435: __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); duke@435: __ add(length, src_pos, tmp); duke@435: __ cmp(tmp2, tmp); duke@435: __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::dst_range_check) { duke@435: __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); duke@435: __ add(length, dst_pos, tmp); duke@435: __ cmp(tmp2, tmp); duke@435: __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::type_check) { duke@435: __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); duke@435: __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); duke@435: __ cmp(tmp, tmp2); duke@435: __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { duke@435: // Sanity check the known type with the incoming class. For the duke@435: // primitive case the types must match exactly with src.klass and duke@435: // dst.klass each exactly matching the default type. For the duke@435: // object array case, if no type check is needed then either the duke@435: // dst type is exactly the expected type and the src type is a duke@435: // subtype which we can't check or src is the same array as dst duke@435: // but not necessarily exactly of type default_type. duke@435: Label known_ok, halt; duke@435: jobject2reg(op->expected_type()->encoding(), tmp); duke@435: __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); duke@435: if (basic_type != T_OBJECT) { duke@435: __ cmp(tmp, tmp2); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, halt); duke@435: __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); duke@435: __ cmp(tmp, tmp2); duke@435: __ br(Assembler::equal, false, Assembler::pn, known_ok); duke@435: __ delayed()->nop(); duke@435: } else { duke@435: __ cmp(tmp, tmp2); duke@435: __ br(Assembler::equal, false, Assembler::pn, known_ok); duke@435: __ delayed()->cmp(src, dst); duke@435: __ br(Assembler::equal, false, Assembler::pn, known_ok); duke@435: __ delayed()->nop(); duke@435: } duke@435: __ bind(halt); duke@435: __ stop("incorrect type information in arraycopy"); duke@435: __ bind(known_ok); duke@435: } duke@435: #endif duke@435: duke@435: int shift = shift_amount(basic_type); duke@435: duke@435: Register src_ptr = O0; duke@435: Register dst_ptr = O1; duke@435: Register len = O2; duke@435: duke@435: __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); duke@435: if (shift == 0) { duke@435: __ add(src_ptr, src_pos, src_ptr); duke@435: } else { duke@435: __ sll(src_pos, shift, tmp); duke@435: __ add(src_ptr, tmp, src_ptr); duke@435: } duke@435: duke@435: __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); duke@435: if (shift == 0) { duke@435: __ add(dst_ptr, dst_pos, dst_ptr); duke@435: } else { duke@435: __ sll(dst_pos, shift, tmp); duke@435: __ add(dst_ptr, tmp, dst_ptr); duke@435: } duke@435: duke@435: if (basic_type != T_OBJECT) { duke@435: if (shift == 0) { duke@435: __ mov(length, len); duke@435: } else { duke@435: __ sll(length, shift, len); duke@435: } duke@435: __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); duke@435: } else { duke@435: // oop_arraycopy takes a length in number of elements, so don't scale it. duke@435: __ mov(length, len); duke@435: __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); duke@435: } duke@435: duke@435: __ bind(*stub->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { duke@435: if (dest->is_single_cpu()) { duke@435: #ifdef _LP64 duke@435: if (left->type() == T_OBJECT) { duke@435: switch (code) { duke@435: case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else duke@435: #endif duke@435: switch (code) { duke@435: case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: #ifdef _LP64 duke@435: switch (code) { duke@435: case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; duke@435: case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; duke@435: case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #else duke@435: switch (code) { duke@435: case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; duke@435: case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; duke@435: case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: #endif duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { duke@435: #ifdef _LP64 duke@435: if (left->type() == T_OBJECT) { duke@435: count = count & 63; // shouldn't shift by more than sizeof(intptr_t) duke@435: Register l = left->as_register(); duke@435: Register d = dest->as_register_lo(); duke@435: switch (code) { duke@435: case lir_shl: __ sllx (l, count, d); break; duke@435: case lir_shr: __ srax (l, count, d); break; duke@435: case lir_ushr: __ srlx (l, count, d); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: return; duke@435: } duke@435: #endif duke@435: duke@435: if (dest->is_single_cpu()) { duke@435: count = count & 0x1F; // Java spec duke@435: switch (code) { duke@435: case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; duke@435: case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; duke@435: case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else if (dest->is_double_cpu()) { duke@435: count = count & 63; // Java spec duke@435: switch (code) { duke@435: case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; duke@435: case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; duke@435: case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { duke@435: assert(op->tmp1()->as_register() == G1 && duke@435: op->tmp2()->as_register() == G3 && duke@435: op->tmp3()->as_register() == G4 && duke@435: op->obj()->as_register() == O0 && duke@435: op->klass()->as_register() == G5, "must be"); duke@435: if (op->init_check()) { duke@435: __ ld(op->klass()->as_register(), duke@435: instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), duke@435: op->tmp1()->as_register()); duke@435: add_debug_info_for_null_check_here(op->stub()->info()); duke@435: __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: __ allocate_object(op->obj()->as_register(), duke@435: op->tmp1()->as_register(), duke@435: op->tmp2()->as_register(), duke@435: op->tmp3()->as_register(), duke@435: op->header_size(), duke@435: op->object_size(), duke@435: op->klass()->as_register(), duke@435: *op->stub()->entry()); duke@435: __ bind(*op->stub()->continuation()); duke@435: __ verify_oop(op->obj()->as_register()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { duke@435: assert(op->tmp1()->as_register() == G1 && duke@435: op->tmp2()->as_register() == G3 && duke@435: op->tmp3()->as_register() == G4 && duke@435: op->tmp4()->as_register() == O1 && duke@435: op->klass()->as_register() == G5, "must be"); duke@435: if (UseSlowPath || duke@435: (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || duke@435: (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { duke@435: __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry()); duke@435: __ delayed()->nop(); duke@435: } else { duke@435: __ allocate_array(op->obj()->as_register(), duke@435: op->len()->as_register(), duke@435: op->tmp1()->as_register(), duke@435: op->tmp2()->as_register(), duke@435: op->tmp3()->as_register(), duke@435: arrayOopDesc::header_size(op->type()), duke@435: type2aelembytes[op->type()], duke@435: op->klass()->as_register(), duke@435: *op->stub()->entry()); duke@435: } duke@435: __ bind(*op->stub()->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { duke@435: LIR_Code code = op->code(); duke@435: if (code == lir_store_check) { duke@435: Register value = op->object()->as_register(); duke@435: Register array = op->array()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register Rtmp1 = op->tmp3()->as_register(); duke@435: duke@435: __ verify_oop(value); duke@435: duke@435: CodeStub* stub = op->stub(); duke@435: Label done; duke@435: __ cmp(value, 0); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); duke@435: load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); duke@435: duke@435: // get instance klass duke@435: load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); duke@435: // get super_check_offset duke@435: load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL); duke@435: // See if we get an immediate positive hit duke@435: __ ld_ptr(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr->as_register()); duke@435: __ cmp(k_RInfo, O7); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: // check for immediate negative hit duke@435: __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: // check for self duke@435: __ cmp(klass_RInfo, k_RInfo); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: duke@435: // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); duke@435: __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: __ cmp(G3, 0); duke@435: __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: __ bind(done); duke@435: } else if (op->code() == lir_checkcast) { duke@435: // we always need a stub for the failure case. duke@435: CodeStub* stub = op->stub(); duke@435: Register obj = op->object()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register dst = op->result_opr()->as_register(); duke@435: Register Rtmp1 = op->tmp3()->as_register(); duke@435: ciKlass* k = op->klass(); duke@435: duke@435: if (obj == k_RInfo) { duke@435: k_RInfo = klass_RInfo; duke@435: klass_RInfo = obj; duke@435: } duke@435: if (op->profiled_method() != NULL) { duke@435: ciMethod* method = op->profiled_method(); duke@435: int bci = op->profiled_bci(); duke@435: duke@435: // We need two temporaries to perform this operation on SPARC, duke@435: // so to keep things simple we perform a redundant test here duke@435: Label profile_done; duke@435: __ cmp(obj, 0); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, profile_done); duke@435: __ delayed()->nop(); duke@435: // Object is null; update methodDataOop duke@435: ciMethodData* md = method->method_data(); duke@435: if (md == NULL) { duke@435: bailout("out of memory building methodDataOop"); duke@435: return; duke@435: } duke@435: ciProfileData* data = md->bci_to_data(bci); duke@435: assert(data != NULL, "need data for checkcast"); duke@435: assert(data->is_BitData(), "need BitData for checkcast"); duke@435: Register mdo = k_RInfo; duke@435: Register data_val = Rtmp1; duke@435: jobject2reg(md->encoding(), mdo); duke@435: duke@435: int mdo_offset_bias = 0; duke@435: if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { duke@435: // The offset is large so bias the mdo by the base of the slot so duke@435: // that the ld can use simm13s to reference the slots of the data duke@435: mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); duke@435: __ set(mdo_offset_bias, data_val); duke@435: __ add(mdo, data_val, mdo); duke@435: } duke@435: duke@435: duke@435: Address flags_addr(mdo, 0, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); duke@435: __ ldub(flags_addr, data_val); duke@435: __ or3(data_val, BitData::null_seen_byte_constant(), data_val); duke@435: __ stb(data_val, flags_addr); duke@435: __ bind(profile_done); duke@435: } duke@435: duke@435: Label done; duke@435: // patching may screw with our temporaries on sparc, duke@435: // so let's do it before loading the class duke@435: if (k->is_loaded()) { duke@435: jobject2reg(k->encoding(), k_RInfo); duke@435: } else { duke@435: jobject2reg_with_patching(k_RInfo, op->info_for_patch()); duke@435: } duke@435: assert(obj != k_RInfo, "must be different"); duke@435: __ cmp(obj, 0); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: duke@435: // get object class duke@435: // not a safepoint as obj null check happens earlier duke@435: load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); duke@435: if (op->fast_check()) { duke@435: assert_different_registers(klass_RInfo, k_RInfo); duke@435: __ cmp(k_RInfo, klass_RInfo); duke@435: __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: __ bind(done); duke@435: } else { duke@435: if (k->is_loaded()) { duke@435: load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL); duke@435: duke@435: if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { duke@435: // See if we get an immediate positive hit duke@435: __ cmp(Rtmp1, k_RInfo ); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } else { duke@435: // See if we get an immediate positive hit duke@435: assert_different_registers(Rtmp1, k_RInfo, klass_RInfo); duke@435: __ cmp(Rtmp1, k_RInfo ); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: // check for self duke@435: __ delayed()->cmp(klass_RInfo, k_RInfo); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: duke@435: // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); duke@435: __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: __ cmp(G3, 0); duke@435: __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: __ bind(done); duke@435: } else { duke@435: assert_different_registers(Rtmp1, klass_RInfo, k_RInfo); duke@435: duke@435: load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL); duke@435: // See if we get an immediate positive hit duke@435: load(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr, T_OBJECT); duke@435: __ cmp(k_RInfo, O7); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: // check for immediate negative hit duke@435: __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); duke@435: __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); duke@435: // check for self duke@435: __ delayed()->cmp(klass_RInfo, k_RInfo); duke@435: __ br(Assembler::equal, false, Assembler::pn, done); duke@435: __ delayed()->nop(); duke@435: duke@435: // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); duke@435: __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: __ cmp(G3, 0); duke@435: __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); duke@435: __ delayed()->nop(); duke@435: __ bind(done); duke@435: } duke@435: duke@435: } duke@435: __ mov(obj, dst); duke@435: } else if (code == lir_instanceof) { duke@435: Register obj = op->object()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register dst = op->result_opr()->as_register(); duke@435: Register Rtmp1 = op->tmp3()->as_register(); duke@435: ciKlass* k = op->klass(); duke@435: duke@435: Label done; duke@435: if (obj == k_RInfo) { duke@435: k_RInfo = klass_RInfo; duke@435: klass_RInfo = obj; duke@435: } duke@435: // patching may screw with our temporaries on sparc, duke@435: // so let's do it before loading the class duke@435: if (k->is_loaded()) { duke@435: jobject2reg(k->encoding(), k_RInfo); duke@435: } else { duke@435: jobject2reg_with_patching(k_RInfo, op->info_for_patch()); duke@435: } duke@435: assert(obj != k_RInfo, "must be different"); duke@435: __ cmp(obj, 0); duke@435: __ br(Assembler::equal, true, Assembler::pn, done); duke@435: __ delayed()->set(0, dst); duke@435: duke@435: // get object class duke@435: // not a safepoint as obj null check happens earlier duke@435: load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); duke@435: if (op->fast_check()) { duke@435: __ cmp(k_RInfo, klass_RInfo); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: __ set(0, dst); duke@435: __ bind(done); duke@435: } else { duke@435: if (k->is_loaded()) { duke@435: assert_different_registers(Rtmp1, klass_RInfo, k_RInfo); duke@435: load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL); duke@435: duke@435: if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { duke@435: // See if we get an immediate positive hit duke@435: __ cmp(Rtmp1, k_RInfo ); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: __ set(0, dst); duke@435: __ bind(done); duke@435: } else { duke@435: // See if we get an immediate positive hit duke@435: assert_different_registers(Rtmp1, k_RInfo, klass_RInfo); duke@435: __ cmp(Rtmp1, k_RInfo ); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: // check for self duke@435: __ cmp(klass_RInfo, k_RInfo); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: duke@435: // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); duke@435: __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: __ mov(G3, dst); duke@435: __ bind(done); duke@435: } duke@435: } else { duke@435: assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); duke@435: duke@435: load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), dst, T_INT, NULL); duke@435: // See if we get an immediate positive hit duke@435: load(klass_RInfo, dst, FrameMap::O7_oop_opr, T_OBJECT); duke@435: __ cmp(k_RInfo, O7); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: // check for immediate negative hit duke@435: __ cmp(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); duke@435: __ br(Assembler::notEqual, true, Assembler::pt, done); duke@435: __ delayed()->set(0, dst); duke@435: // check for self duke@435: __ cmp(klass_RInfo, k_RInfo); duke@435: __ br(Assembler::equal, true, Assembler::pt, done); duke@435: __ delayed()->set(1, dst); duke@435: duke@435: // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); duke@435: __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: __ mov(G3, dst); duke@435: __ bind(done); duke@435: } duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { duke@435: if (op->code() == lir_cas_long) { duke@435: assert(VM_Version::supports_cx8(), "wrong machine"); duke@435: Register addr = op->addr()->as_pointer_register(); duke@435: Register cmp_value_lo = op->cmp_value()->as_register_lo(); duke@435: Register cmp_value_hi = op->cmp_value()->as_register_hi(); duke@435: Register new_value_lo = op->new_value()->as_register_lo(); duke@435: Register new_value_hi = op->new_value()->as_register_hi(); duke@435: Register t1 = op->tmp1()->as_register(); duke@435: Register t2 = op->tmp2()->as_register(); duke@435: #ifdef _LP64 duke@435: __ mov(cmp_value_lo, t1); duke@435: __ mov(new_value_lo, t2); duke@435: #else duke@435: // move high and low halves of long values into single registers duke@435: __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg duke@435: __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half duke@435: __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value duke@435: __ sllx(new_value_hi, 32, t2); duke@435: __ srl(new_value_lo, 0, new_value_lo); duke@435: __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap duke@435: #endif duke@435: // perform the compare and swap operation duke@435: __ casx(addr, t1, t2); duke@435: // generate condition code - if the swap succeeded, t2 ("new value" reg) was duke@435: // overwritten with the original value in "addr" and will be equal to t1. duke@435: __ cmp(t1, t2); duke@435: duke@435: } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { duke@435: Register addr = op->addr()->as_pointer_register(); duke@435: Register cmp_value = op->cmp_value()->as_register(); duke@435: Register new_value = op->new_value()->as_register(); duke@435: Register t1 = op->tmp1()->as_register(); duke@435: Register t2 = op->tmp2()->as_register(); duke@435: __ mov(cmp_value, t1); duke@435: __ mov(new_value, t2); duke@435: #ifdef _LP64 duke@435: if (op->code() == lir_cas_obj) { duke@435: __ casx(addr, t1, t2); duke@435: } else duke@435: #endif duke@435: { duke@435: __ cas(addr, t1, t2); duke@435: } duke@435: __ cmp(t1, t2); duke@435: } else { duke@435: Unimplemented(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::set_24bit_FPU() { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reset_FPU() { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::breakpoint() { duke@435: __ breakpoint_trap(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::push(LIR_Opr opr) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::pop(LIR_Opr opr) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { duke@435: Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); duke@435: Register dst = dst_opr->as_register(); duke@435: Register reg = mon_addr.base(); duke@435: int offset = mon_addr.disp(); duke@435: // compute pointer to BasicLock duke@435: if (mon_addr.is_simm13()) { duke@435: __ add(reg, offset, dst); duke@435: } else { duke@435: __ set(offset, dst); duke@435: __ add(dst, reg, dst); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_lock(LIR_OpLock* op) { duke@435: Register obj = op->obj_opr()->as_register(); duke@435: Register hdr = op->hdr_opr()->as_register(); duke@435: Register lock = op->lock_opr()->as_register(); duke@435: duke@435: // obj may not be an oop duke@435: if (op->code() == lir_lock) { duke@435: MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); duke@435: if (UseFastLocking) { duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: // add debug info for NullPointerException only if one is possible duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check_here(op->info()); duke@435: } duke@435: __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); duke@435: } else { duke@435: // always do slow locking duke@435: // note: the slow locking code could be inlined here, however if we use duke@435: // slow locking, speed doesn't matter anyway and this solution is duke@435: // simpler and requires less duplicated code - additionally, the duke@435: // slow locking code is the same in either case which simplifies duke@435: // debugging duke@435: __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: } else { duke@435: assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); duke@435: if (UseFastLocking) { duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: __ unlock_object(hdr, obj, lock, *op->stub()->entry()); duke@435: } else { duke@435: // always do slow unlocking duke@435: // note: the slow unlocking code could be inlined here, however if we use duke@435: // slow unlocking, speed doesn't matter anyway and this solution is duke@435: // simpler and requires less duplicated code - additionally, the duke@435: // slow unlocking code is the same in either case which simplifies duke@435: // debugging duke@435: __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); duke@435: __ delayed()->nop(); duke@435: } duke@435: } duke@435: __ bind(*op->stub()->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { duke@435: ciMethod* method = op->profiled_method(); duke@435: int bci = op->profiled_bci(); duke@435: duke@435: // Update counter for all call types duke@435: ciMethodData* md = method->method_data(); duke@435: if (md == NULL) { duke@435: bailout("out of memory building methodDataOop"); duke@435: return; duke@435: } duke@435: ciProfileData* data = md->bci_to_data(bci); duke@435: assert(data->is_CounterData(), "need CounterData for calls"); duke@435: assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); duke@435: assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); duke@435: Register mdo = op->mdo()->as_register(); duke@435: Register tmp1 = op->tmp1()->as_register(); duke@435: jobject2reg(md->encoding(), mdo); duke@435: int mdo_offset_bias = 0; duke@435: if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + duke@435: data->size_in_bytes())) { duke@435: // The offset is large so bias the mdo by the base of the slot so duke@435: // that the ld can use simm13s to reference the slots of the data duke@435: mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); duke@435: __ set(mdo_offset_bias, O7); duke@435: __ add(mdo, O7, mdo); duke@435: } duke@435: duke@435: Address counter_addr(mdo, 0, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); duke@435: __ lduw(counter_addr, tmp1); duke@435: __ add(tmp1, DataLayout::counter_increment, tmp1); duke@435: __ stw(tmp1, counter_addr); duke@435: Bytecodes::Code bc = method->java_code_at_bci(bci); duke@435: // Perform additional virtual call profiling for invokevirtual and duke@435: // invokeinterface bytecodes duke@435: if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && duke@435: Tier1ProfileVirtualCalls) { duke@435: assert(op->recv()->is_single_cpu(), "recv must be allocated"); duke@435: Register recv = op->recv()->as_register(); duke@435: assert_different_registers(mdo, tmp1, recv); duke@435: assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); duke@435: ciKlass* known_klass = op->known_holder(); duke@435: if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { duke@435: // We know the type that will be seen at this call site; we can duke@435: // statically update the methodDataOop rather than needing to do duke@435: // dynamic tests on the receiver type duke@435: duke@435: // NOTE: we should probably put a lock around this search to duke@435: // avoid collisions by concurrent compilations duke@435: ciVirtualCallData* vc_data = (ciVirtualCallData*) data; duke@435: uint i; duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: ciKlass* receiver = vc_data->receiver(i); duke@435: if (known_klass->equals(receiver)) { duke@435: Address data_addr(mdo, 0, md->byte_offset_of_slot(data, duke@435: VirtualCallData::receiver_count_offset(i)) - duke@435: mdo_offset_bias); duke@435: __ lduw(data_addr, tmp1); duke@435: __ add(tmp1, DataLayout::counter_increment, tmp1); duke@435: __ stw(tmp1, data_addr); duke@435: return; duke@435: } duke@435: } duke@435: duke@435: // Receiver type not found in profile data; select an empty slot duke@435: duke@435: // Note that this is less efficient than it should be because it duke@435: // always does a write to the receiver part of the duke@435: // VirtualCallData rather than just the first time duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: ciKlass* receiver = vc_data->receiver(i); duke@435: if (receiver == NULL) { duke@435: Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - duke@435: mdo_offset_bias); duke@435: jobject2reg(known_klass->encoding(), tmp1); duke@435: __ st_ptr(tmp1, recv_addr); duke@435: Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - duke@435: mdo_offset_bias); duke@435: __ lduw(data_addr, tmp1); duke@435: __ add(tmp1, DataLayout::counter_increment, tmp1); duke@435: __ stw(tmp1, data_addr); duke@435: return; duke@435: } duke@435: } duke@435: } else { duke@435: load(Address(recv, 0, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); duke@435: Label update_done; duke@435: uint i; duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: Label next_test; duke@435: // See if the receiver is receiver[n]. duke@435: Address receiver_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - duke@435: mdo_offset_bias); duke@435: __ ld_ptr(receiver_addr, tmp1); duke@435: __ verify_oop(tmp1); duke@435: __ cmp(recv, tmp1); duke@435: __ brx(Assembler::notEqual, false, Assembler::pt, next_test); duke@435: __ delayed()->nop(); duke@435: Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - duke@435: mdo_offset_bias); duke@435: __ lduw(data_addr, tmp1); duke@435: __ add(tmp1, DataLayout::counter_increment, tmp1); duke@435: __ stw(tmp1, data_addr); duke@435: __ br(Assembler::always, false, Assembler::pt, update_done); duke@435: __ delayed()->nop(); duke@435: __ bind(next_test); duke@435: } duke@435: duke@435: // Didn't find receiver; find next empty slot and fill it in duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: Label next_test; duke@435: Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - duke@435: mdo_offset_bias); duke@435: load(recv_addr, tmp1, T_OBJECT); duke@435: __ tst(tmp1); duke@435: __ brx(Assembler::notEqual, false, Assembler::pt, next_test); duke@435: __ delayed()->nop(); duke@435: __ st_ptr(recv, recv_addr); duke@435: __ set(DataLayout::counter_increment, tmp1); duke@435: __ st_ptr(tmp1, Address(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - duke@435: mdo_offset_bias)); duke@435: if (i < (VirtualCallData::row_limit() - 1)) { duke@435: __ br(Assembler::always, false, Assembler::pt, update_done); duke@435: __ delayed()->nop(); duke@435: } duke@435: __ bind(next_test); duke@435: } duke@435: duke@435: __ bind(update_done); duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::align_backward_branch_target() { duke@435: __ align(16); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_delay(LIR_OpDelay* op) { duke@435: // make sure we are expecting a delay duke@435: // this has the side effect of clearing the delay state duke@435: // so we can use _masm instead of _masm->delayed() to do the duke@435: // code generation. duke@435: __ delayed(); duke@435: duke@435: // make sure we only emit one instruction duke@435: int offset = code_offset(); duke@435: op->delay_op()->emit_code(this); duke@435: #ifdef ASSERT duke@435: if (code_offset() - offset != NativeInstruction::nop_instruction_size) { duke@435: op->delay_op()->print(); duke@435: } duke@435: assert(code_offset() - offset == NativeInstruction::nop_instruction_size, duke@435: "only one instruction can go in a delay slot"); duke@435: #endif duke@435: duke@435: // we may also be emitting the call info for the instruction duke@435: // which we are the delay slot of. duke@435: CodeEmitInfo * call_info = op->call_info(); duke@435: if (call_info) { duke@435: add_call_info(code_offset(), call_info); duke@435: } duke@435: duke@435: if (VerifyStackAtCalls) { duke@435: _masm->sub(FP, SP, O7); duke@435: _masm->cmp(O7, initial_frame_size_in_bytes()); duke@435: _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { duke@435: assert(left->is_register(), "can only handle registers"); duke@435: duke@435: if (left->is_single_cpu()) { duke@435: __ neg(left->as_register(), dest->as_register()); duke@435: } else if (left->is_single_fpu()) { duke@435: __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); duke@435: } else if (left->is_double_fpu()) { duke@435: __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); duke@435: } else { duke@435: assert (left->is_double_cpu(), "Must be a long"); duke@435: Register Rlow = left->as_register_lo(); duke@435: Register Rhi = left->as_register_hi(); duke@435: #ifdef _LP64 duke@435: __ sub(G0, Rlow, dest->as_register_lo()); duke@435: #else duke@435: __ subcc(G0, Rlow, dest->as_register_lo()); duke@435: __ subc (G0, Rhi, dest->as_register_hi()); duke@435: #endif duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::fxch(int i) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: void LIR_Assembler::fld(int i) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: void LIR_Assembler::ffree(int i) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: void LIR_Assembler::rt_call(LIR_Opr result, address dest, duke@435: const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { duke@435: duke@435: // if tmp is invalid, then the function being called doesn't destroy the thread duke@435: if (tmp->is_valid()) { duke@435: __ save_thread(tmp->as_register()); duke@435: } duke@435: __ call(dest, relocInfo::runtime_call_type); duke@435: __ delayed()->nop(); duke@435: if (info != NULL) { duke@435: add_call_info_here(info); duke@435: } duke@435: if (tmp->is_valid()) { duke@435: __ restore_thread(tmp->as_register()); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: __ verify_thread(); duke@435: #endif // ASSERT duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { duke@435: #ifdef _LP64 duke@435: ShouldNotReachHere(); duke@435: #endif duke@435: duke@435: NEEDS_CLEANUP; duke@435: if (type == T_LONG) { duke@435: LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); duke@435: duke@435: // (extended to allow indexed as well as constant displaced for JSR-166) duke@435: Register idx = noreg; // contains either constant offset or index duke@435: duke@435: int disp = mem_addr->disp(); duke@435: if (mem_addr->index() == LIR_OprFact::illegalOpr) { duke@435: if (!Assembler::is_simm13(disp)) { duke@435: idx = O7; duke@435: __ set(disp, idx); duke@435: } duke@435: } else { duke@435: assert(disp == 0, "not both indexed and disp"); duke@435: idx = mem_addr->index()->as_register(); duke@435: } duke@435: duke@435: int null_check_offset = -1; duke@435: duke@435: Register base = mem_addr->base()->as_register(); duke@435: if (src->is_register() && dest->is_address()) { duke@435: // G4 is high half, G5 is low half duke@435: if (VM_Version::v9_instructions_work()) { duke@435: // clear the top bits of G5, and scale up G4 duke@435: __ srl (src->as_register_lo(), 0, G5); duke@435: __ sllx(src->as_register_hi(), 32, G4); duke@435: // combine the two halves into the 64 bits of G4 duke@435: __ or3(G4, G5, G4); duke@435: null_check_offset = __ offset(); duke@435: if (idx == noreg) { duke@435: __ stx(G4, base, disp); duke@435: } else { duke@435: __ stx(G4, base, idx); duke@435: } duke@435: } else { duke@435: __ mov (src->as_register_hi(), G4); duke@435: __ mov (src->as_register_lo(), G5); duke@435: null_check_offset = __ offset(); duke@435: if (idx == noreg) { duke@435: __ std(G4, base, disp); duke@435: } else { duke@435: __ std(G4, base, idx); duke@435: } duke@435: } duke@435: } else if (src->is_address() && dest->is_register()) { duke@435: null_check_offset = __ offset(); duke@435: if (VM_Version::v9_instructions_work()) { duke@435: if (idx == noreg) { duke@435: __ ldx(base, disp, G5); duke@435: } else { duke@435: __ ldx(base, idx, G5); duke@435: } duke@435: __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi duke@435: __ mov (G5, dest->as_register_lo()); // copy low half into lo duke@435: } else { duke@435: if (idx == noreg) { duke@435: __ ldd(base, disp, G4); duke@435: } else { duke@435: __ ldd(base, idx, G4); duke@435: } duke@435: // G4 is high half, G5 is low half duke@435: __ mov (G4, dest->as_register_hi()); duke@435: __ mov (G5, dest->as_register_lo()); duke@435: } duke@435: } else { duke@435: Unimplemented(); duke@435: } duke@435: if (info != NULL) { duke@435: add_debug_info_for_null_check(null_check_offset, info); duke@435: } duke@435: duke@435: } else { duke@435: // use normal move for all other volatiles since they don't need duke@435: // special handling to remain atomic. duke@435: move_op(src, dest, type, lir_patch_none, info, false, false); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::membar() { duke@435: // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode duke@435: __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); duke@435: } duke@435: duke@435: void LIR_Assembler::membar_acquire() { duke@435: // no-op on TSO duke@435: } duke@435: duke@435: void LIR_Assembler::membar_release() { duke@435: // no-op on TSO duke@435: } duke@435: duke@435: // Macro to Pack two sequential registers containing 32 bit values duke@435: // into a single 64 bit register. duke@435: // rs and rs->successor() are packed into rd duke@435: // rd and rs may be the same register. duke@435: // Note: rs and rs->successor() are destroyed. duke@435: void LIR_Assembler::pack64( Register rs, Register rd ) { duke@435: __ sllx(rs, 32, rs); duke@435: __ srl(rs->successor(), 0, rs->successor()); duke@435: __ or3(rs, rs->successor(), rd); duke@435: } duke@435: duke@435: // Macro to unpack a 64 bit value in a register into duke@435: // two sequential registers. duke@435: // rd is unpacked into rd and rd->successor() duke@435: void LIR_Assembler::unpack64( Register rd ) { duke@435: __ mov(rd, rd->successor()); duke@435: __ srax(rd, 32, rd); duke@435: __ sra(rd->successor(), 0, rd->successor()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { duke@435: LIR_Address* addr = addr_opr->as_address_ptr(); duke@435: assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); duke@435: __ add(addr->base()->as_register(), addr->disp(), dest->as_register()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::get_thread(LIR_Opr result_reg) { duke@435: assert(result_reg->is_register(), "check"); duke@435: __ mov(G2_thread, result_reg->as_register()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::peephole(LIR_List* lir) { duke@435: LIR_OpList* inst = lir->instructions_list(); duke@435: for (int i = 0; i < inst->length(); i++) { duke@435: LIR_Op* op = inst->at(i); duke@435: switch (op->code()) { duke@435: case lir_cond_float_branch: duke@435: case lir_branch: { duke@435: LIR_OpBranch* branch = op->as_OpBranch(); duke@435: assert(branch->info() == NULL, "shouldn't be state on branches anymore"); duke@435: LIR_Op* delay_op = NULL; duke@435: // we'd like to be able to pull following instructions into duke@435: // this slot but we don't know enough to do it safely yet so duke@435: // only optimize block to block control flow. duke@435: if (LIRFillDelaySlots && branch->block()) { duke@435: LIR_Op* prev = inst->at(i - 1); duke@435: if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { duke@435: // swap previous instruction into delay slot duke@435: inst->at_put(i - 1, op); duke@435: inst->at_put(i, new LIR_OpDelay(prev, op->info())); duke@435: #ifndef PRODUCT duke@435: if (LIRTracePeephole) { duke@435: tty->print_cr("delayed"); duke@435: inst->at(i - 1)->print(); duke@435: inst->at(i)->print(); duke@435: } duke@435: #endif duke@435: continue; duke@435: } duke@435: } duke@435: duke@435: if (!delay_op) { duke@435: delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); duke@435: } duke@435: inst->insert_before(i + 1, delay_op); duke@435: break; duke@435: } duke@435: case lir_static_call: duke@435: case lir_virtual_call: duke@435: case lir_icvirtual_call: duke@435: case lir_optvirtual_call: { duke@435: LIR_Op* delay_op = NULL; duke@435: LIR_Op* prev = inst->at(i - 1); duke@435: if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && duke@435: (op->code() != lir_virtual_call || duke@435: !prev->result_opr()->is_single_cpu() || duke@435: prev->result_opr()->as_register() != O0) && duke@435: LIR_Assembler::is_single_instruction(prev)) { duke@435: // Only moves without info can be put into the delay slot. duke@435: // Also don't allow the setup of the receiver in the delay duke@435: // slot for vtable calls. duke@435: inst->at_put(i - 1, op); duke@435: inst->at_put(i, new LIR_OpDelay(prev, op->info())); duke@435: #ifndef PRODUCT duke@435: if (LIRTracePeephole) { duke@435: tty->print_cr("delayed"); duke@435: inst->at(i - 1)->print(); duke@435: inst->at(i)->print(); duke@435: } duke@435: #endif duke@435: continue; duke@435: } duke@435: duke@435: if (!delay_op) { duke@435: delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); duke@435: inst->insert_before(i + 1, delay_op); duke@435: } duke@435: break; duke@435: } duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: duke@435: duke@435: #undef __