twisti@4318: /* twisti@4318: * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. twisti@4318: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. twisti@4318: * twisti@4318: * This code is free software; you can redistribute it and/or modify it twisti@4318: * under the terms of the GNU General Public License version 2 only, as twisti@4318: * published by the Free Software Foundation. twisti@4318: * twisti@4318: * This code is distributed in the hope that it will be useful, but WITHOUT twisti@4318: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or twisti@4318: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License twisti@4318: * version 2 for more details (a copy is included in the LICENSE file that twisti@4318: * accompanied this code). twisti@4318: * twisti@4318: * You should have received a copy of the GNU General Public License version twisti@4318: * 2 along with this work; if not, write to the Free Software Foundation, twisti@4318: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. twisti@4318: * twisti@4318: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA twisti@4318: * or visit www.oracle.com if you need additional information or have any twisti@4318: * questions. twisti@4318: * twisti@4318: */ twisti@4318: twisti@4318: #include "precompiled.hpp" twisti@4318: #include "asm/assembler.hpp" twisti@4318: #include "asm/assembler.inline.hpp" twisti@4318: #include "compiler/disassembler.hpp" twisti@4318: #include "gc_interface/collectedHeap.inline.hpp" twisti@4318: #include "interpreter/interpreter.hpp" twisti@4318: #include "memory/cardTableModRefBS.hpp" twisti@4318: #include "memory/resourceArea.hpp" twisti@4318: #include "prims/methodHandles.hpp" twisti@4318: #include "runtime/biasedLocking.hpp" twisti@4318: #include "runtime/interfaceSupport.hpp" twisti@4318: #include "runtime/objectMonitor.hpp" twisti@4318: #include "runtime/os.hpp" twisti@4318: #include "runtime/sharedRuntime.hpp" twisti@4318: #include "runtime/stubRoutines.hpp" jprovino@4542: #include "utilities/macros.hpp" jprovino@4542: #if INCLUDE_ALL_GCS twisti@4318: #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" twisti@4318: #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" twisti@4318: #include "gc_implementation/g1/heapRegion.hpp" jprovino@4542: #endif // INCLUDE_ALL_GCS twisti@4318: twisti@4318: #ifdef PRODUCT twisti@4318: #define BLOCK_COMMENT(str) /* nothing */ twisti@4318: #define STOP(error) stop(error) twisti@4318: #else twisti@4318: #define BLOCK_COMMENT(str) block_comment(str) twisti@4318: #define STOP(error) block_comment(error); stop(error) twisti@4318: #endif twisti@4318: twisti@4318: #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") twisti@4318: twisti@4318: twisti@4323: #ifdef ASSERT twisti@4323: bool AbstractAssembler::pd_check_instruction_mark() { return true; } twisti@4323: #endif twisti@4323: twisti@4318: static Assembler::Condition reverse[] = { twisti@4318: Assembler::noOverflow /* overflow = 0x0 */ , twisti@4318: Assembler::overflow /* noOverflow = 0x1 */ , twisti@4318: Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , twisti@4318: Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , twisti@4318: Assembler::notZero /* zero = 0x4, equal = 0x4 */ , twisti@4318: Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , twisti@4318: Assembler::above /* belowEqual = 0x6 */ , twisti@4318: Assembler::belowEqual /* above = 0x7 */ , twisti@4318: Assembler::positive /* negative = 0x8 */ , twisti@4318: Assembler::negative /* positive = 0x9 */ , twisti@4318: Assembler::noParity /* parity = 0xa */ , twisti@4318: Assembler::parity /* noParity = 0xb */ , twisti@4318: Assembler::greaterEqual /* less = 0xc */ , twisti@4318: Assembler::less /* greaterEqual = 0xd */ , twisti@4318: Assembler::greater /* lessEqual = 0xe */ , twisti@4318: Assembler::lessEqual /* greater = 0xf, */ twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: twisti@4318: // Implementation of MacroAssembler twisti@4318: twisti@4318: // First all the versions that have distinct versions depending on 32/64 bit twisti@4318: // Unless the difference is trivial (1 line or so). twisti@4318: twisti@4318: #ifndef _LP64 twisti@4318: twisti@4318: // 32bit versions twisti@4318: twisti@4318: Address MacroAssembler::as_Address(AddressLiteral adr) { twisti@4318: return Address(adr.target(), adr.rspec()); twisti@4318: } twisti@4318: twisti@4318: Address MacroAssembler::as_Address(ArrayAddress adr) { twisti@4318: return Address::make_array(adr); twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::biased_locking_enter(Register lock_reg, twisti@4318: Register obj_reg, twisti@4318: Register swap_reg, twisti@4318: Register tmp_reg, twisti@4318: bool swap_reg_contains_mark, twisti@4318: Label& done, twisti@4318: Label* slow_case, twisti@4318: BiasedLockingCounters* counters) { twisti@4318: assert(UseBiasedLocking, "why call this otherwise?"); twisti@4318: assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); twisti@4318: assert_different_registers(lock_reg, obj_reg, swap_reg); twisti@4318: twisti@4318: if (PrintBiasedLockingStatistics && counters == NULL) twisti@4318: counters = BiasedLocking::counters(); twisti@4318: twisti@4318: bool need_tmp_reg = false; twisti@4318: if (tmp_reg == noreg) { twisti@4318: need_tmp_reg = true; twisti@4318: tmp_reg = lock_reg; twisti@4318: } else { twisti@4318: assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); twisti@4318: } twisti@4318: assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); twisti@4318: Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); twisti@4318: Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); twisti@4318: Address saved_mark_addr(lock_reg, 0); twisti@4318: twisti@4318: // Biased locking twisti@4318: // See whether the lock is currently biased toward our thread and twisti@4318: // whether the epoch is still valid twisti@4318: // Note that the runtime guarantees sufficient alignment of JavaThread twisti@4318: // pointers to allow age to be placed into low bits twisti@4318: // First check to see whether biasing is even enabled for this object twisti@4318: Label cas_label; twisti@4318: int null_check_offset = -1; twisti@4318: if (!swap_reg_contains_mark) { twisti@4318: null_check_offset = offset(); twisti@4318: movl(swap_reg, mark_addr); twisti@4318: } twisti@4318: if (need_tmp_reg) { twisti@4318: push(tmp_reg); twisti@4318: } twisti@4318: movl(tmp_reg, swap_reg); twisti@4318: andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); twisti@4318: cmpl(tmp_reg, markOopDesc::biased_lock_pattern); twisti@4318: if (need_tmp_reg) { twisti@4318: pop(tmp_reg); twisti@4318: } twisti@4318: jcc(Assembler::notEqual, cas_label); twisti@4318: // The bias pattern is present in the object's header. Need to check twisti@4318: // whether the bias owner and the epoch are both still current. twisti@4318: // Note that because there is no current thread register on x86 we twisti@4318: // need to store off the mark word we read out of the object to twisti@4318: // avoid reloading it and needing to recheck invariants below. This twisti@4318: // store is unfortunate but it makes the overall code shorter and twisti@4318: // simpler. twisti@4318: movl(saved_mark_addr, swap_reg); twisti@4318: if (need_tmp_reg) { twisti@4318: push(tmp_reg); twisti@4318: } twisti@4318: get_thread(tmp_reg); twisti@4318: xorl(swap_reg, tmp_reg); twisti@4318: if (swap_reg_contains_mark) { twisti@4318: null_check_offset = offset(); twisti@4318: } twisti@4318: movl(tmp_reg, klass_addr); twisti@4318: xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); twisti@4318: andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); twisti@4318: if (need_tmp_reg) { twisti@4318: pop(tmp_reg); twisti@4318: } twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address)counters->biased_lock_entry_count_addr())); twisti@4318: } twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: Label try_revoke_bias; twisti@4318: Label try_rebias; twisti@4318: twisti@4318: // At this point we know that the header has the bias pattern and twisti@4318: // that we are not the bias owner in the current epoch. We need to twisti@4318: // figure out more details about the state of the header in order to twisti@4318: // know what operations can be legally performed on the object's twisti@4318: // header. twisti@4318: twisti@4318: // If the low three bits in the xor result aren't clear, that means twisti@4318: // the prototype header is no longer biased and we have to revoke twisti@4318: // the bias on this object. twisti@4318: testl(swap_reg, markOopDesc::biased_lock_mask_in_place); twisti@4318: jcc(Assembler::notZero, try_revoke_bias); twisti@4318: twisti@4318: // Biasing is still enabled for this data type. See whether the twisti@4318: // epoch of the current bias is still valid, meaning that the epoch twisti@4318: // bits of the mark word are equal to the epoch bits of the twisti@4318: // prototype header. (Note that the prototype header's epoch bits twisti@4318: // only change at a safepoint.) If not, attempt to rebias the object twisti@4318: // toward the current thread. Note that we must be absolutely sure twisti@4318: // that the current epoch is invalid in order to do this because twisti@4318: // otherwise the manipulations it performs on the mark word are twisti@4318: // illegal. twisti@4318: testl(swap_reg, markOopDesc::epoch_mask_in_place); twisti@4318: jcc(Assembler::notZero, try_rebias); twisti@4318: twisti@4318: // The epoch of the current bias is still valid but we know nothing twisti@4318: // about the owner; it might be set or it might be clear. Try to twisti@4318: // acquire the bias of the object using an atomic operation. If this twisti@4318: // fails we will go in to the runtime to revoke the object's bias. twisti@4318: // Note that we first construct the presumed unbiased header so we twisti@4318: // don't accidentally blow away another thread's valid bias. twisti@4318: movl(swap_reg, saved_mark_addr); twisti@4318: andl(swap_reg, twisti@4318: markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); twisti@4318: if (need_tmp_reg) { twisti@4318: push(tmp_reg); twisti@4318: } twisti@4318: get_thread(tmp_reg); twisti@4318: orl(tmp_reg, swap_reg); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgptr(tmp_reg, Address(obj_reg, 0)); twisti@4318: if (need_tmp_reg) { twisti@4318: pop(tmp_reg); twisti@4318: } twisti@4318: // If the biasing toward our thread failed, this means that twisti@4318: // another thread succeeded in biasing it toward itself and we twisti@4318: // need to revoke that bias. The revocation will occur in the twisti@4318: // interpreter runtime in the slow case. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); twisti@4318: } twisti@4318: if (slow_case != NULL) { twisti@4318: jcc(Assembler::notZero, *slow_case); twisti@4318: } twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(try_rebias); twisti@4318: // At this point we know the epoch has expired, meaning that the twisti@4318: // current "bias owner", if any, is actually invalid. Under these twisti@4318: // circumstances _only_, we are allowed to use the current header's twisti@4318: // value as the comparison value when doing the cas to acquire the twisti@4318: // bias in the current epoch. In other words, we allow transfer of twisti@4318: // the bias from one thread to another directly in this situation. twisti@4318: // twisti@4318: // FIXME: due to a lack of registers we currently blow away the age twisti@4318: // bits in this situation. Should attempt to preserve them. twisti@4318: if (need_tmp_reg) { twisti@4318: push(tmp_reg); twisti@4318: } twisti@4318: get_thread(tmp_reg); twisti@4318: movl(swap_reg, klass_addr); twisti@4318: orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); twisti@4318: movl(swap_reg, saved_mark_addr); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgptr(tmp_reg, Address(obj_reg, 0)); twisti@4318: if (need_tmp_reg) { twisti@4318: pop(tmp_reg); twisti@4318: } twisti@4318: // If the biasing toward our thread failed, then another thread twisti@4318: // succeeded in biasing it toward itself and we need to revoke that twisti@4318: // bias. The revocation will occur in the runtime in the slow case. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); twisti@4318: } twisti@4318: if (slow_case != NULL) { twisti@4318: jcc(Assembler::notZero, *slow_case); twisti@4318: } twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(try_revoke_bias); twisti@4318: // The prototype mark in the klass doesn't have the bias bit set any twisti@4318: // more, indicating that objects of this data type are not supposed twisti@4318: // to be biased any more. We are going to try to reset the mark of twisti@4318: // this object to the prototype value and fall through to the twisti@4318: // CAS-based locking scheme. Note that if our CAS fails, it means twisti@4318: // that another thread raced us for the privilege of revoking the twisti@4318: // bias of this particular object, so it's okay to continue in the twisti@4318: // normal locking code. twisti@4318: // twisti@4318: // FIXME: due to a lack of registers we currently blow away the age twisti@4318: // bits in this situation. Should attempt to preserve them. twisti@4318: movl(swap_reg, saved_mark_addr); twisti@4318: if (need_tmp_reg) { twisti@4318: push(tmp_reg); twisti@4318: } twisti@4318: movl(tmp_reg, klass_addr); twisti@4318: movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgptr(tmp_reg, Address(obj_reg, 0)); twisti@4318: if (need_tmp_reg) { twisti@4318: pop(tmp_reg); twisti@4318: } twisti@4318: // Fall through to the normal CAS-based lock, because no matter what twisti@4318: // the result of the above CAS, some thread must have succeeded in twisti@4318: // removing the bias bit from the object's header. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address)counters->revoked_lock_entry_count_addr())); twisti@4318: } twisti@4318: twisti@4318: bind(cas_label); twisti@4318: twisti@4318: return null_check_offset; twisti@4318: } twisti@4318: void MacroAssembler::call_VM_leaf_base(address entry_point, twisti@4318: int number_of_arguments) { twisti@4318: call(RuntimeAddress(entry_point)); twisti@4318: increment(rsp, number_of_arguments * wordSize); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpklass(Address src1, Metadata* obj) { twisti@4318: cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpklass(Register src1, Metadata* obj) { twisti@4318: cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpoop(Address src1, jobject obj) { twisti@4318: cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpoop(Register src1, jobject obj) { twisti@4318: cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::extend_sign(Register hi, Register lo) { twisti@4318: // According to Intel Doc. AP-526, "Integer Divide", p.18. twisti@4318: if (VM_Version::is_P6() && hi == rdx && lo == rax) { twisti@4318: cdql(); twisti@4318: } else { twisti@4318: movl(hi, lo); twisti@4318: sarl(hi, 31); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::jC2(Register tmp, Label& L) { twisti@4318: // set parity bit if FPU flag C2 is set (via rax) twisti@4318: save_rax(tmp); twisti@4318: fwait(); fnstsw_ax(); twisti@4318: sahf(); twisti@4318: restore_rax(tmp); twisti@4318: // branch twisti@4318: jcc(Assembler::parity, L); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::jnC2(Register tmp, Label& L) { twisti@4318: // set parity bit if FPU flag C2 is set (via rax) twisti@4318: save_rax(tmp); twisti@4318: fwait(); fnstsw_ax(); twisti@4318: sahf(); twisti@4318: restore_rax(tmp); twisti@4318: // branch twisti@4318: jcc(Assembler::noParity, L); twisti@4318: } twisti@4318: twisti@4318: // 32bit can do a case table jump in one instruction but we no longer allow the base twisti@4318: // to be installed in the Address class twisti@4318: void MacroAssembler::jump(ArrayAddress entry) { twisti@4318: jmp(as_Address(entry)); twisti@4318: } twisti@4318: twisti@4318: // Note: y_lo will be destroyed twisti@4318: void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { twisti@4318: // Long compare for Java (semantics as described in JVM spec.) twisti@4318: Label high, low, done; twisti@4318: twisti@4318: cmpl(x_hi, y_hi); twisti@4318: jcc(Assembler::less, low); twisti@4318: jcc(Assembler::greater, high); twisti@4318: // x_hi is the return register twisti@4318: xorl(x_hi, x_hi); twisti@4318: cmpl(x_lo, y_lo); twisti@4318: jcc(Assembler::below, low); twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: bind(high); twisti@4318: xorl(x_hi, x_hi); twisti@4318: increment(x_hi); twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(low); twisti@4318: xorl(x_hi, x_hi); twisti@4318: decrementl(x_hi); twisti@4318: twisti@4318: bind(done); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lea(Register dst, AddressLiteral src) { twisti@4318: mov_literal32(dst, (int32_t)src.target(), src.rspec()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lea(Address dst, AddressLiteral adr) { twisti@4318: // leal(dst, as_Address(adr)); twisti@4318: // see note in movl as to why we must use a move twisti@4318: mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::leave() { twisti@4318: mov(rsp, rbp); twisti@4318: pop(rbp); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { twisti@4318: // Multiplication of two Java long values stored on the stack twisti@4318: // as illustrated below. Result is in rdx:rax. twisti@4318: // twisti@4318: // rsp ---> [ ?? ] \ \ twisti@4318: // .... | y_rsp_offset | twisti@4318: // [ y_lo ] / (in bytes) | x_rsp_offset twisti@4318: // [ y_hi ] | (in bytes) twisti@4318: // .... | twisti@4318: // [ x_lo ] / twisti@4318: // [ x_hi ] twisti@4318: // .... twisti@4318: // twisti@4318: // Basic idea: lo(result) = lo(x_lo * y_lo) twisti@4318: // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) twisti@4318: Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); twisti@4318: Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); twisti@4318: Label quick; twisti@4318: // load x_hi, y_hi and check if quick twisti@4318: // multiplication is possible twisti@4318: movl(rbx, x_hi); twisti@4318: movl(rcx, y_hi); twisti@4318: movl(rax, rbx); twisti@4318: orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 twisti@4318: jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply twisti@4318: // do full multiplication twisti@4318: // 1st step twisti@4318: mull(y_lo); // x_hi * y_lo twisti@4318: movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, twisti@4318: // 2nd step twisti@4318: movl(rax, x_lo); twisti@4318: mull(rcx); // x_lo * y_hi twisti@4318: addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, twisti@4318: // 3rd step twisti@4318: bind(quick); // note: rbx, = 0 if quick multiply! twisti@4318: movl(rax, x_lo); twisti@4318: mull(y_lo); // x_lo * y_lo twisti@4318: addl(rdx, rbx); // correct hi(x_lo * y_lo) twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lneg(Register hi, Register lo) { twisti@4318: negl(lo); twisti@4318: adcl(hi, 0); twisti@4318: negl(hi); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lshl(Register hi, Register lo) { twisti@4318: // Java shift left long support (semantics as described in JVM spec., p.305) twisti@4318: // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) twisti@4318: // shift value is in rcx ! twisti@4318: assert(hi != rcx, "must not use rcx"); twisti@4318: assert(lo != rcx, "must not use rcx"); twisti@4318: const Register s = rcx; // shift count twisti@4318: const int n = BitsPerWord; twisti@4318: Label L; twisti@4318: andl(s, 0x3f); // s := s & 0x3f (s < 0x40) twisti@4318: cmpl(s, n); // if (s < n) twisti@4318: jcc(Assembler::less, L); // else (s >= n) twisti@4318: movl(hi, lo); // x := x << n twisti@4318: xorl(lo, lo); twisti@4318: // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! twisti@4318: bind(L); // s (mod n) < n twisti@4318: shldl(hi, lo); // x := x << s twisti@4318: shll(lo); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { twisti@4318: // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) twisti@4318: // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) twisti@4318: assert(hi != rcx, "must not use rcx"); twisti@4318: assert(lo != rcx, "must not use rcx"); twisti@4318: const Register s = rcx; // shift count twisti@4318: const int n = BitsPerWord; twisti@4318: Label L; twisti@4318: andl(s, 0x3f); // s := s & 0x3f (s < 0x40) twisti@4318: cmpl(s, n); // if (s < n) twisti@4318: jcc(Assembler::less, L); // else (s >= n) twisti@4318: movl(lo, hi); // x := x >> n twisti@4318: if (sign_extension) sarl(hi, 31); twisti@4318: else xorl(hi, hi); twisti@4318: // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! twisti@4318: bind(L); // s (mod n) < n twisti@4318: shrdl(lo, hi); // x := x >> s twisti@4318: if (sign_extension) sarl(hi); twisti@4318: else shrl(hi); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movoop(Register dst, jobject obj) { twisti@4318: mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movoop(Address dst, jobject obj) { twisti@4318: mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { twisti@4318: mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { twisti@4318: mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, AddressLiteral src) { twisti@4318: if (src.is_lval()) { twisti@4318: mov_literal32(dst, (intptr_t)src.target(), src.rspec()); twisti@4318: } else { twisti@4318: movl(dst, as_Address(src)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(ArrayAddress dst, Register src) { twisti@4318: movl(as_Address(dst), src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, ArrayAddress src) { twisti@4318: movl(dst, as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: // src should NEVER be a real pointer. Use AddressLiteral for true pointers twisti@4318: void MacroAssembler::movptr(Address dst, intptr_t src) { twisti@4318: movl(dst, src); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::pop_callee_saved_registers() { twisti@4318: pop(rcx); twisti@4318: pop(rdx); twisti@4318: pop(rdi); twisti@4318: pop(rsi); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pop_fTOS() { twisti@4318: fld_d(Address(rsp, 0)); twisti@4318: addl(rsp, 2 * wordSize); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::push_callee_saved_registers() { twisti@4318: push(rsi); twisti@4318: push(rdi); twisti@4318: push(rdx); twisti@4318: push(rcx); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::push_fTOS() { twisti@4318: subl(rsp, 2 * wordSize); twisti@4318: fstp_d(Address(rsp, 0)); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::pushoop(jobject obj) { twisti@4318: push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pushklass(Metadata* obj) { twisti@4318: push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pushptr(AddressLiteral src) { twisti@4318: if (src.is_lval()) { twisti@4318: push_literal32((int32_t)src.target(), src.rspec()); twisti@4318: } else { twisti@4318: pushl(as_Address(src)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_word_if_not_zero(Register dst) { twisti@4318: xorl(dst, dst); twisti@4318: set_byte_if_not_zero(dst); twisti@4318: } twisti@4318: twisti@4318: static void pass_arg0(MacroAssembler* masm, Register arg) { twisti@4318: masm->push(arg); twisti@4318: } twisti@4318: twisti@4318: static void pass_arg1(MacroAssembler* masm, Register arg) { twisti@4318: masm->push(arg); twisti@4318: } twisti@4318: twisti@4318: static void pass_arg2(MacroAssembler* masm, Register arg) { twisti@4318: masm->push(arg); twisti@4318: } twisti@4318: twisti@4318: static void pass_arg3(MacroAssembler* masm, Register arg) { twisti@4318: masm->push(arg); twisti@4318: } twisti@4318: twisti@4318: #ifndef PRODUCT twisti@4318: extern "C" void findpc(intptr_t x); twisti@4318: #endif twisti@4318: twisti@4318: void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { twisti@4318: // In order to get locks to work, we need to fake a in_VM state twisti@4318: JavaThread* thread = JavaThread::current(); twisti@4318: JavaThreadState saved_state = thread->thread_state(); twisti@4318: thread->set_thread_state(_thread_in_vm); twisti@4318: if (ShowMessageBoxOnError) { twisti@4318: JavaThread* thread = JavaThread::current(); twisti@4318: JavaThreadState saved_state = thread->thread_state(); twisti@4318: thread->set_thread_state(_thread_in_vm); twisti@4318: if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { twisti@4318: ttyLocker ttyl; twisti@4318: BytecodeCounter::print(); twisti@4318: } twisti@4318: // To see where a verify_oop failed, get $ebx+40/X for this frame. twisti@4318: // This is the value of eip which points to where verify_oop will return. twisti@4318: if (os::message_box(msg, "Execution stopped, print registers?")) { twisti@4318: print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); twisti@4318: BREAKPOINT; twisti@4318: } twisti@4318: } else { twisti@4318: ttyLocker ttyl; twisti@4318: ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); twisti@4318: } twisti@4318: // Don't assert holding the ttyLock twisti@4318: assert(false, err_msg("DEBUG MESSAGE: %s", msg)); twisti@4318: ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { twisti@4318: ttyLocker ttyl; twisti@4318: FlagSetting fs(Debugging, true); twisti@4318: tty->print_cr("eip = 0x%08x", eip); twisti@4318: #ifndef PRODUCT twisti@4318: if ((WizardMode || Verbose) && PrintMiscellaneous) { twisti@4318: tty->cr(); twisti@4318: findpc(eip); twisti@4318: tty->cr(); twisti@4318: } twisti@4318: #endif twisti@4318: #define PRINT_REG(rax) \ twisti@4318: { tty->print("%s = ", #rax); os::print_location(tty, rax); } twisti@4318: PRINT_REG(rax); twisti@4318: PRINT_REG(rbx); twisti@4318: PRINT_REG(rcx); twisti@4318: PRINT_REG(rdx); twisti@4318: PRINT_REG(rdi); twisti@4318: PRINT_REG(rsi); twisti@4318: PRINT_REG(rbp); twisti@4318: PRINT_REG(rsp); twisti@4318: #undef PRINT_REG twisti@4318: // Print some words near top of staack. twisti@4318: int* dump_sp = (int*) rsp; twisti@4318: for (int col1 = 0; col1 < 8; col1++) { twisti@4318: tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); twisti@4318: os::print_location(tty, *dump_sp++); twisti@4318: } twisti@4318: for (int row = 0; row < 16; row++) { twisti@4318: tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); twisti@4318: for (int col = 0; col < 8; col++) { twisti@4318: tty->print(" 0x%08x", *dump_sp++); twisti@4318: } twisti@4318: tty->cr(); twisti@4318: } twisti@4318: // Print some instructions around pc: twisti@4318: Disassembler::decode((address)eip-64, (address)eip); twisti@4318: tty->print_cr("--------"); twisti@4318: Disassembler::decode((address)eip, (address)eip+32); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::stop(const char* msg) { twisti@4318: ExternalAddress message((address)msg); twisti@4318: // push address of message twisti@4318: pushptr(message.addr()); twisti@4318: { Label L; call(L, relocInfo::none); bind(L); } // push eip twisti@4318: pusha(); // push registers twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); twisti@4318: hlt(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::warn(const char* msg) { twisti@4318: push_CPU_state(); twisti@4318: twisti@4318: ExternalAddress message((address) msg); twisti@4318: // push address of message twisti@4318: pushptr(message.addr()); twisti@4318: twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); twisti@4318: addl(rsp, wordSize); // discard argument twisti@4318: pop_CPU_state(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::print_state() { twisti@4318: { Label L; call(L, relocInfo::none); bind(L); } // push eip twisti@4318: pusha(); // push registers twisti@4318: twisti@4318: push_CPU_state(); twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); twisti@4318: pop_CPU_state(); twisti@4318: twisti@4318: popa(); twisti@4318: addl(rsp, wordSize); twisti@4318: } twisti@4318: twisti@4318: #else // _LP64 twisti@4318: twisti@4318: // 64 bit versions twisti@4318: twisti@4318: Address MacroAssembler::as_Address(AddressLiteral adr) { twisti@4318: // amd64 always does this as a pc-rel twisti@4318: // we can be absolute or disp based on the instruction type twisti@4318: // jmp/call are displacements others are absolute twisti@4318: assert(!adr.is_lval(), "must be rval"); twisti@4318: assert(reachable(adr), "must be"); twisti@4318: return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); twisti@4318: twisti@4318: } twisti@4318: twisti@4318: Address MacroAssembler::as_Address(ArrayAddress adr) { twisti@4318: AddressLiteral base = adr.base(); twisti@4318: lea(rscratch1, base); twisti@4318: Address index = adr.index(); twisti@4318: assert(index._disp == 0, "must not have disp"); // maybe it can? twisti@4318: Address array(rscratch1, index._index, index._scale, index._disp); twisti@4318: return array; twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::biased_locking_enter(Register lock_reg, twisti@4318: Register obj_reg, twisti@4318: Register swap_reg, twisti@4318: Register tmp_reg, twisti@4318: bool swap_reg_contains_mark, twisti@4318: Label& done, twisti@4318: Label* slow_case, twisti@4318: BiasedLockingCounters* counters) { twisti@4318: assert(UseBiasedLocking, "why call this otherwise?"); twisti@4318: assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); twisti@4318: assert(tmp_reg != noreg, "tmp_reg must be supplied"); twisti@4318: assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); twisti@4318: assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); twisti@4318: Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); twisti@4318: Address saved_mark_addr(lock_reg, 0); twisti@4318: twisti@4318: if (PrintBiasedLockingStatistics && counters == NULL) twisti@4318: counters = BiasedLocking::counters(); twisti@4318: twisti@4318: // Biased locking twisti@4318: // See whether the lock is currently biased toward our thread and twisti@4318: // whether the epoch is still valid twisti@4318: // Note that the runtime guarantees sufficient alignment of JavaThread twisti@4318: // pointers to allow age to be placed into low bits twisti@4318: // First check to see whether biasing is even enabled for this object twisti@4318: Label cas_label; twisti@4318: int null_check_offset = -1; twisti@4318: if (!swap_reg_contains_mark) { twisti@4318: null_check_offset = offset(); twisti@4318: movq(swap_reg, mark_addr); twisti@4318: } twisti@4318: movq(tmp_reg, swap_reg); twisti@4318: andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); twisti@4318: cmpq(tmp_reg, markOopDesc::biased_lock_pattern); twisti@4318: jcc(Assembler::notEqual, cas_label); twisti@4318: // The bias pattern is present in the object's header. Need to check twisti@4318: // whether the bias owner and the epoch are both still current. twisti@4318: load_prototype_header(tmp_reg, obj_reg); twisti@4318: orq(tmp_reg, r15_thread); twisti@4318: xorq(tmp_reg, swap_reg); twisti@4318: andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); twisti@4318: } twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: Label try_revoke_bias; twisti@4318: Label try_rebias; twisti@4318: twisti@4318: // At this point we know that the header has the bias pattern and twisti@4318: // that we are not the bias owner in the current epoch. We need to twisti@4318: // figure out more details about the state of the header in order to twisti@4318: // know what operations can be legally performed on the object's twisti@4318: // header. twisti@4318: twisti@4318: // If the low three bits in the xor result aren't clear, that means twisti@4318: // the prototype header is no longer biased and we have to revoke twisti@4318: // the bias on this object. twisti@4318: testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); twisti@4318: jcc(Assembler::notZero, try_revoke_bias); twisti@4318: twisti@4318: // Biasing is still enabled for this data type. See whether the twisti@4318: // epoch of the current bias is still valid, meaning that the epoch twisti@4318: // bits of the mark word are equal to the epoch bits of the twisti@4318: // prototype header. (Note that the prototype header's epoch bits twisti@4318: // only change at a safepoint.) If not, attempt to rebias the object twisti@4318: // toward the current thread. Note that we must be absolutely sure twisti@4318: // that the current epoch is invalid in order to do this because twisti@4318: // otherwise the manipulations it performs on the mark word are twisti@4318: // illegal. twisti@4318: testq(tmp_reg, markOopDesc::epoch_mask_in_place); twisti@4318: jcc(Assembler::notZero, try_rebias); twisti@4318: twisti@4318: // The epoch of the current bias is still valid but we know nothing twisti@4318: // about the owner; it might be set or it might be clear. Try to twisti@4318: // acquire the bias of the object using an atomic operation. If this twisti@4318: // fails we will go in to the runtime to revoke the object's bias. twisti@4318: // Note that we first construct the presumed unbiased header so we twisti@4318: // don't accidentally blow away another thread's valid bias. twisti@4318: andq(swap_reg, twisti@4318: markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); twisti@4318: movq(tmp_reg, swap_reg); twisti@4318: orq(tmp_reg, r15_thread); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgq(tmp_reg, Address(obj_reg, 0)); twisti@4318: // If the biasing toward our thread failed, this means that twisti@4318: // another thread succeeded in biasing it toward itself and we twisti@4318: // need to revoke that bias. The revocation will occur in the twisti@4318: // interpreter runtime in the slow case. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); twisti@4318: } twisti@4318: if (slow_case != NULL) { twisti@4318: jcc(Assembler::notZero, *slow_case); twisti@4318: } twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(try_rebias); twisti@4318: // At this point we know the epoch has expired, meaning that the twisti@4318: // current "bias owner", if any, is actually invalid. Under these twisti@4318: // circumstances _only_, we are allowed to use the current header's twisti@4318: // value as the comparison value when doing the cas to acquire the twisti@4318: // bias in the current epoch. In other words, we allow transfer of twisti@4318: // the bias from one thread to another directly in this situation. twisti@4318: // twisti@4318: // FIXME: due to a lack of registers we currently blow away the age twisti@4318: // bits in this situation. Should attempt to preserve them. twisti@4318: load_prototype_header(tmp_reg, obj_reg); twisti@4318: orq(tmp_reg, r15_thread); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgq(tmp_reg, Address(obj_reg, 0)); twisti@4318: // If the biasing toward our thread failed, then another thread twisti@4318: // succeeded in biasing it toward itself and we need to revoke that twisti@4318: // bias. The revocation will occur in the runtime in the slow case. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); twisti@4318: } twisti@4318: if (slow_case != NULL) { twisti@4318: jcc(Assembler::notZero, *slow_case); twisti@4318: } twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(try_revoke_bias); twisti@4318: // The prototype mark in the klass doesn't have the bias bit set any twisti@4318: // more, indicating that objects of this data type are not supposed twisti@4318: // to be biased any more. We are going to try to reset the mark of twisti@4318: // this object to the prototype value and fall through to the twisti@4318: // CAS-based locking scheme. Note that if our CAS fails, it means twisti@4318: // that another thread raced us for the privilege of revoking the twisti@4318: // bias of this particular object, so it's okay to continue in the twisti@4318: // normal locking code. twisti@4318: // twisti@4318: // FIXME: due to a lack of registers we currently blow away the age twisti@4318: // bits in this situation. Should attempt to preserve them. twisti@4318: load_prototype_header(tmp_reg, obj_reg); twisti@4318: if (os::is_MP()) { twisti@4318: lock(); twisti@4318: } twisti@4318: cmpxchgq(tmp_reg, Address(obj_reg, 0)); twisti@4318: // Fall through to the normal CAS-based lock, because no matter what twisti@4318: // the result of the above CAS, some thread must have succeeded in twisti@4318: // removing the bias bit from the object's header. twisti@4318: if (counters != NULL) { twisti@4318: cond_inc32(Assembler::zero, twisti@4318: ExternalAddress((address) counters->revoked_lock_entry_count_addr())); twisti@4318: } twisti@4318: twisti@4318: bind(cas_label); twisti@4318: twisti@4318: return null_check_offset; twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { twisti@4318: Label L, E; twisti@4318: twisti@4318: #ifdef _WIN64 twisti@4318: // Windows always allocates space for it's register args twisti@4318: assert(num_args <= 4, "only register arguments supported"); twisti@4318: subq(rsp, frame::arg_reg_save_area_bytes); twisti@4318: #endif twisti@4318: twisti@4318: // Align stack if necessary twisti@4318: testl(rsp, 15); twisti@4318: jcc(Assembler::zero, L); twisti@4318: twisti@4318: subq(rsp, 8); twisti@4318: { twisti@4318: call(RuntimeAddress(entry_point)); twisti@4318: } twisti@4318: addq(rsp, 8); twisti@4318: jmp(E); twisti@4318: twisti@4318: bind(L); twisti@4318: { twisti@4318: call(RuntimeAddress(entry_point)); twisti@4318: } twisti@4318: twisti@4318: bind(E); twisti@4318: twisti@4318: #ifdef _WIN64 twisti@4318: // restore stack pointer twisti@4318: addq(rsp, frame::arg_reg_save_area_bytes); twisti@4318: #endif twisti@4318: twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { twisti@4318: assert(!src2.is_lval(), "should use cmpptr"); twisti@4318: twisti@4318: if (reachable(src2)) { twisti@4318: cmpq(src1, as_Address(src2)); twisti@4318: } else { twisti@4318: lea(rscratch1, src2); twisti@4318: Assembler::cmpq(src1, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::corrected_idivq(Register reg) { twisti@4318: // Full implementation of Java ldiv and lrem; checks for special twisti@4318: // case as described in JVM spec., p.243 & p.271. The function twisti@4318: // returns the (pc) offset of the idivl instruction - may be needed twisti@4318: // for implicit exceptions. twisti@4318: // twisti@4318: // normal case special case twisti@4318: // twisti@4318: // input : rax: dividend min_long twisti@4318: // reg: divisor (may not be eax/edx) -1 twisti@4318: // twisti@4318: // output: rax: quotient (= rax idiv reg) min_long twisti@4318: // rdx: remainder (= rax irem reg) 0 twisti@4318: assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); twisti@4318: static const int64_t min_long = 0x8000000000000000; twisti@4318: Label normal_case, special_case; twisti@4318: twisti@4318: // check for special case twisti@4318: cmp64(rax, ExternalAddress((address) &min_long)); twisti@4318: jcc(Assembler::notEqual, normal_case); twisti@4318: xorl(rdx, rdx); // prepare rdx for possible special case (where twisti@4318: // remainder = 0) twisti@4318: cmpq(reg, -1); twisti@4318: jcc(Assembler::equal, special_case); twisti@4318: twisti@4318: // handle normal case twisti@4318: bind(normal_case); twisti@4318: cdqq(); twisti@4318: int idivq_offset = offset(); twisti@4318: idivq(reg); twisti@4318: twisti@4318: // normal and special case exit twisti@4318: bind(special_case); twisti@4318: twisti@4318: return idivq_offset; twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decrementq(Register reg, int value) { twisti@4318: if (value == min_jint) { subq(reg, value); return; } twisti@4318: if (value < 0) { incrementq(reg, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { decq(reg) ; return; } twisti@4318: /* else */ { subq(reg, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decrementq(Address dst, int value) { twisti@4318: if (value == min_jint) { subq(dst, value); return; } twisti@4318: if (value < 0) { incrementq(dst, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { decq(dst) ; return; } twisti@4318: /* else */ { subq(dst, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incrementq(Register reg, int value) { twisti@4318: if (value == min_jint) { addq(reg, value); return; } twisti@4318: if (value < 0) { decrementq(reg, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { incq(reg) ; return; } twisti@4318: /* else */ { addq(reg, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incrementq(Address dst, int value) { twisti@4318: if (value == min_jint) { addq(dst, value); return; } twisti@4318: if (value < 0) { decrementq(dst, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { incq(dst) ; return; } twisti@4318: /* else */ { addq(dst, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: // 32bit can do a case table jump in one instruction but we no longer allow the base twisti@4318: // to be installed in the Address class twisti@4318: void MacroAssembler::jump(ArrayAddress entry) { twisti@4318: lea(rscratch1, entry.base()); twisti@4318: Address dispatch = entry.index(); twisti@4318: assert(dispatch._base == noreg, "must be"); twisti@4318: dispatch._base = rscratch1; twisti@4318: jmp(dispatch); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { twisti@4318: ShouldNotReachHere(); // 64bit doesn't use two regs twisti@4318: cmpq(x_lo, y_lo); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lea(Register dst, AddressLiteral src) { twisti@4318: mov_literal64(dst, (intptr_t)src.target(), src.rspec()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lea(Address dst, AddressLiteral adr) { twisti@4318: mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); twisti@4318: movptr(dst, rscratch1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::leave() { twisti@4318: // %%% is this really better? Why not on 32bit too? twisti@4366: emit_int8((unsigned char)0xC9); // LEAVE twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::lneg(Register hi, Register lo) { twisti@4318: ShouldNotReachHere(); // 64bit doesn't use two regs twisti@4318: negq(lo); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movoop(Register dst, jobject obj) { twisti@4318: mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movoop(Address dst, jobject obj) { twisti@4318: mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); twisti@4318: movq(dst, rscratch1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { twisti@4318: mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { twisti@4318: mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); twisti@4318: movq(dst, rscratch1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, AddressLiteral src) { twisti@4318: if (src.is_lval()) { twisti@4318: mov_literal64(dst, (intptr_t)src.target(), src.rspec()); twisti@4318: } else { twisti@4318: if (reachable(src)) { twisti@4318: movq(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: movq(dst, Address(rscratch1,0)); twisti@4318: } twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(ArrayAddress dst, Register src) { twisti@4318: movq(as_Address(dst), src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, ArrayAddress src) { twisti@4318: movq(dst, as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: // src should NEVER be a real pointer. Use AddressLiteral for true pointers twisti@4318: void MacroAssembler::movptr(Address dst, intptr_t src) { twisti@4318: mov64(rscratch1, src); twisti@4318: movq(dst, rscratch1); twisti@4318: } twisti@4318: twisti@4318: // These are mostly for initializing NULL twisti@4318: void MacroAssembler::movptr(Address dst, int32_t src) { twisti@4318: movslq(dst, src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, int32_t src) { twisti@4318: mov64(dst, (intptr_t)src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pushoop(jobject obj) { twisti@4318: movoop(rscratch1, obj); twisti@4318: push(rscratch1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pushklass(Metadata* obj) { twisti@4318: mov_metadata(rscratch1, obj); twisti@4318: push(rscratch1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pushptr(AddressLiteral src) { twisti@4318: lea(rscratch1, src); twisti@4318: if (src.is_lval()) { twisti@4318: push(rscratch1); twisti@4318: } else { twisti@4318: pushq(Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::reset_last_Java_frame(bool clear_fp, twisti@4318: bool clear_pc) { twisti@4318: // we must set sp to zero to clear frame twisti@4318: movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); twisti@4318: // must clear fp, so that compiled frames are not confused; it is twisti@4318: // possible that we need it only for debugging twisti@4318: if (clear_fp) { twisti@4318: movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); twisti@4318: } twisti@4318: twisti@4318: if (clear_pc) { twisti@4318: movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_last_Java_frame(Register last_java_sp, twisti@4318: Register last_java_fp, twisti@4318: address last_java_pc) { twisti@4318: // determine last_java_sp register twisti@4318: if (!last_java_sp->is_valid()) { twisti@4318: last_java_sp = rsp; twisti@4318: } twisti@4318: twisti@4318: // last_java_fp is optional twisti@4318: if (last_java_fp->is_valid()) { twisti@4318: movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), twisti@4318: last_java_fp); twisti@4318: } twisti@4318: twisti@4318: // last_java_pc is optional twisti@4318: if (last_java_pc != NULL) { twisti@4318: Address java_pc(r15_thread, twisti@4318: JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); twisti@4318: lea(rscratch1, InternalAddress(last_java_pc)); twisti@4318: movptr(java_pc, rscratch1); twisti@4318: } twisti@4318: twisti@4318: movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); twisti@4318: } twisti@4318: twisti@4318: static void pass_arg0(MacroAssembler* masm, Register arg) { twisti@4318: if (c_rarg0 != arg ) { twisti@4318: masm->mov(c_rarg0, arg); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: static void pass_arg1(MacroAssembler* masm, Register arg) { twisti@4318: if (c_rarg1 != arg ) { twisti@4318: masm->mov(c_rarg1, arg); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: static void pass_arg2(MacroAssembler* masm, Register arg) { twisti@4318: if (c_rarg2 != arg ) { twisti@4318: masm->mov(c_rarg2, arg); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: static void pass_arg3(MacroAssembler* masm, Register arg) { twisti@4318: if (c_rarg3 != arg ) { twisti@4318: masm->mov(c_rarg3, arg); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::stop(const char* msg) { twisti@4318: address rip = pc(); twisti@4318: pusha(); // get regs on stack twisti@4318: lea(c_rarg0, ExternalAddress((address) msg)); twisti@4318: lea(c_rarg1, InternalAddress(rip)); twisti@4318: movq(c_rarg2, rsp); // pass pointer to regs array twisti@4318: andq(rsp, -16); // align stack as required by ABI twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); twisti@4318: hlt(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::warn(const char* msg) { twisti@4318: push(rbp); twisti@4318: movq(rbp, rsp); twisti@4318: andq(rsp, -16); // align stack as required by push_CPU_state and call twisti@4318: push_CPU_state(); // keeps alignment at 16 bytes twisti@4318: lea(c_rarg0, ExternalAddress((address) msg)); twisti@4318: call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); twisti@4318: pop_CPU_state(); twisti@4318: mov(rsp, rbp); twisti@4318: pop(rbp); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::print_state() { twisti@4318: address rip = pc(); twisti@4318: pusha(); // get regs on stack twisti@4318: push(rbp); twisti@4318: movq(rbp, rsp); twisti@4318: andq(rsp, -16); // align stack as required by push_CPU_state and call twisti@4318: push_CPU_state(); // keeps alignment at 16 bytes twisti@4318: twisti@4318: lea(c_rarg0, InternalAddress(rip)); twisti@4318: lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array twisti@4318: call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); twisti@4318: twisti@4318: pop_CPU_state(); twisti@4318: mov(rsp, rbp); twisti@4318: pop(rbp); twisti@4318: popa(); twisti@4318: } twisti@4318: twisti@4318: #ifndef PRODUCT twisti@4318: extern "C" void findpc(intptr_t x); twisti@4318: #endif twisti@4318: twisti@4318: void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { twisti@4318: // In order to get locks to work, we need to fake a in_VM state twisti@4318: if (ShowMessageBoxOnError) { twisti@4318: JavaThread* thread = JavaThread::current(); twisti@4318: JavaThreadState saved_state = thread->thread_state(); twisti@4318: thread->set_thread_state(_thread_in_vm); twisti@4318: #ifndef PRODUCT twisti@4318: if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { twisti@4318: ttyLocker ttyl; twisti@4318: BytecodeCounter::print(); twisti@4318: } twisti@4318: #endif twisti@4318: // To see where a verify_oop failed, get $ebx+40/X for this frame. twisti@4318: // XXX correct this offset for amd64 twisti@4318: // This is the value of eip which points to where verify_oop will return. twisti@4318: if (os::message_box(msg, "Execution stopped, print registers?")) { twisti@4318: print_state64(pc, regs); twisti@4318: BREAKPOINT; twisti@4318: assert(false, "start up GDB"); twisti@4318: } twisti@4318: ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); twisti@4318: } else { twisti@4318: ttyLocker ttyl; twisti@4318: ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", twisti@4318: msg); twisti@4318: assert(false, err_msg("DEBUG MESSAGE: %s", msg)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { twisti@4318: ttyLocker ttyl; twisti@4318: FlagSetting fs(Debugging, true); twisti@4318: tty->print_cr("rip = 0x%016lx", pc); twisti@4318: #ifndef PRODUCT twisti@4318: tty->cr(); twisti@4318: findpc(pc); twisti@4318: tty->cr(); twisti@4318: #endif twisti@4318: #define PRINT_REG(rax, value) \ twisti@4318: { tty->print("%s = ", #rax); os::print_location(tty, value); } twisti@4318: PRINT_REG(rax, regs[15]); twisti@4318: PRINT_REG(rbx, regs[12]); twisti@4318: PRINT_REG(rcx, regs[14]); twisti@4318: PRINT_REG(rdx, regs[13]); twisti@4318: PRINT_REG(rdi, regs[8]); twisti@4318: PRINT_REG(rsi, regs[9]); twisti@4318: PRINT_REG(rbp, regs[10]); twisti@4318: PRINT_REG(rsp, regs[11]); twisti@4318: PRINT_REG(r8 , regs[7]); twisti@4318: PRINT_REG(r9 , regs[6]); twisti@4318: PRINT_REG(r10, regs[5]); twisti@4318: PRINT_REG(r11, regs[4]); twisti@4318: PRINT_REG(r12, regs[3]); twisti@4318: PRINT_REG(r13, regs[2]); twisti@4318: PRINT_REG(r14, regs[1]); twisti@4318: PRINT_REG(r15, regs[0]); twisti@4318: #undef PRINT_REG twisti@4318: // Print some words near top of staack. twisti@4318: int64_t* rsp = (int64_t*) regs[11]; twisti@4318: int64_t* dump_sp = rsp; twisti@4318: for (int col1 = 0; col1 < 8; col1++) { twisti@4318: tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); twisti@4318: os::print_location(tty, *dump_sp++); twisti@4318: } twisti@4318: for (int row = 0; row < 25; row++) { twisti@4318: tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); twisti@4318: for (int col = 0; col < 4; col++) { twisti@4318: tty->print(" 0x%016lx", *dump_sp++); twisti@4318: } twisti@4318: tty->cr(); twisti@4318: } twisti@4318: // Print some instructions around pc: twisti@4318: Disassembler::decode((address)pc-64, (address)pc); twisti@4318: tty->print_cr("--------"); twisti@4318: Disassembler::decode((address)pc, (address)pc+32); twisti@4318: } twisti@4318: twisti@4318: #endif // _LP64 twisti@4318: twisti@4318: // Now versions that are common to 32/64 bit twisti@4318: twisti@4318: void MacroAssembler::addptr(Register dst, int32_t imm32) { twisti@4318: LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::addptr(Register dst, Register src) { twisti@4318: LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::addptr(Address dst, Register src) { twisti@4318: LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::addsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::addsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: addss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: addss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::align(int modulus) { twisti@4318: if (offset() % modulus != 0) { twisti@4318: nop(modulus - (offset() % modulus)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { twisti@4318: // Used in sign-masking with aligned address. twisti@4318: assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); twisti@4318: if (reachable(src)) { twisti@4318: Assembler::andpd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::andpd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { twisti@4318: // Used in sign-masking with aligned address. twisti@4318: assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); twisti@4318: if (reachable(src)) { twisti@4318: Assembler::andps(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::andps(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::andptr(Register dst, int32_t imm32) { twisti@4318: LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { twisti@4318: pushf(); twisti@4318: if (os::is_MP()) twisti@4318: lock(); twisti@4318: incrementl(counter_addr); twisti@4318: popf(); twisti@4318: } twisti@4318: twisti@4318: // Writes to stack successive pages until offset reached to check for twisti@4318: // stack overflow + shadow pages. This clobbers tmp. twisti@4318: void MacroAssembler::bang_stack_size(Register size, Register tmp) { twisti@4318: movptr(tmp, rsp); twisti@4318: // Bang stack for total size given plus shadow page size. twisti@4318: // Bang one page at a time because large size can bang beyond yellow and twisti@4318: // red zones. twisti@4318: Label loop; twisti@4318: bind(loop); twisti@4318: movl(Address(tmp, (-os::vm_page_size())), size ); twisti@4318: subptr(tmp, os::vm_page_size()); twisti@4318: subl(size, os::vm_page_size()); twisti@4318: jcc(Assembler::greater, loop); twisti@4318: twisti@4318: // Bang down shadow pages too. twisti@4318: // The -1 because we already subtracted 1 page. twisti@4318: for (int i = 0; i< StackShadowPages-1; i++) { twisti@4318: // this could be any sized move but this is can be a debugging crumb twisti@4318: // so the bigger the better. twisti@4318: movptr(Address(tmp, (-i*os::vm_page_size())), size ); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { twisti@4318: assert(UseBiasedLocking, "why call this otherwise?"); twisti@4318: twisti@4318: // Check for biased locking unlock case, which is a no-op twisti@4318: // Note: we do not have to check the thread ID for two reasons. twisti@4318: // First, the interpreter checks for IllegalMonitorStateException at twisti@4318: // a higher level. Second, if the bias was revoked while we held the twisti@4318: // lock, the object could not be rebiased toward another thread, so twisti@4318: // the bias bit would be clear. twisti@4318: movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); twisti@4318: andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); twisti@4318: cmpptr(temp_reg, markOopDesc::biased_lock_pattern); twisti@4318: jcc(Assembler::equal, done); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::c2bool(Register x) { twisti@4318: // implements x == 0 ? 0 : 1 twisti@4318: // note: must only look at least-significant byte of x twisti@4318: // since C-style booleans are stored in one byte twisti@4318: // only! (was bug) twisti@4318: andl(x, 0xFF); twisti@4318: setb(Assembler::notZero, x); twisti@4318: } twisti@4318: twisti@4318: // Wouldn't need if AddressLiteral version had new name twisti@4318: void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { twisti@4318: Assembler::call(L, rtype); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call(Register entry) { twisti@4318: Assembler::call(entry); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call(AddressLiteral entry) { twisti@4318: if (reachable(entry)) { twisti@4318: Assembler::call_literal(entry.target(), entry.rspec()); twisti@4318: } else { twisti@4318: lea(rscratch1, entry); twisti@4318: Assembler::call(rscratch1); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::ic_call(address entry) { twisti@4318: RelocationHolder rh = virtual_call_Relocation::spec(pc()); twisti@4318: movptr(rax, (intptr_t)Universe::non_oop_word()); twisti@4318: call(AddressLiteral(entry, rh)); twisti@4318: } twisti@4318: twisti@4318: // Implementation of call_VM versions twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: address entry_point, twisti@4318: bool check_exceptions) { twisti@4318: Label C, E; twisti@4318: call(C, relocInfo::none); twisti@4318: jmp(E); twisti@4318: twisti@4318: bind(C); twisti@4318: call_VM_helper(oop_result, entry_point, 0, check_exceptions); twisti@4318: ret(0); twisti@4318: twisti@4318: bind(E); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: bool check_exceptions) { twisti@4318: Label C, E; twisti@4318: call(C, relocInfo::none); twisti@4318: jmp(E); twisti@4318: twisti@4318: bind(C); twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM_helper(oop_result, entry_point, 1, check_exceptions); twisti@4318: ret(0); twisti@4318: twisti@4318: bind(E); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: bool check_exceptions) { twisti@4318: Label C, E; twisti@4318: call(C, relocInfo::none); twisti@4318: jmp(E); twisti@4318: twisti@4318: bind(C); twisti@4318: twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: twisti@4318: pass_arg2(this, arg_2); twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM_helper(oop_result, entry_point, 2, check_exceptions); twisti@4318: ret(0); twisti@4318: twisti@4318: bind(E); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: Register arg_3, twisti@4318: bool check_exceptions) { twisti@4318: Label C, E; twisti@4318: call(C, relocInfo::none); twisti@4318: jmp(E); twisti@4318: twisti@4318: bind(C); twisti@4318: twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); twisti@4318: pass_arg3(this, arg_3); twisti@4318: twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM_helper(oop_result, entry_point, 3, check_exceptions); twisti@4318: ret(0); twisti@4318: twisti@4318: bind(E); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: int number_of_arguments, twisti@4318: bool check_exceptions) { twisti@4318: Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); twisti@4318: call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: bool check_exceptions) { twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: bool check_exceptions) { twisti@4318: twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: Register arg_3, twisti@4318: bool check_exceptions) { twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); twisti@4318: pass_arg3(this, arg_3); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: pass_arg1(this, arg_1); twisti@4318: call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: int number_of_arguments, twisti@4318: bool check_exceptions) { twisti@4318: Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); twisti@4318: MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: bool check_exceptions) { twisti@4318: pass_arg1(this, arg_1); twisti@4318: super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: bool check_exceptions) { twisti@4318: twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: pass_arg1(this, arg_1); twisti@4318: super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM(Register oop_result, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: Register arg_1, twisti@4318: Register arg_2, twisti@4318: Register arg_3, twisti@4318: bool check_exceptions) { twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); twisti@4318: pass_arg3(this, arg_3); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: pass_arg1(this, arg_1); twisti@4318: super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_base(Register oop_result, twisti@4318: Register java_thread, twisti@4318: Register last_java_sp, twisti@4318: address entry_point, twisti@4318: int number_of_arguments, twisti@4318: bool check_exceptions) { twisti@4318: // determine java_thread register twisti@4318: if (!java_thread->is_valid()) { twisti@4318: #ifdef _LP64 twisti@4318: java_thread = r15_thread; twisti@4318: #else twisti@4318: java_thread = rdi; twisti@4318: get_thread(java_thread); twisti@4318: #endif // LP64 twisti@4318: } twisti@4318: // determine last_java_sp register twisti@4318: if (!last_java_sp->is_valid()) { twisti@4318: last_java_sp = rsp; twisti@4318: } twisti@4318: // debugging support twisti@4318: assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); twisti@4318: LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); twisti@4318: #ifdef ASSERT twisti@4318: // TraceBytecodes does not use r12 but saves it over the call, so don't verify twisti@4318: // r12 is the heapbase. twisti@4318: LP64_ONLY(if ((UseCompressedOops || UseCompressedKlassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) twisti@4318: #endif // ASSERT twisti@4318: twisti@4318: assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); twisti@4318: assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); twisti@4318: twisti@4318: // push java thread (becomes first argument of C function) twisti@4318: twisti@4318: NOT_LP64(push(java_thread); number_of_arguments++); twisti@4318: LP64_ONLY(mov(c_rarg0, r15_thread)); twisti@4318: twisti@4318: // set last Java frame before call twisti@4318: assert(last_java_sp != rbp, "can't use ebp/rbp"); twisti@4318: twisti@4318: // Only interpreter should have to set fp twisti@4318: set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); twisti@4318: twisti@4318: // do the call, remove parameters twisti@4318: MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); twisti@4318: twisti@4318: // restore the thread (cannot use the pushed argument since arguments twisti@4318: // may be overwritten by C code generated by an optimizing compiler); twisti@4318: // however can use the register value directly if it is callee saved. twisti@4318: if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { twisti@4318: // rdi & rsi (also r15) are callee saved -> nothing to do twisti@4318: #ifdef ASSERT twisti@4318: guarantee(java_thread != rax, "change this code"); twisti@4318: push(rax); twisti@4318: { Label L; twisti@4318: get_thread(rax); twisti@4318: cmpptr(java_thread, rax); twisti@4318: jcc(Assembler::equal, L); twisti@4318: STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); twisti@4318: bind(L); twisti@4318: } twisti@4318: pop(rax); twisti@4318: #endif twisti@4318: } else { twisti@4318: get_thread(java_thread); twisti@4318: } twisti@4318: // reset last Java frame twisti@4318: // Only interpreter should have to clear fp twisti@4318: reset_last_Java_frame(java_thread, true, false); twisti@4318: twisti@4318: #ifndef CC_INTERP twisti@4318: // C++ interp handles this in the interpreter twisti@4318: check_and_handle_popframe(java_thread); twisti@4318: check_and_handle_earlyret(java_thread); twisti@4318: #endif /* CC_INTERP */ twisti@4318: twisti@4318: if (check_exceptions) { twisti@4318: // check for pending exceptions (java_thread is set upon return) twisti@4318: cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); twisti@4318: #ifndef _LP64 twisti@4318: jump_cc(Assembler::notEqual, twisti@4318: RuntimeAddress(StubRoutines::forward_exception_entry())); twisti@4318: #else twisti@4318: // This used to conditionally jump to forward_exception however it is twisti@4318: // possible if we relocate that the branch will not reach. So we must jump twisti@4318: // around so we can always reach twisti@4318: twisti@4318: Label ok; twisti@4318: jcc(Assembler::equal, ok); twisti@4318: jump(RuntimeAddress(StubRoutines::forward_exception_entry())); twisti@4318: bind(ok); twisti@4318: #endif // LP64 twisti@4318: } twisti@4318: twisti@4318: // get oop result if there is one and reset the value in the thread twisti@4318: if (oop_result->is_valid()) { twisti@4318: get_vm_result(oop_result, java_thread); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { twisti@4318: twisti@4318: // Calculate the value for last_Java_sp twisti@4318: // somewhat subtle. call_VM does an intermediate call twisti@4318: // which places a return address on the stack just under the twisti@4318: // stack pointer as the user finsihed with it. This allows twisti@4318: // use to retrieve last_Java_pc from last_Java_sp[-1]. twisti@4318: // On 32bit we then have to push additional args on the stack to accomplish twisti@4318: // the actual requested call. On 64bit call_VM only can use register args twisti@4318: // so the only extra space is the return address that call_VM created. twisti@4318: // This hopefully explains the calculations here. twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: // We've pushed one address, correct last_Java_sp twisti@4318: lea(rax, Address(rsp, wordSize)); twisti@4318: #else twisti@4318: lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); twisti@4318: #endif // LP64 twisti@4318: twisti@4318: call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); twisti@4318: twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { twisti@4318: call_VM_leaf_base(entry_point, number_of_arguments); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { twisti@4318: pass_arg0(this, arg_0); twisti@4318: call_VM_leaf(entry_point, 1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { twisti@4318: twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); twisti@4318: pass_arg1(this, arg_1); twisti@4318: pass_arg0(this, arg_0); twisti@4318: call_VM_leaf(entry_point, 2); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); twisti@4318: pass_arg1(this, arg_1); twisti@4318: pass_arg0(this, arg_0); twisti@4318: call_VM_leaf(entry_point, 3); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { twisti@4318: pass_arg0(this, arg_0); twisti@4318: MacroAssembler::call_VM_leaf_base(entry_point, 1); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { twisti@4318: twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); twisti@4318: pass_arg1(this, arg_1); twisti@4318: pass_arg0(this, arg_0); twisti@4318: MacroAssembler::call_VM_leaf_base(entry_point, 2); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); twisti@4318: pass_arg1(this, arg_1); twisti@4318: pass_arg0(this, arg_0); twisti@4318: MacroAssembler::call_VM_leaf_base(entry_point, 3); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); twisti@4318: pass_arg3(this, arg_3); twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); twisti@4318: LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); twisti@4318: pass_arg2(this, arg_2); twisti@4318: LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); twisti@4318: pass_arg1(this, arg_1); twisti@4318: pass_arg0(this, arg_0); twisti@4318: MacroAssembler::call_VM_leaf_base(entry_point, 4); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { twisti@4318: movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); twisti@4318: movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); twisti@4318: verify_oop(oop_result, "broken oop in call_VM_base"); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { twisti@4318: movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); twisti@4318: movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::check_and_handle_earlyret(Register java_thread) { twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::check_and_handle_popframe(Register java_thread) { twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { twisti@4318: if (reachable(src1)) { twisti@4318: cmpl(as_Address(src1), imm); twisti@4318: } else { twisti@4318: lea(rscratch1, src1); twisti@4318: cmpl(Address(rscratch1, 0), imm); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { twisti@4318: assert(!src2.is_lval(), "use cmpptr"); twisti@4318: if (reachable(src2)) { twisti@4318: cmpl(src1, as_Address(src2)); twisti@4318: } else { twisti@4318: lea(rscratch1, src2); twisti@4318: cmpl(src1, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp32(Register src1, int32_t imm) { twisti@4318: Assembler::cmpl(src1, imm); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp32(Register src1, Address src2) { twisti@4318: Assembler::cmpl(src1, src2); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { twisti@4318: ucomisd(opr1, opr2); twisti@4318: twisti@4318: Label L; twisti@4318: if (unordered_is_less) { twisti@4318: movl(dst, -1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::below , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: increment(dst); twisti@4318: } else { // unordered is greater twisti@4318: movl(dst, 1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::above , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: decrementl(dst); twisti@4318: } twisti@4318: bind(L); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { twisti@4318: ucomiss(opr1, opr2); twisti@4318: twisti@4318: Label L; twisti@4318: if (unordered_is_less) { twisti@4318: movl(dst, -1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::below , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: increment(dst); twisti@4318: } else { // unordered is greater twisti@4318: movl(dst, 1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::above , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: decrementl(dst); twisti@4318: } twisti@4318: bind(L); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::cmp8(AddressLiteral src1, int imm) { twisti@4318: if (reachable(src1)) { twisti@4318: cmpb(as_Address(src1), imm); twisti@4318: } else { twisti@4318: lea(rscratch1, src1); twisti@4318: cmpb(Address(rscratch1, 0), imm); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { twisti@4318: #ifdef _LP64 twisti@4318: if (src2.is_lval()) { twisti@4318: movptr(rscratch1, src2); twisti@4318: Assembler::cmpq(src1, rscratch1); twisti@4318: } else if (reachable(src2)) { twisti@4318: cmpq(src1, as_Address(src2)); twisti@4318: } else { twisti@4318: lea(rscratch1, src2); twisti@4318: Assembler::cmpq(src1, Address(rscratch1, 0)); twisti@4318: } twisti@4318: #else twisti@4318: if (src2.is_lval()) { twisti@4318: cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); twisti@4318: } else { twisti@4318: cmpl(src1, as_Address(src2)); twisti@4318: } twisti@4318: #endif // _LP64 twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { twisti@4318: assert(src2.is_lval(), "not a mem-mem compare"); twisti@4318: #ifdef _LP64 twisti@4318: // moves src2's literal address twisti@4318: movptr(rscratch1, src2); twisti@4318: Assembler::cmpq(src1, rscratch1); twisti@4318: #else twisti@4318: cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); twisti@4318: #endif // _LP64 twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { twisti@4318: if (reachable(adr)) { twisti@4318: if (os::is_MP()) twisti@4318: lock(); twisti@4318: cmpxchgptr(reg, as_Address(adr)); twisti@4318: } else { twisti@4318: lea(rscratch1, adr); twisti@4318: if (os::is_MP()) twisti@4318: lock(); twisti@4318: cmpxchgptr(reg, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmpxchgptr(Register reg, Address adr) { twisti@4318: LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::comisd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::comisd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::comiss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::comiss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { twisti@4318: Condition negated_cond = negate_condition(cond); twisti@4318: Label L; twisti@4318: jcc(negated_cond, L); twisti@4318: atomic_incl(counter_addr); twisti@4318: bind(L); twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::corrected_idivl(Register reg) { twisti@4318: // Full implementation of Java idiv and irem; checks for twisti@4318: // special case as described in JVM spec., p.243 & p.271. twisti@4318: // The function returns the (pc) offset of the idivl twisti@4318: // instruction - may be needed for implicit exceptions. twisti@4318: // twisti@4318: // normal case special case twisti@4318: // twisti@4318: // input : rax,: dividend min_int twisti@4318: // reg: divisor (may not be rax,/rdx) -1 twisti@4318: // twisti@4318: // output: rax,: quotient (= rax, idiv reg) min_int twisti@4318: // rdx: remainder (= rax, irem reg) 0 twisti@4318: assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); twisti@4318: const int min_int = 0x80000000; twisti@4318: Label normal_case, special_case; twisti@4318: twisti@4318: // check for special case twisti@4318: cmpl(rax, min_int); twisti@4318: jcc(Assembler::notEqual, normal_case); twisti@4318: xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) twisti@4318: cmpl(reg, -1); twisti@4318: jcc(Assembler::equal, special_case); twisti@4318: twisti@4318: // handle normal case twisti@4318: bind(normal_case); twisti@4318: cdql(); twisti@4318: int idivl_offset = offset(); twisti@4318: idivl(reg); twisti@4318: twisti@4318: // normal and special case exit twisti@4318: bind(special_case); twisti@4318: twisti@4318: return idivl_offset; twisti@4318: } twisti@4318: twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::decrementl(Register reg, int value) { twisti@4318: if (value == min_jint) {subl(reg, value) ; return; } twisti@4318: if (value < 0) { incrementl(reg, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { decl(reg) ; return; } twisti@4318: /* else */ { subl(reg, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decrementl(Address dst, int value) { twisti@4318: if (value == min_jint) {subl(dst, value) ; return; } twisti@4318: if (value < 0) { incrementl(dst, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { decl(dst) ; return; } twisti@4318: /* else */ { subl(dst, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::division_with_shift (Register reg, int shift_value) { twisti@4318: assert (shift_value > 0, "illegal shift value"); twisti@4318: Label _is_positive; twisti@4318: testl (reg, reg); twisti@4318: jcc (Assembler::positive, _is_positive); twisti@4318: int offset = (1 << shift_value) - 1 ; twisti@4318: twisti@4318: if (offset == 1) { twisti@4318: incrementl(reg); twisti@4318: } else { twisti@4318: addl(reg, offset); twisti@4318: } twisti@4318: twisti@4318: bind (_is_positive); twisti@4318: sarl(reg, shift_value); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::divsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::divsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::divss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::divss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: // !defined(COMPILER2) is because of stupid core builds twisti@4318: #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) twisti@4318: void MacroAssembler::empty_FPU_stack() { twisti@4318: if (VM_Version::supports_mmx()) { twisti@4318: emms(); twisti@4318: } else { twisti@4318: for (int i = 8; i-- > 0; ) ffree(i); twisti@4318: } twisti@4318: } twisti@4318: #endif // !LP64 || C1 || !C2 twisti@4318: twisti@4318: twisti@4318: // Defines obj, preserves var_size_in_bytes twisti@4318: void MacroAssembler::eden_allocate(Register obj, twisti@4318: Register var_size_in_bytes, twisti@4318: int con_size_in_bytes, twisti@4318: Register t1, twisti@4318: Label& slow_case) { twisti@4318: assert(obj == rax, "obj must be in rax, for cmpxchg"); twisti@4318: assert_different_registers(obj, var_size_in_bytes, t1); twisti@4318: if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { twisti@4318: jmp(slow_case); twisti@4318: } else { twisti@4318: Register end = t1; twisti@4318: Label retry; twisti@4318: bind(retry); twisti@4318: ExternalAddress heap_top((address) Universe::heap()->top_addr()); twisti@4318: movptr(obj, heap_top); twisti@4318: if (var_size_in_bytes == noreg) { twisti@4318: lea(end, Address(obj, con_size_in_bytes)); twisti@4318: } else { twisti@4318: lea(end, Address(obj, var_size_in_bytes, Address::times_1)); twisti@4318: } twisti@4318: // if end < obj then we wrapped around => object too long => slow case twisti@4318: cmpptr(end, obj); twisti@4318: jcc(Assembler::below, slow_case); twisti@4318: cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); twisti@4318: jcc(Assembler::above, slow_case); twisti@4318: // Compare obj with the top addr, and if still equal, store the new top addr in twisti@4318: // end at the address of the top addr pointer. Sets ZF if was equal, and clears twisti@4318: // it otherwise. Use lock prefix for atomicity on MPs. twisti@4318: locked_cmpxchgptr(end, heap_top); twisti@4318: jcc(Assembler::notEqual, retry); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::enter() { twisti@4318: push(rbp); twisti@4318: mov(rbp, rsp); twisti@4318: } twisti@4318: twisti@4318: // A 5 byte nop that is safe for patching (see patch_verified_entry) twisti@4318: void MacroAssembler::fat_nop() { twisti@4318: if (UseAddressNop) { twisti@4318: addr_nop_5(); twisti@4318: } else { twisti@4366: emit_int8(0x26); // es: twisti@4366: emit_int8(0x2e); // cs: twisti@4366: emit_int8(0x64); // fs: twisti@4366: emit_int8(0x65); // gs: twisti@4366: emit_int8((unsigned char)0x90); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fcmp(Register tmp) { twisti@4318: fcmp(tmp, 1, true, true); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { twisti@4318: assert(!pop_right || pop_left, "usage error"); twisti@4318: if (VM_Version::supports_cmov()) { twisti@4318: assert(tmp == noreg, "unneeded temp"); twisti@4318: if (pop_left) { twisti@4318: fucomip(index); twisti@4318: } else { twisti@4318: fucomi(index); twisti@4318: } twisti@4318: if (pop_right) { twisti@4318: fpop(); twisti@4318: } twisti@4318: } else { twisti@4318: assert(tmp != noreg, "need temp"); twisti@4318: if (pop_left) { twisti@4318: if (pop_right) { twisti@4318: fcompp(); twisti@4318: } else { twisti@4318: fcomp(index); twisti@4318: } twisti@4318: } else { twisti@4318: fcom(index); twisti@4318: } twisti@4318: // convert FPU condition into eflags condition via rax, twisti@4318: save_rax(tmp); twisti@4318: fwait(); fnstsw_ax(); twisti@4318: sahf(); twisti@4318: restore_rax(tmp); twisti@4318: } twisti@4318: // condition codes set as follows: twisti@4318: // twisti@4318: // CF (corresponds to C0) if x < y twisti@4318: // PF (corresponds to C2) if unordered twisti@4318: // ZF (corresponds to C3) if x = y twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { twisti@4318: fcmp2int(dst, unordered_is_less, 1, true, true); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { twisti@4318: fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); twisti@4318: Label L; twisti@4318: if (unordered_is_less) { twisti@4318: movl(dst, -1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::below , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: increment(dst); twisti@4318: } else { // unordered is greater twisti@4318: movl(dst, 1); twisti@4318: jcc(Assembler::parity, L); twisti@4318: jcc(Assembler::above , L); twisti@4318: movl(dst, 0); twisti@4318: jcc(Assembler::equal , L); twisti@4318: decrementl(dst); twisti@4318: } twisti@4318: bind(L); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fld_d(AddressLiteral src) { twisti@4318: fld_d(as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fld_s(AddressLiteral src) { twisti@4318: fld_s(as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fld_x(AddressLiteral src) { twisti@4318: Assembler::fld_x(as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fldcw(AddressLiteral src) { twisti@4318: Assembler::fldcw(as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pow_exp_core_encoding() { twisti@4318: // kills rax, rcx, rdx twisti@4318: subptr(rsp,sizeof(jdouble)); twisti@4318: // computes 2^X. Stack: X ... twisti@4318: // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and twisti@4318: // keep it on the thread's stack to compute 2^int(X) later twisti@4318: // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) twisti@4318: // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) twisti@4318: fld_s(0); // Stack: X X ... twisti@4318: frndint(); // Stack: int(X) X ... twisti@4318: fsuba(1); // Stack: int(X) X-int(X) ... twisti@4318: fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... twisti@4318: f2xm1(); // Stack: 2^(X-int(X))-1 ... twisti@4318: fld1(); // Stack: 1 2^(X-int(X))-1 ... twisti@4318: faddp(1); // Stack: 2^(X-int(X)) twisti@4318: // computes 2^(int(X)): add exponent bias (1023) to int(X), then twisti@4318: // shift int(X)+1023 to exponent position. twisti@4318: // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 twisti@4318: // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent twisti@4318: // values so detect them and set result to NaN. twisti@4318: movl(rax,Address(rsp,0)); twisti@4318: movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding twisti@4318: addl(rax, 1023); twisti@4318: movl(rdx,rax); twisti@4318: shll(rax,20); twisti@4318: // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. twisti@4318: addl(rdx,1); twisti@4318: // Check that 1 < int(X)+1023+1 < 2048 twisti@4318: // in 3 steps: twisti@4318: // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 twisti@4318: // 2- (int(X)+1023+1)&-2048 != 0 twisti@4318: // 3- (int(X)+1023+1)&-2048 != 1 twisti@4318: // Do 2- first because addl just updated the flags. twisti@4318: cmov32(Assembler::equal,rax,rcx); twisti@4318: cmpl(rdx,1); twisti@4318: cmov32(Assembler::equal,rax,rcx); twisti@4318: testl(rdx,rcx); twisti@4318: cmov32(Assembler::notEqual,rax,rcx); twisti@4318: movl(Address(rsp,4),rax); twisti@4318: movl(Address(rsp,0),0); twisti@4318: fmul_d(Address(rsp,0)); // Stack: 2^X ... twisti@4318: addptr(rsp,sizeof(jdouble)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::increase_precision() { twisti@4318: subptr(rsp, BytesPerWord); twisti@4318: fnstcw(Address(rsp, 0)); twisti@4318: movl(rax, Address(rsp, 0)); twisti@4318: orl(rax, 0x300); twisti@4318: push(rax); twisti@4318: fldcw(Address(rsp, 0)); twisti@4318: pop(rax); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::restore_precision() { twisti@4318: fldcw(Address(rsp, 0)); twisti@4318: addptr(rsp, BytesPerWord); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fast_pow() { twisti@4318: // computes X^Y = 2^(Y * log2(X)) twisti@4318: // if fast computation is not possible, result is NaN. Requires twisti@4318: // fallback from user of this macro. twisti@4318: // increase precision for intermediate steps of the computation twisti@4318: increase_precision(); twisti@4318: fyl2x(); // Stack: (Y*log2(X)) ... twisti@4318: pow_exp_core_encoding(); // Stack: exp(X) ... twisti@4318: restore_precision(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fast_exp() { twisti@4318: // computes exp(X) = 2^(X * log2(e)) twisti@4318: // if fast computation is not possible, result is NaN. Requires twisti@4318: // fallback from user of this macro. twisti@4318: // increase precision for intermediate steps of the computation twisti@4318: increase_precision(); twisti@4318: fldl2e(); // Stack: log2(e) X ... twisti@4318: fmulp(1); // Stack: (X*log2(e)) ... twisti@4318: pow_exp_core_encoding(); // Stack: exp(X) ... twisti@4318: restore_precision(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { twisti@4318: // kills rax, rcx, rdx twisti@4318: // pow and exp needs 2 extra registers on the fpu stack. twisti@4318: Label slow_case, done; twisti@4318: Register tmp = noreg; twisti@4318: if (!VM_Version::supports_cmov()) { twisti@4318: // fcmp needs a temporary so preserve rdx, twisti@4318: tmp = rdx; twisti@4318: } twisti@4318: Register tmp2 = rax; twisti@4318: Register tmp3 = rcx; twisti@4318: twisti@4318: if (is_exp) { twisti@4318: // Stack: X twisti@4318: fld_s(0); // duplicate argument for runtime call. Stack: X X twisti@4318: fast_exp(); // Stack: exp(X) X twisti@4318: fcmp(tmp, 0, false, false); // Stack: exp(X) X twisti@4318: // exp(X) not equal to itself: exp(X) is NaN go to slow case. twisti@4318: jcc(Assembler::parity, slow_case); twisti@4318: // get rid of duplicate argument. Stack: exp(X) twisti@4318: if (num_fpu_regs_in_use > 0) { twisti@4318: fxch(); twisti@4318: fpop(); twisti@4318: } else { twisti@4318: ffree(1); twisti@4318: } twisti@4318: jmp(done); twisti@4318: } else { twisti@4318: // Stack: X Y twisti@4318: Label x_negative, y_odd; twisti@4318: twisti@4318: fldz(); // Stack: 0 X Y twisti@4318: fcmp(tmp, 1, true, false); // Stack: X Y twisti@4318: jcc(Assembler::above, x_negative); twisti@4318: twisti@4318: // X >= 0 twisti@4318: twisti@4318: fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y twisti@4318: fld_s(1); // Stack: X Y X Y twisti@4318: fast_pow(); // Stack: X^Y X Y twisti@4318: fcmp(tmp, 0, false, false); // Stack: X^Y X Y twisti@4318: // X^Y not equal to itself: X^Y is NaN go to slow case. twisti@4318: jcc(Assembler::parity, slow_case); twisti@4318: // get rid of duplicate arguments. Stack: X^Y twisti@4318: if (num_fpu_regs_in_use > 0) { twisti@4318: fxch(); fpop(); twisti@4318: fxch(); fpop(); twisti@4318: } else { twisti@4318: ffree(2); twisti@4318: ffree(1); twisti@4318: } twisti@4318: jmp(done); twisti@4318: twisti@4318: // X <= 0 twisti@4318: bind(x_negative); twisti@4318: twisti@4318: fld_s(1); // Stack: Y X Y twisti@4318: frndint(); // Stack: int(Y) X Y twisti@4318: fcmp(tmp, 2, false, false); // Stack: int(Y) X Y twisti@4318: jcc(Assembler::notEqual, slow_case); twisti@4318: twisti@4318: subptr(rsp, 8); twisti@4318: twisti@4318: // For X^Y, when X < 0, Y has to be an integer and the final twisti@4318: // result depends on whether it's odd or even. We just checked twisti@4318: // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit twisti@4318: // integer to test its parity. If int(Y) is huge and doesn't fit twisti@4318: // in the 64 bit integer range, the integer indefinite value will twisti@4318: // end up in the gp registers. Huge numbers are all even, the twisti@4318: // integer indefinite number is even so it's fine. twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: // Let's check we don't end up with an integer indefinite number twisti@4318: // when not expected. First test for huge numbers: check whether twisti@4318: // int(Y)+1 == int(Y) which is true for very large numbers and twisti@4318: // those are all even. A 64 bit integer is guaranteed to not twisti@4318: // overflow for numbers where y+1 != y (when precision is set to twisti@4318: // double precision). twisti@4318: Label y_not_huge; twisti@4318: twisti@4318: fld1(); // Stack: 1 int(Y) X Y twisti@4318: fadd(1); // Stack: 1+int(Y) int(Y) X Y twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: // trip to memory to force the precision down from double extended twisti@4318: // precision twisti@4318: fstp_d(Address(rsp, 0)); twisti@4318: fld_d(Address(rsp, 0)); twisti@4318: #endif twisti@4318: twisti@4318: fcmp(tmp, 1, true, false); // Stack: int(Y) X Y twisti@4318: #endif twisti@4318: twisti@4318: // move int(Y) as 64 bit integer to thread's stack twisti@4318: fistp_d(Address(rsp,0)); // Stack: X Y twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: jcc(Assembler::notEqual, y_not_huge); twisti@4318: twisti@4318: // Y is huge so we know it's even. It may not fit in a 64 bit twisti@4318: // integer and we don't want the debug code below to see the twisti@4318: // integer indefinite value so overwrite int(Y) on the thread's twisti@4318: // stack with 0. twisti@4318: movl(Address(rsp, 0), 0); twisti@4318: movl(Address(rsp, 4), 0); twisti@4318: twisti@4318: bind(y_not_huge); twisti@4318: #endif twisti@4318: twisti@4318: fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y twisti@4318: fld_s(1); // Stack: X Y X Y twisti@4318: fabs(); // Stack: abs(X) Y X Y twisti@4318: fast_pow(); // Stack: abs(X)^Y X Y twisti@4318: fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y twisti@4318: // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. twisti@4318: twisti@4318: pop(tmp2); twisti@4318: NOT_LP64(pop(tmp3)); twisti@4318: jcc(Assembler::parity, slow_case); twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: // Check that int(Y) is not integer indefinite value (int twisti@4318: // overflow). Shouldn't happen because for values that would twisti@4318: // overflow, 1+int(Y)==Y which was tested earlier. twisti@4318: #ifndef _LP64 twisti@4318: { twisti@4318: Label integer; twisti@4318: testl(tmp2, tmp2); twisti@4318: jcc(Assembler::notZero, integer); twisti@4318: cmpl(tmp3, 0x80000000); twisti@4318: jcc(Assembler::notZero, integer); twisti@4318: STOP("integer indefinite value shouldn't be seen here"); twisti@4318: bind(integer); twisti@4318: } twisti@4318: #else twisti@4318: { twisti@4318: Label integer; twisti@4318: mov(tmp3, tmp2); // preserve tmp2 for parity check below twisti@4318: shlq(tmp3, 1); twisti@4318: jcc(Assembler::carryClear, integer); twisti@4318: jcc(Assembler::notZero, integer); twisti@4318: STOP("integer indefinite value shouldn't be seen here"); twisti@4318: bind(integer); twisti@4318: } twisti@4318: #endif twisti@4318: #endif twisti@4318: twisti@4318: // get rid of duplicate arguments. Stack: X^Y twisti@4318: if (num_fpu_regs_in_use > 0) { twisti@4318: fxch(); fpop(); twisti@4318: fxch(); fpop(); twisti@4318: } else { twisti@4318: ffree(2); twisti@4318: ffree(1); twisti@4318: } twisti@4318: twisti@4318: testl(tmp2, 1); twisti@4318: jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y twisti@4318: // X <= 0, Y even: X^Y = -abs(X)^Y twisti@4318: twisti@4318: fchs(); // Stack: -abs(X)^Y Y twisti@4318: jmp(done); twisti@4318: } twisti@4318: twisti@4318: // slow case: runtime call twisti@4318: bind(slow_case); twisti@4318: twisti@4318: fpop(); // pop incorrect result or int(Y) twisti@4318: twisti@4318: fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), twisti@4318: is_exp ? 1 : 2, num_fpu_regs_in_use); twisti@4318: twisti@4318: // Come here with result in F-TOS twisti@4318: bind(done); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fpop() { twisti@4318: ffree(); twisti@4318: fincstp(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fremr(Register tmp) { twisti@4318: save_rax(tmp); twisti@4318: { Label L; twisti@4318: bind(L); twisti@4318: fprem(); twisti@4318: fwait(); fnstsw_ax(); twisti@4318: #ifdef _LP64 twisti@4318: testl(rax, 0x400); twisti@4318: jcc(Assembler::notEqual, L); twisti@4318: #else twisti@4318: sahf(); twisti@4318: jcc(Assembler::parity, L); twisti@4318: #endif // _LP64 twisti@4318: } twisti@4318: restore_rax(tmp); twisti@4318: // Result is in ST0. twisti@4318: // Note: fxch & fpop to get rid of ST1 twisti@4318: // (otherwise FPU stack could overflow eventually) twisti@4318: fxch(1); twisti@4318: fpop(); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::incrementl(AddressLiteral dst) { twisti@4318: if (reachable(dst)) { twisti@4318: incrementl(as_Address(dst)); twisti@4318: } else { twisti@4318: lea(rscratch1, dst); twisti@4318: incrementl(Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incrementl(ArrayAddress dst) { twisti@4318: incrementl(as_Address(dst)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incrementl(Register reg, int value) { twisti@4318: if (value == min_jint) {addl(reg, value) ; return; } twisti@4318: if (value < 0) { decrementl(reg, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { incl(reg) ; return; } twisti@4318: /* else */ { addl(reg, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incrementl(Address dst, int value) { twisti@4318: if (value == min_jint) {addl(dst, value) ; return; } twisti@4318: if (value < 0) { decrementl(dst, -value); return; } twisti@4318: if (value == 0) { ; return; } twisti@4318: if (value == 1 && UseIncDec) { incl(dst) ; return; } twisti@4318: /* else */ { addl(dst, value) ; return; } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::jump(AddressLiteral dst) { twisti@4318: if (reachable(dst)) { twisti@4318: jmp_literal(dst.target(), dst.rspec()); twisti@4318: } else { twisti@4318: lea(rscratch1, dst); twisti@4318: jmp(rscratch1); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { twisti@4318: if (reachable(dst)) { twisti@4318: InstructionMark im(this); twisti@4318: relocate(dst.reloc()); twisti@4318: const int short_size = 2; twisti@4318: const int long_size = 6; twisti@4318: int offs = (intptr_t)dst.target() - ((intptr_t)pc()); twisti@4318: if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { twisti@4318: // 0111 tttn #8-bit disp twisti@4366: emit_int8(0x70 | cc); twisti@4366: emit_int8((offs - short_size) & 0xFF); twisti@4318: } else { twisti@4318: // 0000 1111 1000 tttn #32-bit disp twisti@4366: emit_int8(0x0F); twisti@4366: emit_int8((unsigned char)(0x80 | cc)); twisti@4412: emit_int32(offs - long_size); twisti@4318: } twisti@4318: } else { twisti@4318: #ifdef ASSERT twisti@4318: warning("reversing conditional branch"); twisti@4318: #endif /* ASSERT */ twisti@4318: Label skip; twisti@4318: jccb(reverse[cc], skip); twisti@4318: lea(rscratch1, dst); twisti@4318: Assembler::jmp(rscratch1); twisti@4318: bind(skip); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::ldmxcsr(AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::ldmxcsr(as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::ldmxcsr(Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::load_signed_byte(Register dst, Address src) { twisti@4318: int off; twisti@4318: if (LP64_ONLY(true ||) VM_Version::is_P6()) { twisti@4318: off = offset(); twisti@4318: movsbl(dst, src); // movsxb twisti@4318: } else { twisti@4318: off = load_unsigned_byte(dst, src); twisti@4318: shll(dst, 24); twisti@4318: sarl(dst, 24); twisti@4318: } twisti@4318: return off; twisti@4318: } twisti@4318: twisti@4318: // Note: load_signed_short used to be called load_signed_word. twisti@4318: // Although the 'w' in x86 opcodes refers to the term "word" in the assembler twisti@4318: // manual, which means 16 bits, that usage is found nowhere in HotSpot code. twisti@4318: // The term "word" in HotSpot means a 32- or 64-bit machine word. twisti@4318: int MacroAssembler::load_signed_short(Register dst, Address src) { twisti@4318: int off; twisti@4318: if (LP64_ONLY(true ||) VM_Version::is_P6()) { twisti@4318: // This is dubious to me since it seems safe to do a signed 16 => 64 bit twisti@4318: // version but this is what 64bit has always done. This seems to imply twisti@4318: // that users are only using 32bits worth. twisti@4318: off = offset(); twisti@4318: movswl(dst, src); // movsxw twisti@4318: } else { twisti@4318: off = load_unsigned_short(dst, src); twisti@4318: shll(dst, 16); twisti@4318: sarl(dst, 16); twisti@4318: } twisti@4318: return off; twisti@4318: } twisti@4318: twisti@4318: int MacroAssembler::load_unsigned_byte(Register dst, Address src) { twisti@4318: // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, twisti@4318: // and "3.9 Partial Register Penalties", p. 22). twisti@4318: int off; twisti@4318: if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { twisti@4318: off = offset(); twisti@4318: movzbl(dst, src); // movzxb twisti@4318: } else { twisti@4318: xorl(dst, dst); twisti@4318: off = offset(); twisti@4318: movb(dst, src); twisti@4318: } twisti@4318: return off; twisti@4318: } twisti@4318: twisti@4318: // Note: load_unsigned_short used to be called load_unsigned_word. twisti@4318: int MacroAssembler::load_unsigned_short(Register dst, Address src) { twisti@4318: // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, twisti@4318: // and "3.9 Partial Register Penalties", p. 22). twisti@4318: int off; twisti@4318: if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { twisti@4318: off = offset(); twisti@4318: movzwl(dst, src); // movzxw twisti@4318: } else { twisti@4318: xorl(dst, dst); twisti@4318: off = offset(); twisti@4318: movw(dst, src); twisti@4318: } twisti@4318: return off; twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { twisti@4318: switch (size_in_bytes) { twisti@4318: #ifndef _LP64 twisti@4318: case 8: twisti@4318: assert(dst2 != noreg, "second dest register required"); twisti@4318: movl(dst, src); twisti@4318: movl(dst2, src.plus_disp(BytesPerInt)); twisti@4318: break; twisti@4318: #else twisti@4318: case 8: movq(dst, src); break; twisti@4318: #endif twisti@4318: case 4: movl(dst, src); break; twisti@4318: case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; twisti@4318: case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; twisti@4318: default: ShouldNotReachHere(); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { twisti@4318: switch (size_in_bytes) { twisti@4318: #ifndef _LP64 twisti@4318: case 8: twisti@4318: assert(src2 != noreg, "second source register required"); twisti@4318: movl(dst, src); twisti@4318: movl(dst.plus_disp(BytesPerInt), src2); twisti@4318: break; twisti@4318: #else twisti@4318: case 8: movq(dst, src); break; twisti@4318: #endif twisti@4318: case 4: movl(dst, src); break; twisti@4318: case 2: movw(dst, src); break; twisti@4318: case 1: movb(dst, src); break; twisti@4318: default: ShouldNotReachHere(); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov32(AddressLiteral dst, Register src) { twisti@4318: if (reachable(dst)) { twisti@4318: movl(as_Address(dst), src); twisti@4318: } else { twisti@4318: lea(rscratch1, dst); twisti@4318: movl(Address(rscratch1, 0), src); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mov32(Register dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: movl(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: movl(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: // C++ bool manipulation twisti@4318: twisti@4318: void MacroAssembler::movbool(Register dst, Address src) { twisti@4318: if(sizeof(bool) == 1) twisti@4318: movb(dst, src); twisti@4318: else if(sizeof(bool) == 2) twisti@4318: movw(dst, src); twisti@4318: else if(sizeof(bool) == 4) twisti@4318: movl(dst, src); twisti@4318: else twisti@4318: // unsupported twisti@4318: ShouldNotReachHere(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movbool(Address dst, bool boolconst) { twisti@4318: if(sizeof(bool) == 1) twisti@4318: movb(dst, (int) boolconst); twisti@4318: else if(sizeof(bool) == 2) twisti@4318: movw(dst, (int) boolconst); twisti@4318: else if(sizeof(bool) == 4) twisti@4318: movl(dst, (int) boolconst); twisti@4318: else twisti@4318: // unsupported twisti@4318: ShouldNotReachHere(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movbool(Address dst, Register src) { twisti@4318: if(sizeof(bool) == 1) twisti@4318: movb(dst, src); twisti@4318: else if(sizeof(bool) == 2) twisti@4318: movw(dst, src); twisti@4318: else if(sizeof(bool) == 4) twisti@4318: movl(dst, src); twisti@4318: else twisti@4318: // unsupported twisti@4318: ShouldNotReachHere(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movbyte(ArrayAddress dst, int src) { twisti@4318: movb(as_Address(dst), src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: movdl(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: movdl(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: movq(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: movq(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: if (UseXmmLoadAndClearUpper) { twisti@4318: movsd (dst, as_Address(src)); twisti@4318: } else { twisti@4318: movlpd(dst, as_Address(src)); twisti@4318: } twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: if (UseXmmLoadAndClearUpper) { twisti@4318: movsd (dst, Address(rscratch1, 0)); twisti@4318: } else { twisti@4318: movlpd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: movss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: movss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, Register src) { twisti@4318: LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Register dst, Address src) { twisti@4318: LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: // src should NEVER be a real pointer. Use AddressLiteral for true pointers twisti@4318: void MacroAssembler::movptr(Register dst, intptr_t src) { twisti@4318: LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movptr(Address dst, Register src) { twisti@4318: LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::movdqu(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::movdqu(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::movsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::movsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::movss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::movss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::mulsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::mulsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::mulss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::mulss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::null_check(Register reg, int offset) { twisti@4318: if (needs_explicit_null_check(offset)) { twisti@4318: // provoke OS NULL exception if reg = NULL by twisti@4318: // accessing M[reg] w/o changing any (non-CC) registers twisti@4318: // NOTE: cmpl is plenty here to provoke a segv twisti@4318: cmpptr(rax, Address(reg, 0)); twisti@4318: // Note: should probably use testl(rax, Address(reg, 0)); twisti@4318: // may be shorter code (however, this version of twisti@4318: // testl needs to be implemented first) twisti@4318: } else { twisti@4318: // nothing to do, (later) access of M[reg + offset] twisti@4318: // will provoke OS NULL exception if reg = NULL twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::os_breakpoint() { twisti@4318: // instead of directly emitting a breakpoint, call os:breakpoint for better debugability twisti@4318: // (e.g., MSVC can't call ps() otherwise) twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pop_CPU_state() { twisti@4318: pop_FPU_state(); twisti@4318: pop_IU_state(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pop_FPU_state() { twisti@4318: NOT_LP64(frstor(Address(rsp, 0));) twisti@4318: LP64_ONLY(fxrstor(Address(rsp, 0));) twisti@4318: addptr(rsp, FPUStateSizeInWords * wordSize); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pop_IU_state() { twisti@4318: popa(); twisti@4318: LP64_ONLY(addq(rsp, 8)); twisti@4318: popf(); twisti@4318: } twisti@4318: twisti@4318: // Save Integer and Float state twisti@4318: // Warning: Stack must be 16 byte aligned (64bit) twisti@4318: void MacroAssembler::push_CPU_state() { twisti@4318: push_IU_state(); twisti@4318: push_FPU_state(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::push_FPU_state() { twisti@4318: subptr(rsp, FPUStateSizeInWords * wordSize); twisti@4318: #ifndef _LP64 twisti@4318: fnsave(Address(rsp, 0)); twisti@4318: fwait(); twisti@4318: #else twisti@4318: fxsave(Address(rsp, 0)); twisti@4318: #endif // LP64 twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::push_IU_state() { twisti@4318: // Push flags first because pusha kills them twisti@4318: pushf(); twisti@4318: // Make sure rsp stays 16-byte aligned twisti@4318: LP64_ONLY(subq(rsp, 8)); twisti@4318: pusha(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { twisti@4318: // determine java_thread register twisti@4318: if (!java_thread->is_valid()) { twisti@4318: java_thread = rdi; twisti@4318: get_thread(java_thread); twisti@4318: } twisti@4318: // we must set sp to zero to clear frame twisti@4318: movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); twisti@4318: if (clear_fp) { twisti@4318: movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); twisti@4318: } twisti@4318: twisti@4318: if (clear_pc) twisti@4318: movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); twisti@4318: twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::restore_rax(Register tmp) { twisti@4318: if (tmp == noreg) pop(rax); twisti@4318: else if (tmp != rax) mov(rax, tmp); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::round_to(Register reg, int modulus) { twisti@4318: addptr(reg, modulus - 1); twisti@4318: andptr(reg, -modulus); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::save_rax(Register tmp) { twisti@4318: if (tmp == noreg) push(rax); twisti@4318: else if (tmp != rax) mov(tmp, rax); twisti@4318: } twisti@4318: twisti@4318: // Write serialization page so VM thread can do a pseudo remote membar. twisti@4318: // We use the current thread pointer to calculate a thread specific twisti@4318: // offset to write to within the page. This minimizes bus traffic twisti@4318: // due to cache line collision. twisti@4318: void MacroAssembler::serialize_memory(Register thread, Register tmp) { twisti@4318: movl(tmp, thread); twisti@4318: shrl(tmp, os::get_serialize_page_shift_count()); twisti@4318: andl(tmp, (os::vm_page_size() - sizeof(int))); twisti@4318: twisti@4318: Address index(noreg, tmp, Address::times_1); twisti@4318: ExternalAddress page(os::get_memory_serialize_page()); twisti@4318: twisti@4318: // Size of store must match masking code above twisti@4318: movl(as_Address(ArrayAddress(page, index)), tmp); twisti@4318: } twisti@4318: twisti@4318: // Calls to C land twisti@4318: // twisti@4318: // When entering C land, the rbp, & rsp of the last Java frame have to be recorded twisti@4318: // in the (thread-local) JavaThread object. When leaving C land, the last Java fp twisti@4318: // has to be reset to 0. This is required to allow proper stack traversal. twisti@4318: void MacroAssembler::set_last_Java_frame(Register java_thread, twisti@4318: Register last_java_sp, twisti@4318: Register last_java_fp, twisti@4318: address last_java_pc) { twisti@4318: // determine java_thread register twisti@4318: if (!java_thread->is_valid()) { twisti@4318: java_thread = rdi; twisti@4318: get_thread(java_thread); twisti@4318: } twisti@4318: // determine last_java_sp register twisti@4318: if (!last_java_sp->is_valid()) { twisti@4318: last_java_sp = rsp; twisti@4318: } twisti@4318: twisti@4318: // last_java_fp is optional twisti@4318: twisti@4318: if (last_java_fp->is_valid()) { twisti@4318: movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); twisti@4318: } twisti@4318: twisti@4318: // last_java_pc is optional twisti@4318: twisti@4318: if (last_java_pc != NULL) { twisti@4318: lea(Address(java_thread, twisti@4318: JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), twisti@4318: InternalAddress(last_java_pc)); twisti@4318: twisti@4318: } twisti@4318: movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::shlptr(Register dst, int imm8) { twisti@4318: LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::shrptr(Register dst, int imm8) { twisti@4318: LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::sign_extend_byte(Register reg) { twisti@4318: if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { twisti@4318: movsbl(reg, reg); // movsxb twisti@4318: } else { twisti@4318: shll(reg, 24); twisti@4318: sarl(reg, 24); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::sign_extend_short(Register reg) { twisti@4318: if (LP64_ONLY(true ||) VM_Version::is_P6()) { twisti@4318: movswl(reg, reg); // movsxw twisti@4318: } else { twisti@4318: shll(reg, 16); twisti@4318: sarl(reg, 16); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::testl(Register dst, AddressLiteral src) { twisti@4318: assert(reachable(src), "Address should be reachable"); twisti@4318: testl(dst, as_Address(src)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::sqrtsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::sqrtsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::sqrtss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::sqrtss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::subsd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::subsd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::subss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::subss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::ucomisd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::ucomisd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: Assembler::ucomiss(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::ucomiss(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { twisti@4318: // Used in sign-bit flipping with aligned address. twisti@4318: assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); twisti@4318: if (reachable(src)) { twisti@4318: Assembler::xorpd(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::xorpd(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { twisti@4318: // Used in sign-bit flipping with aligned address. twisti@4318: assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); twisti@4318: if (reachable(src)) { twisti@4318: Assembler::xorps(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::xorps(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { twisti@4318: // Used in sign-bit flipping with aligned address. kvn@4363: bool aligned_adr = (((intptr_t)src.target() & 15) == 0); kvn@4363: assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); twisti@4318: if (reachable(src)) { twisti@4318: Assembler::pshufb(dst, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: Assembler::pshufb(dst, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: // AVX 3-operands instructions twisti@4318: twisti@4318: void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vaddsd(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vaddsd(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vaddss(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vaddss(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { twisti@4318: if (reachable(src)) { twisti@4318: vandpd(dst, nds, as_Address(src), vector256); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vandpd(dst, nds, Address(rscratch1, 0), vector256); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { twisti@4318: if (reachable(src)) { twisti@4318: vandps(dst, nds, as_Address(src), vector256); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vandps(dst, nds, Address(rscratch1, 0), vector256); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vdivsd(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vdivsd(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vdivss(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vdivss(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vmulsd(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vmulsd(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vmulss(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vmulss(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vsubsd(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vsubsd(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { twisti@4318: if (reachable(src)) { twisti@4318: vsubss(dst, nds, as_Address(src)); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vsubss(dst, nds, Address(rscratch1, 0)); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { twisti@4318: if (reachable(src)) { twisti@4318: vxorpd(dst, nds, as_Address(src), vector256); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vxorpd(dst, nds, Address(rscratch1, 0), vector256); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { twisti@4318: if (reachable(src)) { twisti@4318: vxorps(dst, nds, as_Address(src), vector256); twisti@4318: } else { twisti@4318: lea(rscratch1, src); twisti@4318: vxorps(dst, nds, Address(rscratch1, 0), vector256); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: twisti@4318: ////////////////////////////////////////////////////////////////////////////////// jprovino@4542: #if INCLUDE_ALL_GCS twisti@4318: twisti@4318: void MacroAssembler::g1_write_barrier_pre(Register obj, twisti@4318: Register pre_val, twisti@4318: Register thread, twisti@4318: Register tmp, twisti@4318: bool tosca_live, twisti@4318: bool expand_call) { twisti@4318: twisti@4318: // If expand_call is true then we expand the call_VM_leaf macro twisti@4318: // directly to skip generating the check by twisti@4318: // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: assert(thread == r15_thread, "must be"); twisti@4318: #endif // _LP64 twisti@4318: twisti@4318: Label done; twisti@4318: Label runtime; twisti@4318: twisti@4318: assert(pre_val != noreg, "check this code"); twisti@4318: twisti@4318: if (obj != noreg) { twisti@4318: assert_different_registers(obj, pre_val, tmp); twisti@4318: assert(pre_val != rax, "check this code"); twisti@4318: } twisti@4318: twisti@4318: Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4318: PtrQueue::byte_offset_of_active())); twisti@4318: Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4318: PtrQueue::byte_offset_of_index())); twisti@4318: Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4318: PtrQueue::byte_offset_of_buf())); twisti@4318: twisti@4318: twisti@4318: // Is marking active? twisti@4318: if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { twisti@4318: cmpl(in_progress, 0); twisti@4318: } else { twisti@4318: assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); twisti@4318: cmpb(in_progress, 0); twisti@4318: } twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: // Do we need to load the previous value? twisti@4318: if (obj != noreg) { twisti@4318: load_heap_oop(pre_val, Address(obj, 0)); twisti@4318: } twisti@4318: twisti@4318: // Is the previous value null? twisti@4318: cmpptr(pre_val, (int32_t) NULL_WORD); twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: // Can we store original value in the thread's buffer? twisti@4318: // Is index == 0? twisti@4318: // (The index field is typed as size_t.) twisti@4318: twisti@4318: movptr(tmp, index); // tmp := *index_adr twisti@4318: cmpptr(tmp, 0); // tmp == 0? twisti@4318: jcc(Assembler::equal, runtime); // If yes, goto runtime twisti@4318: twisti@4318: subptr(tmp, wordSize); // tmp := tmp - wordSize twisti@4318: movptr(index, tmp); // *index_adr := tmp twisti@4318: addptr(tmp, buffer); // tmp := tmp + *buffer_adr twisti@4318: twisti@4318: // Record the previous value twisti@4318: movptr(Address(tmp, 0), pre_val); twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(runtime); twisti@4318: // save the live input values twisti@4318: if(tosca_live) push(rax); twisti@4318: twisti@4318: if (obj != noreg && obj != rax) twisti@4318: push(obj); twisti@4318: twisti@4318: if (pre_val != rax) twisti@4318: push(pre_val); twisti@4318: twisti@4318: // Calling the runtime using the regular call_VM_leaf mechanism generates twisti@4318: // code (generated by InterpreterMacroAssember::call_VM_leaf_base) twisti@4318: // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. twisti@4318: // twisti@4318: // If we care generating the pre-barrier without a frame (e.g. in the twisti@4318: // intrinsified Reference.get() routine) then ebp might be pointing to twisti@4318: // the caller frame and so this check will most likely fail at runtime. twisti@4318: // twisti@4318: // Expanding the call directly bypasses the generation of the check. twisti@4318: // So when we do not have have a full interpreter frame on the stack twisti@4318: // expand_call should be passed true. twisti@4318: twisti@4318: NOT_LP64( push(thread); ) twisti@4318: twisti@4318: if (expand_call) { twisti@4318: LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) twisti@4318: pass_arg1(this, thread); twisti@4318: pass_arg0(this, pre_val); twisti@4318: MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); twisti@4318: } else { twisti@4318: call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); twisti@4318: } twisti@4318: twisti@4318: NOT_LP64( pop(thread); ) twisti@4318: twisti@4318: // save the live input values twisti@4318: if (pre_val != rax) twisti@4318: pop(pre_val); twisti@4318: twisti@4318: if (obj != noreg && obj != rax) twisti@4318: pop(obj); twisti@4318: twisti@4318: if(tosca_live) pop(rax); twisti@4318: twisti@4318: bind(done); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::g1_write_barrier_post(Register store_addr, twisti@4318: Register new_val, twisti@4318: Register thread, twisti@4318: Register tmp, twisti@4318: Register tmp2) { twisti@4318: #ifdef _LP64 twisti@4318: assert(thread == r15_thread, "must be"); twisti@4318: #endif // _LP64 twisti@4318: twisti@4318: Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + twisti@4318: PtrQueue::byte_offset_of_index())); twisti@4318: Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + twisti@4318: PtrQueue::byte_offset_of_buf())); twisti@4318: twisti@4318: BarrierSet* bs = Universe::heap()->barrier_set(); twisti@4318: CardTableModRefBS* ct = (CardTableModRefBS*)bs; twisti@4318: Label done; twisti@4318: Label runtime; twisti@4318: twisti@4318: // Does store cross heap regions? twisti@4318: twisti@4318: movptr(tmp, store_addr); twisti@4318: xorptr(tmp, new_val); twisti@4318: shrptr(tmp, HeapRegion::LogOfHRGrainBytes); twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: // crosses regions, storing NULL? twisti@4318: twisti@4318: cmpptr(new_val, (int32_t) NULL_WORD); twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: // storing region crossing non-NULL, is card already dirty? twisti@4318: twisti@4318: ExternalAddress cardtable((address) ct->byte_map_base); twisti@4318: assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); twisti@4318: #ifdef _LP64 twisti@4318: const Register card_addr = tmp; twisti@4318: twisti@4318: movq(card_addr, store_addr); twisti@4318: shrq(card_addr, CardTableModRefBS::card_shift); twisti@4318: twisti@4318: lea(tmp2, cardtable); twisti@4318: twisti@4318: // get the address of the card twisti@4318: addq(card_addr, tmp2); twisti@4318: #else twisti@4318: const Register card_index = tmp; twisti@4318: twisti@4318: movl(card_index, store_addr); twisti@4318: shrl(card_index, CardTableModRefBS::card_shift); twisti@4318: twisti@4318: Address index(noreg, card_index, Address::times_1); twisti@4318: const Register card_addr = tmp; twisti@4318: lea(card_addr, as_Address(ArrayAddress(cardtable, index))); twisti@4318: #endif twisti@4318: cmpb(Address(card_addr, 0), 0); twisti@4318: jcc(Assembler::equal, done); twisti@4318: twisti@4318: // storing a region crossing, non-NULL oop, card is clean. twisti@4318: // dirty card and log. twisti@4318: twisti@4318: movb(Address(card_addr, 0), 0); twisti@4318: twisti@4318: cmpl(queue_index, 0); twisti@4318: jcc(Assembler::equal, runtime); twisti@4318: subl(queue_index, wordSize); twisti@4318: movptr(tmp2, buffer); twisti@4318: #ifdef _LP64 twisti@4318: movslq(rscratch1, queue_index); twisti@4318: addq(tmp2, rscratch1); twisti@4318: movq(Address(tmp2, 0), card_addr); twisti@4318: #else twisti@4318: addl(tmp2, queue_index); twisti@4318: movl(Address(tmp2, 0), card_index); twisti@4318: #endif twisti@4318: jmp(done); twisti@4318: twisti@4318: bind(runtime); twisti@4318: // save the live input values twisti@4318: push(store_addr); twisti@4318: push(new_val); twisti@4318: #ifdef _LP64 twisti@4318: call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); twisti@4318: #else twisti@4318: push(thread); twisti@4318: call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); twisti@4318: pop(thread); twisti@4318: #endif twisti@4318: pop(new_val); twisti@4318: pop(store_addr); twisti@4318: twisti@4318: bind(done); twisti@4318: } twisti@4318: jprovino@4542: #endif // INCLUDE_ALL_GCS twisti@4318: ////////////////////////////////////////////////////////////////////////////////// twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::store_check(Register obj) { twisti@4318: // Does a store check for the oop in register obj. The content of twisti@4318: // register obj is destroyed afterwards. twisti@4318: store_check_part_1(obj); twisti@4318: store_check_part_2(obj); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::store_check(Register obj, Address dst) { twisti@4318: store_check(obj); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: // split the store check operation so that other instructions can be scheduled inbetween twisti@4318: void MacroAssembler::store_check_part_1(Register obj) { twisti@4318: BarrierSet* bs = Universe::heap()->barrier_set(); twisti@4318: assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); twisti@4318: shrptr(obj, CardTableModRefBS::card_shift); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::store_check_part_2(Register obj) { twisti@4318: BarrierSet* bs = Universe::heap()->barrier_set(); twisti@4318: assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); twisti@4318: CardTableModRefBS* ct = (CardTableModRefBS*)bs; twisti@4318: assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); twisti@4318: twisti@4318: // The calculation for byte_map_base is as follows: twisti@4318: // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); twisti@4318: // So this essentially converts an address to a displacement and twisti@4318: // it will never need to be relocated. On 64bit however the value may be too twisti@4318: // large for a 32bit displacement twisti@4318: twisti@4318: intptr_t disp = (intptr_t) ct->byte_map_base; twisti@4318: if (is_simm32(disp)) { twisti@4318: Address cardtable(noreg, obj, Address::times_1, disp); twisti@4318: movb(cardtable, 0); twisti@4318: } else { twisti@4318: // By doing it as an ExternalAddress disp could be converted to a rip-relative twisti@4318: // displacement and done in a single instruction given favorable mapping and twisti@4318: // a smarter version of as_Address. Worst case it is two instructions which twisti@4318: // is no worse off then loading disp into a register and doing as a simple twisti@4318: // Address() as above. twisti@4318: // We can't do as ExternalAddress as the only style since if disp == 0 we'll twisti@4318: // assert since NULL isn't acceptable in a reloci (see 6644928). In any case twisti@4318: // in some cases we'll get a single instruction version. twisti@4318: twisti@4318: ExternalAddress cardtable((address)disp); twisti@4318: Address index(noreg, obj, Address::times_1); twisti@4318: movb(as_Address(ArrayAddress(cardtable, index)), 0); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::subptr(Register dst, int32_t imm32) { twisti@4318: LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); twisti@4318: } twisti@4318: twisti@4318: // Force generation of a 4 byte immediate value even if it fits into 8bit twisti@4318: void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { twisti@4318: LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::subptr(Register dst, Register src) { twisti@4318: LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: // C++ bool manipulation twisti@4318: void MacroAssembler::testbool(Register dst) { twisti@4318: if(sizeof(bool) == 1) twisti@4318: testb(dst, 0xff); twisti@4318: else if(sizeof(bool) == 2) { twisti@4318: // testw implementation needed for two byte bools twisti@4318: ShouldNotReachHere(); twisti@4318: } else if(sizeof(bool) == 4) twisti@4318: testl(dst, dst); twisti@4318: else twisti@4318: // unsupported twisti@4318: ShouldNotReachHere(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::testptr(Register dst, Register src) { twisti@4318: LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); twisti@4318: } twisti@4318: twisti@4318: // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. twisti@4318: void MacroAssembler::tlab_allocate(Register obj, twisti@4318: Register var_size_in_bytes, twisti@4318: int con_size_in_bytes, twisti@4318: Register t1, twisti@4318: Register t2, twisti@4318: Label& slow_case) { twisti@4318: assert_different_registers(obj, t1, t2); twisti@4318: assert_different_registers(obj, var_size_in_bytes, t1); twisti@4318: Register end = t2; twisti@4318: Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); twisti@4318: twisti@4318: verify_tlab(); twisti@4318: twisti@4318: NOT_LP64(get_thread(thread)); twisti@4318: twisti@4318: movptr(obj, Address(thread, JavaThread::tlab_top_offset())); twisti@4318: if (var_size_in_bytes == noreg) { twisti@4318: lea(end, Address(obj, con_size_in_bytes)); twisti@4318: } else { twisti@4318: lea(end, Address(obj, var_size_in_bytes, Address::times_1)); twisti@4318: } twisti@4318: cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); twisti@4318: jcc(Assembler::above, slow_case); twisti@4318: twisti@4318: // update the tlab top pointer twisti@4318: movptr(Address(thread, JavaThread::tlab_top_offset()), end); twisti@4318: twisti@4318: // recover var_size_in_bytes if necessary twisti@4318: if (var_size_in_bytes == end) { twisti@4318: subptr(var_size_in_bytes, obj); twisti@4318: } twisti@4318: verify_tlab(); twisti@4318: } twisti@4318: twisti@4318: // Preserves rbx, and rdx. twisti@4318: Register MacroAssembler::tlab_refill(Label& retry, twisti@4318: Label& try_eden, twisti@4318: Label& slow_case) { twisti@4318: Register top = rax; twisti@4318: Register t1 = rcx; twisti@4318: Register t2 = rsi; twisti@4318: Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); twisti@4318: assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); twisti@4318: Label do_refill, discard_tlab; twisti@4318: twisti@4318: if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { twisti@4318: // No allocation in the shared eden. twisti@4318: jmp(slow_case); twisti@4318: } twisti@4318: twisti@4318: NOT_LP64(get_thread(thread_reg)); twisti@4318: twisti@4318: movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); twisti@4318: movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); twisti@4318: twisti@4318: // calculate amount of free space twisti@4318: subptr(t1, top); twisti@4318: shrptr(t1, LogHeapWordSize); twisti@4318: twisti@4318: // Retain tlab and allocate object in shared space if twisti@4318: // the amount free in the tlab is too large to discard. twisti@4318: cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); twisti@4318: jcc(Assembler::lessEqual, discard_tlab); twisti@4318: twisti@4318: // Retain twisti@4318: // %%% yuck as movptr... twisti@4318: movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); twisti@4318: addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); twisti@4318: if (TLABStats) { twisti@4318: // increment number of slow_allocations twisti@4318: addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); twisti@4318: } twisti@4318: jmp(try_eden); twisti@4318: twisti@4318: bind(discard_tlab); twisti@4318: if (TLABStats) { twisti@4318: // increment number of refills twisti@4318: addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); twisti@4318: // accumulate wastage -- t1 is amount free in tlab twisti@4318: addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); twisti@4318: } twisti@4318: twisti@4318: // if tlab is currently allocated (top or end != null) then twisti@4318: // fill [top, end + alignment_reserve) with array object twisti@4318: testptr(top, top); twisti@4318: jcc(Assembler::zero, do_refill); twisti@4318: twisti@4318: // set up the mark word twisti@4318: movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); twisti@4318: // set the length to the remaining space twisti@4318: subptr(t1, typeArrayOopDesc::header_size(T_INT)); twisti@4318: addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); twisti@4318: shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); twisti@4318: movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); twisti@4318: // set klass to intArrayKlass twisti@4318: // dubious reloc why not an oop reloc? twisti@4318: movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); twisti@4318: // store klass last. concurrent gcs assumes klass length is valid if twisti@4318: // klass field is not null. twisti@4318: store_klass(top, t1); twisti@4318: twisti@4318: movptr(t1, top); twisti@4318: subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); twisti@4318: incr_allocated_bytes(thread_reg, t1, 0); twisti@4318: twisti@4318: // refill the tlab with an eden allocation twisti@4318: bind(do_refill); twisti@4318: movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); twisti@4318: shlptr(t1, LogHeapWordSize); twisti@4318: // allocate new tlab, address returned in top twisti@4318: eden_allocate(top, t1, 0, t2, slow_case); twisti@4318: twisti@4318: // Check that t1 was preserved in eden_allocate. twisti@4318: #ifdef ASSERT twisti@4318: if (UseTLAB) { twisti@4318: Label ok; twisti@4318: Register tsize = rsi; twisti@4318: assert_different_registers(tsize, thread_reg, t1); twisti@4318: push(tsize); twisti@4318: movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); twisti@4318: shlptr(tsize, LogHeapWordSize); twisti@4318: cmpptr(t1, tsize); twisti@4318: jcc(Assembler::equal, ok); twisti@4318: STOP("assert(t1 != tlab size)"); twisti@4318: should_not_reach_here(); twisti@4318: twisti@4318: bind(ok); twisti@4318: pop(tsize); twisti@4318: } twisti@4318: #endif twisti@4318: movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); twisti@4318: movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); twisti@4318: addptr(top, t1); twisti@4318: subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); twisti@4318: movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); twisti@4318: verify_tlab(); twisti@4318: jmp(retry); twisti@4318: twisti@4318: return thread_reg; // for use by caller twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::incr_allocated_bytes(Register thread, twisti@4318: Register var_size_in_bytes, twisti@4318: int con_size_in_bytes, twisti@4318: Register t1) { twisti@4318: if (!thread->is_valid()) { twisti@4318: #ifdef _LP64 twisti@4318: thread = r15_thread; twisti@4318: #else twisti@4318: assert(t1->is_valid(), "need temp reg"); twisti@4318: thread = t1; twisti@4318: get_thread(thread); twisti@4318: #endif twisti@4318: } twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: if (var_size_in_bytes->is_valid()) { twisti@4318: addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); twisti@4318: } else { twisti@4318: addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); twisti@4318: } twisti@4318: #else twisti@4318: if (var_size_in_bytes->is_valid()) { twisti@4318: addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); twisti@4318: } else { twisti@4318: addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); twisti@4318: } twisti@4318: adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); twisti@4318: #endif twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { twisti@4318: pusha(); twisti@4318: twisti@4318: // if we are coming from c1, xmm registers may be live twisti@4318: int off = 0; twisti@4318: if (UseSSE == 1) { twisti@4318: subptr(rsp, sizeof(jdouble)*8); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); twisti@4318: movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); twisti@4318: } else if (UseSSE >= 2) { twisti@4318: #ifdef COMPILER2 twisti@4318: if (MaxVectorSize > 16) { twisti@4318: assert(UseAVX > 0, "256bit vectors are supported only with AVX"); twisti@4318: // Save upper half of YMM registes twisti@4318: subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); twisti@4318: vextractf128h(Address(rsp, 0),xmm0); twisti@4318: vextractf128h(Address(rsp, 16),xmm1); twisti@4318: vextractf128h(Address(rsp, 32),xmm2); twisti@4318: vextractf128h(Address(rsp, 48),xmm3); twisti@4318: vextractf128h(Address(rsp, 64),xmm4); twisti@4318: vextractf128h(Address(rsp, 80),xmm5); twisti@4318: vextractf128h(Address(rsp, 96),xmm6); twisti@4318: vextractf128h(Address(rsp,112),xmm7); twisti@4318: #ifdef _LP64 twisti@4318: vextractf128h(Address(rsp,128),xmm8); twisti@4318: vextractf128h(Address(rsp,144),xmm9); twisti@4318: vextractf128h(Address(rsp,160),xmm10); twisti@4318: vextractf128h(Address(rsp,176),xmm11); twisti@4318: vextractf128h(Address(rsp,192),xmm12); twisti@4318: vextractf128h(Address(rsp,208),xmm13); twisti@4318: vextractf128h(Address(rsp,224),xmm14); twisti@4318: vextractf128h(Address(rsp,240),xmm15); twisti@4318: #endif twisti@4318: } twisti@4318: #endif twisti@4318: // Save whole 128bit (16 bytes) XMM regiters twisti@4318: subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); twisti@4318: movdqu(Address(rsp,off++*16),xmm0); twisti@4318: movdqu(Address(rsp,off++*16),xmm1); twisti@4318: movdqu(Address(rsp,off++*16),xmm2); twisti@4318: movdqu(Address(rsp,off++*16),xmm3); twisti@4318: movdqu(Address(rsp,off++*16),xmm4); twisti@4318: movdqu(Address(rsp,off++*16),xmm5); twisti@4318: movdqu(Address(rsp,off++*16),xmm6); twisti@4318: movdqu(Address(rsp,off++*16),xmm7); twisti@4318: #ifdef _LP64 twisti@4318: movdqu(Address(rsp,off++*16),xmm8); twisti@4318: movdqu(Address(rsp,off++*16),xmm9); twisti@4318: movdqu(Address(rsp,off++*16),xmm10); twisti@4318: movdqu(Address(rsp,off++*16),xmm11); twisti@4318: movdqu(Address(rsp,off++*16),xmm12); twisti@4318: movdqu(Address(rsp,off++*16),xmm13); twisti@4318: movdqu(Address(rsp,off++*16),xmm14); twisti@4318: movdqu(Address(rsp,off++*16),xmm15); twisti@4318: #endif twisti@4318: } twisti@4318: twisti@4318: // Preserve registers across runtime call twisti@4318: int incoming_argument_and_return_value_offset = -1; twisti@4318: if (num_fpu_regs_in_use > 1) { twisti@4318: // Must preserve all other FPU regs (could alternatively convert twisti@4318: // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash twisti@4318: // FPU state, but can not trust C compiler) twisti@4318: NEEDS_CLEANUP; twisti@4318: // NOTE that in this case we also push the incoming argument(s) to twisti@4318: // the stack and restore it later; we also use this stack slot to twisti@4318: // hold the return value from dsin, dcos etc. twisti@4318: for (int i = 0; i < num_fpu_regs_in_use; i++) { twisti@4318: subptr(rsp, sizeof(jdouble)); twisti@4318: fstp_d(Address(rsp, 0)); twisti@4318: } twisti@4318: incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); twisti@4318: for (int i = nb_args-1; i >= 0; i--) { twisti@4318: fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: subptr(rsp, nb_args*sizeof(jdouble)); twisti@4318: for (int i = 0; i < nb_args; i++) { twisti@4318: fstp_d(Address(rsp, i*sizeof(jdouble))); twisti@4318: } twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: if (nb_args > 0) { twisti@4318: movdbl(xmm0, Address(rsp, 0)); twisti@4318: } twisti@4318: if (nb_args > 1) { twisti@4318: movdbl(xmm1, Address(rsp, sizeof(jdouble))); twisti@4318: } twisti@4318: assert(nb_args <= 2, "unsupported number of args"); twisti@4318: #endif // _LP64 twisti@4318: twisti@4318: // NOTE: we must not use call_VM_leaf here because that requires a twisti@4318: // complete interpreter frame in debug mode -- same bug as 4387334 twisti@4318: // MacroAssembler::call_VM_leaf_base is perfectly safe and will twisti@4318: // do proper 64bit abi twisti@4318: twisti@4318: NEEDS_CLEANUP; twisti@4318: // Need to add stack banging before this runtime call if it needs to twisti@4318: // be taken; however, there is no generic stack banging routine at twisti@4318: // the MacroAssembler level twisti@4318: twisti@4318: MacroAssembler::call_VM_leaf_base(runtime_entry, 0); twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: movsd(Address(rsp, 0), xmm0); twisti@4318: fld_d(Address(rsp, 0)); twisti@4318: #endif // _LP64 twisti@4318: addptr(rsp, sizeof(jdouble) * nb_args); twisti@4318: if (num_fpu_regs_in_use > 1) { twisti@4318: // Must save return value to stack and then restore entire FPU twisti@4318: // stack except incoming arguments twisti@4318: fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); twisti@4318: for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { twisti@4318: fld_d(Address(rsp, 0)); twisti@4318: addptr(rsp, sizeof(jdouble)); twisti@4318: } twisti@4318: fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); twisti@4318: addptr(rsp, sizeof(jdouble) * nb_args); twisti@4318: } twisti@4318: twisti@4318: off = 0; twisti@4318: if (UseSSE == 1) { twisti@4318: movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); twisti@4318: movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); twisti@4318: addptr(rsp, sizeof(jdouble)*8); twisti@4318: } else if (UseSSE >= 2) { twisti@4318: // Restore whole 128bit (16 bytes) XMM regiters twisti@4318: movdqu(xmm0, Address(rsp,off++*16)); twisti@4318: movdqu(xmm1, Address(rsp,off++*16)); twisti@4318: movdqu(xmm2, Address(rsp,off++*16)); twisti@4318: movdqu(xmm3, Address(rsp,off++*16)); twisti@4318: movdqu(xmm4, Address(rsp,off++*16)); twisti@4318: movdqu(xmm5, Address(rsp,off++*16)); twisti@4318: movdqu(xmm6, Address(rsp,off++*16)); twisti@4318: movdqu(xmm7, Address(rsp,off++*16)); twisti@4318: #ifdef _LP64 twisti@4318: movdqu(xmm8, Address(rsp,off++*16)); twisti@4318: movdqu(xmm9, Address(rsp,off++*16)); twisti@4318: movdqu(xmm10, Address(rsp,off++*16)); twisti@4318: movdqu(xmm11, Address(rsp,off++*16)); twisti@4318: movdqu(xmm12, Address(rsp,off++*16)); twisti@4318: movdqu(xmm13, Address(rsp,off++*16)); twisti@4318: movdqu(xmm14, Address(rsp,off++*16)); twisti@4318: movdqu(xmm15, Address(rsp,off++*16)); twisti@4318: #endif twisti@4318: addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); twisti@4318: #ifdef COMPILER2 twisti@4318: if (MaxVectorSize > 16) { twisti@4318: // Restore upper half of YMM registes. twisti@4318: vinsertf128h(xmm0, Address(rsp, 0)); twisti@4318: vinsertf128h(xmm1, Address(rsp, 16)); twisti@4318: vinsertf128h(xmm2, Address(rsp, 32)); twisti@4318: vinsertf128h(xmm3, Address(rsp, 48)); twisti@4318: vinsertf128h(xmm4, Address(rsp, 64)); twisti@4318: vinsertf128h(xmm5, Address(rsp, 80)); twisti@4318: vinsertf128h(xmm6, Address(rsp, 96)); twisti@4318: vinsertf128h(xmm7, Address(rsp,112)); twisti@4318: #ifdef _LP64 twisti@4318: vinsertf128h(xmm8, Address(rsp,128)); twisti@4318: vinsertf128h(xmm9, Address(rsp,144)); twisti@4318: vinsertf128h(xmm10, Address(rsp,160)); twisti@4318: vinsertf128h(xmm11, Address(rsp,176)); twisti@4318: vinsertf128h(xmm12, Address(rsp,192)); twisti@4318: vinsertf128h(xmm13, Address(rsp,208)); twisti@4318: vinsertf128h(xmm14, Address(rsp,224)); twisti@4318: vinsertf128h(xmm15, Address(rsp,240)); twisti@4318: #endif twisti@4318: addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); twisti@4318: } twisti@4318: #endif twisti@4318: } twisti@4318: popa(); twisti@4318: } twisti@4318: twisti@4318: static const double pi_4 = 0.7853981633974483; twisti@4318: twisti@4318: void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { twisti@4318: // A hand-coded argument reduction for values in fabs(pi/4, pi/2) twisti@4318: // was attempted in this code; unfortunately it appears that the twisti@4318: // switch to 80-bit precision and back causes this to be twisti@4318: // unprofitable compared with simply performing a runtime call if twisti@4318: // the argument is out of the (-pi/4, pi/4) range. twisti@4318: twisti@4318: Register tmp = noreg; twisti@4318: if (!VM_Version::supports_cmov()) { twisti@4318: // fcmp needs a temporary so preserve rbx, twisti@4318: tmp = rbx; twisti@4318: push(tmp); twisti@4318: } twisti@4318: twisti@4318: Label slow_case, done; twisti@4318: twisti@4318: ExternalAddress pi4_adr = (address)&pi_4; twisti@4318: if (reachable(pi4_adr)) { twisti@4318: // x ?<= pi/4 twisti@4318: fld_d(pi4_adr); twisti@4318: fld_s(1); // Stack: X PI/4 X twisti@4318: fabs(); // Stack: |X| PI/4 X twisti@4318: fcmp(tmp); twisti@4318: jcc(Assembler::above, slow_case); twisti@4318: twisti@4318: // fastest case: -pi/4 <= x <= pi/4 twisti@4318: switch(trig) { twisti@4318: case 's': twisti@4318: fsin(); twisti@4318: break; twisti@4318: case 'c': twisti@4318: fcos(); twisti@4318: break; twisti@4318: case 't': twisti@4318: ftan(); twisti@4318: break; twisti@4318: default: twisti@4318: assert(false, "bad intrinsic"); twisti@4318: break; twisti@4318: } twisti@4318: jmp(done); twisti@4318: } twisti@4318: twisti@4318: // slow case: runtime call twisti@4318: bind(slow_case); twisti@4318: twisti@4318: switch(trig) { twisti@4318: case 's': twisti@4318: { twisti@4318: fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); twisti@4318: } twisti@4318: break; twisti@4318: case 'c': twisti@4318: { twisti@4318: fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); twisti@4318: } twisti@4318: break; twisti@4318: case 't': twisti@4318: { twisti@4318: fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); twisti@4318: } twisti@4318: break; twisti@4318: default: twisti@4318: assert(false, "bad intrinsic"); twisti@4318: break; twisti@4318: } twisti@4318: twisti@4318: // Come here with result in F-TOS twisti@4318: bind(done); twisti@4318: twisti@4318: if (tmp != noreg) { twisti@4318: pop(tmp); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: twisti@4318: // Look up the method for a megamorphic invokeinterface call. twisti@4318: // The target method is determined by . twisti@4318: // The receiver klass is in recv_klass. twisti@4318: // On success, the result will be in method_result, and execution falls through. twisti@4318: // On failure, execution transfers to the given label. twisti@4318: void MacroAssembler::lookup_interface_method(Register recv_klass, twisti@4318: Register intf_klass, twisti@4318: RegisterOrConstant itable_index, twisti@4318: Register method_result, twisti@4318: Register scan_temp, twisti@4318: Label& L_no_such_interface) { twisti@4318: assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); twisti@4318: assert(itable_index.is_constant() || itable_index.as_register() == method_result, twisti@4318: "caller must use same register for non-constant itable index as for method"); twisti@4318: twisti@4318: // Compute start of first itableOffsetEntry (which is at the end of the vtable) twisti@4318: int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; twisti@4318: int itentry_off = itableMethodEntry::method_offset_in_bytes(); twisti@4318: int scan_step = itableOffsetEntry::size() * wordSize; twisti@4318: int vte_size = vtableEntry::size() * wordSize; twisti@4318: Address::ScaleFactor times_vte_scale = Address::times_ptr; twisti@4318: assert(vte_size == wordSize, "else adjust times_vte_scale"); twisti@4318: twisti@4318: movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); twisti@4318: twisti@4318: // %%% Could store the aligned, prescaled offset in the klassoop. twisti@4318: lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); twisti@4318: if (HeapWordsPerLong > 1) { twisti@4318: // Round up to align_object_offset boundary twisti@4318: // see code for InstanceKlass::start_of_itable! twisti@4318: round_to(scan_temp, BytesPerLong); twisti@4318: } twisti@4318: twisti@4318: // Adjust recv_klass by scaled itable_index, so we can free itable_index. twisti@4318: assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); twisti@4318: lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); twisti@4318: twisti@4318: // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { twisti@4318: // if (scan->interface() == intf) { twisti@4318: // result = (klass + scan->offset() + itable_index); twisti@4318: // } twisti@4318: // } twisti@4318: Label search, found_method; twisti@4318: twisti@4318: for (int peel = 1; peel >= 0; peel--) { twisti@4318: movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); twisti@4318: cmpptr(intf_klass, method_result); twisti@4318: twisti@4318: if (peel) { twisti@4318: jccb(Assembler::equal, found_method); twisti@4318: } else { twisti@4318: jccb(Assembler::notEqual, search); twisti@4318: // (invert the test to fall through to found_method...) twisti@4318: } twisti@4318: twisti@4318: if (!peel) break; twisti@4318: twisti@4318: bind(search); twisti@4318: twisti@4318: // Check that the previous entry is non-null. A null entry means that twisti@4318: // the receiver class doesn't implement the interface, and wasn't the twisti@4318: // same as when the caller was compiled. twisti@4318: testptr(method_result, method_result); twisti@4318: jcc(Assembler::zero, L_no_such_interface); twisti@4318: addptr(scan_temp, scan_step); twisti@4318: } twisti@4318: twisti@4318: bind(found_method); twisti@4318: twisti@4318: // Got a hit. twisti@4318: movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); twisti@4318: movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: // virtual method calling twisti@4318: void MacroAssembler::lookup_virtual_method(Register recv_klass, twisti@4318: RegisterOrConstant vtable_index, twisti@4318: Register method_result) { twisti@4318: const int base = InstanceKlass::vtable_start_offset() * wordSize; twisti@4318: assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); twisti@4318: Address vtable_entry_addr(recv_klass, twisti@4318: vtable_index, Address::times_ptr, twisti@4318: base + vtableEntry::method_offset_in_bytes()); twisti@4318: movptr(method_result, vtable_entry_addr); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::check_klass_subtype(Register sub_klass, twisti@4318: Register super_klass, twisti@4318: Register temp_reg, twisti@4318: Label& L_success) { twisti@4318: Label L_failure; twisti@4318: check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); twisti@4318: check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); twisti@4318: bind(L_failure); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, twisti@4318: Register super_klass, twisti@4318: Register temp_reg, twisti@4318: Label* L_success, twisti@4318: Label* L_failure, twisti@4318: Label* L_slow_path, twisti@4318: RegisterOrConstant super_check_offset) { twisti@4318: assert_different_registers(sub_klass, super_klass, temp_reg); twisti@4318: bool must_load_sco = (super_check_offset.constant_or_zero() == -1); twisti@4318: if (super_check_offset.is_register()) { twisti@4318: assert_different_registers(sub_klass, super_klass, twisti@4318: super_check_offset.as_register()); twisti@4318: } else if (must_load_sco) { twisti@4318: assert(temp_reg != noreg, "supply either a temp or a register offset"); twisti@4318: } twisti@4318: twisti@4318: Label L_fallthrough; twisti@4318: int label_nulls = 0; twisti@4318: if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } twisti@4318: if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } twisti@4318: if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } twisti@4318: assert(label_nulls <= 1, "at most one NULL in the batch"); twisti@4318: twisti@4318: int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); twisti@4318: int sco_offset = in_bytes(Klass::super_check_offset_offset()); twisti@4318: Address super_check_offset_addr(super_klass, sco_offset); twisti@4318: twisti@4318: // Hacked jcc, which "knows" that L_fallthrough, at least, is in twisti@4318: // range of a jccb. If this routine grows larger, reconsider at twisti@4318: // least some of these. twisti@4318: #define local_jcc(assembler_cond, label) \ twisti@4318: if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ twisti@4318: else jcc( assembler_cond, label) /*omit semi*/ twisti@4318: twisti@4318: // Hacked jmp, which may only be used just before L_fallthrough. twisti@4318: #define final_jmp(label) \ twisti@4318: if (&(label) == &L_fallthrough) { /*do nothing*/ } \ twisti@4318: else jmp(label) /*omit semi*/ twisti@4318: twisti@4318: // If the pointers are equal, we are done (e.g., String[] elements). twisti@4318: // This self-check enables sharing of secondary supertype arrays among twisti@4318: // non-primary types such as array-of-interface. Otherwise, each such twisti@4318: // type would need its own customized SSA. twisti@4318: // We move this check to the front of the fast path because many twisti@4318: // type checks are in fact trivially successful in this manner, twisti@4318: // so we get a nicely predicted branch right at the start of the check. twisti@4318: cmpptr(sub_klass, super_klass); twisti@4318: local_jcc(Assembler::equal, *L_success); twisti@4318: twisti@4318: // Check the supertype display: twisti@4318: if (must_load_sco) { twisti@4318: // Positive movl does right thing on LP64. twisti@4318: movl(temp_reg, super_check_offset_addr); twisti@4318: super_check_offset = RegisterOrConstant(temp_reg); twisti@4318: } twisti@4318: Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); twisti@4318: cmpptr(super_klass, super_check_addr); // load displayed supertype twisti@4318: twisti@4318: // This check has worked decisively for primary supers. twisti@4318: // Secondary supers are sought in the super_cache ('super_cache_addr'). twisti@4318: // (Secondary supers are interfaces and very deeply nested subtypes.) twisti@4318: // This works in the same check above because of a tricky aliasing twisti@4318: // between the super_cache and the primary super display elements. twisti@4318: // (The 'super_check_addr' can address either, as the case requires.) twisti@4318: // Note that the cache is updated below if it does not help us find twisti@4318: // what we need immediately. twisti@4318: // So if it was a primary super, we can just fail immediately. twisti@4318: // Otherwise, it's the slow path for us (no success at this point). twisti@4318: twisti@4318: if (super_check_offset.is_register()) { twisti@4318: local_jcc(Assembler::equal, *L_success); twisti@4318: cmpl(super_check_offset.as_register(), sc_offset); twisti@4318: if (L_failure == &L_fallthrough) { twisti@4318: local_jcc(Assembler::equal, *L_slow_path); twisti@4318: } else { twisti@4318: local_jcc(Assembler::notEqual, *L_failure); twisti@4318: final_jmp(*L_slow_path); twisti@4318: } twisti@4318: } else if (super_check_offset.as_constant() == sc_offset) { twisti@4318: // Need a slow path; fast failure is impossible. twisti@4318: if (L_slow_path == &L_fallthrough) { twisti@4318: local_jcc(Assembler::equal, *L_success); twisti@4318: } else { twisti@4318: local_jcc(Assembler::notEqual, *L_slow_path); twisti@4318: final_jmp(*L_success); twisti@4318: } twisti@4318: } else { twisti@4318: // No slow path; it's a fast decision. twisti@4318: if (L_failure == &L_fallthrough) { twisti@4318: local_jcc(Assembler::equal, *L_success); twisti@4318: } else { twisti@4318: local_jcc(Assembler::notEqual, *L_failure); twisti@4318: final_jmp(*L_success); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: bind(L_fallthrough); twisti@4318: twisti@4318: #undef local_jcc twisti@4318: #undef final_jmp twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, twisti@4318: Register super_klass, twisti@4318: Register temp_reg, twisti@4318: Register temp2_reg, twisti@4318: Label* L_success, twisti@4318: Label* L_failure, twisti@4318: bool set_cond_codes) { twisti@4318: assert_different_registers(sub_klass, super_klass, temp_reg); twisti@4318: if (temp2_reg != noreg) twisti@4318: assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); twisti@4318: #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) twisti@4318: twisti@4318: Label L_fallthrough; twisti@4318: int label_nulls = 0; twisti@4318: if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } twisti@4318: if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } twisti@4318: assert(label_nulls <= 1, "at most one NULL in the batch"); twisti@4318: twisti@4318: // a couple of useful fields in sub_klass: twisti@4318: int ss_offset = in_bytes(Klass::secondary_supers_offset()); twisti@4318: int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); twisti@4318: Address secondary_supers_addr(sub_klass, ss_offset); twisti@4318: Address super_cache_addr( sub_klass, sc_offset); twisti@4318: twisti@4318: // Do a linear scan of the secondary super-klass chain. twisti@4318: // This code is rarely used, so simplicity is a virtue here. twisti@4318: // The repne_scan instruction uses fixed registers, which we must spill. twisti@4318: // Don't worry too much about pre-existing connections with the input regs. twisti@4318: twisti@4318: assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) twisti@4318: assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) twisti@4318: twisti@4318: // Get super_klass value into rax (even if it was in rdi or rcx). twisti@4318: bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; twisti@4318: if (super_klass != rax || UseCompressedOops) { twisti@4318: if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } twisti@4318: mov(rax, super_klass); twisti@4318: } twisti@4318: if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } twisti@4318: if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } twisti@4318: twisti@4318: #ifndef PRODUCT twisti@4318: int* pst_counter = &SharedRuntime::_partial_subtype_ctr; twisti@4318: ExternalAddress pst_counter_addr((address) pst_counter); twisti@4318: NOT_LP64( incrementl(pst_counter_addr) ); twisti@4318: LP64_ONLY( lea(rcx, pst_counter_addr) ); twisti@4318: LP64_ONLY( incrementl(Address(rcx, 0)) ); twisti@4318: #endif //PRODUCT twisti@4318: twisti@4318: // We will consult the secondary-super array. twisti@4318: movptr(rdi, secondary_supers_addr); twisti@4318: // Load the array length. (Positive movl does right thing on LP64.) twisti@4318: movl(rcx, Address(rdi, Array::length_offset_in_bytes())); twisti@4318: // Skip to start of data. twisti@4318: addptr(rdi, Array::base_offset_in_bytes()); twisti@4318: twisti@4318: // Scan RCX words at [RDI] for an occurrence of RAX. twisti@4318: // Set NZ/Z based on last compare. twisti@4318: // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does twisti@4318: // not change flags (only scas instruction which is repeated sets flags). twisti@4318: // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. twisti@4318: twisti@4318: testptr(rax,rax); // Set Z = 0 twisti@4318: repne_scan(); twisti@4318: twisti@4318: // Unspill the temp. registers: twisti@4318: if (pushed_rdi) pop(rdi); twisti@4318: if (pushed_rcx) pop(rcx); twisti@4318: if (pushed_rax) pop(rax); twisti@4318: twisti@4318: if (set_cond_codes) { twisti@4318: // Special hack for the AD files: rdi is guaranteed non-zero. twisti@4318: assert(!pushed_rdi, "rdi must be left non-NULL"); twisti@4318: // Also, the condition codes are properly set Z/NZ on succeed/failure. twisti@4318: } twisti@4318: twisti@4318: if (L_failure == &L_fallthrough) twisti@4318: jccb(Assembler::notEqual, *L_failure); twisti@4318: else jcc(Assembler::notEqual, *L_failure); twisti@4318: twisti@4318: // Success. Cache the super we found and proceed in triumph. twisti@4318: movptr(super_cache_addr, super_klass); twisti@4318: twisti@4318: if (L_success != &L_fallthrough) { twisti@4318: jmp(*L_success); twisti@4318: } twisti@4318: twisti@4318: #undef IS_A_TEMP twisti@4318: twisti@4318: bind(L_fallthrough); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { twisti@4318: if (VM_Version::supports_cmov()) { twisti@4318: cmovl(cc, dst, src); twisti@4318: } else { twisti@4318: Label L; twisti@4318: jccb(negate_condition(cc), L); twisti@4318: movl(dst, src); twisti@4318: bind(L); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { twisti@4318: if (VM_Version::supports_cmov()) { twisti@4318: cmovl(cc, dst, src); twisti@4318: } else { twisti@4318: Label L; twisti@4318: jccb(negate_condition(cc), L); twisti@4318: movl(dst, src); twisti@4318: bind(L); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::verify_oop(Register reg, const char* s) { twisti@4318: if (!VerifyOops) return; twisti@4318: twisti@4318: // Pass register number to verify_oop_subroutine roland@4767: const char* b = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("verify_oop: %s: %s", reg->name(), s); roland@4767: b = code_string(ss.as_string()); roland@4767: } twisti@4318: BLOCK_COMMENT("verify_oop {"); twisti@4318: #ifdef _LP64 twisti@4318: push(rscratch1); // save r10, trashed by movptr() twisti@4318: #endif twisti@4318: push(rax); // save rax, twisti@4318: push(reg); // pass register argument twisti@4318: ExternalAddress buffer((address) b); twisti@4318: // avoid using pushptr, as it modifies scratch registers twisti@4318: // and our contract is not to modify anything twisti@4318: movptr(rax, buffer.addr()); twisti@4318: push(rax); twisti@4318: // call indirectly to solve generation ordering problem twisti@4318: movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); twisti@4318: call(rax); twisti@4318: // Caller pops the arguments (oop, message) and restores rax, r10 twisti@4318: BLOCK_COMMENT("} verify_oop"); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, twisti@4318: Register tmp, twisti@4318: int offset) { twisti@4318: intptr_t value = *delayed_value_addr; twisti@4318: if (value != 0) twisti@4318: return RegisterOrConstant(value + offset); twisti@4318: twisti@4318: // load indirectly to solve generation ordering problem twisti@4318: movptr(tmp, ExternalAddress((address) delayed_value_addr)); twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: { Label L; twisti@4318: testptr(tmp, tmp); twisti@4318: if (WizardMode) { roland@4767: const char* buf = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); roland@4767: buf = code_string(ss.as_string()); roland@4767: } twisti@4318: jcc(Assembler::notZero, L); twisti@4318: STOP(buf); twisti@4318: } else { twisti@4318: jccb(Assembler::notZero, L); twisti@4318: hlt(); twisti@4318: } twisti@4318: bind(L); twisti@4318: } twisti@4318: #endif twisti@4318: twisti@4318: if (offset != 0) twisti@4318: addptr(tmp, offset); twisti@4318: twisti@4318: return RegisterOrConstant(tmp); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, twisti@4318: int extra_slot_offset) { twisti@4318: // cf. TemplateTable::prepare_invoke(), if (load_receiver). twisti@4318: int stackElementSize = Interpreter::stackElementSize; twisti@4318: int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); twisti@4318: #ifdef ASSERT twisti@4318: int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); twisti@4318: assert(offset1 - offset == stackElementSize, "correct arithmetic"); twisti@4318: #endif twisti@4318: Register scale_reg = noreg; twisti@4318: Address::ScaleFactor scale_factor = Address::no_scale; twisti@4318: if (arg_slot.is_constant()) { twisti@4318: offset += arg_slot.as_constant() * stackElementSize; twisti@4318: } else { twisti@4318: scale_reg = arg_slot.as_register(); twisti@4318: scale_factor = Address::times(stackElementSize); twisti@4318: } twisti@4318: offset += wordSize; // return PC is on stack twisti@4318: return Address(rsp, scale_reg, scale_factor, offset); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::verify_oop_addr(Address addr, const char* s) { twisti@4318: if (!VerifyOops) return; twisti@4318: twisti@4318: // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); twisti@4318: // Pass register number to verify_oop_subroutine roland@4767: const char* b = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("verify_oop_addr: %s", s); roland@4767: b = code_string(ss.as_string()); roland@4767: } twisti@4318: #ifdef _LP64 twisti@4318: push(rscratch1); // save r10, trashed by movptr() twisti@4318: #endif twisti@4318: push(rax); // save rax, twisti@4318: // addr may contain rsp so we will have to adjust it based on the push twisti@4318: // we just did (and on 64 bit we do two pushes) twisti@4318: // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which twisti@4318: // stores rax into addr which is backwards of what was intended. twisti@4318: if (addr.uses(rsp)) { twisti@4318: lea(rax, addr); twisti@4318: pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); twisti@4318: } else { twisti@4318: pushptr(addr); twisti@4318: } twisti@4318: twisti@4318: ExternalAddress buffer((address) b); twisti@4318: // pass msg argument twisti@4318: // avoid using pushptr, as it modifies scratch registers twisti@4318: // and our contract is not to modify anything twisti@4318: movptr(rax, buffer.addr()); twisti@4318: push(rax); twisti@4318: twisti@4318: // call indirectly to solve generation ordering problem twisti@4318: movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); twisti@4318: call(rax); twisti@4318: // Caller pops the arguments (addr, message) and restores rax, r10. twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::verify_tlab() { twisti@4318: #ifdef ASSERT twisti@4318: if (UseTLAB && VerifyOops) { twisti@4318: Label next, ok; twisti@4318: Register t1 = rsi; twisti@4318: Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); twisti@4318: twisti@4318: push(t1); twisti@4318: NOT_LP64(push(thread_reg)); twisti@4318: NOT_LP64(get_thread(thread_reg)); twisti@4318: twisti@4318: movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); twisti@4318: cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); twisti@4318: jcc(Assembler::aboveEqual, next); twisti@4318: STOP("assert(top >= start)"); twisti@4318: should_not_reach_here(); twisti@4318: twisti@4318: bind(next); twisti@4318: movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); twisti@4318: cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); twisti@4318: jcc(Assembler::aboveEqual, ok); twisti@4318: STOP("assert(top <= end)"); twisti@4318: should_not_reach_here(); twisti@4318: twisti@4318: bind(ok); twisti@4318: NOT_LP64(pop(thread_reg)); twisti@4318: pop(t1); twisti@4318: } twisti@4318: #endif twisti@4318: } twisti@4318: twisti@4318: class ControlWord { twisti@4318: public: twisti@4318: int32_t _value; twisti@4318: twisti@4318: int rounding_control() const { return (_value >> 10) & 3 ; } twisti@4318: int precision_control() const { return (_value >> 8) & 3 ; } twisti@4318: bool precision() const { return ((_value >> 5) & 1) != 0; } twisti@4318: bool underflow() const { return ((_value >> 4) & 1) != 0; } twisti@4318: bool overflow() const { return ((_value >> 3) & 1) != 0; } twisti@4318: bool zero_divide() const { return ((_value >> 2) & 1) != 0; } twisti@4318: bool denormalized() const { return ((_value >> 1) & 1) != 0; } twisti@4318: bool invalid() const { return ((_value >> 0) & 1) != 0; } twisti@4318: twisti@4318: void print() const { twisti@4318: // rounding control twisti@4318: const char* rc; twisti@4318: switch (rounding_control()) { twisti@4318: case 0: rc = "round near"; break; twisti@4318: case 1: rc = "round down"; break; twisti@4318: case 2: rc = "round up "; break; twisti@4318: case 3: rc = "chop "; break; twisti@4318: }; twisti@4318: // precision control twisti@4318: const char* pc; twisti@4318: switch (precision_control()) { twisti@4318: case 0: pc = "24 bits "; break; twisti@4318: case 1: pc = "reserved"; break; twisti@4318: case 2: pc = "53 bits "; break; twisti@4318: case 3: pc = "64 bits "; break; twisti@4318: }; twisti@4318: // flags twisti@4318: char f[9]; twisti@4318: f[0] = ' '; twisti@4318: f[1] = ' '; twisti@4318: f[2] = (precision ()) ? 'P' : 'p'; twisti@4318: f[3] = (underflow ()) ? 'U' : 'u'; twisti@4318: f[4] = (overflow ()) ? 'O' : 'o'; twisti@4318: f[5] = (zero_divide ()) ? 'Z' : 'z'; twisti@4318: f[6] = (denormalized()) ? 'D' : 'd'; twisti@4318: f[7] = (invalid ()) ? 'I' : 'i'; twisti@4318: f[8] = '\x0'; twisti@4318: // output twisti@4318: printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class StatusWord { twisti@4318: public: twisti@4318: int32_t _value; twisti@4318: twisti@4318: bool busy() const { return ((_value >> 15) & 1) != 0; } twisti@4318: bool C3() const { return ((_value >> 14) & 1) != 0; } twisti@4318: bool C2() const { return ((_value >> 10) & 1) != 0; } twisti@4318: bool C1() const { return ((_value >> 9) & 1) != 0; } twisti@4318: bool C0() const { return ((_value >> 8) & 1) != 0; } twisti@4318: int top() const { return (_value >> 11) & 7 ; } twisti@4318: bool error_status() const { return ((_value >> 7) & 1) != 0; } twisti@4318: bool stack_fault() const { return ((_value >> 6) & 1) != 0; } twisti@4318: bool precision() const { return ((_value >> 5) & 1) != 0; } twisti@4318: bool underflow() const { return ((_value >> 4) & 1) != 0; } twisti@4318: bool overflow() const { return ((_value >> 3) & 1) != 0; } twisti@4318: bool zero_divide() const { return ((_value >> 2) & 1) != 0; } twisti@4318: bool denormalized() const { return ((_value >> 1) & 1) != 0; } twisti@4318: bool invalid() const { return ((_value >> 0) & 1) != 0; } twisti@4318: twisti@4318: void print() const { twisti@4318: // condition codes twisti@4318: char c[5]; twisti@4318: c[0] = (C3()) ? '3' : '-'; twisti@4318: c[1] = (C2()) ? '2' : '-'; twisti@4318: c[2] = (C1()) ? '1' : '-'; twisti@4318: c[3] = (C0()) ? '0' : '-'; twisti@4318: c[4] = '\x0'; twisti@4318: // flags twisti@4318: char f[9]; twisti@4318: f[0] = (error_status()) ? 'E' : '-'; twisti@4318: f[1] = (stack_fault ()) ? 'S' : '-'; twisti@4318: f[2] = (precision ()) ? 'P' : '-'; twisti@4318: f[3] = (underflow ()) ? 'U' : '-'; twisti@4318: f[4] = (overflow ()) ? 'O' : '-'; twisti@4318: f[5] = (zero_divide ()) ? 'Z' : '-'; twisti@4318: f[6] = (denormalized()) ? 'D' : '-'; twisti@4318: f[7] = (invalid ()) ? 'I' : '-'; twisti@4318: f[8] = '\x0'; twisti@4318: // output twisti@4318: printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class TagWord { twisti@4318: public: twisti@4318: int32_t _value; twisti@4318: twisti@4318: int tag_at(int i) const { return (_value >> (i*2)) & 3; } twisti@4318: twisti@4318: void print() const { twisti@4318: printf("%04x", _value & 0xFFFF); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class FPU_Register { twisti@4318: public: twisti@4318: int32_t _m0; twisti@4318: int32_t _m1; twisti@4318: int16_t _ex; twisti@4318: twisti@4318: bool is_indefinite() const { twisti@4318: return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; twisti@4318: } twisti@4318: twisti@4318: void print() const { twisti@4318: char sign = (_ex < 0) ? '-' : '+'; twisti@4318: const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; twisti@4318: printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); twisti@4318: }; twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class FPU_State { twisti@4318: public: twisti@4318: enum { twisti@4318: register_size = 10, twisti@4318: number_of_registers = 8, twisti@4318: register_mask = 7 twisti@4318: }; twisti@4318: twisti@4318: ControlWord _control_word; twisti@4318: StatusWord _status_word; twisti@4318: TagWord _tag_word; twisti@4318: int32_t _error_offset; twisti@4318: int32_t _error_selector; twisti@4318: int32_t _data_offset; twisti@4318: int32_t _data_selector; twisti@4318: int8_t _register[register_size * number_of_registers]; twisti@4318: twisti@4318: int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } twisti@4318: FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } twisti@4318: twisti@4318: const char* tag_as_string(int tag) const { twisti@4318: switch (tag) { twisti@4318: case 0: return "valid"; twisti@4318: case 1: return "zero"; twisti@4318: case 2: return "special"; twisti@4318: case 3: return "empty"; twisti@4318: } twisti@4318: ShouldNotReachHere(); twisti@4318: return NULL; twisti@4318: } twisti@4318: twisti@4318: void print() const { twisti@4318: // print computation registers twisti@4318: { int t = _status_word.top(); twisti@4318: for (int i = 0; i < number_of_registers; i++) { twisti@4318: int j = (i - t) & register_mask; twisti@4318: printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); twisti@4318: st(j)->print(); twisti@4318: printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); twisti@4318: } twisti@4318: } twisti@4318: printf("\n"); twisti@4318: // print control registers twisti@4318: printf("ctrl = "); _control_word.print(); printf("\n"); twisti@4318: printf("stat = "); _status_word .print(); printf("\n"); twisti@4318: printf("tags = "); _tag_word .print(); printf("\n"); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class Flag_Register { twisti@4318: public: twisti@4318: int32_t _value; twisti@4318: twisti@4318: bool overflow() const { return ((_value >> 11) & 1) != 0; } twisti@4318: bool direction() const { return ((_value >> 10) & 1) != 0; } twisti@4318: bool sign() const { return ((_value >> 7) & 1) != 0; } twisti@4318: bool zero() const { return ((_value >> 6) & 1) != 0; } twisti@4318: bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } twisti@4318: bool parity() const { return ((_value >> 2) & 1) != 0; } twisti@4318: bool carry() const { return ((_value >> 0) & 1) != 0; } twisti@4318: twisti@4318: void print() const { twisti@4318: // flags twisti@4318: char f[8]; twisti@4318: f[0] = (overflow ()) ? 'O' : '-'; twisti@4318: f[1] = (direction ()) ? 'D' : '-'; twisti@4318: f[2] = (sign ()) ? 'S' : '-'; twisti@4318: f[3] = (zero ()) ? 'Z' : '-'; twisti@4318: f[4] = (auxiliary_carry()) ? 'A' : '-'; twisti@4318: f[5] = (parity ()) ? 'P' : '-'; twisti@4318: f[6] = (carry ()) ? 'C' : '-'; twisti@4318: f[7] = '\x0'; twisti@4318: // output twisti@4318: printf("%08x flags = %s", _value, f); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class IU_Register { twisti@4318: public: twisti@4318: int32_t _value; twisti@4318: twisti@4318: void print() const { twisti@4318: printf("%08x %11d", _value, _value); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: class IU_State { twisti@4318: public: twisti@4318: Flag_Register _eflags; twisti@4318: IU_Register _rdi; twisti@4318: IU_Register _rsi; twisti@4318: IU_Register _rbp; twisti@4318: IU_Register _rsp; twisti@4318: IU_Register _rbx; twisti@4318: IU_Register _rdx; twisti@4318: IU_Register _rcx; twisti@4318: IU_Register _rax; twisti@4318: twisti@4318: void print() const { twisti@4318: // computation registers twisti@4318: printf("rax, = "); _rax.print(); printf("\n"); twisti@4318: printf("rbx, = "); _rbx.print(); printf("\n"); twisti@4318: printf("rcx = "); _rcx.print(); printf("\n"); twisti@4318: printf("rdx = "); _rdx.print(); printf("\n"); twisti@4318: printf("rdi = "); _rdi.print(); printf("\n"); twisti@4318: printf("rsi = "); _rsi.print(); printf("\n"); twisti@4318: printf("rbp, = "); _rbp.print(); printf("\n"); twisti@4318: printf("rsp = "); _rsp.print(); printf("\n"); twisti@4318: printf("\n"); twisti@4318: // control registers twisti@4318: printf("flgs = "); _eflags.print(); printf("\n"); twisti@4318: } twisti@4318: }; twisti@4318: twisti@4318: twisti@4318: class CPU_State { twisti@4318: public: twisti@4318: FPU_State _fpu_state; twisti@4318: IU_State _iu_state; twisti@4318: twisti@4318: void print() const { twisti@4318: printf("--------------------------------------------------\n"); twisti@4318: _iu_state .print(); twisti@4318: printf("\n"); twisti@4318: _fpu_state.print(); twisti@4318: printf("--------------------------------------------------\n"); twisti@4318: } twisti@4318: twisti@4318: }; twisti@4318: twisti@4318: twisti@4318: static void _print_CPU_state(CPU_State* state) { twisti@4318: state->print(); twisti@4318: }; twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::print_CPU_state() { twisti@4318: push_CPU_state(); twisti@4318: push(rsp); // pass CPU state twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); twisti@4318: addptr(rsp, wordSize); // discard argument twisti@4318: pop_CPU_state(); twisti@4318: } twisti@4318: twisti@4318: twisti@4318: static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { twisti@4318: static int counter = 0; twisti@4318: FPU_State* fs = &state->_fpu_state; twisti@4318: counter++; twisti@4318: // For leaf calls, only verify that the top few elements remain empty. twisti@4318: // We only need 1 empty at the top for C2 code. twisti@4318: if( stack_depth < 0 ) { twisti@4318: if( fs->tag_for_st(7) != 3 ) { twisti@4318: printf("FPR7 not empty\n"); twisti@4318: state->print(); twisti@4318: assert(false, "error"); twisti@4318: return false; twisti@4318: } twisti@4318: return true; // All other stack states do not matter twisti@4318: } twisti@4318: twisti@4318: assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, twisti@4318: "bad FPU control word"); twisti@4318: twisti@4318: // compute stack depth twisti@4318: int i = 0; twisti@4318: while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; twisti@4318: int d = i; twisti@4318: while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; twisti@4318: // verify findings twisti@4318: if (i != FPU_State::number_of_registers) { twisti@4318: // stack not contiguous twisti@4318: printf("%s: stack not contiguous at ST%d\n", s, i); twisti@4318: state->print(); twisti@4318: assert(false, "error"); twisti@4318: return false; twisti@4318: } twisti@4318: // check if computed stack depth corresponds to expected stack depth twisti@4318: if (stack_depth < 0) { twisti@4318: // expected stack depth is -stack_depth or less twisti@4318: if (d > -stack_depth) { twisti@4318: // too many elements on the stack twisti@4318: printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); twisti@4318: state->print(); twisti@4318: assert(false, "error"); twisti@4318: return false; twisti@4318: } twisti@4318: } else { twisti@4318: // expected stack depth is stack_depth twisti@4318: if (d != stack_depth) { twisti@4318: // wrong stack depth twisti@4318: printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); twisti@4318: state->print(); twisti@4318: assert(false, "error"); twisti@4318: return false; twisti@4318: } twisti@4318: } twisti@4318: // everything is cool twisti@4318: return true; twisti@4318: } twisti@4318: twisti@4318: twisti@4318: void MacroAssembler::verify_FPU(int stack_depth, const char* s) { twisti@4318: if (!VerifyFPU) return; twisti@4318: push_CPU_state(); twisti@4318: push(rsp); // pass CPU state twisti@4318: ExternalAddress msg((address) s); twisti@4318: // pass message string s twisti@4318: pushptr(msg.addr()); twisti@4318: push(stack_depth); // pass stack depth twisti@4318: call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); twisti@4318: addptr(rsp, 3 * wordSize); // discard arguments twisti@4318: // check for error twisti@4318: { Label L; twisti@4318: testl(rax, rax); twisti@4318: jcc(Assembler::notZero, L); twisti@4318: int3(); // break if error condition twisti@4318: bind(L); twisti@4318: } twisti@4318: pop_CPU_state(); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::load_klass(Register dst, Register src) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedKlassPointers) { twisti@4318: movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); twisti@4318: decode_klass_not_null(dst); twisti@4318: } else twisti@4318: #endif twisti@4318: movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::load_prototype_header(Register dst, Register src) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedKlassPointers) { twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); twisti@4318: if (Universe::narrow_klass_shift() != 0) { twisti@4318: assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); twisti@4318: assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); twisti@4318: movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); twisti@4318: } else { twisti@4318: movq(dst, Address(dst, Klass::prototype_header_offset())); twisti@4318: } twisti@4318: } else twisti@4318: #endif twisti@4318: { twisti@4318: movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); twisti@4318: movptr(dst, Address(dst, Klass::prototype_header_offset())); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::store_klass(Register dst, Register src) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedKlassPointers) { twisti@4318: encode_klass_not_null(src); twisti@4318: movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); twisti@4318: } else twisti@4318: #endif twisti@4318: movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::load_heap_oop(Register dst, Address src) { twisti@4318: #ifdef _LP64 twisti@4318: // FIXME: Must change all places where we try to load the klass. twisti@4318: if (UseCompressedOops) { twisti@4318: movl(dst, src); twisti@4318: decode_heap_oop(dst); twisti@4318: } else twisti@4318: #endif twisti@4318: movptr(dst, src); twisti@4318: } twisti@4318: twisti@4318: // Doesn't do verfication, generates fixed size code twisti@4318: void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedOops) { twisti@4318: movl(dst, src); twisti@4318: decode_heap_oop_not_null(dst); twisti@4318: } else twisti@4318: #endif twisti@4318: movptr(dst, src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::store_heap_oop(Address dst, Register src) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedOops) { twisti@4318: assert(!dst.uses(src), "not enough registers"); twisti@4318: encode_heap_oop(src); twisti@4318: movl(dst, src); twisti@4318: } else twisti@4318: #endif twisti@4318: movptr(dst, src); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { twisti@4318: assert_different_registers(src1, tmp); twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedOops) { twisti@4318: bool did_push = false; twisti@4318: if (tmp == noreg) { twisti@4318: tmp = rax; twisti@4318: push(tmp); twisti@4318: did_push = true; twisti@4318: assert(!src2.uses(rsp), "can't push"); twisti@4318: } twisti@4318: load_heap_oop(tmp, src2); twisti@4318: cmpptr(src1, tmp); twisti@4318: if (did_push) pop(tmp); twisti@4318: } else twisti@4318: #endif twisti@4318: cmpptr(src1, src2); twisti@4318: } twisti@4318: twisti@4318: // Used for storing NULLs. twisti@4318: void MacroAssembler::store_heap_oop_null(Address dst) { twisti@4318: #ifdef _LP64 twisti@4318: if (UseCompressedOops) { twisti@4318: movl(dst, (int32_t)NULL_WORD); twisti@4318: } else { twisti@4318: movslq(dst, (int32_t)NULL_WORD); twisti@4318: } twisti@4318: #else twisti@4318: movl(dst, (int32_t)NULL_WORD); twisti@4318: #endif twisti@4318: } twisti@4318: twisti@4318: #ifdef _LP64 twisti@4318: void MacroAssembler::store_klass_gap(Register dst, Register src) { twisti@4318: if (UseCompressedKlassPointers) { twisti@4318: // Store to klass gap in destination twisti@4318: movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: void MacroAssembler::verify_heapbase(const char* msg) { twisti@4318: assert (UseCompressedOops || UseCompressedKlassPointers, "should be compressed"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: if (CheckCompressedOops) { twisti@4318: Label ok; twisti@4318: push(rscratch1); // cmpptr trashes rscratch1 twisti@4318: cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); twisti@4318: jcc(Assembler::equal, ok); twisti@4318: STOP(msg); twisti@4318: bind(ok); twisti@4318: pop(rscratch1); twisti@4318: } twisti@4318: } twisti@4318: #endif twisti@4318: twisti@4318: // Algorithm must match oop.inline.hpp encode_heap_oop. twisti@4318: void MacroAssembler::encode_heap_oop(Register r) { twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); twisti@4318: #endif twisti@4318: verify_oop(r, "broken oop in encode_heap_oop"); twisti@4318: if (Universe::narrow_oop_base() == NULL) { twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: shrq(r, LogMinObjAlignmentInBytes); twisti@4318: } twisti@4318: return; twisti@4318: } twisti@4318: testq(r, r); twisti@4318: cmovq(Assembler::equal, r, r12_heapbase); twisti@4318: subq(r, r12_heapbase); twisti@4318: shrq(r, LogMinObjAlignmentInBytes); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::encode_heap_oop_not_null(Register r) { twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); twisti@4318: if (CheckCompressedOops) { twisti@4318: Label ok; twisti@4318: testq(r, r); twisti@4318: jcc(Assembler::notEqual, ok); twisti@4318: STOP("null oop passed to encode_heap_oop_not_null"); twisti@4318: bind(ok); twisti@4318: } twisti@4318: #endif twisti@4318: verify_oop(r, "broken oop in encode_heap_oop_not_null"); twisti@4318: if (Universe::narrow_oop_base() != NULL) { twisti@4318: subq(r, r12_heapbase); twisti@4318: } twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: shrq(r, LogMinObjAlignmentInBytes); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); twisti@4318: if (CheckCompressedOops) { twisti@4318: Label ok; twisti@4318: testq(src, src); twisti@4318: jcc(Assembler::notEqual, ok); twisti@4318: STOP("null oop passed to encode_heap_oop_not_null2"); twisti@4318: bind(ok); twisti@4318: } twisti@4318: #endif twisti@4318: verify_oop(src, "broken oop in encode_heap_oop_not_null2"); twisti@4318: if (dst != src) { twisti@4318: movq(dst, src); twisti@4318: } twisti@4318: if (Universe::narrow_oop_base() != NULL) { twisti@4318: subq(dst, r12_heapbase); twisti@4318: } twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: shrq(dst, LogMinObjAlignmentInBytes); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decode_heap_oop(Register r) { twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); twisti@4318: #endif twisti@4318: if (Universe::narrow_oop_base() == NULL) { twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: shlq(r, LogMinObjAlignmentInBytes); twisti@4318: } twisti@4318: } else { twisti@4318: Label done; twisti@4318: shlq(r, LogMinObjAlignmentInBytes); twisti@4318: jccb(Assembler::equal, done); twisti@4318: addq(r, r12_heapbase); twisti@4318: bind(done); twisti@4318: } twisti@4318: verify_oop(r, "broken oop in decode_heap_oop"); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decode_heap_oop_not_null(Register r) { twisti@4318: // Note: it will change flags twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: // Cannot assert, unverified entry point counts instructions (see .ad file) twisti@4318: // vtableStubs also counts instructions in pd_code_size_limit. twisti@4318: // Also do not verify_oop as this is called by verify_oop. twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: shlq(r, LogMinObjAlignmentInBytes); twisti@4318: if (Universe::narrow_oop_base() != NULL) { twisti@4318: addq(r, r12_heapbase); twisti@4318: } twisti@4318: } else { twisti@4318: assert (Universe::narrow_oop_base() == NULL, "sanity"); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { twisti@4318: // Note: it will change flags twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: // Cannot assert, unverified entry point counts instructions (see .ad file) twisti@4318: // vtableStubs also counts instructions in pd_code_size_limit. twisti@4318: // Also do not verify_oop as this is called by verify_oop. twisti@4318: if (Universe::narrow_oop_shift() != 0) { twisti@4318: assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4318: if (LogMinObjAlignmentInBytes == Address::times_8) { twisti@4318: leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); twisti@4318: } else { twisti@4318: if (dst != src) { twisti@4318: movq(dst, src); twisti@4318: } twisti@4318: shlq(dst, LogMinObjAlignmentInBytes); twisti@4318: if (Universe::narrow_oop_base() != NULL) { twisti@4318: addq(dst, r12_heapbase); twisti@4318: } twisti@4318: } twisti@4318: } else { twisti@4318: assert (Universe::narrow_oop_base() == NULL, "sanity"); twisti@4318: if (dst != src) { twisti@4318: movq(dst, src); twisti@4318: } twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::encode_klass_not_null(Register r) { twisti@4318: assert(Metaspace::is_initialized(), "metaspace should be initialized"); twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::encode_klass_not_null: heap base corrupted?"); twisti@4318: #endif twisti@4318: if (Universe::narrow_klass_base() != NULL) { twisti@4318: subq(r, r12_heapbase); twisti@4318: } twisti@4318: if (Universe::narrow_klass_shift() != 0) { twisti@4318: assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); twisti@4318: shrq(r, LogKlassAlignmentInBytes); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::encode_klass_not_null(Register dst, Register src) { twisti@4318: assert(Metaspace::is_initialized(), "metaspace should be initialized"); twisti@4318: #ifdef ASSERT twisti@4318: verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); twisti@4318: #endif twisti@4318: if (dst != src) { twisti@4318: movq(dst, src); twisti@4318: } twisti@4318: if (Universe::narrow_klass_base() != NULL) { twisti@4318: subq(dst, r12_heapbase); twisti@4318: } twisti@4318: if (Universe::narrow_klass_shift() != 0) { twisti@4318: assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); twisti@4318: shrq(dst, LogKlassAlignmentInBytes); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decode_klass_not_null(Register r) { twisti@4318: assert(Metaspace::is_initialized(), "metaspace should be initialized"); twisti@4318: // Note: it will change flags twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: // Cannot assert, unverified entry point counts instructions (see .ad file) twisti@4318: // vtableStubs also counts instructions in pd_code_size_limit. twisti@4318: // Also do not verify_oop as this is called by verify_oop. twisti@4318: if (Universe::narrow_klass_shift() != 0) { twisti@4318: assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); twisti@4318: shlq(r, LogKlassAlignmentInBytes); twisti@4318: if (Universe::narrow_klass_base() != NULL) { twisti@4318: addq(r, r12_heapbase); twisti@4318: } twisti@4318: } else { twisti@4318: assert (Universe::narrow_klass_base() == NULL, "sanity"); twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::decode_klass_not_null(Register dst, Register src) { twisti@4318: assert(Metaspace::is_initialized(), "metaspace should be initialized"); twisti@4318: // Note: it will change flags twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: // Cannot assert, unverified entry point counts instructions (see .ad file) twisti@4318: // vtableStubs also counts instructions in pd_code_size_limit. twisti@4318: // Also do not verify_oop as this is called by verify_oop. twisti@4318: if (Universe::narrow_klass_shift() != 0) { twisti@4318: assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); twisti@4318: assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); twisti@4318: leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); twisti@4318: } else { twisti@4318: assert (Universe::narrow_klass_base() == NULL, "sanity"); twisti@4318: if (dst != src) { twisti@4318: movq(dst, src); twisti@4318: } twisti@4318: } twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int oop_index = oop_recorder()->find_index(obj); twisti@4318: RelocationHolder rspec = oop_Relocation::spec(oop_index); twisti@4318: mov_narrow_oop(dst, oop_index, rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int oop_index = oop_recorder()->find_index(obj); twisti@4318: RelocationHolder rspec = oop_Relocation::spec(oop_index); twisti@4318: mov_narrow_oop(dst, oop_index, rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int klass_index = oop_recorder()->find_index(k); twisti@4318: RelocationHolder rspec = metadata_Relocation::spec(klass_index); twisti@4318: mov_narrow_oop(dst, oopDesc::encode_klass(k), rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int klass_index = oop_recorder()->find_index(k); twisti@4318: RelocationHolder rspec = metadata_Relocation::spec(klass_index); twisti@4318: mov_narrow_oop(dst, oopDesc::encode_klass(k), rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int oop_index = oop_recorder()->find_index(obj); twisti@4318: RelocationHolder rspec = oop_Relocation::spec(oop_index); twisti@4318: Assembler::cmp_narrow_oop(dst, oop_index, rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { twisti@4318: assert (UseCompressedOops, "should only be used for compressed headers"); twisti@4318: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int oop_index = oop_recorder()->find_index(obj); twisti@4318: RelocationHolder rspec = oop_Relocation::spec(oop_index); twisti@4318: Assembler::cmp_narrow_oop(dst, oop_index, rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int klass_index = oop_recorder()->find_index(k); twisti@4318: RelocationHolder rspec = metadata_Relocation::spec(klass_index); twisti@4318: Assembler::cmp_narrow_oop(dst, oopDesc::encode_klass(k), rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { twisti@4318: assert (UseCompressedKlassPointers, "should only be used for compressed headers"); twisti@4318: assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4318: int klass_index = oop_recorder()->find_index(k); twisti@4318: RelocationHolder rspec = metadata_Relocation::spec(klass_index); twisti@4318: Assembler::cmp_narrow_oop(dst, oopDesc::encode_klass(k), rspec); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::reinit_heapbase() { twisti@4318: if (UseCompressedOops || UseCompressedKlassPointers) { twisti@4318: movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); twisti@4318: } twisti@4318: } twisti@4318: #endif // _LP64 twisti@4318: twisti@4318: twisti@4318: // C2 compiled method's prolog code. twisti@4318: void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) { twisti@4318: twisti@4318: // WARNING: Initial instruction MUST be 5 bytes or longer so that twisti@4318: // NativeJump::patch_verified_entry will be able to patch out the entry twisti@4318: // code safely. The push to verify stack depth is ok at 5 bytes, twisti@4318: // the frame allocation can be either 3 or 6 bytes. So if we don't do twisti@4318: // stack bang then we must use the 6 byte frame allocation even if twisti@4318: // we have no frame. :-( twisti@4318: twisti@4318: assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); twisti@4318: // Remove word for return addr twisti@4318: framesize -= wordSize; twisti@4318: twisti@4318: // Calls to C2R adapters often do not accept exceptional returns. twisti@4318: // We require that their callers must bang for them. But be careful, because twisti@4318: // some VM calls (such as call site linkage) can use several kilobytes of twisti@4318: // stack. But the stack safety zone should account for that. twisti@4318: // See bugs 4446381, 4468289, 4497237. twisti@4318: if (stack_bang) { twisti@4318: generate_stack_overflow_check(framesize); twisti@4318: twisti@4318: // We always push rbp, so that on return to interpreter rbp, will be twisti@4318: // restored correctly and we can correct the stack. twisti@4318: push(rbp); twisti@4318: // Remove word for ebp twisti@4318: framesize -= wordSize; twisti@4318: twisti@4318: // Create frame twisti@4318: if (framesize) { twisti@4318: subptr(rsp, framesize); twisti@4318: } twisti@4318: } else { twisti@4318: // Create frame (force generation of a 4 byte immediate value) twisti@4318: subptr_imm32(rsp, framesize); twisti@4318: twisti@4318: // Save RBP register now. twisti@4318: framesize -= wordSize; twisti@4318: movptr(Address(rsp, framesize), rbp); twisti@4318: } twisti@4318: twisti@4318: if (VerifyStackAtCalls) { // Majik cookie to verify stack depth twisti@4318: framesize -= wordSize; twisti@4318: movptr(Address(rsp, framesize), (int32_t)0xbadb100d); twisti@4318: } twisti@4318: twisti@4318: #ifndef _LP64 twisti@4318: // If method sets FPU control word do it now twisti@4318: if (fp_mode_24b) { twisti@4318: fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); twisti@4318: } twisti@4318: if (UseSSE >= 2 && VerifyFPU) { twisti@4318: verify_FPU(0, "FPU stack must be clean on entry"); twisti@4318: } twisti@4318: #endif twisti@4318: twisti@4318: #ifdef ASSERT twisti@4318: if (VerifyStackAtCalls) { twisti@4318: Label L; twisti@4318: push(rax); twisti@4318: mov(rax, rsp); twisti@4318: andptr(rax, StackAlignmentInBytes-1); twisti@4318: cmpptr(rax, StackAlignmentInBytes-wordSize); twisti@4318: pop(rax); twisti@4318: jcc(Assembler::equal, L); twisti@4318: STOP("Stack is not properly aligned!"); twisti@4318: bind(L); twisti@4318: } twisti@4318: #endif twisti@4318: twisti@4318: } twisti@4318: kvn@4410: void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) { kvn@4410: // cnt - number of qwords (8-byte words). kvn@4410: // base - start address, qword aligned. kvn@4410: assert(base==rdi, "base register must be edi for rep stos"); kvn@4410: assert(tmp==rax, "tmp register must be eax for rep stos"); kvn@4410: assert(cnt==rcx, "cnt register must be ecx for rep stos"); kvn@4410: kvn@4410: xorptr(tmp, tmp); kvn@4410: if (UseFastStosb) { kvn@4410: shlptr(cnt,3); // convert to number of bytes kvn@4410: rep_stosb(); kvn@4410: } else { kvn@4410: NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM kvn@4410: rep_stos(); kvn@4410: } kvn@4410: } twisti@4318: twisti@4318: // IndexOf for constant substrings with size >= 8 chars twisti@4318: // which don't need to be loaded through stack. twisti@4318: void MacroAssembler::string_indexofC8(Register str1, Register str2, twisti@4318: Register cnt1, Register cnt2, twisti@4318: int int_cnt2, Register result, twisti@4318: XMMRegister vec, Register tmp) { twisti@4318: ShortBranchVerifier sbv(this); twisti@4318: assert(UseSSE42Intrinsics, "SSE4.2 is required"); twisti@4318: twisti@4318: // This method uses pcmpestri inxtruction with bound registers twisti@4318: // inputs: twisti@4318: // xmm - substring twisti@4318: // rax - substring length (elements count) twisti@4318: // mem - scanned string twisti@4318: // rdx - string length (elements count) twisti@4318: // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) twisti@4318: // outputs: twisti@4318: // rcx - matched index in string twisti@4318: assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); twisti@4318: twisti@4318: Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, twisti@4318: RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, twisti@4318: MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; twisti@4318: twisti@4318: // Note, inline_string_indexOf() generates checks: twisti@4318: // if (substr.count > string.count) return -1; twisti@4318: // if (substr.count == 0) return 0; twisti@4318: assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); twisti@4318: twisti@4318: // Load substring. twisti@4318: movdqu(vec, Address(str2, 0)); twisti@4318: movl(cnt2, int_cnt2); twisti@4318: movptr(result, str1); // string addr twisti@4318: twisti@4318: if (int_cnt2 > 8) { twisti@4318: jmpb(SCAN_TO_SUBSTR); twisti@4318: twisti@4318: // Reload substr for rescan, this code twisti@4318: // is executed only for large substrings (> 8 chars) twisti@4318: bind(RELOAD_SUBSTR); twisti@4318: movdqu(vec, Address(str2, 0)); twisti@4318: negptr(cnt2); // Jumped here with negative cnt2, convert to positive twisti@4318: twisti@4318: bind(RELOAD_STR); twisti@4318: // We came here after the beginning of the substring was twisti@4318: // matched but the rest of it was not so we need to search twisti@4318: // again. Start from the next element after the previous match. twisti@4318: twisti@4318: // cnt2 is number of substring reminding elements and twisti@4318: // cnt1 is number of string reminding elements when cmp failed. twisti@4318: // Restored cnt1 = cnt1 - cnt2 + int_cnt2 twisti@4318: subl(cnt1, cnt2); twisti@4318: addl(cnt1, int_cnt2); twisti@4318: movl(cnt2, int_cnt2); // Now restore cnt2 twisti@4318: twisti@4318: decrementl(cnt1); // Shift to next element twisti@4318: cmpl(cnt1, cnt2); twisti@4318: jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring twisti@4318: twisti@4318: addptr(result, 2); twisti@4318: twisti@4318: } // (int_cnt2 > 8) twisti@4318: twisti@4318: // Scan string for start of substr in 16-byte vectors twisti@4318: bind(SCAN_TO_SUBSTR); twisti@4318: pcmpestri(vec, Address(result, 0), 0x0d); twisti@4318: jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 twisti@4318: subl(cnt1, 8); twisti@4318: jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string twisti@4318: cmpl(cnt1, cnt2); twisti@4318: jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring twisti@4318: addptr(result, 16); twisti@4318: jmpb(SCAN_TO_SUBSTR); twisti@4318: twisti@4318: // Found a potential substr twisti@4318: bind(FOUND_CANDIDATE); twisti@4318: // Matched whole vector if first element matched (tmp(rcx) == 0). twisti@4318: if (int_cnt2 == 8) { twisti@4318: jccb(Assembler::overflow, RET_FOUND); // OF == 1 twisti@4318: } else { // int_cnt2 > 8 twisti@4318: jccb(Assembler::overflow, FOUND_SUBSTR); twisti@4318: } twisti@4318: // After pcmpestri tmp(rcx) contains matched element index twisti@4318: // Compute start addr of substr twisti@4318: lea(result, Address(result, tmp, Address::times_2)); twisti@4318: twisti@4318: // Make sure string is still long enough twisti@4318: subl(cnt1, tmp); twisti@4318: cmpl(cnt1, cnt2); twisti@4318: if (int_cnt2 == 8) { twisti@4318: jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); twisti@4318: } else { // int_cnt2 > 8 twisti@4318: jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); twisti@4318: } twisti@4318: // Left less then substring. twisti@4318: twisti@4318: bind(RET_NOT_FOUND); twisti@4318: movl(result, -1); twisti@4318: jmpb(EXIT); twisti@4318: twisti@4318: if (int_cnt2 > 8) { twisti@4318: // This code is optimized for the case when whole substring twisti@4318: // is matched if its head is matched. twisti@4318: bind(MATCH_SUBSTR_HEAD); twisti@4318: pcmpestri(vec, Address(result, 0), 0x0d); twisti@4318: // Reload only string if does not match twisti@4318: jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 twisti@4318: twisti@4318: Label CONT_SCAN_SUBSTR; twisti@4318: // Compare the rest of substring (> 8 chars). twisti@4318: bind(FOUND_SUBSTR); twisti@4318: // First 8 chars are already matched. twisti@4318: negptr(cnt2); twisti@4318: addptr(cnt2, 8); twisti@4318: twisti@4318: bind(SCAN_SUBSTR); twisti@4318: subl(cnt1, 8); twisti@4318: cmpl(cnt2, -8); // Do not read beyond substring twisti@4318: jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); twisti@4318: // Back-up strings to avoid reading beyond substring: twisti@4318: // cnt1 = cnt1 - cnt2 + 8 twisti@4318: addl(cnt1, cnt2); // cnt2 is negative twisti@4318: addl(cnt1, 8); twisti@4318: movl(cnt2, 8); negptr(cnt2); twisti@4318: bind(CONT_SCAN_SUBSTR); twisti@4318: if (int_cnt2 < (int)G) { twisti@4318: movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); twisti@4318: pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); twisti@4318: } else { twisti@4318: // calculate index in register to avoid integer overflow (int_cnt2*2) twisti@4318: movl(tmp, int_cnt2); twisti@4318: addptr(tmp, cnt2); twisti@4318: movdqu(vec, Address(str2, tmp, Address::times_2, 0)); twisti@4318: pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); twisti@4318: } twisti@4318: // Need to reload strings pointers if not matched whole vector twisti@4318: jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 twisti@4318: addptr(cnt2, 8); twisti@4318: jcc(Assembler::negative, SCAN_SUBSTR); twisti@4318: // Fall through if found full substring twisti@4318: twisti@4318: } // (int_cnt2 > 8) twisti@4318: twisti@4318: bind(RET_FOUND); twisti@4318: // Found result if we matched full small substring. twisti@4318: // Compute substr offset twisti@4318: subptr(result, str1); twisti@4318: shrl(result, 1); // index twisti@4318: bind(EXIT); twisti@4318: twisti@4318: } // string_indexofC8 twisti@4318: twisti@4318: // Small strings are loaded through stack if they cross page boundary. twisti@4318: void MacroAssembler::string_indexof(Register str1, Register str2, twisti@4318: Register cnt1, Register cnt2, twisti@4318: int int_cnt2, Register result, twisti@4318: XMMRegister vec, Register tmp) { twisti@4318: ShortBranchVerifier sbv(this); twisti@4318: assert(UseSSE42Intrinsics, "SSE4.2 is required"); twisti@4318: // twisti@4318: // int_cnt2 is length of small (< 8 chars) constant substring twisti@4318: // or (-1) for non constant substring in which case its length twisti@4318: // is in cnt2 register. twisti@4318: // twisti@4318: // Note, inline_string_indexOf() generates checks: twisti@4318: // if (substr.count > string.count) return -1; twisti@4318: // if (substr.count == 0) return 0; twisti@4318: // twisti@4318: assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); twisti@4318: twisti@4318: // This method uses pcmpestri inxtruction with bound registers twisti@4318: // inputs: twisti@4318: // xmm - substring twisti@4318: // rax - substring length (elements count) twisti@4318: // mem - scanned string twisti@4318: // rdx - string length (elements count) twisti@4318: // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) twisti@4318: // outputs: twisti@4318: // rcx - matched index in string twisti@4318: assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); twisti@4318: twisti@4318: Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, twisti@4318: RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, twisti@4318: FOUND_CANDIDATE; twisti@4318: twisti@4318: { //======================================================== twisti@4318: // We don't know where these strings are located twisti@4318: // and we can't read beyond them. Load them through stack. twisti@4318: Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; twisti@4318: twisti@4318: movptr(tmp, rsp); // save old SP twisti@4318: twisti@4318: if (int_cnt2 > 0) { // small (< 8 chars) constant substring twisti@4318: if (int_cnt2 == 1) { // One char twisti@4318: load_unsigned_short(result, Address(str2, 0)); twisti@4318: movdl(vec, result); // move 32 bits twisti@4318: } else if (int_cnt2 == 2) { // Two chars twisti@4318: movdl(vec, Address(str2, 0)); // move 32 bits twisti@4318: } else if (int_cnt2 == 4) { // Four chars twisti@4318: movq(vec, Address(str2, 0)); // move 64 bits twisti@4318: } else { // cnt2 = { 3, 5, 6, 7 } twisti@4318: // Array header size is 12 bytes in 32-bit VM twisti@4318: // + 6 bytes for 3 chars == 18 bytes, twisti@4318: // enough space to load vec and shift. twisti@4318: assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); twisti@4318: movdqu(vec, Address(str2, (int_cnt2*2)-16)); twisti@4318: psrldq(vec, 16-(int_cnt2*2)); twisti@4318: } twisti@4318: } else { // not constant substring twisti@4318: cmpl(cnt2, 8); twisti@4318: jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough twisti@4318: twisti@4318: // We can read beyond string if srt+16 does not cross page boundary twisti@4318: // since heaps are aligned and mapped by pages. twisti@4318: assert(os::vm_page_size() < (int)G, "default page should be small"); twisti@4318: movl(result, str2); // We need only low 32 bits twisti@4318: andl(result, (os::vm_page_size()-1)); twisti@4318: cmpl(result, (os::vm_page_size()-16)); twisti@4318: jccb(Assembler::belowEqual, CHECK_STR); twisti@4318: twisti@4318: // Move small strings to stack to allow load 16 bytes into vec. twisti@4318: subptr(rsp, 16); twisti@4318: int stk_offset = wordSize-2; twisti@4318: push(cnt2); twisti@4318: twisti@4318: bind(COPY_SUBSTR); twisti@4318: load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); twisti@4318: movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); twisti@4318: decrement(cnt2); twisti@4318: jccb(Assembler::notZero, COPY_SUBSTR); twisti@4318: twisti@4318: pop(cnt2); twisti@4318: movptr(str2, rsp); // New substring address twisti@4318: } // non constant twisti@4318: twisti@4318: bind(CHECK_STR); twisti@4318: cmpl(cnt1, 8); twisti@4318: jccb(Assembler::aboveEqual, BIG_STRINGS); twisti@4318: twisti@4318: // Check cross page boundary. twisti@4318: movl(result, str1); // We need only low 32 bits twisti@4318: andl(result, (os::vm_page_size()-1)); twisti@4318: cmpl(result, (os::vm_page_size()-16)); twisti@4318: jccb(Assembler::belowEqual, BIG_STRINGS); twisti@4318: twisti@4318: subptr(rsp, 16); twisti@4318: int stk_offset = -2; twisti@4318: if (int_cnt2 < 0) { // not constant twisti@4318: push(cnt2); twisti@4318: stk_offset += wordSize; twisti@4318: } twisti@4318: movl(cnt2, cnt1); twisti@4318: twisti@4318: bind(COPY_STR); twisti@4318: load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); twisti@4318: movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); twisti@4318: decrement(cnt2); twisti@4318: jccb(Assembler::notZero, COPY_STR); twisti@4318: twisti@4318: if (int_cnt2 < 0) { // not constant twisti@4318: pop(cnt2); twisti@4318: } twisti@4318: movptr(str1, rsp); // New string address twisti@4318: twisti@4318: bind(BIG_STRINGS); twisti@4318: // Load substring. twisti@4318: if (int_cnt2 < 0) { // -1 twisti@4318: movdqu(vec, Address(str2, 0)); twisti@4318: push(cnt2); // substr count twisti@4318: push(str2); // substr addr twisti@4318: push(str1); // string addr twisti@4318: } else { twisti@4318: // Small (< 8 chars) constant substrings are loaded already. twisti@4318: movl(cnt2, int_cnt2); twisti@4318: } twisti@4318: push(tmp); // original SP twisti@4318: twisti@4318: } // Finished loading twisti@4318: twisti@4318: //======================================================== twisti@4318: // Start search twisti@4318: // twisti@4318: twisti@4318: movptr(result, str1); // string addr twisti@4318: twisti@4318: if (int_cnt2 < 0) { // Only for non constant substring twisti@4318: jmpb(SCAN_TO_SUBSTR); twisti@4318: twisti@4318: // SP saved at sp+0 twisti@4318: // String saved at sp+1*wordSize twisti@4318: // Substr saved at sp+2*wordSize twisti@4318: // Substr count saved at sp+3*wordSize twisti@4318: twisti@4318: // Reload substr for rescan, this code twisti@4318: // is executed only for large substrings (> 8 chars) twisti@4318: bind(RELOAD_SUBSTR); twisti@4318: movptr(str2, Address(rsp, 2*wordSize)); twisti@4318: movl(cnt2, Address(rsp, 3*wordSize)); twisti@4318: movdqu(vec, Address(str2, 0)); twisti@4318: // We came here after the beginning of the substring was twisti@4318: // matched but the rest of it was not so we need to search twisti@4318: // again. Start from the next element after the previous match. twisti@4318: subptr(str1, result); // Restore counter twisti@4318: shrl(str1, 1); twisti@4318: addl(cnt1, str1); twisti@4318: decrementl(cnt1); // Shift to next element twisti@4318: cmpl(cnt1, cnt2); twisti@4318: jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring twisti@4318: twisti@4318: addptr(result, 2); twisti@4318: } // non constant twisti@4318: twisti@4318: // Scan string for start of substr in 16-byte vectors twisti@4318: bind(SCAN_TO_SUBSTR); twisti@4318: assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); twisti@4318: pcmpestri(vec, Address(result, 0), 0x0d); twisti@4318: jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 twisti@4318: subl(cnt1, 8); twisti@4318: jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string twisti@4318: cmpl(cnt1, cnt2); twisti@4318: jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring twisti@4318: addptr(result, 16); twisti@4318: twisti@4318: bind(ADJUST_STR); twisti@4318: cmpl(cnt1, 8); // Do not read beyond string twisti@4318: jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); twisti@4318: // Back-up string to avoid reading beyond string. twisti@4318: lea(result, Address(result, cnt1, Address::times_2, -16)); twisti@4318: movl(cnt1, 8); twisti@4318: jmpb(SCAN_TO_SUBSTR); twisti@4318: twisti@4318: // Found a potential substr twisti@4318: bind(FOUND_CANDIDATE); twisti@4318: // After pcmpestri tmp(rcx) contains matched element index twisti@4318: twisti@4318: // Make sure string is still long enough twisti@4318: subl(cnt1, tmp); twisti@4318: cmpl(cnt1, cnt2); twisti@4318: jccb(Assembler::greaterEqual, FOUND_SUBSTR); twisti@4318: // Left less then substring. twisti@4318: twisti@4318: bind(RET_NOT_FOUND); twisti@4318: movl(result, -1); twisti@4318: jmpb(CLEANUP); twisti@4318: twisti@4318: bind(FOUND_SUBSTR); twisti@4318: // Compute start addr of substr twisti@4318: lea(result, Address(result, tmp, Address::times_2)); twisti@4318: twisti@4318: if (int_cnt2 > 0) { // Constant substring twisti@4318: // Repeat search for small substring (< 8 chars) twisti@4318: // from new point without reloading substring. twisti@4318: // Have to check that we don't read beyond string. twisti@4318: cmpl(tmp, 8-int_cnt2); twisti@4318: jccb(Assembler::greater, ADJUST_STR); twisti@4318: // Fall through if matched whole substring. twisti@4318: } else { // non constant twisti@4318: assert(int_cnt2 == -1, "should be != 0"); twisti@4318: twisti@4318: addl(tmp, cnt2); twisti@4318: // Found result if we matched whole substring. twisti@4318: cmpl(tmp, 8); twisti@4318: jccb(Assembler::lessEqual, RET_FOUND); twisti@4318: twisti@4318: // Repeat search for small substring (<= 8 chars) twisti@4318: // from new point 'str1' without reloading substring. twisti@4318: cmpl(cnt2, 8); twisti@4318: // Have to check that we don't read beyond string. twisti@4318: jccb(Assembler::lessEqual, ADJUST_STR); twisti@4318: twisti@4318: Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; twisti@4318: // Compare the rest of substring (> 8 chars). twisti@4318: movptr(str1, result); twisti@4318: twisti@4318: cmpl(tmp, cnt2); twisti@4318: // First 8 chars are already matched. twisti@4318: jccb(Assembler::equal, CHECK_NEXT); twisti@4318: twisti@4318: bind(SCAN_SUBSTR); twisti@4318: pcmpestri(vec, Address(str1, 0), 0x0d); twisti@4318: // Need to reload strings pointers if not matched whole vector twisti@4318: jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 twisti@4318: twisti@4318: bind(CHECK_NEXT); twisti@4318: subl(cnt2, 8); twisti@4318: jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring twisti@4318: addptr(str1, 16); twisti@4318: addptr(str2, 16); twisti@4318: subl(cnt1, 8); twisti@4318: cmpl(cnt2, 8); // Do not read beyond substring twisti@4318: jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); twisti@4318: // Back-up strings to avoid reading beyond substring. twisti@4318: lea(str2, Address(str2, cnt2, Address::times_2, -16)); twisti@4318: lea(str1, Address(str1, cnt2, Address::times_2, -16)); twisti@4318: subl(cnt1, cnt2); twisti@4318: movl(cnt2, 8); twisti@4318: addl(cnt1, 8); twisti@4318: bind(CONT_SCAN_SUBSTR); twisti@4318: movdqu(vec, Address(str2, 0)); twisti@4318: jmpb(SCAN_SUBSTR); twisti@4318: twisti@4318: bind(RET_FOUND_LONG); twisti@4318: movptr(str1, Address(rsp, wordSize)); twisti@4318: } // non constant twisti@4318: twisti@4318: bind(RET_FOUND); twisti@4318: // Compute substr offset twisti@4318: subptr(result, str1); twisti@4318: shrl(result, 1); // index twisti@4318: twisti@4318: bind(CLEANUP); twisti@4318: pop(rsp); // restore SP twisti@4318: twisti@4318: } // string_indexof twisti@4318: twisti@4318: // Compare strings. twisti@4318: void MacroAssembler::string_compare(Register str1, Register str2, twisti@4318: Register cnt1, Register cnt2, Register result, twisti@4318: XMMRegister vec1) { twisti@4318: ShortBranchVerifier sbv(this); twisti@4318: Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; twisti@4318: twisti@4318: // Compute the minimum of the string lengths and the twisti@4318: // difference of the string lengths (stack). twisti@4318: // Do the conditional move stuff twisti@4318: movl(result, cnt1); twisti@4318: subl(cnt1, cnt2); twisti@4318: push(cnt1); twisti@4318: cmov32(Assembler::lessEqual, cnt2, result); twisti@4318: twisti@4318: // Is the minimum length zero? twisti@4318: testl(cnt2, cnt2); twisti@4318: jcc(Assembler::zero, LENGTH_DIFF_LABEL); twisti@4318: kvn@4413: // Compare first characters twisti@4318: load_unsigned_short(result, Address(str1, 0)); twisti@4318: load_unsigned_short(cnt1, Address(str2, 0)); twisti@4318: subl(result, cnt1); twisti@4318: jcc(Assembler::notZero, POP_LABEL); kvn@4413: cmpl(cnt2, 1); kvn@4413: jcc(Assembler::equal, LENGTH_DIFF_LABEL); kvn@4413: kvn@4413: // Check if the strings start at the same location. kvn@4413: cmpptr(str1, str2); kvn@4413: jcc(Assembler::equal, LENGTH_DIFF_LABEL); twisti@4318: twisti@4318: Address::ScaleFactor scale = Address::times_2; twisti@4318: int stride = 8; twisti@4318: kvn@4583: if (UseAVX >= 2 && UseSSE42Intrinsics) { kvn@4413: Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; kvn@4413: Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; kvn@4413: Label COMPARE_TAIL_LONG; kvn@4413: int pcmpmask = 0x19; kvn@4413: kvn@4413: // Setup to compare 16-chars (32-bytes) vectors, kvn@4413: // start from first character again because it has aligned address. kvn@4413: int stride2 = 16; kvn@4413: int adr_stride = stride << scale; kvn@4413: int adr_stride2 = stride2 << scale; kvn@4413: kvn@4413: assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); kvn@4413: // rax and rdx are used by pcmpestri as elements counters kvn@4413: movl(result, cnt2); kvn@4413: andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count kvn@4413: jcc(Assembler::zero, COMPARE_TAIL_LONG); kvn@4413: kvn@4413: // fast path : compare first 2 8-char vectors. kvn@4413: bind(COMPARE_16_CHARS); kvn@4413: movdqu(vec1, Address(str1, 0)); kvn@4413: pcmpestri(vec1, Address(str2, 0), pcmpmask); kvn@4413: jccb(Assembler::below, COMPARE_INDEX_CHAR); kvn@4413: kvn@4413: movdqu(vec1, Address(str1, adr_stride)); kvn@4413: pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); kvn@4413: jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); kvn@4413: addl(cnt1, stride); kvn@4413: kvn@4413: // Compare the characters at index in cnt1 kvn@4413: bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character kvn@4413: load_unsigned_short(result, Address(str1, cnt1, scale)); kvn@4413: load_unsigned_short(cnt2, Address(str2, cnt1, scale)); kvn@4413: subl(result, cnt2); kvn@4413: jmp(POP_LABEL); kvn@4413: kvn@4413: // Setup the registers to start vector comparison loop kvn@4413: bind(COMPARE_WIDE_VECTORS); kvn@4413: lea(str1, Address(str1, result, scale)); kvn@4413: lea(str2, Address(str2, result, scale)); kvn@4413: subl(result, stride2); kvn@4413: subl(cnt2, stride2); kvn@4413: jccb(Assembler::zero, COMPARE_WIDE_TAIL); kvn@4413: negptr(result); kvn@4413: kvn@4413: // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) kvn@4413: bind(COMPARE_WIDE_VECTORS_LOOP); kvn@4413: vmovdqu(vec1, Address(str1, result, scale)); kvn@4413: vpxor(vec1, Address(str2, result, scale)); kvn@4413: vptest(vec1, vec1); kvn@4413: jccb(Assembler::notZero, VECTOR_NOT_EQUAL); kvn@4413: addptr(result, stride2); kvn@4413: subl(cnt2, stride2); kvn@4413: jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); kvn@4413: kvn@4413: // compare wide vectors tail kvn@4413: bind(COMPARE_WIDE_TAIL); kvn@4413: testptr(result, result); kvn@4413: jccb(Assembler::zero, LENGTH_DIFF_LABEL); kvn@4413: kvn@4413: movl(result, stride2); kvn@4413: movl(cnt2, result); kvn@4413: negptr(result); kvn@4413: jmpb(COMPARE_WIDE_VECTORS_LOOP); kvn@4413: kvn@4413: // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. kvn@4413: bind(VECTOR_NOT_EQUAL); kvn@4413: lea(str1, Address(str1, result, scale)); kvn@4413: lea(str2, Address(str2, result, scale)); kvn@4413: jmp(COMPARE_16_CHARS); kvn@4413: kvn@4413: // Compare tail chars, length between 1 to 15 chars kvn@4413: bind(COMPARE_TAIL_LONG); kvn@4413: movl(cnt2, result); kvn@4413: cmpl(cnt2, stride); kvn@4413: jccb(Assembler::less, COMPARE_SMALL_STR); kvn@4413: kvn@4413: movdqu(vec1, Address(str1, 0)); kvn@4413: pcmpestri(vec1, Address(str2, 0), pcmpmask); kvn@4413: jcc(Assembler::below, COMPARE_INDEX_CHAR); kvn@4413: subptr(cnt2, stride); kvn@4413: jccb(Assembler::zero, LENGTH_DIFF_LABEL); kvn@4413: lea(str1, Address(str1, result, scale)); kvn@4413: lea(str2, Address(str2, result, scale)); kvn@4413: negptr(cnt2); kvn@4413: jmpb(WHILE_HEAD_LABEL); kvn@4413: kvn@4413: bind(COMPARE_SMALL_STR); kvn@4413: } else if (UseSSE42Intrinsics) { twisti@4318: Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; twisti@4318: int pcmpmask = 0x19; kvn@4413: // Setup to compare 8-char (16-byte) vectors, kvn@4413: // start from first character again because it has aligned address. twisti@4318: movl(result, cnt2); twisti@4318: andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count twisti@4318: jccb(Assembler::zero, COMPARE_TAIL); twisti@4318: twisti@4318: lea(str1, Address(str1, result, scale)); twisti@4318: lea(str2, Address(str2, result, scale)); twisti@4318: negptr(result); twisti@4318: twisti@4318: // pcmpestri twisti@4318: // inputs: twisti@4318: // vec1- substring twisti@4318: // rax - negative string length (elements count) twisti@4318: // mem - scaned string twisti@4318: // rdx - string length (elements count) twisti@4318: // pcmpmask - cmp mode: 11000 (string compare with negated result) twisti@4318: // + 00 (unsigned bytes) or + 01 (unsigned shorts) twisti@4318: // outputs: twisti@4318: // rcx - first mismatched element index twisti@4318: assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); twisti@4318: twisti@4318: bind(COMPARE_WIDE_VECTORS); twisti@4318: movdqu(vec1, Address(str1, result, scale)); twisti@4318: pcmpestri(vec1, Address(str2, result, scale), pcmpmask); twisti@4318: // After pcmpestri cnt1(rcx) contains mismatched element index twisti@4318: twisti@4318: jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 twisti@4318: addptr(result, stride); twisti@4318: subptr(cnt2, stride); twisti@4318: jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); twisti@4318: twisti@4318: // compare wide vectors tail kvn@4413: testptr(result, result); twisti@4318: jccb(Assembler::zero, LENGTH_DIFF_LABEL); twisti@4318: twisti@4318: movl(cnt2, stride); twisti@4318: movl(result, stride); twisti@4318: negptr(result); twisti@4318: movdqu(vec1, Address(str1, result, scale)); twisti@4318: pcmpestri(vec1, Address(str2, result, scale), pcmpmask); twisti@4318: jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); twisti@4318: twisti@4318: // Mismatched characters in the vectors twisti@4318: bind(VECTOR_NOT_EQUAL); kvn@4413: addptr(cnt1, result); kvn@4413: load_unsigned_short(result, Address(str1, cnt1, scale)); kvn@4413: load_unsigned_short(cnt2, Address(str2, cnt1, scale)); kvn@4413: subl(result, cnt2); twisti@4318: jmpb(POP_LABEL); twisti@4318: twisti@4318: bind(COMPARE_TAIL); // limit is zero twisti@4318: movl(cnt2, result); twisti@4318: // Fallthru to tail compare twisti@4318: } twisti@4318: // Shift str2 and str1 to the end of the arrays, negate min kvn@4413: lea(str1, Address(str1, cnt2, scale)); kvn@4413: lea(str2, Address(str2, cnt2, scale)); kvn@4413: decrementl(cnt2); // first character was compared already twisti@4318: negptr(cnt2); twisti@4318: twisti@4318: // Compare the rest of the elements twisti@4318: bind(WHILE_HEAD_LABEL); twisti@4318: load_unsigned_short(result, Address(str1, cnt2, scale, 0)); twisti@4318: load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); twisti@4318: subl(result, cnt1); twisti@4318: jccb(Assembler::notZero, POP_LABEL); twisti@4318: increment(cnt2); twisti@4318: jccb(Assembler::notZero, WHILE_HEAD_LABEL); twisti@4318: twisti@4318: // Strings are equal up to min length. Return the length difference. twisti@4318: bind(LENGTH_DIFF_LABEL); twisti@4318: pop(result); twisti@4318: jmpb(DONE_LABEL); twisti@4318: twisti@4318: // Discard the stored length difference twisti@4318: bind(POP_LABEL); twisti@4318: pop(cnt1); twisti@4318: twisti@4318: // That's it twisti@4318: bind(DONE_LABEL); twisti@4318: } twisti@4318: twisti@4318: // Compare char[] arrays aligned to 4 bytes or substrings. twisti@4318: void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, twisti@4318: Register limit, Register result, Register chr, twisti@4318: XMMRegister vec1, XMMRegister vec2) { twisti@4318: ShortBranchVerifier sbv(this); twisti@4318: Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; twisti@4318: twisti@4318: int length_offset = arrayOopDesc::length_offset_in_bytes(); twisti@4318: int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); twisti@4318: twisti@4318: // Check the input args twisti@4318: cmpptr(ary1, ary2); twisti@4318: jcc(Assembler::equal, TRUE_LABEL); twisti@4318: twisti@4318: if (is_array_equ) { twisti@4318: // Need additional checks for arrays_equals. twisti@4318: testptr(ary1, ary1); twisti@4318: jcc(Assembler::zero, FALSE_LABEL); twisti@4318: testptr(ary2, ary2); twisti@4318: jcc(Assembler::zero, FALSE_LABEL); twisti@4318: twisti@4318: // Check the lengths twisti@4318: movl(limit, Address(ary1, length_offset)); twisti@4318: cmpl(limit, Address(ary2, length_offset)); twisti@4318: jcc(Assembler::notEqual, FALSE_LABEL); twisti@4318: } twisti@4318: twisti@4318: // count == 0 twisti@4318: testl(limit, limit); twisti@4318: jcc(Assembler::zero, TRUE_LABEL); twisti@4318: twisti@4318: if (is_array_equ) { twisti@4318: // Load array address twisti@4318: lea(ary1, Address(ary1, base_offset)); twisti@4318: lea(ary2, Address(ary2, base_offset)); twisti@4318: } twisti@4318: twisti@4318: shll(limit, 1); // byte count != 0 twisti@4318: movl(result, limit); // copy twisti@4318: kvn@4413: if (UseAVX >= 2) { kvn@4413: // With AVX2, use 32-byte vector compare kvn@4413: Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; kvn@4413: kvn@4413: // Compare 32-byte vectors kvn@4413: andl(result, 0x0000001e); // tail count (in bytes) kvn@4413: andl(limit, 0xffffffe0); // vector count (in bytes) kvn@4413: jccb(Assembler::zero, COMPARE_TAIL); kvn@4413: kvn@4413: lea(ary1, Address(ary1, limit, Address::times_1)); kvn@4413: lea(ary2, Address(ary2, limit, Address::times_1)); kvn@4413: negptr(limit); kvn@4413: kvn@4413: bind(COMPARE_WIDE_VECTORS); kvn@4413: vmovdqu(vec1, Address(ary1, limit, Address::times_1)); kvn@4413: vmovdqu(vec2, Address(ary2, limit, Address::times_1)); kvn@4413: vpxor(vec1, vec2); kvn@4413: kvn@4413: vptest(vec1, vec1); kvn@4413: jccb(Assembler::notZero, FALSE_LABEL); kvn@4413: addptr(limit, 32); kvn@4413: jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); kvn@4413: kvn@4413: testl(result, result); kvn@4413: jccb(Assembler::zero, TRUE_LABEL); kvn@4413: kvn@4413: vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); kvn@4413: vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); kvn@4413: vpxor(vec1, vec2); kvn@4413: kvn@4413: vptest(vec1, vec1); kvn@4413: jccb(Assembler::notZero, FALSE_LABEL); kvn@4413: jmpb(TRUE_LABEL); kvn@4413: kvn@4413: bind(COMPARE_TAIL); // limit is zero kvn@4413: movl(limit, result); kvn@4413: // Fallthru to tail compare kvn@4413: } else if (UseSSE42Intrinsics) { twisti@4318: // With SSE4.2, use double quad vector compare twisti@4318: Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; twisti@4318: twisti@4318: // Compare 16-byte vectors twisti@4318: andl(result, 0x0000000e); // tail count (in bytes) twisti@4318: andl(limit, 0xfffffff0); // vector count (in bytes) twisti@4318: jccb(Assembler::zero, COMPARE_TAIL); twisti@4318: twisti@4318: lea(ary1, Address(ary1, limit, Address::times_1)); twisti@4318: lea(ary2, Address(ary2, limit, Address::times_1)); twisti@4318: negptr(limit); twisti@4318: twisti@4318: bind(COMPARE_WIDE_VECTORS); twisti@4318: movdqu(vec1, Address(ary1, limit, Address::times_1)); twisti@4318: movdqu(vec2, Address(ary2, limit, Address::times_1)); twisti@4318: pxor(vec1, vec2); twisti@4318: twisti@4318: ptest(vec1, vec1); twisti@4318: jccb(Assembler::notZero, FALSE_LABEL); twisti@4318: addptr(limit, 16); twisti@4318: jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); twisti@4318: twisti@4318: testl(result, result); twisti@4318: jccb(Assembler::zero, TRUE_LABEL); twisti@4318: twisti@4318: movdqu(vec1, Address(ary1, result, Address::times_1, -16)); twisti@4318: movdqu(vec2, Address(ary2, result, Address::times_1, -16)); twisti@4318: pxor(vec1, vec2); twisti@4318: twisti@4318: ptest(vec1, vec1); twisti@4318: jccb(Assembler::notZero, FALSE_LABEL); twisti@4318: jmpb(TRUE_LABEL); twisti@4318: twisti@4318: bind(COMPARE_TAIL); // limit is zero twisti@4318: movl(limit, result); twisti@4318: // Fallthru to tail compare twisti@4318: } twisti@4318: twisti@4318: // Compare 4-byte vectors twisti@4318: andl(limit, 0xfffffffc); // vector count (in bytes) twisti@4318: jccb(Assembler::zero, COMPARE_CHAR); twisti@4318: twisti@4318: lea(ary1, Address(ary1, limit, Address::times_1)); twisti@4318: lea(ary2, Address(ary2, limit, Address::times_1)); twisti@4318: negptr(limit); twisti@4318: twisti@4318: bind(COMPARE_VECTORS); twisti@4318: movl(chr, Address(ary1, limit, Address::times_1)); twisti@4318: cmpl(chr, Address(ary2, limit, Address::times_1)); twisti@4318: jccb(Assembler::notEqual, FALSE_LABEL); twisti@4318: addptr(limit, 4); twisti@4318: jcc(Assembler::notZero, COMPARE_VECTORS); twisti@4318: twisti@4318: // Compare trailing char (final 2 bytes), if any twisti@4318: bind(COMPARE_CHAR); twisti@4318: testl(result, 0x2); // tail char twisti@4318: jccb(Assembler::zero, TRUE_LABEL); twisti@4318: load_unsigned_short(chr, Address(ary1, 0)); twisti@4318: load_unsigned_short(limit, Address(ary2, 0)); twisti@4318: cmpl(chr, limit); twisti@4318: jccb(Assembler::notEqual, FALSE_LABEL); twisti@4318: twisti@4318: bind(TRUE_LABEL); twisti@4318: movl(result, 1); // return true twisti@4318: jmpb(DONE); twisti@4318: twisti@4318: bind(FALSE_LABEL); twisti@4318: xorl(result, result); // return false twisti@4318: twisti@4318: // That's it twisti@4318: bind(DONE); twisti@4318: } twisti@4318: twisti@4318: void MacroAssembler::generate_fill(BasicType t, bool aligned, twisti@4318: Register to, Register value, Register count, twisti@4318: Register rtmp, XMMRegister xtmp) { twisti@4318: ShortBranchVerifier sbv(this); twisti@4318: assert_different_registers(to, value, count, rtmp); twisti@4318: Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; twisti@4318: Label L_fill_2_bytes, L_fill_4_bytes; twisti@4318: twisti@4318: int shift = -1; twisti@4318: switch (t) { twisti@4318: case T_BYTE: twisti@4318: shift = 2; twisti@4318: break; twisti@4318: case T_SHORT: twisti@4318: shift = 1; twisti@4318: break; twisti@4318: case T_INT: twisti@4318: shift = 0; twisti@4318: break; twisti@4318: default: ShouldNotReachHere(); twisti@4318: } twisti@4318: twisti@4318: if (t == T_BYTE) { twisti@4318: andl(value, 0xff); twisti@4318: movl(rtmp, value); twisti@4318: shll(rtmp, 8); twisti@4318: orl(value, rtmp); twisti@4318: } twisti@4318: if (t == T_SHORT) { twisti@4318: andl(value, 0xffff); twisti@4318: } twisti@4318: if (t == T_BYTE || t == T_SHORT) { twisti@4318: movl(rtmp, value); twisti@4318: shll(rtmp, 16); twisti@4318: orl(value, rtmp); twisti@4318: } twisti@4318: twisti@4318: cmpl(count, 2<= 2, "supported cpu only" ); twisti@4318: Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; twisti@4318: movdl(xtmp, value); kvn@4411: if (UseAVX >= 2 && UseUnalignedLoadStores) { kvn@4411: // Fill 64-byte chunks kvn@4411: Label L_fill_64_bytes_loop, L_check_fill_32_bytes; kvn@4411: vpbroadcastd(xtmp, xtmp); kvn@4411: kvn@4411: subl(count, 16 << shift); kvn@4411: jcc(Assembler::less, L_check_fill_32_bytes); kvn@4411: align(16); kvn@4411: kvn@4411: BIND(L_fill_64_bytes_loop); kvn@4411: vmovdqu(Address(to, 0), xtmp); kvn@4411: vmovdqu(Address(to, 32), xtmp); kvn@4411: addptr(to, 64); kvn@4411: subl(count, 16 << shift); kvn@4411: jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); kvn@4411: kvn@4411: BIND(L_check_fill_32_bytes); kvn@4411: addl(count, 8 << shift); kvn@4411: jccb(Assembler::less, L_check_fill_8_bytes); kvn@4411: vmovdqu(Address(to, 0), xtmp); kvn@4411: addptr(to, 32); kvn@4411: subl(count, 8 << shift); twisti@4318: } else { kvn@4411: // Fill 32-byte chunks kvn@4411: pshufd(xtmp, xtmp, 0); kvn@4411: kvn@4411: subl(count, 8 << shift); kvn@4411: jcc(Assembler::less, L_check_fill_8_bytes); kvn@4411: align(16); kvn@4411: kvn@4411: BIND(L_fill_32_bytes_loop); kvn@4411: kvn@4411: if (UseUnalignedLoadStores) { kvn@4411: movdqu(Address(to, 0), xtmp); kvn@4411: movdqu(Address(to, 16), xtmp); kvn@4411: } else { kvn@4411: movq(Address(to, 0), xtmp); kvn@4411: movq(Address(to, 8), xtmp); kvn@4411: movq(Address(to, 16), xtmp); kvn@4411: movq(Address(to, 24), xtmp); kvn@4411: } kvn@4411: kvn@4411: addptr(to, 32); kvn@4411: subl(count, 8 << shift); kvn@4411: jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); twisti@4318: } twisti@4318: BIND(L_check_fill_8_bytes); twisti@4318: addl(count, 8 << shift); twisti@4318: jccb(Assembler::zero, L_exit); twisti@4318: jmpb(L_fill_8_bytes); twisti@4318: twisti@4318: // twisti@4318: // length is too short, just fill qwords twisti@4318: // twisti@4318: BIND(L_fill_8_bytes_loop); twisti@4318: movq(Address(to, 0), xtmp); twisti@4318: addptr(to, 8); twisti@4318: BIND(L_fill_8_bytes); twisti@4318: subl(count, 1 << (shift + 1)); twisti@4318: jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); twisti@4318: } twisti@4318: } twisti@4318: // fill trailing 4 bytes twisti@4318: BIND(L_fill_4_bytes); twisti@4318: testl(count, 1<= 2) { kvn@4479: Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; kvn@4479: Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; kvn@4479: kvn@4479: if (UseAVX >= 2) { kvn@4479: Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; kvn@4479: movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector kvn@4479: movdl(tmp1Reg, tmp5); kvn@4479: vpbroadcastd(tmp1Reg, tmp1Reg); kvn@4479: jmpb(L_chars_32_check); kvn@4479: kvn@4479: bind(L_copy_32_chars); kvn@4479: vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); kvn@4479: vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); kvn@4479: vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true); kvn@4479: vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector kvn@4479: jccb(Assembler::notZero, L_copy_32_chars_exit); kvn@4479: vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true); kvn@4479: vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true); kvn@4479: vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); kvn@4479: kvn@4479: bind(L_chars_32_check); kvn@4479: addptr(len, 32); kvn@4479: jccb(Assembler::lessEqual, L_copy_32_chars); kvn@4479: kvn@4479: bind(L_copy_32_chars_exit); kvn@4479: subptr(len, 16); kvn@4479: jccb(Assembler::greater, L_copy_16_chars_exit); kvn@4479: kvn@4479: } else if (UseSSE42Intrinsics) { kvn@4479: movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector kvn@4479: movdl(tmp1Reg, tmp5); kvn@4479: pshufd(tmp1Reg, tmp1Reg, 0); kvn@4479: jmpb(L_chars_16_check); kvn@4479: } kvn@4479: kvn@4479: bind(L_copy_16_chars); kvn@4479: if (UseAVX >= 2) { kvn@4479: vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); kvn@4479: vptest(tmp2Reg, tmp1Reg); kvn@4479: jccb(Assembler::notZero, L_copy_16_chars_exit); kvn@4479: vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true); kvn@4479: vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true); kvn@4479: } else { kvn@4479: if (UseAVX > 0) { kvn@4479: movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); kvn@4479: movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); kvn@4479: vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false); kvn@4479: } else { kvn@4479: movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); kvn@4479: por(tmp2Reg, tmp3Reg); kvn@4479: movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); kvn@4479: por(tmp2Reg, tmp4Reg); kvn@4479: } kvn@4479: ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector kvn@4479: jccb(Assembler::notZero, L_copy_16_chars_exit); kvn@4479: packuswb(tmp3Reg, tmp4Reg); kvn@4479: } kvn@4479: movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); kvn@4479: kvn@4479: bind(L_chars_16_check); kvn@4479: addptr(len, 16); kvn@4479: jccb(Assembler::lessEqual, L_copy_16_chars); kvn@4479: kvn@4479: bind(L_copy_16_chars_exit); kvn@4479: subptr(len, 8); kvn@4479: jccb(Assembler::greater, L_copy_8_chars_exit); kvn@4479: kvn@4479: bind(L_copy_8_chars); kvn@4479: movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); kvn@4479: ptest(tmp3Reg, tmp1Reg); kvn@4479: jccb(Assembler::notZero, L_copy_8_chars_exit); kvn@4479: packuswb(tmp3Reg, tmp1Reg); kvn@4479: movq(Address(dst, len, Address::times_1, -8), tmp3Reg); kvn@4479: addptr(len, 8); kvn@4479: jccb(Assembler::lessEqual, L_copy_8_chars); kvn@4479: kvn@4479: bind(L_copy_8_chars_exit); kvn@4479: subptr(len, 8); kvn@4479: jccb(Assembler::zero, L_done); kvn@4479: } kvn@4479: kvn@4479: bind(L_copy_1_char); kvn@4479: load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); kvn@4479: testl(tmp5, 0xff00); // check if Unicode char kvn@4479: jccb(Assembler::notZero, L_copy_1_char_exit); kvn@4479: movb(Address(dst, len, Address::times_1, 0), tmp5); kvn@4479: addptr(len, 1); kvn@4479: jccb(Assembler::less, L_copy_1_char); kvn@4479: kvn@4479: bind(L_copy_1_char_exit); kvn@4479: addptr(result, len); // len is negative count of not processed elements kvn@4479: bind(L_done); kvn@4479: } kvn@4479: twisti@4318: #undef BIND twisti@4318: #undef BLOCK_COMMENT twisti@4318: twisti@4318: twisti@4318: Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { twisti@4318: switch (cond) { twisti@4318: // Note some conditions are synonyms for others twisti@4318: case Assembler::zero: return Assembler::notZero; twisti@4318: case Assembler::notZero: return Assembler::zero; twisti@4318: case Assembler::less: return Assembler::greaterEqual; twisti@4318: case Assembler::lessEqual: return Assembler::greater; twisti@4318: case Assembler::greater: return Assembler::lessEqual; twisti@4318: case Assembler::greaterEqual: return Assembler::less; twisti@4318: case Assembler::below: return Assembler::aboveEqual; twisti@4318: case Assembler::belowEqual: return Assembler::above; twisti@4318: case Assembler::above: return Assembler::belowEqual; twisti@4318: case Assembler::aboveEqual: return Assembler::below; twisti@4318: case Assembler::overflow: return Assembler::noOverflow; twisti@4318: case Assembler::noOverflow: return Assembler::overflow; twisti@4318: case Assembler::negative: return Assembler::positive; twisti@4318: case Assembler::positive: return Assembler::negative; twisti@4318: case Assembler::parity: return Assembler::noParity; twisti@4318: case Assembler::noParity: return Assembler::parity; twisti@4318: } twisti@4318: ShouldNotReachHere(); return Assembler::overflow; twisti@4318: } twisti@4318: twisti@4318: SkipIfEqual::SkipIfEqual( twisti@4318: MacroAssembler* masm, const bool* flag_addr, bool value) { twisti@4318: _masm = masm; twisti@4318: _masm->cmp8(ExternalAddress((address)flag_addr), value); twisti@4318: _masm->jcc(Assembler::equal, _label); twisti@4318: } twisti@4318: twisti@4318: SkipIfEqual::~SkipIfEqual() { twisti@4318: _masm->bind(_label); twisti@4318: }