duke@435: /* xdono@631: * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: #include "incls/_precompiled.incl" duke@435: #include "incls/_matcher.cpp.incl" duke@435: duke@435: OptoReg::Name OptoReg::c_frame_pointer; duke@435: duke@435: duke@435: duke@435: const int Matcher::base2reg[Type::lastype] = { coleenp@548: Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN, duke@435: Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */ duke@435: Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */ duke@435: 0, 0/*abio*/, duke@435: Op_RegP /* Return address */, 0, /* the memories */ duke@435: Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD, duke@435: 0 /*bottom*/ duke@435: }; duke@435: duke@435: const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; duke@435: RegMask Matcher::mreg2regmask[_last_Mach_Reg]; duke@435: RegMask Matcher::STACK_ONLY_mask; duke@435: RegMask Matcher::c_frame_ptr_mask; duke@435: const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; duke@435: const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; duke@435: duke@435: //---------------------------Matcher------------------------------------------- duke@435: Matcher::Matcher( Node_List &proj_list ) : duke@435: PhaseTransform( Phase::Ins_Select ), duke@435: #ifdef ASSERT duke@435: _old2new_map(C->comp_arena()), never@657: _new2old_map(C->comp_arena()), duke@435: #endif kvn@603: _shared_nodes(C->comp_arena()), duke@435: _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), duke@435: _swallowed(swallowed), duke@435: _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), duke@435: _end_inst_chain_rule(_END_INST_CHAIN_RULE), duke@435: _must_clone(must_clone), _proj_list(proj_list), duke@435: _register_save_policy(register_save_policy), duke@435: _c_reg_save_policy(c_reg_save_policy), duke@435: _register_save_type(register_save_type), duke@435: _ruleName(ruleName), duke@435: _allocation_started(false), duke@435: _states_arena(Chunk::medium_size), duke@435: _visited(&_states_arena), duke@435: _shared(&_states_arena), duke@435: _dontcare(&_states_arena) { duke@435: C->set_matcher(this); duke@435: duke@435: idealreg2spillmask[Op_RegI] = NULL; coleenp@548: idealreg2spillmask[Op_RegN] = NULL; duke@435: idealreg2spillmask[Op_RegL] = NULL; duke@435: idealreg2spillmask[Op_RegF] = NULL; duke@435: idealreg2spillmask[Op_RegD] = NULL; duke@435: idealreg2spillmask[Op_RegP] = NULL; duke@435: duke@435: idealreg2debugmask[Op_RegI] = NULL; coleenp@548: idealreg2debugmask[Op_RegN] = NULL; duke@435: idealreg2debugmask[Op_RegL] = NULL; duke@435: idealreg2debugmask[Op_RegF] = NULL; duke@435: idealreg2debugmask[Op_RegD] = NULL; duke@435: idealreg2debugmask[Op_RegP] = NULL; kvn@651: debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node duke@435: } duke@435: duke@435: //------------------------------warp_incoming_stk_arg------------------------ duke@435: // This warps a VMReg into an OptoReg::Name duke@435: OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { duke@435: OptoReg::Name warped; duke@435: if( reg->is_stack() ) { // Stack slot argument? duke@435: warped = OptoReg::add(_old_SP, reg->reg2stack() ); duke@435: warped = OptoReg::add(warped, C->out_preserve_stack_slots()); duke@435: if( warped >= _in_arg_limit ) duke@435: _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen duke@435: if (!RegMask::can_represent(warped)) { duke@435: // the compiler cannot represent this method's calling sequence duke@435: C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence"); duke@435: return OptoReg::Bad; duke@435: } duke@435: return warped; duke@435: } duke@435: return OptoReg::as_OptoReg(reg); duke@435: } duke@435: duke@435: //---------------------------compute_old_SP------------------------------------ duke@435: OptoReg::Name Compile::compute_old_SP() { duke@435: int fixed = fixed_slots(); duke@435: int preserve = in_preserve_stack_slots(); duke@435: return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots())); duke@435: } duke@435: duke@435: duke@435: duke@435: #ifdef ASSERT duke@435: void Matcher::verify_new_nodes_only(Node* xroot) { duke@435: // Make sure that the new graph only references new nodes duke@435: ResourceMark rm; duke@435: Unique_Node_List worklist; duke@435: VectorSet visited(Thread::current()->resource_area()); duke@435: worklist.push(xroot); duke@435: while (worklist.size() > 0) { duke@435: Node* n = worklist.pop(); duke@435: visited <<= n->_idx; duke@435: assert(C->node_arena()->contains(n), "dead node"); duke@435: for (uint j = 0; j < n->req(); j++) { duke@435: Node* in = n->in(j); duke@435: if (in != NULL) { duke@435: assert(C->node_arena()->contains(in), "dead node"); duke@435: if (!visited.test(in->_idx)) { duke@435: worklist.push(in); duke@435: } duke@435: } duke@435: } duke@435: } duke@435: } duke@435: #endif duke@435: duke@435: duke@435: //---------------------------match--------------------------------------------- duke@435: void Matcher::match( ) { duke@435: // One-time initialization of some register masks. duke@435: init_spill_mask( C->root()->in(1) ); duke@435: _return_addr_mask = return_addr(); duke@435: #ifdef _LP64 duke@435: // Pointers take 2 slots in 64-bit land duke@435: _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); duke@435: #endif duke@435: duke@435: // Map a Java-signature return type into return register-value duke@435: // machine registers for 0, 1 and 2 returned values. duke@435: const TypeTuple *range = C->tf()->range(); duke@435: if( range->cnt() > TypeFunc::Parms ) { // If not a void function duke@435: // Get ideal-register return type duke@435: int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()]; duke@435: // Get machine return register duke@435: uint sop = C->start()->Opcode(); duke@435: OptoRegPair regs = return_value(ireg, false); duke@435: duke@435: // And mask for same duke@435: _return_value_mask = RegMask(regs.first()); duke@435: if( OptoReg::is_valid(regs.second()) ) duke@435: _return_value_mask.Insert(regs.second()); duke@435: } duke@435: duke@435: // --------------- duke@435: // Frame Layout duke@435: duke@435: // Need the method signature to determine the incoming argument types, duke@435: // because the types determine which registers the incoming arguments are duke@435: // in, and this affects the matched code. duke@435: const TypeTuple *domain = C->tf()->domain(); duke@435: uint argcnt = domain->cnt() - TypeFunc::Parms; duke@435: BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); duke@435: VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); duke@435: _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); duke@435: _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); duke@435: uint i; duke@435: for( i = 0; ifield_at(i+TypeFunc::Parms)->basic_type(); duke@435: } duke@435: duke@435: // Pass array of ideal registers and length to USER code (from the AD file) duke@435: // that will convert this to an array of register numbers. duke@435: const StartNode *start = C->start(); duke@435: start->calling_convention( sig_bt, vm_parm_regs, argcnt ); duke@435: #ifdef ASSERT duke@435: // Sanity check users' calling convention. Real handy while trying to duke@435: // get the initial port correct. duke@435: { for (uint i = 0; iis_valid() && !vm_parm_regs[i].second()->is_valid() ) { duke@435: assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); duke@435: _parm_regs[i].set_bad(); duke@435: continue; duke@435: } duke@435: VMReg parm_reg = vm_parm_regs[i].first(); duke@435: assert(parm_reg->is_valid(), "invalid arg?"); duke@435: if (parm_reg->is_reg()) { duke@435: OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); duke@435: assert(can_be_java_arg(opto_parm_reg) || duke@435: C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || duke@435: opto_parm_reg == inline_cache_reg(), duke@435: "parameters in register must be preserved by runtime stubs"); duke@435: } duke@435: for (uint j = 0; j < i; j++) { duke@435: assert(parm_reg != vm_parm_regs[j].first(), duke@435: "calling conv. must produce distinct regs"); duke@435: } duke@435: } duke@435: } duke@435: #endif duke@435: duke@435: // Do some initial frame layout. duke@435: duke@435: // Compute the old incoming SP (may be called FP) as duke@435: // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. duke@435: _old_SP = C->compute_old_SP(); duke@435: assert( is_even(_old_SP), "must be even" ); duke@435: duke@435: // Compute highest incoming stack argument as duke@435: // _old_SP + out_preserve_stack_slots + incoming argument size. duke@435: _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); duke@435: assert( is_even(_in_arg_limit), "out_preserve must be even" ); duke@435: for( i = 0; i < argcnt; i++ ) { duke@435: // Permit args to have no register duke@435: _calling_convention_mask[i].Clear(); duke@435: if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { duke@435: continue; duke@435: } duke@435: // calling_convention returns stack arguments as a count of duke@435: // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to duke@435: // the allocators point of view, taking into account all the duke@435: // preserve area, locks & pad2. duke@435: duke@435: OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); duke@435: if( OptoReg::is_valid(reg1)) duke@435: _calling_convention_mask[i].Insert(reg1); duke@435: duke@435: OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); duke@435: if( OptoReg::is_valid(reg2)) duke@435: _calling_convention_mask[i].Insert(reg2); duke@435: duke@435: // Saved biased stack-slot register number duke@435: _parm_regs[i].set_pair(reg2, reg1); duke@435: } duke@435: duke@435: // Finally, make sure the incoming arguments take up an even number of duke@435: // words, in case the arguments or locals need to contain doubleword stack duke@435: // slots. The rest of the system assumes that stack slot pairs (in duke@435: // particular, in the spill area) which look aligned will in fact be duke@435: // aligned relative to the stack pointer in the target machine. Double duke@435: // stack slots will always be allocated aligned. duke@435: _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong)); duke@435: duke@435: // Compute highest outgoing stack argument as duke@435: // _new_SP + out_preserve_stack_slots + max(outgoing argument size). duke@435: _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); duke@435: assert( is_even(_out_arg_limit), "out_preserve must be even" ); duke@435: duke@435: if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) { duke@435: // the compiler cannot represent this method's calling sequence duke@435: C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); duke@435: } duke@435: duke@435: if (C->failing()) return; // bailed out on incoming arg failure duke@435: duke@435: // --------------- duke@435: // Collect roots of matcher trees. Every node for which duke@435: // _shared[_idx] is cleared is guaranteed to not be shared, and thus duke@435: // can be a valid interior of some tree. duke@435: find_shared( C->root() ); duke@435: find_shared( C->top() ); duke@435: duke@435: C->print_method("Before Matching", 2); duke@435: duke@435: // Swap out to old-space; emptying new-space duke@435: Arena *old = C->node_arena()->move_contents(C->old_arena()); duke@435: duke@435: // Save debug and profile information for nodes in old space: duke@435: _old_node_note_array = C->node_note_array(); duke@435: if (_old_node_note_array != NULL) { duke@435: C->set_node_note_array(new(C->comp_arena()) GrowableArray duke@435: (C->comp_arena(), _old_node_note_array->length(), duke@435: 0, NULL)); duke@435: } duke@435: duke@435: // Pre-size the new_node table to avoid the need for range checks. duke@435: grow_new_node_array(C->unique()); duke@435: duke@435: // Reset node counter so MachNodes start with _idx at 0 duke@435: int nodes = C->unique(); // save value duke@435: C->set_unique(0); duke@435: duke@435: // Recursively match trees from old space into new space. duke@435: // Correct leaves of new-space Nodes; they point to old-space. duke@435: _visited.Clear(); // Clear visit bits for xform call duke@435: C->set_cached_top_node(xform( C->top(), nodes )); duke@435: if (!C->failing()) { duke@435: Node* xroot = xform( C->root(), 1 ); duke@435: if (xroot == NULL) { duke@435: Matcher::soft_match_failure(); // recursive matching process failed duke@435: C->record_method_not_compilable("instruction match failed"); duke@435: } else { duke@435: // During matching shared constants were attached to C->root() duke@435: // because xroot wasn't available yet, so transfer the uses to duke@435: // the xroot. duke@435: for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { duke@435: Node* n = C->root()->fast_out(j); duke@435: if (C->node_arena()->contains(n)) { duke@435: assert(n->in(0) == C->root(), "should be control user"); duke@435: n->set_req(0, xroot); duke@435: --j; duke@435: --jmax; duke@435: } duke@435: } duke@435: duke@435: C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); duke@435: #ifdef ASSERT duke@435: verify_new_nodes_only(xroot); duke@435: #endif duke@435: } duke@435: } duke@435: if (C->top() == NULL || C->root() == NULL) { duke@435: C->record_method_not_compilable("graph lost"); // %%% cannot happen? duke@435: } duke@435: if (C->failing()) { duke@435: // delete old; duke@435: old->destruct_contents(); duke@435: return; duke@435: } duke@435: assert( C->top(), "" ); duke@435: assert( C->root(), "" ); duke@435: validate_null_checks(); duke@435: duke@435: // Now smoke old-space duke@435: NOT_DEBUG( old->destruct_contents() ); duke@435: duke@435: // ------------------------ duke@435: // Set up save-on-entry registers duke@435: Fixup_Save_On_Entry( ); duke@435: } duke@435: duke@435: duke@435: //------------------------------Fixup_Save_On_Entry---------------------------- duke@435: // The stated purpose of this routine is to take care of save-on-entry duke@435: // registers. However, the overall goal of the Match phase is to convert into duke@435: // machine-specific instructions which have RegMasks to guide allocation. duke@435: // So what this procedure really does is put a valid RegMask on each input duke@435: // to the machine-specific variations of all Return, TailCall and Halt duke@435: // instructions. It also adds edgs to define the save-on-entry values (and of duke@435: // course gives them a mask). duke@435: duke@435: static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { duke@435: RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); duke@435: // Do all the pre-defined register masks duke@435: rms[TypeFunc::Control ] = RegMask::Empty; duke@435: rms[TypeFunc::I_O ] = RegMask::Empty; duke@435: rms[TypeFunc::Memory ] = RegMask::Empty; duke@435: rms[TypeFunc::ReturnAdr] = ret_adr; duke@435: rms[TypeFunc::FramePtr ] = fp; duke@435: return rms; duke@435: } duke@435: duke@435: //---------------------------init_first_stack_mask----------------------------- duke@435: // Create the initial stack mask used by values spilling to the stack. duke@435: // Disallow any debug info in outgoing argument areas by setting the duke@435: // initial mask accordingly. duke@435: void Matcher::init_first_stack_mask() { duke@435: duke@435: // Allocate storage for spill masks as masks for the appropriate load type. coleenp@548: RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask)*12); coleenp@548: idealreg2spillmask[Op_RegN] = &rms[0]; coleenp@548: idealreg2spillmask[Op_RegI] = &rms[1]; coleenp@548: idealreg2spillmask[Op_RegL] = &rms[2]; coleenp@548: idealreg2spillmask[Op_RegF] = &rms[3]; coleenp@548: idealreg2spillmask[Op_RegD] = &rms[4]; coleenp@548: idealreg2spillmask[Op_RegP] = &rms[5]; coleenp@548: idealreg2debugmask[Op_RegN] = &rms[6]; coleenp@548: idealreg2debugmask[Op_RegI] = &rms[7]; coleenp@548: idealreg2debugmask[Op_RegL] = &rms[8]; coleenp@548: idealreg2debugmask[Op_RegF] = &rms[9]; coleenp@548: idealreg2debugmask[Op_RegD] = &rms[10]; coleenp@548: idealreg2debugmask[Op_RegP] = &rms[11]; duke@435: duke@435: OptoReg::Name i; duke@435: duke@435: // At first, start with the empty mask duke@435: C->FIRST_STACK_mask().Clear(); duke@435: duke@435: // Add in the incoming argument area duke@435: OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); duke@435: for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1)) duke@435: C->FIRST_STACK_mask().Insert(i); duke@435: duke@435: // Add in all bits past the outgoing argument area duke@435: guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)), duke@435: "must be able to represent all call arguments in reg mask"); duke@435: init = _out_arg_limit; duke@435: for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) duke@435: C->FIRST_STACK_mask().Insert(i); duke@435: duke@435: // Finally, set the "infinite stack" bit. duke@435: C->FIRST_STACK_mask().set_AllStack(); duke@435: duke@435: // Make spill masks. Registers for their class, plus FIRST_STACK_mask. coleenp@548: #ifdef _LP64 coleenp@548: *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; coleenp@548: idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); coleenp@548: #endif duke@435: *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; duke@435: idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); duke@435: *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; duke@435: idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask()); duke@435: *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; duke@435: idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); duke@435: *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; duke@435: idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask()); duke@435: *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; duke@435: idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); duke@435: duke@435: // Make up debug masks. Any spill slot plus callee-save registers. duke@435: // Caller-save registers are assumed to be trashable by the various duke@435: // inline-cache fixup routines. coleenp@548: *idealreg2debugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; duke@435: *idealreg2debugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; duke@435: *idealreg2debugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; duke@435: *idealreg2debugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; duke@435: *idealreg2debugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; duke@435: *idealreg2debugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; duke@435: duke@435: // Prevent stub compilations from attempting to reference duke@435: // callee-saved registers from debug info duke@435: bool exclude_soe = !Compile::current()->is_method_compilation(); duke@435: duke@435: for( i=OptoReg::Name(0); iRemove(i); duke@435: idealreg2debugmask[Op_RegI]->Remove(i); // Exclude save-on-call duke@435: idealreg2debugmask[Op_RegL]->Remove(i); // registers from debug duke@435: idealreg2debugmask[Op_RegF]->Remove(i); // masks duke@435: idealreg2debugmask[Op_RegD]->Remove(i); duke@435: idealreg2debugmask[Op_RegP]->Remove(i); duke@435: } duke@435: } duke@435: } duke@435: duke@435: //---------------------------is_save_on_entry---------------------------------- duke@435: bool Matcher::is_save_on_entry( int reg ) { duke@435: return duke@435: _register_save_policy[reg] == 'E' || duke@435: _register_save_policy[reg] == 'A' || // Save-on-entry register? duke@435: // Also save argument registers in the trampolining stubs duke@435: (C->save_argument_registers() && is_spillable_arg(reg)); duke@435: } duke@435: duke@435: //---------------------------Fixup_Save_On_Entry------------------------------- duke@435: void Matcher::Fixup_Save_On_Entry( ) { duke@435: init_first_stack_mask(); duke@435: duke@435: Node *root = C->root(); // Short name for root duke@435: // Count number of save-on-entry registers. duke@435: uint soe_cnt = number_of_saved_registers(); duke@435: uint i; duke@435: duke@435: // Find the procedure Start Node duke@435: StartNode *start = C->start(); duke@435: assert( start, "Expect a start node" ); duke@435: duke@435: // Save argument registers in the trampolining stubs duke@435: if( C->save_argument_registers() ) duke@435: for( i = 0; i < _last_Mach_Reg; i++ ) duke@435: if( is_spillable_arg(i) ) duke@435: soe_cnt++; duke@435: duke@435: // Input RegMask array shared by all Returns. duke@435: // The type for doubles and longs has a count of 2, but duke@435: // there is only 1 returned value duke@435: uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); duke@435: RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); duke@435: // Returns have 0 or 1 returned values depending on call signature. duke@435: // Return register is specified by return_value in the AD file. duke@435: if (ret_edge_cnt > TypeFunc::Parms) duke@435: ret_rms[TypeFunc::Parms+0] = _return_value_mask; duke@435: duke@435: // Input RegMask array shared by all Rethrows. duke@435: uint reth_edge_cnt = TypeFunc::Parms+1; duke@435: RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); duke@435: // Rethrow takes exception oop only, but in the argument 0 slot. duke@435: reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)]; duke@435: #ifdef _LP64 duke@435: // Need two slots for ptrs in 64-bit land duke@435: reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1)); duke@435: #endif duke@435: duke@435: // Input RegMask array shared by all TailCalls duke@435: uint tail_call_edge_cnt = TypeFunc::Parms+2; duke@435: RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); duke@435: duke@435: // Input RegMask array shared by all TailJumps duke@435: uint tail_jump_edge_cnt = TypeFunc::Parms+2; duke@435: RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); duke@435: duke@435: // TailCalls have 2 returned values (target & moop), whose masks come duke@435: // from the usual MachNode/MachOper mechanism. Find a sample duke@435: // TailCall to extract these masks and put the correct masks into duke@435: // the tail_call_rms array. duke@435: for( i=1; i < root->req(); i++ ) { duke@435: MachReturnNode *m = root->in(i)->as_MachReturn(); duke@435: if( m->ideal_Opcode() == Op_TailCall ) { duke@435: tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); duke@435: tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); duke@435: break; duke@435: } duke@435: } duke@435: duke@435: // TailJumps have 2 returned values (target & ex_oop), whose masks come duke@435: // from the usual MachNode/MachOper mechanism. Find a sample duke@435: // TailJump to extract these masks and put the correct masks into duke@435: // the tail_jump_rms array. duke@435: for( i=1; i < root->req(); i++ ) { duke@435: MachReturnNode *m = root->in(i)->as_MachReturn(); duke@435: if( m->ideal_Opcode() == Op_TailJump ) { duke@435: tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); duke@435: tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); duke@435: break; duke@435: } duke@435: } duke@435: duke@435: // Input RegMask array shared by all Halts duke@435: uint halt_edge_cnt = TypeFunc::Parms; duke@435: RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); duke@435: duke@435: // Capture the return input masks into each exit flavor duke@435: for( i=1; i < root->req(); i++ ) { duke@435: MachReturnNode *exit = root->in(i)->as_MachReturn(); duke@435: switch( exit->ideal_Opcode() ) { duke@435: case Op_Return : exit->_in_rms = ret_rms; break; duke@435: case Op_Rethrow : exit->_in_rms = reth_rms; break; duke@435: case Op_TailCall : exit->_in_rms = tail_call_rms; break; duke@435: case Op_TailJump : exit->_in_rms = tail_jump_rms; break; duke@435: case Op_Halt : exit->_in_rms = halt_rms; break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: // Next unused projection number from Start. duke@435: int proj_cnt = C->tf()->domain()->cnt(); duke@435: duke@435: // Do all the save-on-entry registers. Make projections from Start for duke@435: // them, and give them a use at the exit points. To the allocator, they duke@435: // look like incoming register arguments. duke@435: for( i = 0; i < _last_Mach_Reg; i++ ) { duke@435: if( is_save_on_entry(i) ) { duke@435: duke@435: // Add the save-on-entry to the mask array duke@435: ret_rms [ ret_edge_cnt] = mreg2regmask[i]; duke@435: reth_rms [ reth_edge_cnt] = mreg2regmask[i]; duke@435: tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; duke@435: tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; duke@435: // Halts need the SOE registers, but only in the stack as debug info. duke@435: // A just-prior uncommon-trap or deoptimization will use the SOE regs. duke@435: halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; duke@435: duke@435: Node *mproj; duke@435: duke@435: // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's duke@435: // into a single RegD. duke@435: if( (i&1) == 0 && duke@435: _register_save_type[i ] == Op_RegF && duke@435: _register_save_type[i+1] == Op_RegF && duke@435: is_save_on_entry(i+1) ) { duke@435: // Add other bit for double duke@435: ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); duke@435: proj_cnt += 2; // Skip 2 for doubles duke@435: } duke@435: else if( (i&1) == 1 && // Else check for high half of double duke@435: _register_save_type[i-1] == Op_RegF && duke@435: _register_save_type[i ] == Op_RegF && duke@435: is_save_on_entry(i-1) ) { duke@435: ret_rms [ ret_edge_cnt] = RegMask::Empty; duke@435: reth_rms [ reth_edge_cnt] = RegMask::Empty; duke@435: tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; duke@435: tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; duke@435: halt_rms [ halt_edge_cnt] = RegMask::Empty; duke@435: mproj = C->top(); duke@435: } duke@435: // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's duke@435: // into a single RegL. duke@435: else if( (i&1) == 0 && duke@435: _register_save_type[i ] == Op_RegI && duke@435: _register_save_type[i+1] == Op_RegI && duke@435: is_save_on_entry(i+1) ) { duke@435: // Add other bit for long duke@435: ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); duke@435: mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); duke@435: proj_cnt += 2; // Skip 2 for longs duke@435: } duke@435: else if( (i&1) == 1 && // Else check for high half of long duke@435: _register_save_type[i-1] == Op_RegI && duke@435: _register_save_type[i ] == Op_RegI && duke@435: is_save_on_entry(i-1) ) { duke@435: ret_rms [ ret_edge_cnt] = RegMask::Empty; duke@435: reth_rms [ reth_edge_cnt] = RegMask::Empty; duke@435: tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; duke@435: tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; duke@435: halt_rms [ halt_edge_cnt] = RegMask::Empty; duke@435: mproj = C->top(); duke@435: } else { duke@435: // Make a projection for it off the Start duke@435: mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); duke@435: } duke@435: duke@435: ret_edge_cnt ++; duke@435: reth_edge_cnt ++; duke@435: tail_call_edge_cnt ++; duke@435: tail_jump_edge_cnt ++; duke@435: halt_edge_cnt ++; duke@435: duke@435: // Add a use of the SOE register to all exit paths duke@435: for( uint j=1; j < root->req(); j++ ) duke@435: root->in(j)->add_req(mproj); duke@435: } // End of if a save-on-entry register duke@435: } // End of for all machine registers duke@435: } duke@435: duke@435: //------------------------------init_spill_mask-------------------------------- duke@435: void Matcher::init_spill_mask( Node *ret ) { duke@435: if( idealreg2regmask[Op_RegI] ) return; // One time only init duke@435: duke@435: OptoReg::c_frame_pointer = c_frame_pointer(); duke@435: c_frame_ptr_mask = c_frame_pointer(); duke@435: #ifdef _LP64 duke@435: // pointers are twice as big duke@435: c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); duke@435: #endif duke@435: duke@435: // Start at OptoReg::stack0() duke@435: STACK_ONLY_mask.Clear(); duke@435: OptoReg::Name init = OptoReg::stack2reg(0); duke@435: // STACK_ONLY_mask is all stack bits duke@435: OptoReg::Name i; duke@435: for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) duke@435: STACK_ONLY_mask.Insert(i); duke@435: // Also set the "infinite stack" bit. duke@435: STACK_ONLY_mask.set_AllStack(); duke@435: duke@435: // Copy the register names over into the shared world duke@435: for( i=OptoReg::Name(0); iin(TypeFunc::FramePtr); duke@435: Node *mem = ret->in(TypeFunc::Memory); duke@435: const TypePtr* atp = TypePtr::BOTTOM; duke@435: // Share frame pointer while making spill ops duke@435: set_shared(fp); duke@435: duke@435: // Compute generic short-offset Loads coleenp@548: #ifdef _LP64 coleenp@548: MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); coleenp@548: #endif duke@435: MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp)); duke@435: MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp)); duke@435: MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp)); duke@435: MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp)); duke@435: MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); duke@435: assert(spillI != NULL && spillL != NULL && spillF != NULL && duke@435: spillD != NULL && spillP != NULL, ""); duke@435: duke@435: // Get the ADLC notion of the right regmask, for each basic type. coleenp@548: #ifdef _LP64 coleenp@548: idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); coleenp@548: #endif duke@435: idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); duke@435: idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); duke@435: idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); duke@435: idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); duke@435: idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: static void match_alias_type(Compile* C, Node* n, Node* m) { duke@435: if (!VerifyAliases) return; // do not go looking for trouble by default duke@435: const TypePtr* nat = n->adr_type(); duke@435: const TypePtr* mat = m->adr_type(); duke@435: int nidx = C->get_alias_index(nat); duke@435: int midx = C->get_alias_index(mat); duke@435: // Detune the assert for cases like (AndI 0xFF (LoadB p)). duke@435: if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { duke@435: for (uint i = 1; i < n->req(); i++) { duke@435: Node* n1 = n->in(i); duke@435: const TypePtr* n1at = n1->adr_type(); duke@435: if (n1at != NULL) { duke@435: nat = n1at; duke@435: nidx = C->get_alias_index(n1at); duke@435: } duke@435: } duke@435: } duke@435: // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: duke@435: if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { duke@435: switch (n->Opcode()) { duke@435: case Op_PrefetchRead: duke@435: case Op_PrefetchWrite: duke@435: nidx = Compile::AliasIdxRaw; duke@435: nat = TypeRawPtr::BOTTOM; duke@435: break; duke@435: } duke@435: } duke@435: if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { duke@435: switch (n->Opcode()) { duke@435: case Op_ClearArray: duke@435: midx = Compile::AliasIdxRaw; duke@435: mat = TypeRawPtr::BOTTOM; duke@435: break; duke@435: } duke@435: } duke@435: if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { duke@435: switch (n->Opcode()) { duke@435: case Op_Return: duke@435: case Op_Rethrow: duke@435: case Op_Halt: duke@435: case Op_TailCall: duke@435: case Op_TailJump: duke@435: nidx = Compile::AliasIdxBot; duke@435: nat = TypePtr::BOTTOM; duke@435: break; duke@435: } duke@435: } duke@435: if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { duke@435: switch (n->Opcode()) { duke@435: case Op_StrComp: rasbold@604: case Op_AryEq: duke@435: case Op_MemBarVolatile: duke@435: case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? duke@435: nidx = Compile::AliasIdxTop; duke@435: nat = NULL; duke@435: break; duke@435: } duke@435: } duke@435: if (nidx != midx) { duke@435: if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { duke@435: tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); duke@435: n->dump(); duke@435: m->dump(); duke@435: } duke@435: assert(C->subsume_loads() && C->must_alias(nat, midx), duke@435: "must not lose alias info when matching"); duke@435: } duke@435: } duke@435: #endif duke@435: duke@435: duke@435: //------------------------------MStack----------------------------------------- duke@435: // State and MStack class used in xform() and find_shared() iterative methods. duke@435: enum Node_State { Pre_Visit, // node has to be pre-visited duke@435: Visit, // visit node duke@435: Post_Visit, // post-visit node duke@435: Alt_Post_Visit // alternative post-visit path duke@435: }; duke@435: duke@435: class MStack: public Node_Stack { duke@435: public: duke@435: MStack(int size) : Node_Stack(size) { } duke@435: duke@435: void push(Node *n, Node_State ns) { duke@435: Node_Stack::push(n, (uint)ns); duke@435: } duke@435: void push(Node *n, Node_State ns, Node *parent, int indx) { duke@435: ++_inode_top; duke@435: if ((_inode_top + 1) >= _inode_max) grow(); duke@435: _inode_top->node = parent; duke@435: _inode_top->indx = (uint)indx; duke@435: ++_inode_top; duke@435: _inode_top->node = n; duke@435: _inode_top->indx = (uint)ns; duke@435: } duke@435: Node *parent() { duke@435: pop(); duke@435: return node(); duke@435: } duke@435: Node_State state() const { duke@435: return (Node_State)index(); duke@435: } duke@435: void set_state(Node_State ns) { duke@435: set_index((uint)ns); duke@435: } duke@435: }; duke@435: duke@435: duke@435: //------------------------------xform------------------------------------------ duke@435: // Given a Node in old-space, Match him (Label/Reduce) to produce a machine duke@435: // Node in new-space. Given a new-space Node, recursively walk his children. duke@435: Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } duke@435: Node *Matcher::xform( Node *n, int max_stack ) { duke@435: // Use one stack to keep both: child's node/state and parent's node/index duke@435: MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2 duke@435: mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root duke@435: duke@435: while (mstack.is_nonempty()) { duke@435: n = mstack.node(); // Leave node on stack duke@435: Node_State nstate = mstack.state(); duke@435: if (nstate == Visit) { duke@435: mstack.set_state(Post_Visit); duke@435: Node *oldn = n; duke@435: // Old-space or new-space check duke@435: if (!C->node_arena()->contains(n)) { duke@435: // Old space! duke@435: Node* m; duke@435: if (has_new_node(n)) { // Not yet Label/Reduced duke@435: m = new_node(n); duke@435: } else { duke@435: if (!is_dontcare(n)) { // Matcher can match this guy duke@435: // Calls match special. They match alone with no children. duke@435: // Their children, the incoming arguments, match normally. duke@435: m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); duke@435: if (C->failing()) return NULL; duke@435: if (m == NULL) { Matcher::soft_match_failure(); return NULL; } duke@435: } else { // Nothing the matcher cares about duke@435: if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections? duke@435: // Convert to machine-dependent projection duke@435: m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); never@657: #ifdef ASSERT never@657: _new2old_map.map(m->_idx, n); never@657: #endif duke@435: if (m->in(0) != NULL) // m might be top duke@435: collect_null_checks(m); duke@435: } else { // Else just a regular 'ol guy duke@435: m = n->clone(); // So just clone into new-space never@657: #ifdef ASSERT never@657: _new2old_map.map(m->_idx, n); never@657: #endif duke@435: // Def-Use edges will be added incrementally as Uses duke@435: // of this node are matched. duke@435: assert(m->outcnt() == 0, "no Uses of this clone yet"); duke@435: } duke@435: } duke@435: duke@435: set_new_node(n, m); // Map old to new duke@435: if (_old_node_note_array != NULL) { duke@435: Node_Notes* nn = C->locate_node_notes(_old_node_note_array, duke@435: n->_idx); duke@435: C->set_node_notes_at(m->_idx, nn); duke@435: } duke@435: debug_only(match_alias_type(C, n, m)); duke@435: } duke@435: n = m; // n is now a new-space node duke@435: mstack.set_node(n); duke@435: } duke@435: duke@435: // New space! duke@435: if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) duke@435: duke@435: int i; duke@435: // Put precedence edges on stack first (match them last). duke@435: for (i = oldn->req(); (uint)i < oldn->len(); i++) { duke@435: Node *m = oldn->in(i); duke@435: if (m == NULL) break; duke@435: // set -1 to call add_prec() instead of set_req() during Step1 duke@435: mstack.push(m, Visit, n, -1); duke@435: } duke@435: duke@435: // For constant debug info, I'd rather have unmatched constants. duke@435: int cnt = n->req(); duke@435: JVMState* jvms = n->jvms(); duke@435: int debug_cnt = jvms ? jvms->debug_start() : cnt; duke@435: duke@435: // Now do only debug info. Clone constants rather than matching. duke@435: // Constants are represented directly in the debug info without duke@435: // the need for executable machine instructions. duke@435: // Monitor boxes are also represented directly. duke@435: for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do duke@435: Node *m = n->in(i); // Get input duke@435: int op = m->Opcode(); duke@435: assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); kvn@598: if( op == Op_ConI || op == Op_ConP || op == Op_ConN || duke@435: op == Op_ConF || op == Op_ConD || op == Op_ConL duke@435: // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp duke@435: ) { duke@435: m = m->clone(); never@657: #ifdef ASSERT never@657: _new2old_map.map(m->_idx, n); never@657: #endif duke@435: mstack.push(m, Post_Visit, n, i); // Don't neet to visit duke@435: mstack.push(m->in(0), Visit, m, 0); duke@435: } else { duke@435: mstack.push(m, Visit, n, i); duke@435: } duke@435: } duke@435: duke@435: // And now walk his children, and convert his inputs to new-space. duke@435: for( ; i >= 0; --i ) { // For all normal inputs do duke@435: Node *m = n->in(i); // Get input duke@435: if(m != NULL) duke@435: mstack.push(m, Visit, n, i); duke@435: } duke@435: duke@435: } duke@435: else if (nstate == Post_Visit) { duke@435: // Set xformed input duke@435: Node *p = mstack.parent(); duke@435: if (p != NULL) { // root doesn't have parent duke@435: int i = (int)mstack.index(); duke@435: if (i >= 0) duke@435: p->set_req(i, n); // required input duke@435: else if (i == -1) duke@435: p->add_prec(n); // precedence input duke@435: else duke@435: ShouldNotReachHere(); duke@435: } duke@435: mstack.pop(); // remove processed node from stack duke@435: } duke@435: else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } // while (mstack.is_nonempty()) duke@435: return n; // Return new-space Node duke@435: } duke@435: duke@435: //------------------------------warp_outgoing_stk_arg------------------------ duke@435: OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { duke@435: // Convert outgoing argument location to a pre-biased stack offset duke@435: if (reg->is_stack()) { duke@435: OptoReg::Name warped = reg->reg2stack(); duke@435: // Adjust the stack slot offset to be the register number used duke@435: // by the allocator. duke@435: warped = OptoReg::add(begin_out_arg_area, warped); duke@435: // Keep track of the largest numbered stack slot used for an arg. duke@435: // Largest used slot per call-site indicates the amount of stack duke@435: // that is killed by the call. duke@435: if( warped >= out_arg_limit_per_call ) duke@435: out_arg_limit_per_call = OptoReg::add(warped,1); duke@435: if (!RegMask::can_represent(warped)) { duke@435: C->record_method_not_compilable_all_tiers("unsupported calling sequence"); duke@435: return OptoReg::Bad; duke@435: } duke@435: return warped; duke@435: } duke@435: return OptoReg::as_OptoReg(reg); duke@435: } duke@435: duke@435: duke@435: //------------------------------match_sfpt------------------------------------- duke@435: // Helper function to match call instructions. Calls match special. duke@435: // They match alone with no children. Their children, the incoming duke@435: // arguments, match normally. duke@435: MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { duke@435: MachSafePointNode *msfpt = NULL; duke@435: MachCallNode *mcall = NULL; duke@435: uint cnt; duke@435: // Split out case for SafePoint vs Call duke@435: CallNode *call; duke@435: const TypeTuple *domain; duke@435: ciMethod* method = NULL; duke@435: if( sfpt->is_Call() ) { duke@435: call = sfpt->as_Call(); duke@435: domain = call->tf()->domain(); duke@435: cnt = domain->cnt(); duke@435: duke@435: // Match just the call, nothing else duke@435: MachNode *m = match_tree(call); duke@435: if (C->failing()) return NULL; duke@435: if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } duke@435: duke@435: // Copy data from the Ideal SafePoint to the machine version duke@435: mcall = m->as_MachCall(); duke@435: duke@435: mcall->set_tf( call->tf()); duke@435: mcall->set_entry_point(call->entry_point()); duke@435: mcall->set_cnt( call->cnt()); duke@435: duke@435: if( mcall->is_MachCallJava() ) { duke@435: MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); duke@435: const CallJavaNode *call_java = call->as_CallJava(); duke@435: method = call_java->method(); duke@435: mcall_java->_method = method; duke@435: mcall_java->_bci = call_java->_bci; duke@435: mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); duke@435: if( mcall_java->is_MachCallStaticJava() ) duke@435: mcall_java->as_MachCallStaticJava()->_name = duke@435: call_java->as_CallStaticJava()->_name; duke@435: if( mcall_java->is_MachCallDynamicJava() ) duke@435: mcall_java->as_MachCallDynamicJava()->_vtable_index = duke@435: call_java->as_CallDynamicJava()->_vtable_index; duke@435: } duke@435: else if( mcall->is_MachCallRuntime() ) { duke@435: mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; duke@435: } duke@435: msfpt = mcall; duke@435: } duke@435: // This is a non-call safepoint duke@435: else { duke@435: call = NULL; duke@435: domain = NULL; duke@435: MachNode *mn = match_tree(sfpt); duke@435: if (C->failing()) return NULL; duke@435: msfpt = mn->as_MachSafePoint(); duke@435: cnt = TypeFunc::Parms; duke@435: } duke@435: duke@435: // Advertise the correct memory effects (for anti-dependence computation). duke@435: msfpt->set_adr_type(sfpt->adr_type()); duke@435: duke@435: // Allocate a private array of RegMasks. These RegMasks are not shared. duke@435: msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); duke@435: // Empty them all. duke@435: memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); duke@435: duke@435: // Do all the pre-defined non-Empty register masks duke@435: msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; duke@435: msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; duke@435: duke@435: // Place first outgoing argument can possibly be put. duke@435: OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); duke@435: assert( is_even(begin_out_arg_area), "" ); duke@435: // Compute max outgoing register number per call site. duke@435: OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; duke@435: // Calls to C may hammer extra stack slots above and beyond any arguments. duke@435: // These are usually backing store for register arguments for varargs. duke@435: if( call != NULL && call->is_CallRuntime() ) duke@435: out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); duke@435: duke@435: duke@435: // Do the normal argument list (parameters) register masks duke@435: int argcnt = cnt - TypeFunc::Parms; duke@435: if( argcnt > 0 ) { // Skip it all if we have no args duke@435: BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); duke@435: VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); duke@435: int i; duke@435: for( i = 0; i < argcnt; i++ ) { duke@435: sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); duke@435: } duke@435: // V-call to pick proper calling convention duke@435: call->calling_convention( sig_bt, parm_regs, argcnt ); duke@435: duke@435: #ifdef ASSERT duke@435: // Sanity check users' calling convention. Really handy during duke@435: // the initial porting effort. Fairly expensive otherwise. duke@435: { for (int i = 0; iis_valid() && duke@435: !parm_regs[i].second()->is_valid() ) continue; duke@435: VMReg reg1 = parm_regs[i].first(); duke@435: VMReg reg2 = parm_regs[i].second(); duke@435: for (int j = 0; j < i; j++) { duke@435: if( !parm_regs[j].first()->is_valid() && duke@435: !parm_regs[j].second()->is_valid() ) continue; duke@435: VMReg reg3 = parm_regs[j].first(); duke@435: VMReg reg4 = parm_regs[j].second(); duke@435: if( !reg1->is_valid() ) { duke@435: assert( !reg2->is_valid(), "valid halvsies" ); duke@435: } else if( !reg3->is_valid() ) { duke@435: assert( !reg4->is_valid(), "valid halvsies" ); duke@435: } else { duke@435: assert( reg1 != reg2, "calling conv. must produce distinct regs"); duke@435: assert( reg1 != reg3, "calling conv. must produce distinct regs"); duke@435: assert( reg1 != reg4, "calling conv. must produce distinct regs"); duke@435: assert( reg2 != reg3, "calling conv. must produce distinct regs"); duke@435: assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); duke@435: assert( reg3 != reg4, "calling conv. must produce distinct regs"); duke@435: } duke@435: } duke@435: } duke@435: } duke@435: #endif duke@435: duke@435: // Visit each argument. Compute its outgoing register mask. duke@435: // Return results now can have 2 bits returned. duke@435: // Compute max over all outgoing arguments both per call-site duke@435: // and over the entire method. duke@435: for( i = 0; i < argcnt; i++ ) { duke@435: // Address of incoming argument mask to fill in duke@435: RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; duke@435: if( !parm_regs[i].first()->is_valid() && duke@435: !parm_regs[i].second()->is_valid() ) { duke@435: continue; // Avoid Halves duke@435: } duke@435: // Grab first register, adjust stack slots and insert in mask. duke@435: OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); duke@435: if (OptoReg::is_valid(reg1)) duke@435: rm->Insert( reg1 ); duke@435: // Grab second register (if any), adjust stack slots and insert in mask. duke@435: OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); duke@435: if (OptoReg::is_valid(reg2)) duke@435: rm->Insert( reg2 ); duke@435: } // End of for all arguments duke@435: duke@435: // Compute number of stack slots needed to restore stack in case of duke@435: // Pascal-style argument popping. duke@435: mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; duke@435: } duke@435: duke@435: // Compute the max stack slot killed by any call. These will not be duke@435: // available for debug info, and will be used to adjust FIRST_STACK_mask duke@435: // after all call sites have been visited. duke@435: if( _out_arg_limit < out_arg_limit_per_call) duke@435: _out_arg_limit = out_arg_limit_per_call; duke@435: duke@435: if (mcall) { duke@435: // Kill the outgoing argument area, including any non-argument holes and duke@435: // any legacy C-killed slots. Use Fat-Projections to do the killing. duke@435: // Since the max-per-method covers the max-per-call-site and debug info duke@435: // is excluded on the max-per-method basis, debug info cannot land in duke@435: // this killed area. duke@435: uint r_cnt = mcall->tf()->range()->cnt(); duke@435: MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); duke@435: if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) { duke@435: C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence"); duke@435: } else { duke@435: for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) duke@435: proj->_rout.Insert(OptoReg::Name(i)); duke@435: } duke@435: if( proj->_rout.is_NotEmpty() ) duke@435: _proj_list.push(proj); duke@435: } duke@435: // Transfer the safepoint information from the call to the mcall duke@435: // Move the JVMState list duke@435: msfpt->set_jvms(sfpt->jvms()); duke@435: for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { duke@435: jvms->set_map(sfpt); duke@435: } duke@435: duke@435: // Debug inputs begin just after the last incoming parameter duke@435: assert( (mcall == NULL) || (mcall->jvms() == NULL) || duke@435: (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" ); duke@435: duke@435: // Move the OopMap duke@435: msfpt->_oop_map = sfpt->_oop_map; duke@435: duke@435: // Registers killed by the call are set in the local scheduling pass duke@435: // of Global Code Motion. duke@435: return msfpt; duke@435: } duke@435: duke@435: //---------------------------match_tree---------------------------------------- duke@435: // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part duke@435: // of the whole-sale conversion from Ideal to Mach Nodes. Also used for duke@435: // making GotoNodes while building the CFG and in init_spill_mask() to identify duke@435: // a Load's result RegMask for memoization in idealreg2regmask[] duke@435: MachNode *Matcher::match_tree( const Node *n ) { duke@435: assert( n->Opcode() != Op_Phi, "cannot match" ); duke@435: assert( !n->is_block_start(), "cannot match" ); duke@435: // Set the mark for all locally allocated State objects. duke@435: // When this call returns, the _states_arena arena will be reset duke@435: // freeing all State objects. duke@435: ResourceMark rm( &_states_arena ); duke@435: duke@435: LabelRootDepth = 0; duke@435: duke@435: // StoreNodes require their Memory input to match any LoadNodes duke@435: Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; kvn@651: #ifdef ASSERT kvn@651: Node* save_mem_node = _mem_node; kvn@651: _mem_node = n->is_Store() ? (Node*)n : NULL; kvn@651: #endif duke@435: // State object for root node of match tree duke@435: // Allocate it on _states_arena - stack allocation can cause stack overflow. duke@435: State *s = new (&_states_arena) State; duke@435: s->_kids[0] = NULL; duke@435: s->_kids[1] = NULL; duke@435: s->_leaf = (Node*)n; duke@435: // Label the input tree, allocating labels from top-level arena duke@435: Label_Root( n, s, n->in(0), mem ); duke@435: if (C->failing()) return NULL; duke@435: duke@435: // The minimum cost match for the whole tree is found at the root State duke@435: uint mincost = max_juint; duke@435: uint cost = max_juint; duke@435: uint i; duke@435: for( i = 0; i < NUM_OPERANDS; i++ ) { duke@435: if( s->valid(i) && // valid entry and duke@435: s->_cost[i] < cost && // low cost and duke@435: s->_rule[i] >= NUM_OPERANDS ) // not an operand duke@435: cost = s->_cost[mincost=i]; duke@435: } duke@435: if (mincost == max_juint) { duke@435: #ifndef PRODUCT duke@435: tty->print("No matching rule for:"); duke@435: s->dump(); duke@435: #endif duke@435: Matcher::soft_match_failure(); duke@435: return NULL; duke@435: } duke@435: // Reduce input tree based upon the state labels to machine Nodes duke@435: MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); duke@435: #ifdef ASSERT duke@435: _old2new_map.map(n->_idx, m); never@657: _new2old_map.map(m->_idx, (Node*)n); duke@435: #endif duke@435: duke@435: // Add any Matcher-ignored edges duke@435: uint cnt = n->req(); duke@435: uint start = 1; duke@435: if( mem != (Node*)1 ) start = MemNode::Memory+1; kvn@603: if( n->is_AddP() ) { duke@435: assert( mem == (Node*)1, "" ); duke@435: start = AddPNode::Base+1; duke@435: } duke@435: for( i = start; i < cnt; i++ ) { duke@435: if( !n->match_edge(i) ) { duke@435: if( i < m->req() ) duke@435: m->ins_req( i, n->in(i) ); duke@435: else duke@435: m->add_req( n->in(i) ); duke@435: } duke@435: } duke@435: kvn@651: debug_only( _mem_node = save_mem_node; ) duke@435: return m; duke@435: } duke@435: duke@435: duke@435: //------------------------------match_into_reg--------------------------------- duke@435: // Choose to either match this Node in a register or part of the current duke@435: // match tree. Return true for requiring a register and false for matching duke@435: // as part of the current match tree. duke@435: static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { duke@435: duke@435: const Type *t = m->bottom_type(); duke@435: duke@435: if( t->singleton() ) { duke@435: // Never force constants into registers. Allow them to match as duke@435: // constants or registers. Copies of the same value will share kvn@603: // the same register. See find_shared_node. duke@435: return false; duke@435: } else { // Not a constant duke@435: // Stop recursion if they have different Controls. duke@435: // Slot 0 of constants is not really a Control. duke@435: if( control && m->in(0) && control != m->in(0) ) { duke@435: duke@435: // Actually, we can live with the most conservative control we duke@435: // find, if it post-dominates the others. This allows us to duke@435: // pick up load/op/store trees where the load can float a little duke@435: // above the store. duke@435: Node *x = control; duke@435: const uint max_scan = 6; // Arbitrary scan cutoff duke@435: uint j; duke@435: for( j=0; jis_Region() ) // Bail out at merge points duke@435: return true; duke@435: x = x->in(0); duke@435: if( x == m->in(0) ) // Does 'control' post-dominate duke@435: break; // m->in(0)? If so, we can use it duke@435: } duke@435: if( j == max_scan ) // No post-domination before scan end? duke@435: return true; // Then break the match tree up duke@435: } kvn@603: if (m->is_DecodeN() && Matcher::clone_shift_expressions) { coleenp@548: // These are commonly used in address expressions and can kvn@603: // efficiently fold into them on X64 in some cases. kvn@603: return false; coleenp@548: } duke@435: } duke@435: duke@435: // Not forceably cloning. If shared, put it into a register. duke@435: return shared; duke@435: } duke@435: duke@435: duke@435: //------------------------------Instruction Selection-------------------------- duke@435: // Label method walks a "tree" of nodes, using the ADLC generated DFA to match duke@435: // ideal nodes to machine instructions. Trees are delimited by shared Nodes, duke@435: // things the Matcher does not match (e.g., Memory), and things with different duke@435: // Controls (hence forced into different blocks). We pass in the Control duke@435: // selected for this entire State tree. duke@435: duke@435: // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the duke@435: // Store and the Load must have identical Memories (as well as identical duke@435: // pointers). Since the Matcher does not have anything for Memory (and duke@435: // does not handle DAGs), I have to match the Memory input myself. If the duke@435: // Tree root is a Store, I require all Loads to have the identical memory. duke@435: Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ duke@435: // Since Label_Root is a recursive function, its possible that we might run duke@435: // out of stack space. See bugs 6272980 & 6227033 for more info. duke@435: LabelRootDepth++; duke@435: if (LabelRootDepth > MaxLabelRootDepth) { duke@435: C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth"); duke@435: return NULL; duke@435: } duke@435: uint care = 0; // Edges matcher cares about duke@435: uint cnt = n->req(); duke@435: uint i = 0; duke@435: duke@435: // Examine children for memory state duke@435: // Can only subsume a child into your match-tree if that child's memory state duke@435: // is not modified along the path to another input. duke@435: // It is unsafe even if the other inputs are separate roots. duke@435: Node *input_mem = NULL; duke@435: for( i = 1; i < cnt; i++ ) { duke@435: if( !n->match_edge(i) ) continue; duke@435: Node *m = n->in(i); // Get ith input duke@435: assert( m, "expect non-null children" ); duke@435: if( m->is_Load() ) { duke@435: if( input_mem == NULL ) { duke@435: input_mem = m->in(MemNode::Memory); duke@435: } else if( input_mem != m->in(MemNode::Memory) ) { duke@435: input_mem = NodeSentinel; duke@435: } duke@435: } duke@435: } duke@435: duke@435: for( i = 1; i < cnt; i++ ){// For my children duke@435: if( !n->match_edge(i) ) continue; duke@435: Node *m = n->in(i); // Get ith input duke@435: // Allocate states out of a private arena duke@435: State *s = new (&_states_arena) State; duke@435: svec->_kids[care++] = s; duke@435: assert( care <= 2, "binary only for now" ); duke@435: duke@435: // Recursively label the State tree. duke@435: s->_kids[0] = NULL; duke@435: s->_kids[1] = NULL; duke@435: s->_leaf = m; duke@435: duke@435: // Check for leaves of the State Tree; things that cannot be a part of duke@435: // the current tree. If it finds any, that value is matched as a duke@435: // register operand. If not, then the normal matching is used. duke@435: if( match_into_reg(n, m, control, i, is_shared(m)) || duke@435: // duke@435: // Stop recursion if this is LoadNode and the root of this tree is a duke@435: // StoreNode and the load & store have different memories. duke@435: ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || duke@435: // Can NOT include the match of a subtree when its memory state duke@435: // is used by any of the other subtrees duke@435: (input_mem == NodeSentinel) ) { duke@435: #ifndef PRODUCT duke@435: // Print when we exclude matching due to different memory states at input-loads duke@435: if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) duke@435: && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) { duke@435: tty->print_cr("invalid input_mem"); duke@435: } duke@435: #endif duke@435: // Switch to a register-only opcode; this value must be in a register duke@435: // and cannot be subsumed as part of a larger instruction. duke@435: s->DFA( m->ideal_reg(), m ); duke@435: duke@435: } else { duke@435: // If match tree has no control and we do, adopt it for entire tree duke@435: if( control == NULL && m->in(0) != NULL && m->req() > 1 ) duke@435: control = m->in(0); // Pick up control duke@435: // Else match as a normal part of the match tree. duke@435: control = Label_Root(m,s,control,mem); duke@435: if (C->failing()) return NULL; duke@435: } duke@435: } duke@435: duke@435: duke@435: // Call DFA to match this node, and return duke@435: svec->DFA( n->Opcode(), n ); duke@435: duke@435: #ifdef ASSERT duke@435: uint x; duke@435: for( x = 0; x < _LAST_MACH_OPER; x++ ) duke@435: if( svec->valid(x) ) duke@435: break; duke@435: duke@435: if (x >= _LAST_MACH_OPER) { duke@435: n->dump(); duke@435: svec->dump(); duke@435: assert( false, "bad AD file" ); duke@435: } duke@435: #endif duke@435: return control; duke@435: } duke@435: duke@435: duke@435: // Con nodes reduced using the same rule can share their MachNode duke@435: // which reduces the number of copies of a constant in the final duke@435: // program. The register allocator is free to split uses later to duke@435: // split live ranges. kvn@603: MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { kvn@603: if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL; duke@435: duke@435: // See if this Con has already been reduced using this rule. kvn@603: if (_shared_nodes.Size() <= leaf->_idx) return NULL; kvn@603: MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); duke@435: if (last != NULL && rule == last->rule()) { kvn@603: // Don't expect control change for DecodeN kvn@603: if (leaf->is_DecodeN()) kvn@603: return last; duke@435: // Get the new space root. duke@435: Node* xroot = new_node(C->root()); duke@435: if (xroot == NULL) { duke@435: // This shouldn't happen give the order of matching. duke@435: return NULL; duke@435: } duke@435: duke@435: // Shared constants need to have their control be root so they duke@435: // can be scheduled properly. duke@435: Node* control = last->in(0); duke@435: if (control != xroot) { duke@435: if (control == NULL || control == C->root()) { duke@435: last->set_req(0, xroot); duke@435: } else { duke@435: assert(false, "unexpected control"); duke@435: return NULL; duke@435: } duke@435: } duke@435: return last; duke@435: } duke@435: return NULL; duke@435: } duke@435: duke@435: duke@435: //------------------------------ReduceInst------------------------------------- duke@435: // Reduce a State tree (with given Control) into a tree of MachNodes. duke@435: // This routine (and it's cohort ReduceOper) convert Ideal Nodes into duke@435: // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. duke@435: // Each MachNode has a number of complicated MachOper operands; each duke@435: // MachOper also covers a further tree of Ideal Nodes. duke@435: duke@435: // The root of the Ideal match tree is always an instruction, so we enter duke@435: // the recursion here. After building the MachNode, we need to recurse duke@435: // the tree checking for these cases: duke@435: // (1) Child is an instruction - duke@435: // Build the instruction (recursively), add it as an edge. duke@435: // Build a simple operand (register) to hold the result of the instruction. duke@435: // (2) Child is an interior part of an instruction - duke@435: // Skip over it (do nothing) duke@435: // (3) Child is the start of a operand - duke@435: // Build the operand, place it inside the instruction duke@435: // Call ReduceOper. duke@435: MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { duke@435: assert( rule >= NUM_OPERANDS, "called with operand rule" ); duke@435: kvn@603: MachNode* shared_node = find_shared_node(s->_leaf, rule); kvn@603: if (shared_node != NULL) { kvn@603: return shared_node; duke@435: } duke@435: duke@435: // Build the object to represent this state & prepare for recursive calls duke@435: MachNode *mach = s->MachNodeGenerator( rule, C ); duke@435: mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C ); duke@435: assert( mach->_opnds[0] != NULL, "Missing result operand" ); duke@435: Node *leaf = s->_leaf; duke@435: // Check for instruction or instruction chain rule duke@435: if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { duke@435: // Instruction duke@435: mach->add_req( leaf->in(0) ); // Set initial control duke@435: // Reduce interior of complex instruction duke@435: ReduceInst_Interior( s, rule, mem, mach, 1 ); duke@435: } else { duke@435: // Instruction chain rules are data-dependent on their inputs duke@435: mach->add_req(0); // Set initial control to none duke@435: ReduceInst_Chain_Rule( s, rule, mem, mach ); duke@435: } duke@435: duke@435: // If a Memory was used, insert a Memory edge kvn@651: if( mem != (Node*)1 ) { duke@435: mach->ins_req(MemNode::Memory,mem); kvn@651: #ifdef ASSERT kvn@651: // Verify adr type after matching memory operation kvn@651: const MachOper* oper = mach->memory_operand(); kvn@651: if (oper != NULL && oper != (MachOper*)-1 && kvn@651: mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode kvn@651: // It has a unique memory operand. Find corresponding ideal mem node. kvn@651: Node* m = NULL; kvn@651: if (leaf->is_Mem()) { kvn@651: m = leaf; kvn@651: } else { kvn@651: m = _mem_node; kvn@651: assert(m != NULL && m->is_Mem(), "expecting memory node"); kvn@651: } kvn@651: if (m->adr_type() != mach->adr_type()) { kvn@651: m->dump(); kvn@651: tty->print_cr("mach:"); kvn@651: mach->dump(1); kvn@651: } kvn@651: assert(m->adr_type() == mach->adr_type(), "matcher should not change adr type"); kvn@651: } kvn@651: #endif kvn@651: } duke@435: duke@435: // If the _leaf is an AddP, insert the base edge kvn@603: if( leaf->is_AddP() ) duke@435: mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); duke@435: duke@435: uint num_proj = _proj_list.size(); duke@435: duke@435: // Perform any 1-to-many expansions required duke@435: MachNode *ex = mach->Expand(s,_proj_list); duke@435: if( ex != mach ) { duke@435: assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); duke@435: if( ex->in(1)->is_Con() ) duke@435: ex->in(1)->set_req(0, C->root()); duke@435: // Remove old node from the graph duke@435: for( uint i=0; ireq(); i++ ) { duke@435: mach->set_req(i,NULL); duke@435: } never@657: #ifdef ASSERT never@657: _new2old_map.map(ex->_idx, s->_leaf); never@657: #endif duke@435: } duke@435: duke@435: // PhaseChaitin::fixup_spills will sometimes generate spill code duke@435: // via the matcher. By the time, nodes have been wired into the CFG, duke@435: // and any further nodes generated by expand rules will be left hanging duke@435: // in space, and will not get emitted as output code. Catch this. duke@435: // Also, catch any new register allocation constraints ("projections") duke@435: // generated belatedly during spill code generation. duke@435: if (_allocation_started) { duke@435: guarantee(ex == mach, "no expand rules during spill generation"); duke@435: guarantee(_proj_list.size() == num_proj, "no allocation during spill generation"); duke@435: } duke@435: kvn@603: if (leaf->is_Con() || leaf->is_DecodeN()) { duke@435: // Record the con for sharing kvn@603: _shared_nodes.map(leaf->_idx, ex); duke@435: } duke@435: duke@435: return ex; duke@435: } duke@435: duke@435: void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { duke@435: // 'op' is what I am expecting to receive duke@435: int op = _leftOp[rule]; duke@435: // Operand type to catch childs result duke@435: // This is what my child will give me. duke@435: int opnd_class_instance = s->_rule[op]; duke@435: // Choose between operand class or not. duke@435: // This is what I will recieve. duke@435: int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; duke@435: // New rule for child. Chase operand classes to get the actual rule. duke@435: int newrule = s->_rule[catch_op]; duke@435: duke@435: if( newrule < NUM_OPERANDS ) { duke@435: // Chain from operand or operand class, may be output of shared node duke@435: assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, duke@435: "Bad AD file: Instruction chain rule must chain from operand"); duke@435: // Insert operand into array of operands for this instruction duke@435: mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C ); duke@435: duke@435: ReduceOper( s, newrule, mem, mach ); duke@435: } else { duke@435: // Chain from the result of an instruction duke@435: assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); duke@435: mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); duke@435: Node *mem1 = (Node*)1; kvn@651: debug_only(Node *save_mem_node = _mem_node;) duke@435: mach->add_req( ReduceInst(s, newrule, mem1) ); kvn@651: debug_only(_mem_node = save_mem_node;) duke@435: } duke@435: return; duke@435: } duke@435: duke@435: duke@435: uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { duke@435: if( s->_leaf->is_Load() ) { duke@435: Node *mem2 = s->_leaf->in(MemNode::Memory); duke@435: assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); kvn@651: debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) duke@435: mem = mem2; duke@435: } duke@435: if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { duke@435: if( mach->in(0) == NULL ) duke@435: mach->set_req(0, s->_leaf->in(0)); duke@435: } duke@435: duke@435: // Now recursively walk the state tree & add operand list. duke@435: for( uint i=0; i<2; i++ ) { // binary tree duke@435: State *newstate = s->_kids[i]; duke@435: if( newstate == NULL ) break; // Might only have 1 child duke@435: // 'op' is what I am expecting to receive duke@435: int op; duke@435: if( i == 0 ) { duke@435: op = _leftOp[rule]; duke@435: } else { duke@435: op = _rightOp[rule]; duke@435: } duke@435: // Operand type to catch childs result duke@435: // This is what my child will give me. duke@435: int opnd_class_instance = newstate->_rule[op]; duke@435: // Choose between operand class or not. duke@435: // This is what I will receive. duke@435: int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; duke@435: // New rule for child. Chase operand classes to get the actual rule. duke@435: int newrule = newstate->_rule[catch_op]; duke@435: duke@435: if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? duke@435: // Operand/operandClass duke@435: // Insert operand into array of operands for this instruction duke@435: mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C ); duke@435: ReduceOper( newstate, newrule, mem, mach ); duke@435: duke@435: } else { // Child is internal operand or new instruction duke@435: if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? duke@435: // internal operand --> call ReduceInst_Interior duke@435: // Interior of complex instruction. Do nothing but recurse. duke@435: num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); duke@435: } else { duke@435: // instruction --> call build operand( ) to catch result duke@435: // --> ReduceInst( newrule ) duke@435: mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); duke@435: Node *mem1 = (Node*)1; kvn@651: debug_only(Node *save_mem_node = _mem_node;) duke@435: mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); kvn@651: debug_only(_mem_node = save_mem_node;) duke@435: } duke@435: } duke@435: assert( mach->_opnds[num_opnds-1], "" ); duke@435: } duke@435: return num_opnds; duke@435: } duke@435: duke@435: // This routine walks the interior of possible complex operands. duke@435: // At each point we check our children in the match tree: duke@435: // (1) No children - duke@435: // We are a leaf; add _leaf field as an input to the MachNode duke@435: // (2) Child is an internal operand - duke@435: // Skip over it ( do nothing ) duke@435: // (3) Child is an instruction - duke@435: // Call ReduceInst recursively and duke@435: // and instruction as an input to the MachNode duke@435: void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { duke@435: assert( rule < _LAST_MACH_OPER, "called with operand rule" ); duke@435: State *kid = s->_kids[0]; duke@435: assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); duke@435: duke@435: // Leaf? And not subsumed? duke@435: if( kid == NULL && !_swallowed[rule] ) { duke@435: mach->add_req( s->_leaf ); // Add leaf pointer duke@435: return; // Bail out duke@435: } duke@435: duke@435: if( s->_leaf->is_Load() ) { duke@435: assert( mem == (Node*)1, "multiple Memories being matched at once?" ); duke@435: mem = s->_leaf->in(MemNode::Memory); kvn@651: debug_only(_mem_node = s->_leaf;) duke@435: } duke@435: if( s->_leaf->in(0) && s->_leaf->req() > 1) { duke@435: if( !mach->in(0) ) duke@435: mach->set_req(0,s->_leaf->in(0)); duke@435: else { duke@435: assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); duke@435: } duke@435: } duke@435: duke@435: for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree duke@435: int newrule; duke@435: if( i == 0 ) duke@435: newrule = kid->_rule[_leftOp[rule]]; duke@435: else duke@435: newrule = kid->_rule[_rightOp[rule]]; duke@435: duke@435: if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? duke@435: // Internal operand; recurse but do nothing else duke@435: ReduceOper( kid, newrule, mem, mach ); duke@435: duke@435: } else { // Child is a new instruction duke@435: // Reduce the instruction, and add a direct pointer from this duke@435: // machine instruction to the newly reduced one. duke@435: Node *mem1 = (Node*)1; kvn@651: debug_only(Node *save_mem_node = _mem_node;) duke@435: mach->add_req( ReduceInst( kid, newrule, mem1 ) ); kvn@651: debug_only(_mem_node = save_mem_node;) duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: // ------------------------------------------------------------------------- duke@435: // Java-Java calling convention duke@435: // (what you use when Java calls Java) duke@435: duke@435: //------------------------------find_receiver---------------------------------- duke@435: // For a given signature, return the OptoReg for parameter 0. duke@435: OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { duke@435: VMRegPair regs; duke@435: BasicType sig_bt = T_OBJECT; duke@435: calling_convention(&sig_bt, ®s, 1, is_outgoing); duke@435: // Return argument 0 register. In the LP64 build pointers duke@435: // take 2 registers, but the VM wants only the 'main' name. duke@435: return OptoReg::as_OptoReg(regs.first()); duke@435: } duke@435: duke@435: // A method-klass-holder may be passed in the inline_cache_reg duke@435: // and then expanded into the inline_cache_reg and a method_oop register duke@435: // defined in ad_.cpp duke@435: duke@435: duke@435: //------------------------------find_shared------------------------------------ duke@435: // Set bits if Node is shared or otherwise a root duke@435: void Matcher::find_shared( Node *n ) { duke@435: // Allocate stack of size C->unique() * 2 to avoid frequent realloc duke@435: MStack mstack(C->unique() * 2); duke@435: mstack.push(n, Visit); // Don't need to pre-visit root node duke@435: while (mstack.is_nonempty()) { duke@435: n = mstack.node(); // Leave node on stack duke@435: Node_State nstate = mstack.state(); duke@435: if (nstate == Pre_Visit) { duke@435: if (is_visited(n)) { // Visited already? duke@435: // Node is shared and has no reason to clone. Flag it as shared. duke@435: // This causes it to match into a register for the sharing. duke@435: set_shared(n); // Flag as shared and duke@435: mstack.pop(); // remove node from stack duke@435: continue; duke@435: } duke@435: nstate = Visit; // Not already visited; so visit now duke@435: } duke@435: if (nstate == Visit) { duke@435: mstack.set_state(Post_Visit); duke@435: set_visited(n); // Flag as visited now duke@435: bool mem_op = false; duke@435: duke@435: switch( n->Opcode() ) { // Handle some opcodes special duke@435: case Op_Phi: // Treat Phis as shared roots duke@435: case Op_Parm: duke@435: case Op_Proj: // All handled specially during matching kvn@498: case Op_SafePointScalarObject: duke@435: set_shared(n); duke@435: set_dontcare(n); duke@435: break; duke@435: case Op_If: duke@435: case Op_CountedLoopEnd: duke@435: mstack.set_state(Alt_Post_Visit); // Alternative way duke@435: // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps duke@435: // with matching cmp/branch in 1 instruction. The Matcher needs the duke@435: // Bool and CmpX side-by-side, because it can only get at constants duke@435: // that are at the leaves of Match trees, and the Bool's condition acts duke@435: // as a constant here. duke@435: mstack.push(n->in(1), Visit); // Clone the Bool duke@435: mstack.push(n->in(0), Pre_Visit); // Visit control input duke@435: continue; // while (mstack.is_nonempty()) duke@435: case Op_ConvI2D: // These forms efficiently match with a prior duke@435: case Op_ConvI2F: // Load but not a following Store duke@435: if( n->in(1)->is_Load() && // Prior load duke@435: n->outcnt() == 1 && // Not already shared duke@435: n->unique_out()->is_Store() ) // Following store duke@435: set_shared(n); // Force it to be a root duke@435: break; duke@435: case Op_ReverseBytesI: duke@435: case Op_ReverseBytesL: duke@435: if( n->in(1)->is_Load() && // Prior load duke@435: n->outcnt() == 1 ) // Not already shared duke@435: set_shared(n); // Force it to be a root duke@435: break; duke@435: case Op_BoxLock: // Cant match until we get stack-regs in ADLC duke@435: case Op_IfFalse: duke@435: case Op_IfTrue: duke@435: case Op_MachProj: duke@435: case Op_MergeMem: duke@435: case Op_Catch: duke@435: case Op_CatchProj: duke@435: case Op_CProj: duke@435: case Op_JumpProj: duke@435: case Op_JProj: duke@435: case Op_NeverBranch: duke@435: set_dontcare(n); duke@435: break; duke@435: case Op_Jump: duke@435: mstack.push(n->in(1), Visit); // Switch Value duke@435: mstack.push(n->in(0), Pre_Visit); // Visit Control input duke@435: continue; // while (mstack.is_nonempty()) duke@435: case Op_StrComp: rasbold@604: case Op_AryEq: duke@435: set_shared(n); // Force result into register (it will be anyways) duke@435: break; duke@435: case Op_ConP: { // Convert pointers above the centerline to NUL duke@435: TypeNode *tn = n->as_Type(); // Constants derive from type nodes duke@435: const TypePtr* tp = tn->type()->is_ptr(); duke@435: if (tp->_ptr == TypePtr::AnyNull) { duke@435: tn->set_type(TypePtr::NULL_PTR); duke@435: } duke@435: break; duke@435: } kvn@598: case Op_ConN: { // Convert narrow pointers above the centerline to NUL kvn@598: TypeNode *tn = n->as_Type(); // Constants derive from type nodes kvn@656: const TypePtr* tp = tn->type()->make_ptr(); kvn@656: if (tp && tp->_ptr == TypePtr::AnyNull) { kvn@598: tn->set_type(TypeNarrowOop::NULL_PTR); kvn@598: } kvn@598: break; kvn@598: } duke@435: case Op_Binary: // These are introduced in the Post_Visit state. duke@435: ShouldNotReachHere(); duke@435: break; duke@435: case Op_StoreB: // Do match these, despite no ideal reg duke@435: case Op_StoreC: duke@435: case Op_StoreCM: duke@435: case Op_StoreD: duke@435: case Op_StoreF: duke@435: case Op_StoreI: duke@435: case Op_StoreL: duke@435: case Op_StoreP: coleenp@548: case Op_StoreN: duke@435: case Op_Store16B: duke@435: case Op_Store8B: duke@435: case Op_Store4B: duke@435: case Op_Store8C: duke@435: case Op_Store4C: duke@435: case Op_Store2C: duke@435: case Op_Store4I: duke@435: case Op_Store2I: duke@435: case Op_Store2L: duke@435: case Op_Store4F: duke@435: case Op_Store2F: duke@435: case Op_Store2D: duke@435: case Op_ClearArray: duke@435: case Op_SafePoint: duke@435: mem_op = true; duke@435: break; duke@435: case Op_LoadB: duke@435: case Op_LoadC: duke@435: case Op_LoadD: duke@435: case Op_LoadF: duke@435: case Op_LoadI: duke@435: case Op_LoadKlass: kvn@599: case Op_LoadNKlass: duke@435: case Op_LoadL: duke@435: case Op_LoadS: duke@435: case Op_LoadP: coleenp@548: case Op_LoadN: duke@435: case Op_LoadRange: duke@435: case Op_LoadD_unaligned: duke@435: case Op_LoadL_unaligned: duke@435: case Op_Load16B: duke@435: case Op_Load8B: duke@435: case Op_Load4B: duke@435: case Op_Load4C: duke@435: case Op_Load2C: duke@435: case Op_Load8C: duke@435: case Op_Load8S: duke@435: case Op_Load4S: duke@435: case Op_Load2S: duke@435: case Op_Load4I: duke@435: case Op_Load2I: duke@435: case Op_Load2L: duke@435: case Op_Load4F: duke@435: case Op_Load2F: duke@435: case Op_Load2D: duke@435: mem_op = true; duke@435: // Must be root of match tree due to prior load conflict duke@435: if( C->subsume_loads() == false ) { duke@435: set_shared(n); duke@435: } duke@435: // Fall into default case duke@435: default: duke@435: if( !n->ideal_reg() ) duke@435: set_dontcare(n); // Unmatchable Nodes duke@435: } // end_switch duke@435: duke@435: for(int i = n->req() - 1; i >= 0; --i) { // For my children duke@435: Node *m = n->in(i); // Get ith input duke@435: if (m == NULL) continue; // Ignore NULLs duke@435: uint mop = m->Opcode(); duke@435: duke@435: // Must clone all producers of flags, or we will not match correctly. duke@435: // Suppose a compare setting int-flags is shared (e.g., a switch-tree) duke@435: // then it will match into an ideal Op_RegFlags. Alas, the fp-flags duke@435: // are also there, so we may match a float-branch to int-flags and duke@435: // expect the allocator to haul the flags from the int-side to the duke@435: // fp-side. No can do. duke@435: if( _must_clone[mop] ) { duke@435: mstack.push(m, Visit); duke@435: continue; // for(int i = ...) duke@435: } duke@435: duke@435: // Clone addressing expressions as they are "free" in most instructions duke@435: if( mem_op && i == MemNode::Address && mop == Op_AddP ) { duke@435: Node *off = m->in(AddPNode::Offset); duke@435: if( off->is_Con() ) { duke@435: set_visited(m); // Flag as visited now duke@435: Node *adr = m->in(AddPNode::Address); duke@435: duke@435: // Intel, ARM and friends can handle 2 adds in addressing mode kvn@603: if( clone_shift_expressions && adr->is_AddP() && duke@435: // AtomicAdd is not an addressing expression. duke@435: // Cheap to find it by looking for screwy base. duke@435: !adr->in(AddPNode::Base)->is_top() ) { duke@435: set_visited(adr); // Flag as visited now duke@435: Node *shift = adr->in(AddPNode::Offset); duke@435: // Check for shift by small constant as well duke@435: if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() && duke@435: shift->in(2)->get_int() <= 3 ) { duke@435: set_visited(shift); // Flag as visited now duke@435: mstack.push(shift->in(2), Visit); duke@435: #ifdef _LP64 duke@435: // Allow Matcher to match the rule which bypass duke@435: // ConvI2L operation for an array index on LP64 duke@435: // if the index value is positive. duke@435: if( shift->in(1)->Opcode() == Op_ConvI2L && duke@435: shift->in(1)->as_Type()->type()->is_long()->_lo >= 0 ) { duke@435: set_visited(shift->in(1)); // Flag as visited now duke@435: mstack.push(shift->in(1)->in(1), Pre_Visit); duke@435: } else duke@435: #endif duke@435: mstack.push(shift->in(1), Pre_Visit); duke@435: } else { duke@435: mstack.push(shift, Pre_Visit); duke@435: } duke@435: mstack.push(adr->in(AddPNode::Address), Pre_Visit); duke@435: mstack.push(adr->in(AddPNode::Base), Pre_Visit); duke@435: } else { // Sparc, Alpha, PPC and friends duke@435: mstack.push(adr, Pre_Visit); duke@435: } duke@435: duke@435: // Clone X+offset as it also folds into most addressing expressions duke@435: mstack.push(off, Visit); duke@435: mstack.push(m->in(AddPNode::Base), Pre_Visit); duke@435: continue; // for(int i = ...) duke@435: } // if( off->is_Con() ) duke@435: } // if( mem_op && duke@435: mstack.push(m, Pre_Visit); duke@435: } // for(int i = ...) duke@435: } duke@435: else if (nstate == Alt_Post_Visit) { duke@435: mstack.pop(); // Remove node from stack duke@435: // We cannot remove the Cmp input from the Bool here, as the Bool may be duke@435: // shared and all users of the Bool need to move the Cmp in parallel. duke@435: // This leaves both the Bool and the If pointing at the Cmp. To duke@435: // prevent the Matcher from trying to Match the Cmp along both paths duke@435: // BoolNode::match_edge always returns a zero. duke@435: duke@435: // We reorder the Op_If in a pre-order manner, so we can visit without duke@435: // accidently sharing the Cmp (the Bool and the If make 2 users). duke@435: n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool duke@435: } duke@435: else if (nstate == Post_Visit) { duke@435: mstack.pop(); // Remove node from stack duke@435: duke@435: // Now hack a few special opcodes duke@435: switch( n->Opcode() ) { // Handle some opcodes special duke@435: case Op_StorePConditional: duke@435: case Op_StoreLConditional: duke@435: case Op_CompareAndSwapI: duke@435: case Op_CompareAndSwapL: coleenp@548: case Op_CompareAndSwapP: coleenp@548: case Op_CompareAndSwapN: { // Convert trinary to binary-tree duke@435: Node *newval = n->in(MemNode::ValueIn ); duke@435: Node *oldval = n->in(LoadStoreNode::ExpectedIn); duke@435: Node *pair = new (C, 3) BinaryNode( oldval, newval ); duke@435: n->set_req(MemNode::ValueIn,pair); duke@435: n->del_req(LoadStoreNode::ExpectedIn); duke@435: break; duke@435: } duke@435: case Op_CMoveD: // Convert trinary to binary-tree duke@435: case Op_CMoveF: duke@435: case Op_CMoveI: duke@435: case Op_CMoveL: kvn@599: case Op_CMoveN: duke@435: case Op_CMoveP: { duke@435: // Restructure into a binary tree for Matching. It's possible that duke@435: // we could move this code up next to the graph reshaping for IfNodes duke@435: // or vice-versa, but I do not want to debug this for Ladybird. duke@435: // 10/2/2000 CNC. duke@435: Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1)); duke@435: n->set_req(1,pair1); duke@435: Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3)); duke@435: n->set_req(2,pair2); duke@435: n->del_req(3); duke@435: break; duke@435: } duke@435: default: duke@435: break; duke@435: } duke@435: } duke@435: else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } // end of while (mstack.is_nonempty()) duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: // machine-independent root to machine-dependent root duke@435: void Matcher::dump_old2new_map() { duke@435: _old2new_map.dump(); duke@435: } duke@435: #endif duke@435: duke@435: //---------------------------collect_null_checks------------------------------- duke@435: // Find null checks in the ideal graph; write a machine-specific node for duke@435: // it. Used by later implicit-null-check handling. Actually collects duke@435: // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal duke@435: // value being tested. duke@435: void Matcher::collect_null_checks( Node *proj ) { duke@435: Node *iff = proj->in(0); duke@435: if( iff->Opcode() == Op_If ) { duke@435: // During matching If's have Bool & Cmp side-by-side duke@435: BoolNode *b = iff->in(1)->as_Bool(); duke@435: Node *cmp = iff->in(2); coleenp@548: int opc = cmp->Opcode(); coleenp@548: if (opc != Op_CmpP && opc != Op_CmpN) return; duke@435: coleenp@548: const Type* ct = cmp->in(2)->bottom_type(); coleenp@548: if (ct == TypePtr::NULL_PTR || coleenp@548: (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { coleenp@548: coleenp@548: if( proj->Opcode() == Op_IfTrue ) { coleenp@548: extern int all_null_checks_found; coleenp@548: all_null_checks_found++; coleenp@548: if( b->_test._test == BoolTest::ne ) { coleenp@548: _null_check_tests.push(proj); coleenp@548: _null_check_tests.push(cmp->in(1)); coleenp@548: } coleenp@548: } else { coleenp@548: assert( proj->Opcode() == Op_IfFalse, "" ); coleenp@548: if( b->_test._test == BoolTest::eq ) { coleenp@548: _null_check_tests.push(proj); coleenp@548: _null_check_tests.push(cmp->in(1)); duke@435: } duke@435: } duke@435: } duke@435: } duke@435: } duke@435: duke@435: //---------------------------validate_null_checks------------------------------ duke@435: // Its possible that the value being NULL checked is not the root of a match duke@435: // tree. If so, I cannot use the value in an implicit null check. duke@435: void Matcher::validate_null_checks( ) { duke@435: uint cnt = _null_check_tests.size(); duke@435: for( uint i=0; i < cnt; i+=2 ) { duke@435: Node *test = _null_check_tests[i]; duke@435: Node *val = _null_check_tests[i+1]; duke@435: if (has_new_node(val)) { duke@435: // Is a match-tree root, so replace with the matched value duke@435: _null_check_tests.map(i+1, new_node(val)); duke@435: } else { duke@435: // Yank from candidate list duke@435: _null_check_tests.map(i+1,_null_check_tests[--cnt]); duke@435: _null_check_tests.map(i,_null_check_tests[--cnt]); duke@435: _null_check_tests.pop(); duke@435: _null_check_tests.pop(); duke@435: i-=2; duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock duke@435: // acting as an Acquire and thus we don't need an Acquire here. We duke@435: // retain the Node to act as a compiler ordering barrier. duke@435: bool Matcher::prior_fast_lock( const Node *acq ) { duke@435: Node *r = acq->in(0); duke@435: if( !r->is_Region() || r->req() <= 1 ) return false; duke@435: Node *proj = r->in(1); duke@435: if( !proj->is_Proj() ) return false; duke@435: Node *call = proj->in(0); duke@435: if( !call->is_Call() || call->as_Call()->entry_point() != OptoRuntime::complete_monitor_locking_Java() ) duke@435: return false; duke@435: duke@435: return true; duke@435: } duke@435: duke@435: // Used by the DFA in dfa_sparc.cpp. Check for a following FastUnLock duke@435: // acting as a Release and thus we don't need a Release here. We duke@435: // retain the Node to act as a compiler ordering barrier. duke@435: bool Matcher::post_fast_unlock( const Node *rel ) { duke@435: Compile *C = Compile::current(); duke@435: assert( rel->Opcode() == Op_MemBarRelease, "" ); duke@435: const MemBarReleaseNode *mem = (const MemBarReleaseNode*)rel; duke@435: DUIterator_Fast imax, i = mem->fast_outs(imax); duke@435: Node *ctrl = NULL; duke@435: while( true ) { duke@435: ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found duke@435: assert( ctrl->is_Proj(), "only projections here" ); duke@435: ProjNode *proj = (ProjNode*)ctrl; duke@435: if( proj->_con == TypeFunc::Control && duke@435: !C->node_arena()->contains(ctrl) ) // Unmatched old-space only duke@435: break; duke@435: i++; duke@435: } duke@435: Node *iff = NULL; duke@435: for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) { duke@435: Node *x = ctrl->fast_out(j); duke@435: if( x->is_If() && x->req() > 1 && duke@435: !C->node_arena()->contains(x) ) { // Unmatched old-space only duke@435: iff = x; duke@435: break; duke@435: } duke@435: } duke@435: if( !iff ) return false; duke@435: Node *bol = iff->in(1); duke@435: // The iff might be some random subclass of If or bol might be Con-Top duke@435: if (!bol->is_Bool()) return false; duke@435: assert( bol->req() > 1, "" ); duke@435: return (bol->in(1)->Opcode() == Op_FastUnlock); duke@435: } duke@435: duke@435: // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or duke@435: // atomic instruction acting as a store_load barrier without any duke@435: // intervening volatile load, and thus we don't need a barrier here. duke@435: // We retain the Node to act as a compiler ordering barrier. duke@435: bool Matcher::post_store_load_barrier(const Node *vmb) { duke@435: Compile *C = Compile::current(); duke@435: assert( vmb->is_MemBar(), "" ); duke@435: assert( vmb->Opcode() != Op_MemBarAcquire, "" ); duke@435: const MemBarNode *mem = (const MemBarNode*)vmb; duke@435: duke@435: // Get the Proj node, ctrl, that can be used to iterate forward duke@435: Node *ctrl = NULL; duke@435: DUIterator_Fast imax, i = mem->fast_outs(imax); duke@435: while( true ) { duke@435: ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found duke@435: assert( ctrl->is_Proj(), "only projections here" ); duke@435: ProjNode *proj = (ProjNode*)ctrl; duke@435: if( proj->_con == TypeFunc::Control && duke@435: !C->node_arena()->contains(ctrl) ) // Unmatched old-space only duke@435: break; duke@435: i++; duke@435: } duke@435: duke@435: for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) { duke@435: Node *x = ctrl->fast_out(j); duke@435: int xop = x->Opcode(); duke@435: duke@435: // We don't need current barrier if we see another or a lock duke@435: // before seeing volatile load. duke@435: // duke@435: // Op_Fastunlock previously appeared in the Op_* list below. duke@435: // With the advent of 1-0 lock operations we're no longer guaranteed duke@435: // that a monitor exit operation contains a serializing instruction. duke@435: duke@435: if (xop == Op_MemBarVolatile || duke@435: xop == Op_FastLock || duke@435: xop == Op_CompareAndSwapL || duke@435: xop == Op_CompareAndSwapP || coleenp@548: xop == Op_CompareAndSwapN || duke@435: xop == Op_CompareAndSwapI) duke@435: return true; duke@435: duke@435: if (x->is_MemBar()) { duke@435: // We must retain this membar if there is an upcoming volatile duke@435: // load, which will be preceded by acquire membar. duke@435: if (xop == Op_MemBarAcquire) duke@435: return false; duke@435: // For other kinds of barriers, check by pretending we duke@435: // are them, and seeing if we can be removed. duke@435: else duke@435: return post_store_load_barrier((const MemBarNode*)x); duke@435: } duke@435: duke@435: // Delicate code to detect case of an upcoming fastlock block duke@435: if( x->is_If() && x->req() > 1 && duke@435: !C->node_arena()->contains(x) ) { // Unmatched old-space only duke@435: Node *iff = x; duke@435: Node *bol = iff->in(1); duke@435: // The iff might be some random subclass of If or bol might be Con-Top duke@435: if (!bol->is_Bool()) return false; duke@435: assert( bol->req() > 1, "" ); duke@435: return (bol->in(1)->Opcode() == Op_FastUnlock); duke@435: } duke@435: // probably not necessary to check for these duke@435: if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) duke@435: return false; duke@435: } duke@435: return false; duke@435: } duke@435: duke@435: //============================================================================= duke@435: //---------------------------State--------------------------------------------- duke@435: State::State(void) { duke@435: #ifdef ASSERT duke@435: _id = 0; duke@435: _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); duke@435: _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); duke@435: //memset(_cost, -1, sizeof(_cost)); duke@435: //memset(_rule, -1, sizeof(_rule)); duke@435: #endif duke@435: memset(_valid, 0, sizeof(_valid)); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: State::~State() { duke@435: _id = 99; duke@435: _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); duke@435: _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); duke@435: memset(_cost, -3, sizeof(_cost)); duke@435: memset(_rule, -3, sizeof(_rule)); duke@435: } duke@435: #endif duke@435: duke@435: #ifndef PRODUCT duke@435: //---------------------------dump---------------------------------------------- duke@435: void State::dump() { duke@435: tty->print("\n"); duke@435: dump(0); duke@435: } duke@435: duke@435: void State::dump(int depth) { duke@435: for( int j = 0; j < depth; j++ ) duke@435: tty->print(" "); duke@435: tty->print("--N: "); duke@435: _leaf->dump(); duke@435: uint i; duke@435: for( i = 0; i < _LAST_MACH_OPER; i++ ) duke@435: // Check for valid entry duke@435: if( valid(i) ) { duke@435: for( int j = 0; j < depth; j++ ) duke@435: tty->print(" "); duke@435: assert(_cost[i] != max_juint, "cost must be a valid value"); duke@435: assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); duke@435: tty->print_cr("%s %d %s", duke@435: ruleName[i], _cost[i], ruleName[_rule[i]] ); duke@435: } duke@435: tty->print_cr(""); duke@435: duke@435: for( i=0; i<2; i++ ) duke@435: if( _kids[i] ) duke@435: _kids[i]->dump(depth+1); duke@435: } duke@435: #endif