duke@435: /* xdono@631: * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: class Compile; duke@435: class Node; duke@435: class MachNode; duke@435: class MachTypeNode; duke@435: class MachOper; duke@435: duke@435: //---------------------------Matcher------------------------------------------- duke@435: class Matcher : public PhaseTransform { duke@435: friend class VMStructs; duke@435: // Private arena of State objects duke@435: ResourceArea _states_arena; duke@435: duke@435: VectorSet _visited; // Visit bits duke@435: duke@435: // Used to control the Label pass duke@435: VectorSet _shared; // Shared Ideal Node duke@435: VectorSet _dontcare; // Nothing the matcher cares about duke@435: duke@435: // Private methods which perform the actual matching and reduction duke@435: // Walks the label tree, generating machine nodes duke@435: MachNode *ReduceInst( State *s, int rule, Node *&mem); duke@435: void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); duke@435: uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); duke@435: void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); duke@435: duke@435: // If this node already matched using "rule", return the MachNode for it. kvn@603: MachNode* find_shared_node(Node* n, uint rule); duke@435: duke@435: // Convert a dense opcode number to an expanded rule number duke@435: const int *_reduceOp; duke@435: const int *_leftOp; duke@435: const int *_rightOp; duke@435: duke@435: // Map dense opcode number to info on when rule is swallowed constant. duke@435: const bool *_swallowed; duke@435: duke@435: // Map dense rule number to determine if this is an instruction chain rule duke@435: const uint _begin_inst_chain_rule; duke@435: const uint _end_inst_chain_rule; duke@435: duke@435: // We want to clone constants and possible CmpI-variants. duke@435: // If we do not clone CmpI, then we can have many instances of duke@435: // condition codes alive at once. This is OK on some chips and duke@435: // bad on others. Hence the machine-dependent table lookup. duke@435: const char *_must_clone; duke@435: duke@435: // Find shared Nodes, or Nodes that otherwise are Matcher roots duke@435: void find_shared( Node *n ); duke@435: duke@435: // Debug and profile information for nodes in old space: duke@435: GrowableArray* _old_node_note_array; duke@435: duke@435: // Node labeling iterator for instruction selection duke@435: Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); duke@435: duke@435: Node *transform( Node *dummy ); duke@435: duke@435: Node_List &_proj_list; // For Machine nodes killing many values duke@435: kvn@603: Node_Array _shared_nodes; duke@435: duke@435: debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots never@657: debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal duke@435: duke@435: // Accessors for the inherited field PhaseTransform::_nodes: duke@435: void grow_new_node_array(uint idx_limit) { duke@435: _nodes.map(idx_limit-1, NULL); duke@435: } duke@435: bool has_new_node(const Node* n) const { duke@435: return _nodes.at(n->_idx) != NULL; duke@435: } duke@435: Node* new_node(const Node* n) const { duke@435: assert(has_new_node(n), "set before get"); duke@435: return _nodes.at(n->_idx); duke@435: } duke@435: void set_new_node(const Node* n, Node *nn) { duke@435: assert(!has_new_node(n), "set only once"); duke@435: _nodes.map(n->_idx, nn); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: // Make sure only new nodes are reachable from this node duke@435: void verify_new_nodes_only(Node* root); kvn@651: kvn@651: Node* _mem_node; // Ideal memory node consumed by mach node duke@435: #endif duke@435: duke@435: public: duke@435: int LabelRootDepth; duke@435: static const int base2reg[]; // Map Types to machine register types duke@435: // Convert ideal machine register to a register mask for spill-loads duke@435: static const RegMask *idealreg2regmask[]; duke@435: RegMask *idealreg2spillmask[_last_machine_leaf]; duke@435: RegMask *idealreg2debugmask[_last_machine_leaf]; duke@435: void init_spill_mask( Node *ret ); duke@435: // Convert machine register number to register mask duke@435: static uint mreg2regmask_max; duke@435: static RegMask mreg2regmask[]; duke@435: static RegMask STACK_ONLY_mask; duke@435: duke@435: bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } duke@435: void set_shared( Node *n ) { _shared.set(n->_idx); } duke@435: bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } duke@435: void set_visited( Node *n ) { _visited.set(n->_idx); } duke@435: bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } duke@435: void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } duke@435: duke@435: // Mode bit to tell DFA and expand rules whether we are running after duke@435: // (or during) register selection. Usually, the matcher runs before, duke@435: // but it will also get called to generate post-allocation spill code. duke@435: // In this situation, it is a deadly error to attempt to allocate more duke@435: // temporary registers. duke@435: bool _allocation_started; duke@435: duke@435: // Machine register names duke@435: static const char *regName[]; duke@435: // Machine register encodings duke@435: static const unsigned char _regEncode[]; duke@435: // Machine Node names duke@435: const char **_ruleName; duke@435: // Rules that are cheaper to rematerialize than to spill duke@435: static const uint _begin_rematerialize; duke@435: static const uint _end_rematerialize; duke@435: duke@435: // An array of chars, from 0 to _last_Mach_Reg. duke@435: // No Save = 'N' (for register windows) duke@435: // Save on Entry = 'E' duke@435: // Save on Call = 'C' duke@435: // Always Save = 'A' (same as SOE + SOC) duke@435: const char *_register_save_policy; duke@435: const char *_c_reg_save_policy; duke@435: // Convert a machine register to a machine register type, so-as to duke@435: // properly match spill code. duke@435: const int *_register_save_type; duke@435: // Maps from machine register to boolean; true if machine register can duke@435: // be holding a call argument in some signature. duke@435: static bool can_be_java_arg( int reg ); duke@435: // Maps from machine register to boolean; true if machine register holds duke@435: // a spillable argument. duke@435: static bool is_spillable_arg( int reg ); duke@435: duke@435: // List of IfFalse or IfTrue Nodes that indicate a taken null test. duke@435: // List is valid in the post-matching space. duke@435: Node_List _null_check_tests; kvn@803: void collect_null_checks( Node *proj, Node *orig_proj ); duke@435: void validate_null_checks( ); duke@435: duke@435: Matcher( Node_List &proj_list ); duke@435: duke@435: // Select instructions for entire method duke@435: void match( ); duke@435: // Helper for match duke@435: OptoReg::Name warp_incoming_stk_arg( VMReg reg ); duke@435: duke@435: // Transform, then walk. Does implicit DCE while walking. duke@435: // Name changed from "transform" to avoid it being virtual. duke@435: Node *xform( Node *old_space_node, int Nodes ); duke@435: duke@435: // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. duke@435: MachNode *match_tree( const Node *n ); duke@435: MachNode *match_sfpt( SafePointNode *sfpt ); duke@435: // Helper for match_sfpt duke@435: OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); duke@435: duke@435: // Initialize first stack mask and related masks. duke@435: void init_first_stack_mask(); duke@435: duke@435: // If we should save-on-entry this register duke@435: bool is_save_on_entry( int reg ); duke@435: duke@435: // Fixup the save-on-entry registers duke@435: void Fixup_Save_On_Entry( ); duke@435: duke@435: // --- Frame handling --- duke@435: duke@435: // Register number of the stack slot corresponding to the incoming SP. duke@435: // Per the Big Picture in the AD file, it is: duke@435: // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. duke@435: OptoReg::Name _old_SP; duke@435: duke@435: // Register number of the stack slot corresponding to the highest incoming duke@435: // argument on the stack. Per the Big Picture in the AD file, it is: duke@435: // _old_SP + out_preserve_stack_slots + incoming argument size. duke@435: OptoReg::Name _in_arg_limit; duke@435: duke@435: // Register number of the stack slot corresponding to the new SP. duke@435: // Per the Big Picture in the AD file, it is: duke@435: // _in_arg_limit + pad0 duke@435: OptoReg::Name _new_SP; duke@435: duke@435: // Register number of the stack slot corresponding to the highest outgoing duke@435: // argument on the stack. Per the Big Picture in the AD file, it is: duke@435: // _new_SP + max outgoing arguments of all calls duke@435: OptoReg::Name _out_arg_limit; duke@435: duke@435: OptoRegPair *_parm_regs; // Array of machine registers per argument duke@435: RegMask *_calling_convention_mask; // Array of RegMasks per argument duke@435: duke@435: // Does matcher support this ideal node? duke@435: static const bool has_match_rule(int opcode); duke@435: static const bool _hasMatchRule[_last_opcode]; duke@435: duke@435: // Used to determine if we have fast l2f conversion duke@435: // USII has it, USIII doesn't duke@435: static const bool convL2FSupported(void); duke@435: duke@435: // Vector width in bytes duke@435: static const uint vector_width_in_bytes(void); duke@435: duke@435: // Vector ideal reg duke@435: static const uint vector_ideal_reg(void); duke@435: duke@435: // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) duke@435: // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). duke@435: // Depends on the details of 64-bit constant generation on the CPU. duke@435: static const bool isSimpleConstant64(jlong con); duke@435: duke@435: // These calls are all generated by the ADLC duke@435: duke@435: // TRUE - grows up, FALSE - grows down (Intel) duke@435: virtual bool stack_direction() const; duke@435: duke@435: // Java-Java calling convention duke@435: // (what you use when Java calls Java) duke@435: duke@435: // Alignment of stack in bytes, standard Intel word alignment is 4. duke@435: // Sparc probably wants at least double-word (8). duke@435: static uint stack_alignment_in_bytes(); duke@435: // Alignment of stack, measured in stack slots. duke@435: // The size of stack slots is defined by VMRegImpl::stack_slot_size. duke@435: static uint stack_alignment_in_slots() { duke@435: return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); duke@435: } duke@435: duke@435: // Array mapping arguments to registers. Argument 0 is usually the 'this' duke@435: // pointer. Registers can include stack-slots and regular registers. duke@435: static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); duke@435: duke@435: // Convert a sig into a calling convention register layout duke@435: // and find interesting things about it. duke@435: static OptoReg::Name find_receiver( bool is_outgoing ); duke@435: // Return address register. On Intel it is a stack-slot. On PowerPC duke@435: // it is the Link register. On Sparc it is r31? duke@435: virtual OptoReg::Name return_addr() const; duke@435: RegMask _return_addr_mask; duke@435: // Return value register. On Intel it is EAX. On Sparc i0/o0. duke@435: static OptoRegPair return_value(int ideal_reg, bool is_outgoing); duke@435: static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); duke@435: RegMask _return_value_mask; duke@435: // Inline Cache Register duke@435: static OptoReg::Name inline_cache_reg(); duke@435: static const RegMask &inline_cache_reg_mask(); duke@435: static int inline_cache_reg_encode(); duke@435: duke@435: // Register for DIVI projection of divmodI duke@435: static RegMask divI_proj_mask(); duke@435: // Register for MODI projection of divmodI duke@435: static RegMask modI_proj_mask(); duke@435: duke@435: // Register for DIVL projection of divmodL duke@435: static RegMask divL_proj_mask(); duke@435: // Register for MODL projection of divmodL duke@435: static RegMask modL_proj_mask(); duke@435: duke@435: // Java-Interpreter calling convention duke@435: // (what you use when calling between compiled-Java and Interpreted-Java duke@435: duke@435: // Number of callee-save + always-save registers duke@435: // Ignores frame pointer and "special" registers duke@435: static int number_of_saved_registers(); duke@435: duke@435: // The Method-klass-holder may be passed in the inline_cache_reg duke@435: // and then expanded into the inline_cache_reg and a method_oop register duke@435: duke@435: static OptoReg::Name interpreter_method_oop_reg(); duke@435: static const RegMask &interpreter_method_oop_reg_mask(); duke@435: static int interpreter_method_oop_reg_encode(); duke@435: duke@435: static OptoReg::Name compiler_method_oop_reg(); duke@435: static const RegMask &compiler_method_oop_reg_mask(); duke@435: static int compiler_method_oop_reg_encode(); duke@435: duke@435: // Interpreter's Frame Pointer Register duke@435: static OptoReg::Name interpreter_frame_pointer_reg(); duke@435: static const RegMask &interpreter_frame_pointer_reg_mask(); duke@435: duke@435: // Java-Native calling convention duke@435: // (what you use when intercalling between Java and C++ code) duke@435: duke@435: // Array mapping arguments to registers. Argument 0 is usually the 'this' duke@435: // pointer. Registers can include stack-slots and regular registers. duke@435: static void c_calling_convention( BasicType*, VMRegPair *, uint ); duke@435: // Frame pointer. The frame pointer is kept at the base of the stack duke@435: // and so is probably the stack pointer for most machines. On Intel duke@435: // it is ESP. On the PowerPC it is R1. On Sparc it is SP. duke@435: OptoReg::Name c_frame_pointer() const; duke@435: static RegMask c_frame_ptr_mask; duke@435: duke@435: // !!!!! Special stuff for building ScopeDescs duke@435: virtual int regnum_to_fpu_offset(int regnum); duke@435: duke@435: // Is this branch offset small enough to be addressed by a short branch? never@850: bool is_short_branch_offset(int rule, int offset); duke@435: duke@435: // Optional scaling for the parameter to the ClearArray/CopyArray node. duke@435: static const bool init_array_count_is_in_bytes; duke@435: duke@435: // Threshold small size (in bytes) for a ClearArray/CopyArray node. duke@435: // Anything this size or smaller may get converted to discrete scalar stores. duke@435: static const int init_array_short_size; duke@435: duke@435: // Should the Matcher clone shifts on addressing modes, expecting them to duke@435: // be subsumed into complex addressing expressions or compute them into duke@435: // registers? True for Intel but false for most RISCs duke@435: static const bool clone_shift_expressions; duke@435: duke@435: // Is it better to copy float constants, or load them directly from memory? duke@435: // Intel can load a float constant from a direct address, requiring no duke@435: // extra registers. Most RISCs will have to materialize an address into a duke@435: // register first, so they may as well materialize the constant immediately. duke@435: static const bool rematerialize_float_constants; duke@435: duke@435: // If CPU can load and store mis-aligned doubles directly then no fixup is duke@435: // needed. Else we split the double into 2 integer pieces and move it duke@435: // piece-by-piece. Only happens when passing doubles into C code or when duke@435: // calling i2c adapters as the Java calling convention forces doubles to be duke@435: // aligned. duke@435: static const bool misaligned_doubles_ok; duke@435: duke@435: // Perform a platform dependent implicit null fixup. This is needed duke@435: // on windows95 to take care of some unusual register constraints. duke@435: void pd_implicit_null_fixup(MachNode *load, uint idx); duke@435: duke@435: // Advertise here if the CPU requires explicit rounding operations duke@435: // to implement the UseStrictFP mode. duke@435: static const bool strict_fp_requires_explicit_rounding; duke@435: duke@435: // Do floats take an entire double register or just half? duke@435: static const bool float_in_double; duke@435: // Do ints take an entire long register or just half? duke@435: static const bool int_in_long; duke@435: duke@435: // This routine is run whenever a graph fails to match. duke@435: // If it returns, the compiler should bailout to interpreter without error. duke@435: // In non-product mode, SoftMatchFailure is false to detect non-canonical duke@435: // graphs. Print a message and exit. duke@435: static void soft_match_failure() { duke@435: if( SoftMatchFailure ) return; duke@435: else { fatal("SoftMatchFailure is not allowed except in product"); } duke@435: } duke@435: duke@435: // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock duke@435: // acting as an Acquire and thus we don't need an Acquire here. We duke@435: // retain the Node to act as a compiler ordering barrier. duke@435: static bool prior_fast_lock( const Node *acq ); duke@435: duke@435: // Used by the DFA in dfa_sparc.cpp. Check for a following duke@435: // FastUnLock acting as a Release and thus we don't need a Release duke@435: // here. We retain the Node to act as a compiler ordering barrier. duke@435: static bool post_fast_unlock( const Node *rel ); duke@435: duke@435: // Check for a following volatile memory barrier without an duke@435: // intervening load and thus we don't need a barrier here. We duke@435: // retain the Node to act as a compiler ordering barrier. duke@435: static bool post_store_load_barrier(const Node* mb); duke@435: duke@435: duke@435: #ifdef ASSERT duke@435: void dump_old2new_map(); // machine-independent to machine-dependent never@657: never@657: Node* find_old_node(Node* new_node) { never@657: return _new2old_map[new_node->_idx]; never@657: } duke@435: #endif duke@435: };