duke@435: //
trims@1907: // Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved.
duke@435: // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435: //
duke@435: // This code is free software; you can redistribute it and/or modify it
duke@435: // under the terms of the GNU General Public License version 2 only, as
duke@435: // published by the Free Software Foundation.
duke@435: //
duke@435: // This code is distributed in the hope that it will be useful, but WITHOUT
duke@435: // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435: // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435: // version 2 for more details (a copy is included in the LICENSE file that
duke@435: // accompanied this code).
duke@435: //
duke@435: // You should have received a copy of the GNU General Public License version
duke@435: // 2 along with this work; if not, write to the Free Software Foundation,
duke@435: // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435: //
trims@1907: // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907: // or visit www.oracle.com if you need additional information or have any
trims@1907: // questions.
duke@435: //
duke@435: //
duke@435: 
duke@435: // AMD64 Linux Architecture Description File
duke@435: 
duke@435: //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
duke@435: // This block specifies the encoding classes used by the compiler to
duke@435: // output byte streams.  Encoding classes generate functions which are
duke@435: // called by Machine Instruction Nodes in order to generate the bit
duke@435: // encoding of the instruction.  Operands specify their base encoding
duke@435: // interface with the interface keyword.  There are currently
duke@435: // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@435: // COND_INTER.  REG_INTER causes an operand to generate a function
duke@435: // which returns its register number when queried.  CONST_INTER causes
duke@435: // an operand to generate a function which returns the value of the
duke@435: // constant when queried.  MEMORY_INTER causes an operand to generate
duke@435: // four functions which return the Base Register, the Index Register,
duke@435: // the Scale Value, and the Offset Value of the operand when queried.
duke@435: // COND_INTER causes an operand to generate six functions which return
duke@435: // the encoding code (ie - encoding bits for the instruction)
duke@435: // associated with each basic boolean condition for a conditional
duke@435: // instruction.  Instructions specify two basic values for encoding.
duke@435: // They use the ins_encode keyword to specify their encoding class
duke@435: // (which must be one of the class names specified in the encoding
duke@435: // block), and they use the opcode keyword to specify, in order, their
duke@435: // primary, secondary, and tertiary opcode.  Only the opcode sections
duke@435: // which a particular instruction needs for encoding need to be
duke@435: // specified.
duke@435: encode %{
duke@435:   // Build emit functions for each basic byte or larger field in the intel
duke@435:   // encoding scheme (opcode, rm, sib, immediate), and call them from C++
duke@435:   // code in the enc_class source block.  Emit functions will live in the
duke@435:   // main source block for now.  In future, we can generalize this by
duke@435:   // adding a syntax that specifies the sizes of fields in an order,
duke@435:   // so that the adlc can build the emit functions automagically
duke@435: 
duke@435:   enc_class Java_To_Runtime(method meth)
duke@435:   %{
duke@435:     // No relocation needed
duke@435: 
duke@435:     // movq r10, <meth>
duke@435:     emit_opcode(cbuf, Assembler::REX_WB);
duke@435:     emit_opcode(cbuf, 0xB8 | (R10_enc - 8));
duke@435:     emit_d64(cbuf, (int64_t) $meth$$method);
duke@435: 
duke@435:     // call (r10)
duke@435:     emit_opcode(cbuf, Assembler::REX_B);
duke@435:     emit_opcode(cbuf, 0xFF);
duke@435:     emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
duke@435:   %}
duke@435: 
duke@435:   enc_class linux_breakpoint
duke@435:   %{
duke@435:     MacroAssembler* masm = new MacroAssembler(&cbuf);
duke@435:     masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
duke@435:   %}
duke@435: 
duke@435:   enc_class call_epilog
duke@435:   %{
duke@435:     if (VerifyStackAtCalls) {
duke@435:       // Check that stack depth is unchanged: find majik cookie on stack
duke@435:       int framesize =
duke@435:         ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
duke@435:       if (framesize) {
duke@435:         if (framesize < 0x80) {
duke@435:           emit_opcode(cbuf, Assembler::REX_W);
duke@435:           emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
duke@435:           emit_d8(cbuf, 0x7C);
duke@435:           emit_d8(cbuf, 0x24);
duke@435:           emit_d8(cbuf, framesize); // Find majik cookie from ESP
duke@435:           emit_d32(cbuf, 0xbadb100d);
duke@435:         } else {
duke@435:           emit_opcode(cbuf, Assembler::REX_W);
duke@435:           emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
duke@435:           emit_d8(cbuf, 0xBC);
duke@435:           emit_d8(cbuf, 0x24);
duke@435:           emit_d32(cbuf, framesize); // Find majik cookie from ESP
duke@435:           emit_d32(cbuf, 0xbadb100d);
duke@435:         }
duke@435:       }
duke@435:       // jmp EQ around INT3
duke@435:       // QQQ TODO
duke@435:       const int jump_around = 5; // size of call to breakpoint, 1 for CC
duke@435:       emit_opcode(cbuf, 0x74);
duke@435:       emit_d8(cbuf, jump_around);
duke@435:       // QQQ temporary
duke@435:       emit_break(cbuf);
duke@435:       // Die if stack mismatch
duke@435:       // emit_opcode(cbuf,0xCC);
duke@435:     }
duke@435:   %}
duke@435: 
duke@435: %}
duke@435: 
duke@435: // INSTRUCTIONS -- Platform dependent
duke@435: 
duke@435: //----------OS and Locking Instructions----------------------------------------
duke@435: 
duke@435: // This name is KNOWN by the ADLC and cannot be changed.
duke@435: // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
duke@435: // for this guy.
duke@435: instruct tlsLoadP(r15_RegP dst)
duke@435: %{
duke@435:   match(Set dst (ThreadLocal));
duke@435:   effect(DEF dst);
duke@435: 
duke@435:   size(0);
duke@435:   format %{ "# TLS is in R15" %}
duke@435:   ins_encode( /*empty encoding*/ );
duke@435:   ins_pipe(ialu_reg_reg);
duke@435: %}
duke@435: 
duke@435: // Die now
duke@435: instruct ShouldNotReachHere()
duke@435: %{
duke@435:   match(Halt);
duke@435: 
duke@435:   // Use the following format syntax
duke@435:   format %{ "int3\t# ShouldNotReachHere" %}
duke@435:   // QQQ TODO for now call breakpoint
duke@435:   // opcode(0xCC);
duke@435:   // ins_encode(Opc);
duke@435:   ins_encode(linux_breakpoint);
duke@435:   ins_pipe(pipe_slow);
duke@435: %}
duke@435: 
duke@435: 
duke@435: // Platform dependent source
duke@435: 
duke@435: source
duke@435: %{
duke@435: 
duke@435: int MachCallRuntimeNode::ret_addr_offset() {
duke@435:   return 13; // movq r10,#addr; callq (r10)
duke@435: }
duke@435: 
duke@435: // emit an interrupt that is caught by the debugger
duke@435: void emit_break(CodeBuffer& cbuf) {
duke@435:   // Debugger doesn't really catch this but best we can do so far QQQ
duke@435:   MacroAssembler* masm = new MacroAssembler(&cbuf);
duke@435:   masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
duke@435: }
duke@435: 
duke@435: void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
duke@435:   emit_break(cbuf);
duke@435: }
duke@435: 
duke@435: uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
kvn@3049:   // distance could be far and requires load and call through register
kvn@3049:   return MachNode::size(ra_);
duke@435: }
duke@435: 
duke@435: %}