aoqi@0: /* mchinnathamb@9290: * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@0: #include "precompiled.hpp" aoqi@0: #include "asm/assembler.hpp" aoqi@0: #include "c1/c1_Defs.hpp" aoqi@0: #include "c1/c1_MacroAssembler.hpp" aoqi@0: #include "c1/c1_Runtime1.hpp" aoqi@0: #include "interpreter/interpreter.hpp" aoqi@0: #include "nativeInst_x86.hpp" aoqi@0: #include "oops/compiledICHolder.hpp" aoqi@0: #include "oops/oop.inline.hpp" aoqi@0: #include "prims/jvmtiExport.hpp" aoqi@0: #include "register_x86.hpp" aoqi@0: #include "runtime/sharedRuntime.hpp" aoqi@0: #include "runtime/signature.hpp" aoqi@0: #include "runtime/vframeArray.hpp" aoqi@0: #include "utilities/macros.hpp" aoqi@0: #include "vmreg_x86.inline.hpp" aoqi@0: #if INCLUDE_ALL_GCS aoqi@0: #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: // Implementation of StubAssembler aoqi@0: aoqi@0: int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) { aoqi@0: // setup registers aoqi@0: const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions) aoqi@0: assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different"); aoqi@0: assert(oop_result1 != thread && metadata_result != thread, "registers must be different"); aoqi@0: assert(args_size >= 0, "illegal args_size"); aoqi@0: bool align_stack = false; aoqi@0: #ifdef _LP64 aoqi@0: // At a method handle call, the stack may not be properly aligned aoqi@0: // when returning with an exception. aoqi@0: align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id); aoqi@0: #endif aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: mov(c_rarg0, thread); aoqi@0: set_num_rt_args(0); // Nothing on stack aoqi@0: #else aoqi@0: set_num_rt_args(1 + args_size); aoqi@0: aoqi@0: // push java thread (becomes first argument of C function) aoqi@0: get_thread(thread); aoqi@0: push(thread); aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: int call_offset; aoqi@0: if (!align_stack) { aoqi@0: set_last_Java_frame(thread, noreg, rbp, NULL); aoqi@0: } else { aoqi@0: address the_pc = pc(); aoqi@0: call_offset = offset(); aoqi@0: set_last_Java_frame(thread, noreg, rbp, the_pc); aoqi@0: andptr(rsp, -(StackAlignmentInBytes)); // Align stack aoqi@0: } aoqi@0: aoqi@0: // do the call aoqi@0: call(RuntimeAddress(entry)); aoqi@0: if (!align_stack) { aoqi@0: call_offset = offset(); aoqi@0: } aoqi@0: // verify callee-saved register aoqi@0: #ifdef ASSERT aoqi@0: guarantee(thread != rax, "change this code"); aoqi@0: push(rax); aoqi@0: { Label L; aoqi@0: get_thread(rax); aoqi@0: cmpptr(thread, rax); aoqi@0: jcc(Assembler::equal, L); aoqi@0: int3(); aoqi@0: stop("StubAssembler::call_RT: rdi not callee saved?"); aoqi@0: bind(L); aoqi@0: } aoqi@0: pop(rax); aoqi@0: #endif kevinw@8877: reset_last_Java_frame(thread, true); aoqi@0: aoqi@0: // discard thread and arguments aoqi@0: NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord)); aoqi@0: aoqi@0: // check for pending exceptions aoqi@0: { Label L; aoqi@0: cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); aoqi@0: jcc(Assembler::equal, L); aoqi@0: // exception pending => remove activation and forward to exception handler aoqi@0: movptr(rax, Address(thread, Thread::pending_exception_offset())); aoqi@0: // make sure that the vm_results are cleared aoqi@0: if (oop_result1->is_valid()) { aoqi@0: movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); aoqi@0: } aoqi@0: if (metadata_result->is_valid()) { aoqi@0: movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); aoqi@0: } aoqi@0: if (frame_size() == no_frame_size) { aoqi@0: leave(); aoqi@0: jump(RuntimeAddress(StubRoutines::forward_exception_entry())); aoqi@0: } else if (_stub_id == Runtime1::forward_exception_id) { aoqi@0: should_not_reach_here(); aoqi@0: } else { aoqi@0: jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); aoqi@0: } aoqi@0: bind(L); aoqi@0: } aoqi@0: // get oop results if there are any and reset the values in the thread aoqi@0: if (oop_result1->is_valid()) { aoqi@0: get_vm_result(oop_result1, thread); aoqi@0: } aoqi@0: if (metadata_result->is_valid()) { aoqi@0: get_vm_result_2(metadata_result, thread); aoqi@0: } aoqi@0: return call_offset; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) { aoqi@0: #ifdef _LP64 aoqi@0: mov(c_rarg1, arg1); aoqi@0: #else aoqi@0: push(arg1); aoqi@0: #endif // _LP64 aoqi@0: return call_RT(oop_result1, metadata_result, entry, 1); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) { aoqi@0: #ifdef _LP64 aoqi@0: if (c_rarg1 == arg2) { aoqi@0: if (c_rarg2 == arg1) { aoqi@0: xchgq(arg1, arg2); aoqi@0: } else { aoqi@0: mov(c_rarg2, arg2); aoqi@0: mov(c_rarg1, arg1); aoqi@0: } aoqi@0: } else { aoqi@0: mov(c_rarg1, arg1); aoqi@0: mov(c_rarg2, arg2); aoqi@0: } aoqi@0: #else aoqi@0: push(arg2); aoqi@0: push(arg1); aoqi@0: #endif // _LP64 aoqi@0: return call_RT(oop_result1, metadata_result, entry, 2); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) { aoqi@0: #ifdef _LP64 aoqi@0: // if there is any conflict use the stack aoqi@0: if (arg1 == c_rarg2 || arg1 == c_rarg3 || aoqi@0: arg2 == c_rarg1 || arg1 == c_rarg3 || aoqi@0: arg3 == c_rarg1 || arg1 == c_rarg2) { aoqi@0: push(arg3); aoqi@0: push(arg2); aoqi@0: push(arg1); aoqi@0: pop(c_rarg1); aoqi@0: pop(c_rarg2); aoqi@0: pop(c_rarg3); aoqi@0: } else { aoqi@0: mov(c_rarg1, arg1); aoqi@0: mov(c_rarg2, arg2); aoqi@0: mov(c_rarg3, arg3); aoqi@0: } aoqi@0: #else aoqi@0: push(arg3); aoqi@0: push(arg2); aoqi@0: push(arg1); aoqi@0: #endif // _LP64 aoqi@0: return call_RT(oop_result1, metadata_result, entry, 3); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Implementation of StubFrame aoqi@0: aoqi@0: class StubFrame: public StackObj { aoqi@0: private: aoqi@0: StubAssembler* _sasm; aoqi@0: aoqi@0: public: aoqi@0: StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments); aoqi@0: void load_argument(int offset_in_words, Register reg); aoqi@0: aoqi@0: ~StubFrame(); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: #define __ _sasm-> aoqi@0: aoqi@0: StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) { aoqi@0: _sasm = sasm; aoqi@0: __ set_info(name, must_gc_arguments); aoqi@0: __ enter(); aoqi@0: } aoqi@0: aoqi@0: // load parameters that were stored with LIR_Assembler::store_parameter aoqi@0: // Note: offsets for store_parameter and load_argument must match aoqi@0: void StubFrame::load_argument(int offset_in_words, Register reg) { aoqi@0: // rbp, + 0: link aoqi@0: // + 1: return address aoqi@0: // + 2: argument with offset 0 aoqi@0: // + 3: argument with offset 1 aoqi@0: // + 4: ... aoqi@0: aoqi@0: __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord)); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: StubFrame::~StubFrame() { aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: aoqi@0: #undef __ aoqi@0: aoqi@0: aoqi@0: // Implementation of Runtime1 aoqi@0: aoqi@0: #define __ sasm-> aoqi@0: aoqi@0: const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2; aoqi@0: const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2; aoqi@0: aoqi@0: // Stack layout for saving/restoring all the registers needed during a runtime aoqi@0: // call (this includes deoptimization) aoqi@0: // Note: note that users of this frame may well have arguments to some runtime aoqi@0: // while these values are on the stack. These positions neglect those arguments aoqi@0: // but the code in save_live_registers will take the argument count into aoqi@0: // account. aoqi@0: // aoqi@0: #ifdef _LP64 aoqi@0: #define SLOT2(x) x, aoqi@0: #define SLOT_PER_WORD 2 aoqi@0: #else aoqi@0: #define SLOT2(x) aoqi@0: #define SLOT_PER_WORD 1 aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: enum reg_save_layout { aoqi@0: // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that aoqi@0: // happen and will assert if the stack size we create is misaligned aoqi@0: #ifdef _LP64 aoqi@0: align_dummy_0, align_dummy_1, aoqi@0: #endif // _LP64 aoqi@0: #ifdef _WIN64 aoqi@0: // Windows always allocates space for it's argument registers (see aoqi@0: // frame::arg_reg_save_area_bytes). aoqi@0: arg_reg_save_1, arg_reg_save_1H, // 0, 4 aoqi@0: arg_reg_save_2, arg_reg_save_2H, // 8, 12 aoqi@0: arg_reg_save_3, arg_reg_save_3H, // 16, 20 aoqi@0: arg_reg_save_4, arg_reg_save_4H, // 24, 28 aoqi@0: #endif // _WIN64 aoqi@0: xmm_regs_as_doubles_off, // 32 aoqi@0: float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160 aoqi@0: fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224 aoqi@0: // fpu_state_end_off is exclusive aoqi@0: fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352 aoqi@0: marker = fpu_state_end_off, SLOT2(markerH) // 352, 356 aoqi@0: extra_space_offset, // 360 aoqi@0: #ifdef _LP64 aoqi@0: r15_off = extra_space_offset, r15H_off, // 360, 364 aoqi@0: r14_off, r14H_off, // 368, 372 aoqi@0: r13_off, r13H_off, // 376, 380 aoqi@0: r12_off, r12H_off, // 384, 388 aoqi@0: r11_off, r11H_off, // 392, 396 aoqi@0: r10_off, r10H_off, // 400, 404 aoqi@0: r9_off, r9H_off, // 408, 412 aoqi@0: r8_off, r8H_off, // 416, 420 aoqi@0: rdi_off, rdiH_off, // 424, 428 aoqi@0: #else aoqi@0: rdi_off = extra_space_offset, aoqi@0: #endif // _LP64 aoqi@0: rsi_off, SLOT2(rsiH_off) // 432, 436 aoqi@0: rbp_off, SLOT2(rbpH_off) // 440, 444 aoqi@0: rsp_off, SLOT2(rspH_off) // 448, 452 aoqi@0: rbx_off, SLOT2(rbxH_off) // 456, 460 aoqi@0: rdx_off, SLOT2(rdxH_off) // 464, 468 aoqi@0: rcx_off, SLOT2(rcxH_off) // 472, 476 aoqi@0: rax_off, SLOT2(raxH_off) // 480, 484 aoqi@0: saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492 aoqi@0: return_off, SLOT2(returnH_off) // 496, 500 aoqi@0: reg_save_frame_size // As noted: neglects any parameters to runtime // 504 aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: aoqi@0: // Save off registers which might be killed by calls into the runtime. aoqi@0: // Tries to smart of about FP registers. In particular we separate aoqi@0: // saving and describing the FPU registers for deoptimization since we aoqi@0: // have to save the FPU registers twice if we describe them and on P4 aoqi@0: // saving FPU registers which don't contain anything appears aoqi@0: // expensive. The deopt blob is the only thing which needs to aoqi@0: // describe FPU registers. In all other cases it should be sufficient aoqi@0: // to simply save their current value. aoqi@0: aoqi@0: static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args, aoqi@0: bool save_fpu_registers = true) { aoqi@0: aoqi@0: // In 64bit all the args are in regs so there are no additional stack slots aoqi@0: LP64_ONLY(num_rt_args = 0); aoqi@0: LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");) aoqi@0: int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread aoqi@0: sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word ); aoqi@0: aoqi@0: // record saved value locations in an OopMap aoqi@0: // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread aoqi@0: OopMap* map = new OopMap(frame_size_in_slots, 0); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg()); aoqi@0: #ifdef _LP64 aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg()); aoqi@0: aoqi@0: // This is stupid but needed. aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next()); aoqi@0: aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next()); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next()); aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: if (save_fpu_registers) { aoqi@0: if (UseSSE < 2) { aoqi@0: int fpu_off = float_regs_as_doubles_off; aoqi@0: for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { aoqi@0: VMReg fpu_name_0 = FrameMap::fpu_regname(n); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0); aoqi@0: // %%% This is really a waste but we'll keep things as they were for now aoqi@0: if (true) { aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next()); aoqi@0: } aoqi@0: fpu_off += 2; aoqi@0: } aoqi@0: assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots"); aoqi@0: } aoqi@0: aoqi@0: if (UseSSE >= 2) { aoqi@0: int xmm_off = xmm_regs_as_doubles_off; aoqi@0: for (int n = 0; n < FrameMap::nof_xmm_regs; n++) { aoqi@0: VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); aoqi@0: // %%% This is really a waste but we'll keep things as they were for now aoqi@0: if (true) { aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next()); aoqi@0: } aoqi@0: xmm_off += 2; aoqi@0: } aoqi@0: assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); aoqi@0: aoqi@0: } else if (UseSSE == 1) { aoqi@0: int xmm_off = xmm_regs_as_doubles_off; aoqi@0: for (int n = 0; n < FrameMap::nof_xmm_regs; n++) { aoqi@0: VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); aoqi@0: map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); aoqi@0: xmm_off += 2; aoqi@0: } aoqi@0: assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: return map; aoqi@0: } aoqi@0: aoqi@0: static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args, aoqi@0: bool save_fpu_registers = true) { aoqi@0: __ block_comment("save_live_registers"); aoqi@0: aoqi@0: __ pusha(); // integer registers aoqi@0: aoqi@0: // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset"); aoqi@0: // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset"); aoqi@0: aoqi@0: __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); aoqi@0: #endif aoqi@0: aoqi@0: if (save_fpu_registers) { aoqi@0: if (UseSSE < 2) { aoqi@0: // save FPU stack aoqi@0: __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); aoqi@0: __ fwait(); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: Label ok; aoqi@0: __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); aoqi@0: __ jccb(Assembler::equal, ok); aoqi@0: __ stop("corrupted control word detected"); aoqi@0: __ bind(ok); aoqi@0: #endif aoqi@0: aoqi@0: // Reset the control word to guard against exceptions being unmasked aoqi@0: // since fstp_d can cause FPU stack underflow exceptions. Write it aoqi@0: // into the on stack copy and then reload that to make sure that the aoqi@0: // current and future values are correct. aoqi@0: __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); aoqi@0: __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); aoqi@0: aoqi@0: // Save the FPU registers in de-opt-able form aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48)); aoqi@0: __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56)); aoqi@0: } aoqi@0: aoqi@0: if (UseSSE >= 2) { aoqi@0: // save XMM registers aoqi@0: // XMM registers can contain float or double values, but this is not known here, aoqi@0: // so always save them as doubles. aoqi@0: // note that float values are _not_ converted automatically, so for float values aoqi@0: // the second word contains only garbage data. aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7); aoqi@0: #ifdef _LP64 aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14); aoqi@0: __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15); aoqi@0: #endif // _LP64 aoqi@0: } else if (UseSSE == 1) { aoqi@0: // save XMM registers as float because double not supported without SSE2 aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6); aoqi@0: __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // FPU stack must be empty now aoqi@0: __ verify_FPU(0, "save_live_registers"); aoqi@0: aoqi@0: return generate_oop_map(sasm, num_rt_args, save_fpu_registers); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) { aoqi@0: if (restore_fpu_registers) { aoqi@0: if (UseSSE >= 2) { aoqi@0: // restore XMM registers aoqi@0: __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0)); aoqi@0: __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8)); aoqi@0: __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16)); aoqi@0: __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24)); aoqi@0: __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32)); aoqi@0: __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40)); aoqi@0: __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48)); aoqi@0: __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56)); aoqi@0: #ifdef _LP64 aoqi@0: __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64)); aoqi@0: __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72)); aoqi@0: __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80)); aoqi@0: __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88)); aoqi@0: __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96)); aoqi@0: __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104)); aoqi@0: __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112)); aoqi@0: __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120)); aoqi@0: #endif // _LP64 aoqi@0: } else if (UseSSE == 1) { aoqi@0: // restore XMM registers aoqi@0: __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0)); aoqi@0: __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8)); aoqi@0: __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16)); aoqi@0: __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24)); aoqi@0: __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32)); aoqi@0: __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40)); aoqi@0: __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48)); aoqi@0: __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56)); aoqi@0: } aoqi@0: aoqi@0: if (UseSSE < 2) { aoqi@0: __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); aoqi@0: } else { aoqi@0: // check that FPU stack is really empty aoqi@0: __ verify_FPU(0, "restore_live_registers"); aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // check that FPU stack is really empty aoqi@0: __ verify_FPU(0, "restore_live_registers"); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: { aoqi@0: Label ok; aoqi@0: __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); aoqi@0: __ jcc(Assembler::equal, ok); aoqi@0: __ stop("bad offsets in frame"); aoqi@0: __ bind(ok); aoqi@0: } aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) { aoqi@0: __ block_comment("restore_live_registers"); aoqi@0: aoqi@0: restore_fpu(sasm, restore_fpu_registers); aoqi@0: __ popa(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) { aoqi@0: __ block_comment("restore_live_registers_except_rax"); aoqi@0: aoqi@0: restore_fpu(sasm, restore_fpu_registers); aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: __ movptr(r15, Address(rsp, 0)); aoqi@0: __ movptr(r14, Address(rsp, wordSize)); aoqi@0: __ movptr(r13, Address(rsp, 2 * wordSize)); aoqi@0: __ movptr(r12, Address(rsp, 3 * wordSize)); aoqi@0: __ movptr(r11, Address(rsp, 4 * wordSize)); aoqi@0: __ movptr(r10, Address(rsp, 5 * wordSize)); aoqi@0: __ movptr(r9, Address(rsp, 6 * wordSize)); aoqi@0: __ movptr(r8, Address(rsp, 7 * wordSize)); aoqi@0: __ movptr(rdi, Address(rsp, 8 * wordSize)); aoqi@0: __ movptr(rsi, Address(rsp, 9 * wordSize)); aoqi@0: __ movptr(rbp, Address(rsp, 10 * wordSize)); aoqi@0: // skip rsp aoqi@0: __ movptr(rbx, Address(rsp, 12 * wordSize)); aoqi@0: __ movptr(rdx, Address(rsp, 13 * wordSize)); aoqi@0: __ movptr(rcx, Address(rsp, 14 * wordSize)); aoqi@0: aoqi@0: __ addptr(rsp, 16 * wordSize); aoqi@0: #else aoqi@0: aoqi@0: __ pop(rdi); aoqi@0: __ pop(rsi); aoqi@0: __ pop(rbp); aoqi@0: __ pop(rbx); // skip this value aoqi@0: __ pop(rbx); aoqi@0: __ pop(rdx); aoqi@0: __ pop(rcx); aoqi@0: __ addptr(rsp, BytesPerWord); aoqi@0: #endif // _LP64 aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void Runtime1::initialize_pd() { aoqi@0: // nothing to do aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // target: the entry point of the method that creates and posts the exception oop aoqi@0: // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved) aoqi@0: aoqi@0: OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) { aoqi@0: // preserve all registers aoqi@0: int num_rt_args = has_argument ? 2 : 1; aoqi@0: OopMap* oop_map = save_live_registers(sasm, num_rt_args); aoqi@0: aoqi@0: // now all registers are saved and can be used freely aoqi@0: // verify that no old value is used accidentally aoqi@0: __ invalidate_registers(true, true, true, true, true, true); aoqi@0: aoqi@0: // registers used by this stub aoqi@0: const Register temp_reg = rbx; aoqi@0: aoqi@0: // load argument for exception that is passed as an argument into the stub aoqi@0: if (has_argument) { aoqi@0: #ifdef _LP64 aoqi@0: __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord)); aoqi@0: #else aoqi@0: __ movptr(temp_reg, Address(rbp, 2*BytesPerWord)); aoqi@0: __ push(temp_reg); aoqi@0: #endif // _LP64 aoqi@0: } aoqi@0: int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1); aoqi@0: aoqi@0: OopMapSet* oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, oop_map); aoqi@0: aoqi@0: __ stop("should not reach here"); aoqi@0: aoqi@0: return oop_maps; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) { aoqi@0: __ block_comment("generate_handle_exception"); aoqi@0: aoqi@0: // incoming parameters aoqi@0: const Register exception_oop = rax; aoqi@0: const Register exception_pc = rdx; aoqi@0: // other registers used in this stub aoqi@0: const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); aoqi@0: aoqi@0: // Save registers, if required. aoqi@0: OopMapSet* oop_maps = new OopMapSet(); aoqi@0: OopMap* oop_map = NULL; aoqi@0: switch (id) { aoqi@0: case forward_exception_id: aoqi@0: // We're handling an exception in the context of a compiled frame. aoqi@0: // The registers have been saved in the standard places. Perform aoqi@0: // an exception lookup in the caller and dispatch to the handler aoqi@0: // if found. Otherwise unwind and dispatch to the callers aoqi@0: // exception handler. aoqi@0: oop_map = generate_oop_map(sasm, 1 /*thread*/); aoqi@0: aoqi@0: // load and clear pending exception oop into RAX aoqi@0: __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset())); aoqi@0: __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); aoqi@0: aoqi@0: // load issuing PC (the return address for this stub) into rdx aoqi@0: __ movptr(exception_pc, Address(rbp, 1*BytesPerWord)); aoqi@0: aoqi@0: // make sure that the vm_results are cleared (may be unnecessary) aoqi@0: __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); aoqi@0: __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); aoqi@0: break; aoqi@0: case handle_exception_nofpu_id: aoqi@0: case handle_exception_id: aoqi@0: // At this point all registers MAY be live. iveresov@7416: oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id); aoqi@0: break; aoqi@0: case handle_exception_from_callee_id: { aoqi@0: // At this point all registers except exception oop (RAX) and aoqi@0: // exception pc (RDX) are dead. aoqi@0: const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord); aoqi@0: oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0); aoqi@0: sasm->set_frame_size(frame_size); aoqi@0: WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes)); aoqi@0: break; aoqi@0: } aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: aoqi@0: #ifdef TIERED aoqi@0: // C2 can leave the fpu stack dirty aoqi@0: if (UseSSE < 2) { aoqi@0: __ empty_FPU_stack(); aoqi@0: } aoqi@0: #endif // TIERED aoqi@0: aoqi@0: // verify that only rax, and rdx is valid at this time aoqi@0: __ invalidate_registers(false, true, true, false, true, true); aoqi@0: // verify that rax, contains a valid exception aoqi@0: __ verify_not_null_oop(exception_oop); aoqi@0: aoqi@0: // load address of JavaThread object for thread-local data aoqi@0: NOT_LP64(__ get_thread(thread);) aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // check that fields in JavaThread for exception oop and issuing pc are aoqi@0: // empty before writing to them aoqi@0: Label oop_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD); aoqi@0: __ jcc(Assembler::equal, oop_empty); aoqi@0: __ stop("exception oop already set"); aoqi@0: __ bind(oop_empty); aoqi@0: aoqi@0: Label pc_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); aoqi@0: __ jcc(Assembler::equal, pc_empty); aoqi@0: __ stop("exception pc already set"); aoqi@0: __ bind(pc_empty); aoqi@0: #endif aoqi@0: aoqi@0: // save exception oop and issuing pc into JavaThread aoqi@0: // (exception handler will load it from here) aoqi@0: __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop); aoqi@0: __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc); aoqi@0: aoqi@0: // patch throwing pc into return address (has bci & oop map) aoqi@0: __ movptr(Address(rbp, 1*BytesPerWord), exception_pc); aoqi@0: aoqi@0: // compute the exception handler. aoqi@0: // the exception oop and the throwing pc are read from the fields in JavaThread aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc)); aoqi@0: oop_maps->add_gc_map(call_offset, oop_map); aoqi@0: aoqi@0: // rax: handler address aoqi@0: // will be the deopt blob if nmethod was deoptimized while we looked up aoqi@0: // handler regardless of whether handler existed in the nmethod. aoqi@0: aoqi@0: // only rax, is valid at this time, all other registers have been destroyed by the runtime call aoqi@0: __ invalidate_registers(false, true, true, true, true, true); aoqi@0: aoqi@0: // patch the return address, this stub will directly return to the exception handler aoqi@0: __ movptr(Address(rbp, 1*BytesPerWord), rax); aoqi@0: aoqi@0: switch (id) { aoqi@0: case forward_exception_id: aoqi@0: case handle_exception_nofpu_id: aoqi@0: case handle_exception_id: aoqi@0: // Restore the registers that were saved at the beginning. iveresov@7416: restore_live_registers(sasm, id != handle_exception_nofpu_id); aoqi@0: break; aoqi@0: case handle_exception_from_callee_id: aoqi@0: // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP aoqi@0: // since we do a leave anyway. aoqi@0: zmajo@7854: // Pop the return address. aoqi@0: __ leave(); aoqi@0: __ pop(rcx); aoqi@0: __ jmp(rcx); // jump to exception handler aoqi@0: break; aoqi@0: default: ShouldNotReachHere(); aoqi@0: } aoqi@0: aoqi@0: return oop_maps; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void Runtime1::generate_unwind_exception(StubAssembler *sasm) { aoqi@0: // incoming parameters aoqi@0: const Register exception_oop = rax; aoqi@0: // callee-saved copy of exception_oop during runtime call aoqi@0: const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14); aoqi@0: // other registers used in this stub aoqi@0: const Register exception_pc = rdx; aoqi@0: const Register handler_addr = rbx; aoqi@0: const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); aoqi@0: aoqi@0: // verify that only rax, is valid at this time aoqi@0: __ invalidate_registers(false, true, true, true, true, true); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // check that fields in JavaThread for exception oop and issuing pc are empty aoqi@0: NOT_LP64(__ get_thread(thread);) aoqi@0: Label oop_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0); aoqi@0: __ jcc(Assembler::equal, oop_empty); aoqi@0: __ stop("exception oop must be empty"); aoqi@0: __ bind(oop_empty); aoqi@0: aoqi@0: Label pc_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); aoqi@0: __ jcc(Assembler::equal, pc_empty); aoqi@0: __ stop("exception pc must be empty"); aoqi@0: __ bind(pc_empty); aoqi@0: #endif aoqi@0: aoqi@0: // clear the FPU stack in case any FPU results are left behind aoqi@0: __ empty_FPU_stack(); aoqi@0: aoqi@0: // save exception_oop in callee-saved register to preserve it during runtime calls aoqi@0: __ verify_not_null_oop(exception_oop); aoqi@0: __ movptr(exception_oop_callee_saved, exception_oop); aoqi@0: aoqi@0: NOT_LP64(__ get_thread(thread);) aoqi@0: // Get return address (is on top of stack after leave). aoqi@0: __ movptr(exception_pc, Address(rsp, 0)); aoqi@0: aoqi@0: // search the exception handler address of the caller (using the return address) aoqi@0: __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc); aoqi@0: // rax: exception handler address of the caller aoqi@0: aoqi@0: // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call. aoqi@0: __ invalidate_registers(false, true, true, true, false, true); aoqi@0: aoqi@0: // move result of call into correct register aoqi@0: __ movptr(handler_addr, rax); aoqi@0: aoqi@0: // Restore exception oop to RAX (required convention of exception handler). aoqi@0: __ movptr(exception_oop, exception_oop_callee_saved); aoqi@0: aoqi@0: // verify that there is really a valid exception in rax aoqi@0: __ verify_not_null_oop(exception_oop); aoqi@0: aoqi@0: // get throwing pc (= return address). aoqi@0: // rdx has been destroyed by the call, so it must be set again aoqi@0: // the pop is also necessary to simulate the effect of a ret(0) aoqi@0: __ pop(exception_pc); aoqi@0: aoqi@0: // continue at exception handler (return address removed) aoqi@0: // note: do *not* remove arguments when unwinding the aoqi@0: // activation since the caller assumes having aoqi@0: // all arguments on the stack when entering the aoqi@0: // runtime to determine the exception handler aoqi@0: // (GC happens at call site with arguments!) aoqi@0: // rax: exception oop aoqi@0: // rdx: throwing pc aoqi@0: // rbx: exception handler aoqi@0: __ jmp(handler_addr); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) { aoqi@0: // use the maximum number of runtime-arguments here because it is difficult to aoqi@0: // distinguish each RT-Call. aoqi@0: // Note: This number affects also the RT-Call in generate_handle_exception because aoqi@0: // the oop-map is shared for all calls. aoqi@0: const int num_rt_args = 2; // thread + dummy aoqi@0: aoqi@0: DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); aoqi@0: assert(deopt_blob != NULL, "deoptimization blob must have been created"); aoqi@0: aoqi@0: OopMap* oop_map = save_live_registers(sasm, num_rt_args); aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: const Register thread = r15_thread; aoqi@0: // No need to worry about dummy aoqi@0: __ mov(c_rarg0, thread); aoqi@0: #else aoqi@0: __ push(rax); // push dummy aoqi@0: aoqi@0: const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions) aoqi@0: // push java thread (becomes first argument of C function) aoqi@0: __ get_thread(thread); aoqi@0: __ push(thread); aoqi@0: #endif // _LP64 aoqi@0: __ set_last_Java_frame(thread, noreg, rbp, NULL); aoqi@0: // do the call aoqi@0: __ call(RuntimeAddress(target)); aoqi@0: OopMapSet* oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(__ offset(), oop_map); aoqi@0: // verify callee-saved register aoqi@0: #ifdef ASSERT aoqi@0: guarantee(thread != rax, "change this code"); aoqi@0: __ push(rax); aoqi@0: { Label L; aoqi@0: __ get_thread(rax); aoqi@0: __ cmpptr(thread, rax); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?"); aoqi@0: __ bind(L); aoqi@0: } aoqi@0: __ pop(rax); aoqi@0: #endif kevinw@8877: __ reset_last_Java_frame(thread, true); aoqi@0: #ifndef _LP64 aoqi@0: __ pop(rcx); // discard thread arg aoqi@0: __ pop(rcx); // discard dummy aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: // check for pending exceptions aoqi@0: { Label L; aoqi@0: __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, L); aoqi@0: // exception pending => remove activation and forward to exception handler aoqi@0: aoqi@0: __ testptr(rax, rax); // have we deoptimized? aoqi@0: __ jump_cc(Assembler::equal, aoqi@0: RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); aoqi@0: aoqi@0: // the deopt blob expects exceptions in the special fields of aoqi@0: // JavaThread, so copy and clear pending exception. aoqi@0: aoqi@0: // load and clear pending exception aoqi@0: __ movptr(rax, Address(thread, Thread::pending_exception_offset())); aoqi@0: __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); aoqi@0: aoqi@0: // check that there is really a valid exception aoqi@0: __ verify_not_null_oop(rax); aoqi@0: aoqi@0: // load throwing pc: this is the return address of the stub aoqi@0: __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size)); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // check that fields in JavaThread for exception oop and issuing pc are empty aoqi@0: Label oop_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, oop_empty); aoqi@0: __ stop("exception oop must be empty"); aoqi@0: __ bind(oop_empty); aoqi@0: aoqi@0: Label pc_empty; aoqi@0: __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); aoqi@0: __ jcc(Assembler::equal, pc_empty); aoqi@0: __ stop("exception pc must be empty"); aoqi@0: __ bind(pc_empty); aoqi@0: #endif aoqi@0: aoqi@0: // store exception oop and throwing pc to JavaThread aoqi@0: __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax); aoqi@0: __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx); aoqi@0: aoqi@0: restore_live_registers(sasm); aoqi@0: aoqi@0: __ leave(); aoqi@0: __ addptr(rsp, BytesPerWord); // remove return address from stack aoqi@0: aoqi@0: // Forward the exception directly to deopt blob. We can blow no aoqi@0: // registers and must leave throwing pc on the stack. A patch may aoqi@0: // have values live in registers so the entry point with the aoqi@0: // exception in tls. aoqi@0: __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls())); aoqi@0: aoqi@0: __ bind(L); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Runtime will return true if the nmethod has been deoptimized during aoqi@0: // the patching process. In that case we must do a deopt reexecute instead. aoqi@0: aoqi@0: Label reexecuteEntry, cont; aoqi@0: aoqi@0: __ testptr(rax, rax); // have we deoptimized? aoqi@0: __ jcc(Assembler::equal, cont); // no aoqi@0: aoqi@0: // Will reexecute. Proper return address is already on the stack we just restore aoqi@0: // registers, pop all of our frame but the return address and jump to the deopt blob aoqi@0: restore_live_registers(sasm); aoqi@0: __ leave(); aoqi@0: __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); aoqi@0: aoqi@0: __ bind(cont); aoqi@0: restore_live_registers(sasm); aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: aoqi@0: return oop_maps; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) { aoqi@0: aoqi@0: // for better readability aoqi@0: const bool must_gc_arguments = true; aoqi@0: const bool dont_gc_arguments = false; aoqi@0: aoqi@0: // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu aoqi@0: bool save_fpu_registers = true; aoqi@0: aoqi@0: // stub code & info for the different stubs aoqi@0: OopMapSet* oop_maps = NULL; aoqi@0: switch (id) { aoqi@0: case forward_exception_id: aoqi@0: { aoqi@0: oop_maps = generate_handle_exception(id, sasm); aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case new_instance_id: aoqi@0: case fast_new_instance_id: aoqi@0: case fast_new_instance_init_check_id: aoqi@0: { aoqi@0: Register klass = rdx; // Incoming aoqi@0: Register obj = rax; // Result aoqi@0: aoqi@0: if (id == new_instance_id) { aoqi@0: __ set_info("new_instance", dont_gc_arguments); aoqi@0: } else if (id == fast_new_instance_id) { aoqi@0: __ set_info("fast new_instance", dont_gc_arguments); aoqi@0: } else { aoqi@0: assert(id == fast_new_instance_init_check_id, "bad StubID"); aoqi@0: __ set_info("fast new_instance init check", dont_gc_arguments); aoqi@0: } aoqi@0: aoqi@0: if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) && aoqi@0: UseTLAB && FastTLABRefill) { aoqi@0: Label slow_path; aoqi@0: Register obj_size = rcx; aoqi@0: Register t1 = rbx; aoqi@0: Register t2 = rsi; aoqi@0: assert_different_registers(klass, obj, obj_size, t1, t2); aoqi@0: aoqi@0: __ push(rdi); aoqi@0: __ push(rbx); aoqi@0: aoqi@0: if (id == fast_new_instance_init_check_id) { aoqi@0: // make sure the klass is initialized aoqi@0: __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); aoqi@0: __ jcc(Assembler::notEqual, slow_path); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // assert object can be fast path allocated aoqi@0: { aoqi@0: Label ok, not_ok; aoqi@0: __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); aoqi@0: __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0) aoqi@0: __ jcc(Assembler::lessEqual, not_ok); aoqi@0: __ testl(obj_size, Klass::_lh_instance_slow_path_bit); aoqi@0: __ jcc(Assembler::zero, ok); aoqi@0: __ bind(not_ok); aoqi@0: __ stop("assert(can be fast path allocated)"); aoqi@0: __ should_not_reach_here(); aoqi@0: __ bind(ok); aoqi@0: } aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: // if we got here then the TLAB allocation failed, so try aoqi@0: // refilling the TLAB or allocating directly from eden. aoqi@0: Label retry_tlab, try_eden; aoqi@0: const Register thread = aoqi@0: __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy rdx (klass), returns rdi aoqi@0: aoqi@0: __ bind(retry_tlab); aoqi@0: aoqi@0: // get the instance size (size is postive so movl is fine for 64bit) aoqi@0: __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); aoqi@0: aoqi@0: __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path); aoqi@0: aoqi@0: __ initialize_object(obj, klass, obj_size, 0, t1, t2); aoqi@0: __ verify_oop(obj); aoqi@0: __ pop(rbx); aoqi@0: __ pop(rdi); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(try_eden); aoqi@0: // get the instance size (size is postive so movl is fine for 64bit) aoqi@0: __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); aoqi@0: aoqi@0: __ eden_allocate(obj, obj_size, 0, t1, slow_path); aoqi@0: __ incr_allocated_bytes(thread, obj_size, 0); aoqi@0: aoqi@0: __ initialize_object(obj, klass, obj_size, 0, t1, t2); aoqi@0: __ verify_oop(obj); aoqi@0: __ pop(rbx); aoqi@0: __ pop(rdi); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(slow_path); aoqi@0: __ pop(rbx); aoqi@0: __ pop(rdi); aoqi@0: } aoqi@0: aoqi@0: __ enter(); aoqi@0: OopMap* map = save_live_registers(sasm, 2); aoqi@0: int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass); aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers_except_rax(sasm); aoqi@0: __ verify_oop(obj); aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: aoqi@0: // rax,: new instance aoqi@0: } aoqi@0: aoqi@0: break; aoqi@0: aoqi@0: case counter_overflow_id: aoqi@0: { aoqi@0: Register bci = rax, method = rbx; aoqi@0: __ enter(); aoqi@0: OopMap* map = save_live_registers(sasm, 3); aoqi@0: // Retrieve bci aoqi@0: __ movl(bci, Address(rbp, 2*BytesPerWord)); aoqi@0: // And a pointer to the Method* aoqi@0: __ movptr(method, Address(rbp, 3*BytesPerWord)); aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method); aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers(sasm); aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case new_type_array_id: aoqi@0: case new_object_array_id: aoqi@0: { aoqi@0: Register length = rbx; // Incoming aoqi@0: Register klass = rdx; // Incoming aoqi@0: Register obj = rax; // Result aoqi@0: aoqi@0: if (id == new_type_array_id) { aoqi@0: __ set_info("new_type_array", dont_gc_arguments); aoqi@0: } else { aoqi@0: __ set_info("new_object_array", dont_gc_arguments); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // assert object type is really an array of the proper kind aoqi@0: { aoqi@0: Label ok; aoqi@0: Register t0 = obj; aoqi@0: __ movl(t0, Address(klass, Klass::layout_helper_offset())); aoqi@0: __ sarl(t0, Klass::_lh_array_tag_shift); aoqi@0: int tag = ((id == new_type_array_id) aoqi@0: ? Klass::_lh_array_tag_type_value aoqi@0: : Klass::_lh_array_tag_obj_value); aoqi@0: __ cmpl(t0, tag); aoqi@0: __ jcc(Assembler::equal, ok); aoqi@0: __ stop("assert(is an array klass)"); aoqi@0: __ should_not_reach_here(); aoqi@0: __ bind(ok); aoqi@0: } aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: if (UseTLAB && FastTLABRefill) { aoqi@0: Register arr_size = rsi; aoqi@0: Register t1 = rcx; // must be rcx for use as shift count aoqi@0: Register t2 = rdi; aoqi@0: Label slow_path; aoqi@0: assert_different_registers(length, klass, obj, arr_size, t1, t2); aoqi@0: aoqi@0: // check that array length is small enough for fast path. aoqi@0: __ cmpl(length, C1_MacroAssembler::max_array_allocation_length); aoqi@0: __ jcc(Assembler::above, slow_path); aoqi@0: aoqi@0: // if we got here then the TLAB allocation failed, so try aoqi@0: // refilling the TLAB or allocating directly from eden. aoqi@0: Label retry_tlab, try_eden; aoqi@0: const Register thread = aoqi@0: __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves rbx & rdx, returns rdi aoqi@0: aoqi@0: __ bind(retry_tlab); aoqi@0: aoqi@0: // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F)) aoqi@0: // since size is positive movl does right thing on 64bit aoqi@0: __ movl(t1, Address(klass, Klass::layout_helper_offset())); aoqi@0: // since size is postive movl does right thing on 64bit aoqi@0: __ movl(arr_size, length); aoqi@0: assert(t1 == rcx, "fixed register usage"); aoqi@0: __ shlptr(arr_size /* by t1=rcx, mod 32 */); aoqi@0: __ shrptr(t1, Klass::_lh_header_size_shift); aoqi@0: __ andptr(t1, Klass::_lh_header_size_mask); aoqi@0: __ addptr(arr_size, t1); aoqi@0: __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up aoqi@0: __ andptr(arr_size, ~MinObjAlignmentInBytesMask); aoqi@0: aoqi@0: __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size aoqi@0: aoqi@0: __ initialize_header(obj, klass, length, t1, t2); aoqi@0: __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte))); aoqi@0: assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise"); aoqi@0: assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise"); aoqi@0: __ andptr(t1, Klass::_lh_header_size_mask); aoqi@0: __ subptr(arr_size, t1); // body length aoqi@0: __ addptr(t1, obj); // body start aoqi@0: __ initialize_body(t1, arr_size, 0, t2); aoqi@0: __ verify_oop(obj); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(try_eden); aoqi@0: // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F)) aoqi@0: // since size is positive movl does right thing on 64bit aoqi@0: __ movl(t1, Address(klass, Klass::layout_helper_offset())); aoqi@0: // since size is postive movl does right thing on 64bit aoqi@0: __ movl(arr_size, length); aoqi@0: assert(t1 == rcx, "fixed register usage"); aoqi@0: __ shlptr(arr_size /* by t1=rcx, mod 32 */); aoqi@0: __ shrptr(t1, Klass::_lh_header_size_shift); aoqi@0: __ andptr(t1, Klass::_lh_header_size_mask); aoqi@0: __ addptr(arr_size, t1); aoqi@0: __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up aoqi@0: __ andptr(arr_size, ~MinObjAlignmentInBytesMask); aoqi@0: aoqi@0: __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size aoqi@0: __ incr_allocated_bytes(thread, arr_size, 0); aoqi@0: aoqi@0: __ initialize_header(obj, klass, length, t1, t2); aoqi@0: __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte))); aoqi@0: assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise"); aoqi@0: assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise"); aoqi@0: __ andptr(t1, Klass::_lh_header_size_mask); aoqi@0: __ subptr(arr_size, t1); // body length aoqi@0: __ addptr(t1, obj); // body start aoqi@0: __ initialize_body(t1, arr_size, 0, t2); aoqi@0: __ verify_oop(obj); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(slow_path); aoqi@0: } aoqi@0: aoqi@0: __ enter(); aoqi@0: OopMap* map = save_live_registers(sasm, 3); aoqi@0: int call_offset; aoqi@0: if (id == new_type_array_id) { aoqi@0: call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length); aoqi@0: } else { aoqi@0: call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length); aoqi@0: } aoqi@0: aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers_except_rax(sasm); aoqi@0: aoqi@0: __ verify_oop(obj); aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: aoqi@0: // rax,: new array aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case new_multi_array_id: aoqi@0: { StubFrame f(sasm, "new_multi_array", dont_gc_arguments); aoqi@0: // rax,: klass aoqi@0: // rbx,: rank aoqi@0: // rcx: address of 1st dimension aoqi@0: OopMap* map = save_live_registers(sasm, 4); aoqi@0: int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx); aoqi@0: aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers_except_rax(sasm); aoqi@0: aoqi@0: // rax,: new multi array aoqi@0: __ verify_oop(rax); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case register_finalizer_id: aoqi@0: { aoqi@0: __ set_info("register_finalizer", dont_gc_arguments); aoqi@0: aoqi@0: // This is called via call_runtime so the arguments aoqi@0: // will be place in C abi locations aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: __ verify_oop(c_rarg0); aoqi@0: __ mov(rax, c_rarg0); aoqi@0: #else aoqi@0: // The object is passed on the stack and we haven't pushed a aoqi@0: // frame yet so it's one work away from top of stack. aoqi@0: __ movptr(rax, Address(rsp, 1 * BytesPerWord)); aoqi@0: __ verify_oop(rax); aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: // load the klass and check the has finalizer flag aoqi@0: Label register_finalizer; aoqi@0: Register t = rsi; aoqi@0: __ load_klass(t, rax); aoqi@0: __ movl(t, Address(t, Klass::access_flags_offset())); aoqi@0: __ testl(t, JVM_ACC_HAS_FINALIZER); aoqi@0: __ jcc(Assembler::notZero, register_finalizer); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(register_finalizer); aoqi@0: __ enter(); aoqi@0: OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */); aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax); aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, oop_map); aoqi@0: aoqi@0: // Now restore all the live registers aoqi@0: restore_live_registers(sasm); aoqi@0: aoqi@0: __ leave(); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_range_check_failed_id: aoqi@0: { StubFrame f(sasm, "range_check_failed", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_index_exception_id: aoqi@0: { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_div0_exception_id: aoqi@0: { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_null_pointer_exception_id: aoqi@0: { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case handle_exception_nofpu_id: aoqi@0: case handle_exception_id: aoqi@0: { StubFrame f(sasm, "handle_exception", dont_gc_arguments); aoqi@0: oop_maps = generate_handle_exception(id, sasm); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case handle_exception_from_callee_id: aoqi@0: { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments); aoqi@0: oop_maps = generate_handle_exception(id, sasm); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case unwind_exception_id: aoqi@0: { __ set_info("unwind_exception", dont_gc_arguments); aoqi@0: // note: no stubframe since we are about to leave the current aoqi@0: // activation and we are calling a leaf VM function only. aoqi@0: generate_unwind_exception(sasm); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_array_store_exception_id: aoqi@0: { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments); aoqi@0: // tos + 0: link aoqi@0: // + 1: return address aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_class_cast_exception_id: aoqi@0: { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case throw_incompatible_class_change_error_id: aoqi@0: { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments); aoqi@0: oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case slow_subtype_check_id: aoqi@0: { aoqi@0: // Typical calling sequence: aoqi@0: // __ push(klass_RInfo); // object klass or other subclass aoqi@0: // __ push(sup_k_RInfo); // array element klass or other superclass aoqi@0: // __ call(slow_subtype_check); aoqi@0: // Note that the subclass is pushed first, and is therefore deepest. aoqi@0: // Previous versions of this code reversed the names 'sub' and 'super'. aoqi@0: // This was operationally harmless but made the code unreadable. aoqi@0: enum layout { aoqi@0: rax_off, SLOT2(raxH_off) aoqi@0: rcx_off, SLOT2(rcxH_off) aoqi@0: rsi_off, SLOT2(rsiH_off) aoqi@0: rdi_off, SLOT2(rdiH_off) aoqi@0: // saved_rbp_off, SLOT2(saved_rbpH_off) aoqi@0: return_off, SLOT2(returnH_off) aoqi@0: sup_k_off, SLOT2(sup_kH_off) aoqi@0: klass_off, SLOT2(superH_off) aoqi@0: framesize, aoqi@0: result_off = klass_off // deepest argument is also the return value aoqi@0: }; aoqi@0: aoqi@0: __ set_info("slow_subtype_check", dont_gc_arguments); aoqi@0: __ push(rdi); aoqi@0: __ push(rsi); aoqi@0: __ push(rcx); aoqi@0: __ push(rax); aoqi@0: aoqi@0: // This is called by pushing args and not with C abi aoqi@0: __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass aoqi@0: __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass aoqi@0: aoqi@0: Label miss; aoqi@0: __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss); aoqi@0: aoqi@0: // fallthrough on success: aoqi@0: __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result aoqi@0: __ pop(rax); aoqi@0: __ pop(rcx); aoqi@0: __ pop(rsi); aoqi@0: __ pop(rdi); aoqi@0: __ ret(0); aoqi@0: aoqi@0: __ bind(miss); aoqi@0: __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result aoqi@0: __ pop(rax); aoqi@0: __ pop(rcx); aoqi@0: __ pop(rsi); aoqi@0: __ pop(rdi); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case monitorenter_nofpu_id: aoqi@0: save_fpu_registers = false; aoqi@0: // fall through aoqi@0: case monitorenter_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "monitorenter", dont_gc_arguments); aoqi@0: OopMap* map = save_live_registers(sasm, 3, save_fpu_registers); aoqi@0: aoqi@0: // Called with store_parameter and not C abi aoqi@0: aoqi@0: f.load_argument(1, rax); // rax,: object aoqi@0: f.load_argument(0, rbx); // rbx,: lock address aoqi@0: aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx); aoqi@0: aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers(sasm, save_fpu_registers); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case monitorexit_nofpu_id: aoqi@0: save_fpu_registers = false; aoqi@0: // fall through aoqi@0: case monitorexit_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "monitorexit", dont_gc_arguments); aoqi@0: OopMap* map = save_live_registers(sasm, 2, save_fpu_registers); aoqi@0: aoqi@0: // Called with store_parameter and not C abi aoqi@0: aoqi@0: f.load_argument(0, rax); // rax,: lock address aoqi@0: aoqi@0: // note: really a leaf routine but must setup last java sp aoqi@0: // => use call_RT for now (speed can be improved by aoqi@0: // doing last java sp setup manually) aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax); aoqi@0: aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers(sasm, save_fpu_registers); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case deoptimize_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "deoptimize", dont_gc_arguments); aoqi@0: const int num_rt_args = 1; // thread aoqi@0: OopMap* oop_map = save_live_registers(sasm, num_rt_args); aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize)); aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, oop_map); aoqi@0: restore_live_registers(sasm); aoqi@0: DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); aoqi@0: assert(deopt_blob != NULL, "deoptimization blob must have been created"); aoqi@0: __ leave(); aoqi@0: __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case access_field_patching_id: aoqi@0: { StubFrame f(sasm, "access_field_patching", dont_gc_arguments); aoqi@0: // we should set up register map aoqi@0: oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching)); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case load_klass_patching_id: aoqi@0: { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments); aoqi@0: // we should set up register map aoqi@0: oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching)); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case load_mirror_patching_id: aoqi@0: { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments); aoqi@0: // we should set up register map aoqi@0: oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching)); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case load_appendix_patching_id: aoqi@0: { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments); aoqi@0: // we should set up register map aoqi@0: oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching)); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case dtrace_object_alloc_id: aoqi@0: { // rax,: object aoqi@0: StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments); aoqi@0: // we can't gc here so skip the oopmap but make sure that all aoqi@0: // the live registers get saved. aoqi@0: save_live_registers(sasm, 1); aoqi@0: aoqi@0: __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax)); aoqi@0: __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc))); aoqi@0: NOT_LP64(__ pop(rax)); aoqi@0: aoqi@0: restore_live_registers(sasm); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case fpu2long_stub_id: aoqi@0: { aoqi@0: // rax, and rdx are destroyed, but should be free since the result is returned there aoqi@0: // preserve rsi,ecx aoqi@0: __ push(rsi); aoqi@0: __ push(rcx); aoqi@0: LP64_ONLY(__ push(rdx);) aoqi@0: aoqi@0: // check for NaN aoqi@0: Label return0, do_return, return_min_jlong, do_convert; aoqi@0: aoqi@0: Address value_high_word(rsp, wordSize + 4); aoqi@0: Address value_low_word(rsp, wordSize); aoqi@0: Address result_high_word(rsp, 3*wordSize + 4); aoqi@0: Address result_low_word(rsp, 3*wordSize); aoqi@0: aoqi@0: __ subptr(rsp, 32); // more than enough on 32bit aoqi@0: __ fst_d(value_low_word); aoqi@0: __ movl(rax, value_high_word); aoqi@0: __ andl(rax, 0x7ff00000); aoqi@0: __ cmpl(rax, 0x7ff00000); aoqi@0: __ jcc(Assembler::notEqual, do_convert); aoqi@0: __ movl(rax, value_high_word); aoqi@0: __ andl(rax, 0xfffff); aoqi@0: __ orl(rax, value_low_word); aoqi@0: __ jcc(Assembler::notZero, return0); aoqi@0: aoqi@0: __ bind(do_convert); aoqi@0: __ fnstcw(Address(rsp, 0)); aoqi@0: __ movzwl(rax, Address(rsp, 0)); aoqi@0: __ orl(rax, 0xc00); aoqi@0: __ movw(Address(rsp, 2), rax); aoqi@0: __ fldcw(Address(rsp, 2)); aoqi@0: __ fwait(); aoqi@0: __ fistp_d(result_low_word); aoqi@0: __ fldcw(Address(rsp, 0)); aoqi@0: __ fwait(); aoqi@0: // This gets the entire long in rax on 64bit aoqi@0: __ movptr(rax, result_low_word); aoqi@0: // testing of high bits aoqi@0: __ movl(rdx, result_high_word); aoqi@0: __ mov(rcx, rax); aoqi@0: // What the heck is the point of the next instruction??? aoqi@0: __ xorl(rcx, 0x0); aoqi@0: __ movl(rsi, 0x80000000); aoqi@0: __ xorl(rsi, rdx); aoqi@0: __ orl(rcx, rsi); aoqi@0: __ jcc(Assembler::notEqual, do_return); aoqi@0: __ fldz(); aoqi@0: __ fcomp_d(value_low_word); aoqi@0: __ fnstsw_ax(); aoqi@0: #ifdef _LP64 aoqi@0: __ testl(rax, 0x4100); // ZF & CF == 0 aoqi@0: __ jcc(Assembler::equal, return_min_jlong); aoqi@0: #else aoqi@0: __ sahf(); aoqi@0: __ jcc(Assembler::above, return_min_jlong); aoqi@0: #endif // _LP64 aoqi@0: // return max_jlong aoqi@0: #ifndef _LP64 aoqi@0: __ movl(rdx, 0x7fffffff); aoqi@0: __ movl(rax, 0xffffffff); aoqi@0: #else aoqi@0: __ mov64(rax, CONST64(0x7fffffffffffffff)); aoqi@0: #endif // _LP64 aoqi@0: __ jmp(do_return); aoqi@0: aoqi@0: __ bind(return_min_jlong); aoqi@0: #ifndef _LP64 aoqi@0: __ movl(rdx, 0x80000000); aoqi@0: __ xorl(rax, rax); aoqi@0: #else aoqi@0: __ mov64(rax, CONST64(0x8000000000000000)); aoqi@0: #endif // _LP64 aoqi@0: __ jmp(do_return); aoqi@0: aoqi@0: __ bind(return0); aoqi@0: __ fpop(); aoqi@0: #ifndef _LP64 aoqi@0: __ xorptr(rdx,rdx); aoqi@0: __ xorptr(rax,rax); aoqi@0: #else aoqi@0: __ xorptr(rax, rax); aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: __ bind(do_return); aoqi@0: __ addptr(rsp, 32); aoqi@0: LP64_ONLY(__ pop(rdx);) aoqi@0: __ pop(rcx); aoqi@0: __ pop(rsi); aoqi@0: __ ret(0); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: #if INCLUDE_ALL_GCS aoqi@0: case g1_pre_barrier_slow_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments); aoqi@0: // arg0 : previous value of memory aoqi@0: aoqi@0: BarrierSet* bs = Universe::heap()->barrier_set(); aoqi@0: if (bs->kind() != BarrierSet::G1SATBCTLogging) { aoqi@0: __ movptr(rax, (int)id); aoqi@0: __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); aoqi@0: __ should_not_reach_here(); aoqi@0: break; aoqi@0: } aoqi@0: __ push(rax); aoqi@0: __ push(rdx); aoqi@0: aoqi@0: const Register pre_val = rax; aoqi@0: const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); aoqi@0: const Register tmp = rdx; aoqi@0: aoqi@0: NOT_LP64(__ get_thread(thread);) aoqi@0: aoqi@0: Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + aoqi@0: PtrQueue::byte_offset_of_active())); aoqi@0: aoqi@0: Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + aoqi@0: PtrQueue::byte_offset_of_index())); aoqi@0: Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + aoqi@0: PtrQueue::byte_offset_of_buf())); aoqi@0: aoqi@0: aoqi@0: Label done; aoqi@0: Label runtime; aoqi@0: aoqi@0: // Can we store original value in the thread's buffer? aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: __ movslq(tmp, queue_index); aoqi@0: __ cmpq(tmp, 0); aoqi@0: #else aoqi@0: __ cmpl(queue_index, 0); aoqi@0: #endif aoqi@0: __ jcc(Assembler::equal, runtime); aoqi@0: #ifdef _LP64 aoqi@0: __ subq(tmp, wordSize); aoqi@0: __ movl(queue_index, tmp); aoqi@0: __ addq(tmp, buffer); aoqi@0: #else aoqi@0: __ subl(queue_index, wordSize); aoqi@0: __ movl(tmp, buffer); aoqi@0: __ addl(tmp, queue_index); aoqi@0: #endif aoqi@0: aoqi@0: // prev_val (rax) aoqi@0: f.load_argument(0, pre_val); aoqi@0: __ movptr(Address(tmp, 0), pre_val); aoqi@0: __ jmp(done); aoqi@0: aoqi@0: __ bind(runtime); mchinnathamb@9290: mchinnathamb@9290: save_live_registers(sasm, 3); mchinnathamb@9290: aoqi@0: // load the pre-value aoqi@0: f.load_argument(0, rcx); aoqi@0: __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread); mchinnathamb@9290: mchinnathamb@9290: restore_live_registers(sasm); mchinnathamb@9290: aoqi@0: __ bind(done); aoqi@0: aoqi@0: __ pop(rdx); aoqi@0: __ pop(rax); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case g1_post_barrier_slow_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments); aoqi@0: aoqi@0: aoqi@0: // arg0: store_address aoqi@0: Address store_addr(rbp, 2*BytesPerWord); aoqi@0: aoqi@0: BarrierSet* bs = Universe::heap()->barrier_set(); aoqi@0: CardTableModRefBS* ct = (CardTableModRefBS*)bs; aoqi@0: assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); aoqi@0: aoqi@0: Label done; aoqi@0: Label runtime; aoqi@0: aoqi@0: // At this point we know new_value is non-NULL and the new_value crosses regions. aoqi@0: // Must check to see if card is already dirty aoqi@0: aoqi@0: const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); aoqi@0: aoqi@0: Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + aoqi@0: PtrQueue::byte_offset_of_index())); aoqi@0: Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + aoqi@0: PtrQueue::byte_offset_of_buf())); aoqi@0: aoqi@0: __ push(rax); aoqi@0: __ push(rcx); aoqi@0: aoqi@0: const Register cardtable = rax; aoqi@0: const Register card_addr = rcx; aoqi@0: aoqi@0: f.load_argument(0, card_addr); aoqi@0: __ shrptr(card_addr, CardTableModRefBS::card_shift); aoqi@0: // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT aoqi@0: // a valid address and therefore is not properly handled by the relocation code. aoqi@0: __ movptr(cardtable, (intptr_t)ct->byte_map_base); aoqi@0: __ addptr(card_addr, cardtable); aoqi@0: aoqi@0: NOT_LP64(__ get_thread(thread);) aoqi@0: aoqi@0: __ cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); aoqi@0: __ jcc(Assembler::equal, done); aoqi@0: aoqi@0: __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); aoqi@0: __ cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); aoqi@0: __ jcc(Assembler::equal, done); aoqi@0: aoqi@0: // storing region crossing non-NULL, card is clean. aoqi@0: // dirty card and log. aoqi@0: aoqi@0: __ movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); aoqi@0: aoqi@0: __ cmpl(queue_index, 0); aoqi@0: __ jcc(Assembler::equal, runtime); aoqi@0: __ subl(queue_index, wordSize); aoqi@0: aoqi@0: const Register buffer_addr = rbx; aoqi@0: __ push(rbx); aoqi@0: aoqi@0: __ movptr(buffer_addr, buffer); aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: __ movslq(rscratch1, queue_index); aoqi@0: __ addptr(buffer_addr, rscratch1); aoqi@0: #else aoqi@0: __ addptr(buffer_addr, queue_index); aoqi@0: #endif aoqi@0: __ movptr(Address(buffer_addr, 0), card_addr); aoqi@0: aoqi@0: __ pop(rbx); aoqi@0: __ jmp(done); aoqi@0: aoqi@0: __ bind(runtime); aoqi@0: __ push(rdx); mchinnathamb@9290: mchinnathamb@9290: save_live_registers(sasm, 3); mchinnathamb@9290: aoqi@0: __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); mchinnathamb@9290: mchinnathamb@9290: restore_live_registers(sasm); mchinnathamb@9290: aoqi@0: __ pop(rdx); aoqi@0: __ bind(done); aoqi@0: aoqi@0: __ pop(rcx); aoqi@0: __ pop(rax); aoqi@0: aoqi@0: } aoqi@0: break; aoqi@0: #endif // INCLUDE_ALL_GCS aoqi@0: aoqi@0: case predicate_failed_trap_id: aoqi@0: { aoqi@0: StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments); aoqi@0: aoqi@0: OopMap* map = save_live_registers(sasm, 1); aoqi@0: aoqi@0: int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap)); aoqi@0: oop_maps = new OopMapSet(); aoqi@0: oop_maps->add_gc_map(call_offset, map); aoqi@0: restore_live_registers(sasm); aoqi@0: __ leave(); aoqi@0: DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); aoqi@0: assert(deopt_blob != NULL, "deoptimization blob must have been created"); aoqi@0: aoqi@0: __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: default: aoqi@0: { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments); aoqi@0: __ movptr(rax, (int)id); aoqi@0: __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); aoqi@0: __ should_not_reach_here(); aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: return oop_maps; aoqi@0: } aoqi@0: aoqi@0: #undef __ aoqi@0: aoqi@0: const char *Runtime1::pd_name_for_address(address entry) { aoqi@0: return ""; aoqi@0: }