duke@435: /* twisti@1639: * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. duke@435: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. duke@435: * duke@435: * This code is free software; you can redistribute it and/or modify it duke@435: * under the terms of the GNU General Public License version 2 only, as duke@435: * published by the Free Software Foundation. duke@435: * duke@435: * This code is distributed in the hope that it will be useful, but WITHOUT duke@435: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or duke@435: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License duke@435: * version 2 for more details (a copy is included in the LICENSE file that duke@435: * accompanied this code). duke@435: * duke@435: * You should have received a copy of the GNU General Public License version duke@435: * 2 along with this work; if not, write to the Free Software Foundation, duke@435: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. duke@435: * duke@435: * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, duke@435: * CA 95054 USA or visit www.sun.com if you need additional information or duke@435: * have any questions. duke@435: * duke@435: */ duke@435: duke@435: # include "incls/_precompiled.incl" duke@435: # include "incls/_c1_LIRAssembler_x86.cpp.incl" duke@435: duke@435: duke@435: // These masks are used to provide 128-bit aligned bitmasks to the XMM duke@435: // instructions, to allow sign-masking or sign-bit flipping. They allow duke@435: // fast versions of NegF/NegD and AbsF/AbsD. duke@435: duke@435: // Note: 'double' and 'long long' have 32-bits alignment on x86. duke@435: static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { duke@435: // Use the expression (adr)&(~0xF) to provide 128-bits aligned address duke@435: // of 128-bits operands for SSE instructions. duke@435: jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); duke@435: // Store the value to a 128-bits operand. duke@435: operand[0] = lo; duke@435: operand[1] = hi; duke@435: return operand; duke@435: } duke@435: duke@435: // Buffer for 128-bits masks used by SSE instructions. duke@435: static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) duke@435: duke@435: // Static initialization during VM startup. duke@435: static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); duke@435: static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); duke@435: static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); duke@435: static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); duke@435: duke@435: duke@435: duke@435: NEEDS_CLEANUP // remove this definitions ? duke@435: const Register IC_Klass = rax; // where the IC klass is cached duke@435: const Register SYNC_header = rax; // synchronization header duke@435: const Register SHIFT_count = rcx; // where count for shift operations must be duke@435: duke@435: #define __ _masm-> duke@435: duke@435: duke@435: static void select_different_registers(Register preserve, duke@435: Register extra, duke@435: Register &tmp1, duke@435: Register &tmp2) { duke@435: if (tmp1 == preserve) { duke@435: assert_different_registers(tmp1, tmp2, extra); duke@435: tmp1 = extra; duke@435: } else if (tmp2 == preserve) { duke@435: assert_different_registers(tmp1, tmp2, extra); duke@435: tmp2 = extra; duke@435: } duke@435: assert_different_registers(preserve, tmp1, tmp2); duke@435: } duke@435: duke@435: duke@435: duke@435: static void select_different_registers(Register preserve, duke@435: Register extra, duke@435: Register &tmp1, duke@435: Register &tmp2, duke@435: Register &tmp3) { duke@435: if (tmp1 == preserve) { duke@435: assert_different_registers(tmp1, tmp2, tmp3, extra); duke@435: tmp1 = extra; duke@435: } else if (tmp2 == preserve) { duke@435: assert_different_registers(tmp1, tmp2, tmp3, extra); duke@435: tmp2 = extra; duke@435: } else if (tmp3 == preserve) { duke@435: assert_different_registers(tmp1, tmp2, tmp3, extra); duke@435: tmp3 = extra; duke@435: } duke@435: assert_different_registers(preserve, tmp1, tmp2, tmp3); duke@435: } duke@435: duke@435: duke@435: duke@435: bool LIR_Assembler::is_small_constant(LIR_Opr opr) { duke@435: if (opr->is_constant()) { duke@435: LIR_Const* constant = opr->as_constant_ptr(); duke@435: switch (constant->type()) { duke@435: case T_INT: { duke@435: return true; duke@435: } duke@435: duke@435: default: duke@435: return false; duke@435: } duke@435: } duke@435: return false; duke@435: } duke@435: duke@435: duke@435: LIR_Opr LIR_Assembler::receiverOpr() { never@739: return FrameMap::receiver_opr; duke@435: } duke@435: duke@435: LIR_Opr LIR_Assembler::incomingReceiverOpr() { duke@435: return receiverOpr(); duke@435: } duke@435: duke@435: LIR_Opr LIR_Assembler::osrBufferPointer() { never@739: return FrameMap::as_pointer_opr(receiverOpr()->as_register()); duke@435: } duke@435: duke@435: //--------------fpu register translations----------------------- duke@435: duke@435: duke@435: address LIR_Assembler::float_constant(float f) { duke@435: address const_addr = __ float_constant(f); duke@435: if (const_addr == NULL) { duke@435: bailout("const section overflow"); duke@435: return __ code()->consts()->start(); duke@435: } else { duke@435: return const_addr; duke@435: } duke@435: } duke@435: duke@435: duke@435: address LIR_Assembler::double_constant(double d) { duke@435: address const_addr = __ double_constant(d); duke@435: if (const_addr == NULL) { duke@435: bailout("const section overflow"); duke@435: return __ code()->consts()->start(); duke@435: } else { duke@435: return const_addr; duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::set_24bit_FPU() { duke@435: __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); duke@435: } duke@435: duke@435: void LIR_Assembler::reset_FPU() { duke@435: __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); duke@435: } duke@435: duke@435: void LIR_Assembler::fpop() { duke@435: __ fpop(); duke@435: } duke@435: duke@435: void LIR_Assembler::fxch(int i) { duke@435: __ fxch(i); duke@435: } duke@435: duke@435: void LIR_Assembler::fld(int i) { duke@435: __ fld_s(i); duke@435: } duke@435: duke@435: void LIR_Assembler::ffree(int i) { duke@435: __ ffree(i); duke@435: } duke@435: duke@435: void LIR_Assembler::breakpoint() { duke@435: __ int3(); duke@435: } duke@435: duke@435: void LIR_Assembler::push(LIR_Opr opr) { duke@435: if (opr->is_single_cpu()) { duke@435: __ push_reg(opr->as_register()); duke@435: } else if (opr->is_double_cpu()) { never@739: NOT_LP64(__ push_reg(opr->as_register_hi())); duke@435: __ push_reg(opr->as_register_lo()); duke@435: } else if (opr->is_stack()) { duke@435: __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); duke@435: } else if (opr->is_constant()) { duke@435: LIR_Const* const_opr = opr->as_constant_ptr(); duke@435: if (const_opr->type() == T_OBJECT) { duke@435: __ push_oop(const_opr->as_jobject()); duke@435: } else if (const_opr->type() == T_INT) { duke@435: __ push_jint(const_opr->as_jint()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::pop(LIR_Opr opr) { duke@435: if (opr->is_single_cpu()) { never@739: __ pop_reg(opr->as_register()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: never@739: bool LIR_Assembler::is_literal_address(LIR_Address* addr) { never@739: return addr->base()->is_illegal() && addr->index()->is_illegal(); never@739: } never@739: duke@435: //------------------------------------------- never@739: duke@435: Address LIR_Assembler::as_Address(LIR_Address* addr) { never@739: return as_Address(addr, rscratch1); never@739: } never@739: never@739: Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { duke@435: if (addr->base()->is_illegal()) { duke@435: assert(addr->index()->is_illegal(), "must be illegal too"); never@739: AddressLiteral laddr((address)addr->disp(), relocInfo::none); never@739: if (! __ reachable(laddr)) { never@739: __ movptr(tmp, laddr.addr()); never@739: Address res(tmp, 0); never@739: return res; never@739: } else { never@739: return __ as_Address(laddr); never@739: } duke@435: } duke@435: never@739: Register base = addr->base()->as_pointer_register(); duke@435: duke@435: if (addr->index()->is_illegal()) { duke@435: return Address( base, addr->disp()); never@739: } else if (addr->index()->is_cpu_register()) { never@739: Register index = addr->index()->as_pointer_register(); duke@435: return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); duke@435: } else if (addr->index()->is_constant()) { never@739: intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); never@739: assert(Assembler::is_simm32(addr_offset), "must be"); duke@435: duke@435: return Address(base, addr_offset); duke@435: } else { duke@435: Unimplemented(); duke@435: return Address(); duke@435: } duke@435: } duke@435: duke@435: duke@435: Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { duke@435: Address base = as_Address(addr); duke@435: return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); duke@435: } duke@435: duke@435: duke@435: Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { duke@435: return as_Address(addr); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::osr_entry() { duke@435: offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); duke@435: BlockBegin* osr_entry = compilation()->hir()->osr_entry(); duke@435: ValueStack* entry_state = osr_entry->state(); duke@435: int number_of_locks = entry_state->locks_size(); duke@435: duke@435: // we jump here if osr happens with the interpreter duke@435: // state set up to continue at the beginning of the duke@435: // loop that triggered osr - in particular, we have duke@435: // the following registers setup: duke@435: // duke@435: // rcx: osr buffer duke@435: // duke@435: duke@435: // build frame duke@435: ciMethod* m = compilation()->method(); duke@435: __ build_frame(initial_frame_size_in_bytes()); duke@435: duke@435: // OSR buffer is duke@435: // duke@435: // locals[nlocals-1..0] duke@435: // monitors[0..number_of_locks] duke@435: // duke@435: // locals is a direct copy of the interpreter frame so in the osr buffer duke@435: // so first slot in the local array is the last local from the interpreter duke@435: // and last slot is local[0] (receiver) from the interpreter duke@435: // duke@435: // Similarly with locks. The first lock slot in the osr buffer is the nth lock duke@435: // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock duke@435: // in the interpreter frame (the method lock if a sync method) duke@435: duke@435: // Initialize monitors in the compiled activation. duke@435: // rcx: pointer to osr buffer duke@435: // duke@435: // All other registers are dead at this point and the locals will be duke@435: // copied into place by code emitted in the IR. duke@435: never@739: Register OSR_buf = osrBufferPointer()->as_pointer_register(); duke@435: { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); duke@435: int monitor_offset = BytesPerWord * method()->max_locals() + roland@1495: (2 * BytesPerWord) * (number_of_locks - 1); roland@1495: // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in roland@1495: // the OSR buffer using 2 word entries: first the lock and then roland@1495: // the oop. duke@435: for (int i = 0; i < number_of_locks; i++) { roland@1495: int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); duke@435: #ifdef ASSERT duke@435: // verify the interpreter's monitor has a non-null object duke@435: { duke@435: Label L; roland@1495: __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::notZero, L); duke@435: __ stop("locked object is NULL"); duke@435: __ bind(L); duke@435: } duke@435: #endif roland@1495: __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); never@739: __ movptr(frame_map()->address_for_monitor_lock(i), rbx); roland@1495: __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); never@739: __ movptr(frame_map()->address_for_monitor_object(i), rbx); duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: // inline cache check; done before the frame is built. duke@435: int LIR_Assembler::check_icache() { duke@435: Register receiver = FrameMap::receiver_opr->as_register(); duke@435: Register ic_klass = IC_Klass; never@739: const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); duke@435: duke@435: if (!VerifyOops) { duke@435: // insert some nops so that the verified entry point is aligned on CodeEntryAlignment never@739: while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { duke@435: __ nop(); duke@435: } duke@435: } duke@435: int offset = __ offset(); duke@435: __ inline_cache_check(receiver, IC_Klass); duke@435: assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); duke@435: if (VerifyOops) { duke@435: // force alignment after the cache check. duke@435: // It's been verified to be aligned if !VerifyOops duke@435: __ align(CodeEntryAlignment); duke@435: } duke@435: return offset; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { duke@435: jobject o = NULL; duke@435: PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); duke@435: __ movoop(reg, o); duke@435: patching_epilog(patch, lir_patch_normal, reg, info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { duke@435: if (exception->is_valid()) { duke@435: // preserve exception duke@435: // note: the monitor_exit runtime call is a leaf routine duke@435: // and cannot block => no GC can happen duke@435: // The slow case (MonitorAccessStub) uses the first two stack slots duke@435: // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] never@739: __ movptr (Address(rsp, 2*wordSize), exception); duke@435: } duke@435: duke@435: Register obj_reg = obj_opr->as_register(); duke@435: Register lock_reg = lock_opr->as_register(); duke@435: duke@435: // setup registers (lock_reg must be rax, for lock_object) duke@435: assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); duke@435: Register hdr = lock_reg; duke@435: assert(new_hdr == SYNC_header, "wrong register"); duke@435: lock_reg = new_hdr; duke@435: // compute pointer to BasicLock duke@435: Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); never@739: __ lea(lock_reg, lock_addr); duke@435: // unlock object duke@435: MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); duke@435: // _slow_case_stubs->append(slow_case); duke@435: // temporary fix: must be created after exceptionhandler, therefore as call stub duke@435: _slow_case_stubs->append(slow_case); duke@435: if (UseFastLocking) { duke@435: // try inlined fast unlocking first, revert to slow locking if it fails duke@435: // note: lock_reg points to the displaced header since the displaced header offset is 0! duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); duke@435: } else { duke@435: // always do slow unlocking duke@435: // note: the slow unlocking code could be inlined here, however if we use duke@435: // slow unlocking, speed doesn't matter anyway and this solution is duke@435: // simpler and requires less duplicated code - additionally, the duke@435: // slow unlocking code is the same in either case which simplifies duke@435: // debugging duke@435: __ jmp(*slow_case->entry()); duke@435: } duke@435: // done duke@435: __ bind(*slow_case->continuation()); duke@435: duke@435: if (exception->is_valid()) { duke@435: // restore exception never@739: __ movptr (exception, Address(rsp, 2 * wordSize)); duke@435: } duke@435: } duke@435: duke@435: // This specifies the rsp decrement needed to build the frame duke@435: int LIR_Assembler::initial_frame_size_in_bytes() { duke@435: // if rounding, must let FrameMap know! never@739: never@739: // The frame_map records size in slots (32bit word) never@739: never@739: // subtract two words to account for return address and link never@739: return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; duke@435: } duke@435: duke@435: twisti@1639: int LIR_Assembler::emit_exception_handler() { duke@435: // if the last instruction is a call (typically to do a throw which duke@435: // is coming at the end after block reordering) the return address duke@435: // must still point into the code area in order to avoid assertion duke@435: // failures when searching for the corresponding bci => add a nop duke@435: // (was bug 5/14/1999 - gri) duke@435: __ nop(); duke@435: duke@435: // generate code for exception handler duke@435: address handler_base = __ start_a_stub(exception_handler_size); duke@435: if (handler_base == NULL) { duke@435: // not enough space left for the handler duke@435: bailout("exception handler overflow"); twisti@1639: return -1; duke@435: } twisti@1639: duke@435: int offset = code_offset(); duke@435: duke@435: // if the method does not have an exception handler, then there is duke@435: // no reason to search for one kvn@1215: if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_exceptions()) { duke@435: // the exception oop and pc are in rax, and rdx duke@435: // no other registers need to be preserved, so invalidate them duke@435: __ invalidate_registers(false, true, true, false, true, true); duke@435: duke@435: // check that there is really an exception duke@435: __ verify_not_null_oop(rax); duke@435: duke@435: // search an exception handler (rax: exception oop, rdx: throwing pc) duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); duke@435: duke@435: // if the call returns here, then the exception handler for particular duke@435: // exception doesn't exist -> unwind activation and forward exception to caller duke@435: } duke@435: duke@435: // the exception oop is in rax, duke@435: // no other registers need to be preserved, so invalidate them duke@435: __ invalidate_registers(false, true, true, true, true, true); duke@435: duke@435: // check that there is really an exception duke@435: __ verify_not_null_oop(rax); duke@435: duke@435: // unlock the receiver/klass if necessary duke@435: // rax,: exception duke@435: ciMethod* method = compilation()->method(); duke@435: if (method->is_synchronized() && GenerateSynchronizationCode) { duke@435: monitorexit(FrameMap::rbx_oop_opr, FrameMap::rcx_opr, SYNC_header, 0, rax); duke@435: } duke@435: duke@435: // unwind activation and forward exception to caller duke@435: // rax,: exception duke@435: __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); duke@435: assert(code_offset() - offset <= exception_handler_size, "overflow"); duke@435: __ end_a_stub(); twisti@1639: twisti@1639: return offset; duke@435: } duke@435: twisti@1639: twisti@1639: int LIR_Assembler::emit_deopt_handler() { duke@435: // if the last instruction is a call (typically to do a throw which duke@435: // is coming at the end after block reordering) the return address duke@435: // must still point into the code area in order to avoid assertion duke@435: // failures when searching for the corresponding bci => add a nop duke@435: // (was bug 5/14/1999 - gri) duke@435: __ nop(); duke@435: duke@435: // generate code for exception handler duke@435: address handler_base = __ start_a_stub(deopt_handler_size); duke@435: if (handler_base == NULL) { duke@435: // not enough space left for the handler duke@435: bailout("deopt handler overflow"); twisti@1639: return -1; duke@435: } twisti@1639: duke@435: int offset = code_offset(); duke@435: InternalAddress here(__ pc()); duke@435: __ pushptr(here.addr()); duke@435: __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); duke@435: assert(code_offset() - offset <= deopt_handler_size, "overflow"); duke@435: __ end_a_stub(); duke@435: twisti@1639: return offset; duke@435: } duke@435: duke@435: duke@435: // This is the fast version of java.lang.String.compare; it has not duke@435: // OSR-entry and therefore, we generate a slow version for OSR's duke@435: void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { never@739: __ movptr (rbx, rcx); // receiver is in rcx never@739: __ movptr (rax, arg1->as_register()); duke@435: duke@435: // Get addresses of first characters from both Strings never@739: __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); never@739: __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); never@739: __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); duke@435: duke@435: duke@435: // rbx, may be NULL duke@435: add_debug_info_for_null_check_here(info); never@739: __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); never@739: __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); never@739: __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); duke@435: duke@435: // compute minimum length (in rax) and difference of lengths (on top of stack) duke@435: if (VM_Version::supports_cmov()) { never@739: __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); never@739: __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); never@739: __ mov (rcx, rbx); never@739: __ subptr (rbx, rax); // subtract lengths never@739: __ push (rbx); // result never@739: __ cmov (Assembler::lessEqual, rax, rcx); duke@435: } else { duke@435: Label L; never@739: __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); never@739: __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); never@739: __ mov (rax, rbx); never@739: __ subptr (rbx, rcx); never@739: __ push (rbx); never@739: __ jcc (Assembler::lessEqual, L); never@739: __ mov (rax, rcx); duke@435: __ bind (L); duke@435: } duke@435: // is minimum length 0? duke@435: Label noLoop, haveResult; never@739: __ testptr (rax, rax); duke@435: __ jcc (Assembler::zero, noLoop); duke@435: duke@435: // compare first characters jrose@1057: __ load_unsigned_short(rcx, Address(rdi, 0)); jrose@1057: __ load_unsigned_short(rbx, Address(rsi, 0)); duke@435: __ subl(rcx, rbx); duke@435: __ jcc(Assembler::notZero, haveResult); duke@435: // starting loop duke@435: __ decrement(rax); // we already tested index: skip one duke@435: __ jcc(Assembler::zero, noLoop); duke@435: duke@435: // set rsi.edi to the end of the arrays (arrays have same length) duke@435: // negate the index duke@435: never@739: __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); never@739: __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); never@739: __ negptr(rax); duke@435: duke@435: // compare the strings in a loop duke@435: duke@435: Label loop; duke@435: __ align(wordSize); duke@435: __ bind(loop); jrose@1057: __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); jrose@1057: __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); duke@435: __ subl(rcx, rbx); duke@435: __ jcc(Assembler::notZero, haveResult); duke@435: __ increment(rax); duke@435: __ jcc(Assembler::notZero, loop); duke@435: duke@435: // strings are equal up to min length duke@435: duke@435: __ bind(noLoop); never@739: __ pop(rax); duke@435: return_op(LIR_OprFact::illegalOpr); duke@435: duke@435: __ bind(haveResult); duke@435: // leave instruction is going to discard the TOS value never@739: __ mov (rax, rcx); // result of call is in rax, duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::return_op(LIR_Opr result) { duke@435: assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); duke@435: if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { duke@435: assert(result->fpu() == 0, "result must already be on TOS"); duke@435: } duke@435: duke@435: // Pop the stack before the safepoint code duke@435: __ leave(); duke@435: duke@435: bool result_is_oop = result->is_valid() ? result->is_oop() : false; duke@435: duke@435: // Note: we do not need to round double result; float result has the right precision duke@435: // the poll sets the condition code, but no data registers duke@435: AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), duke@435: relocInfo::poll_return_type); never@739: never@739: // NOTE: the requires that the polling page be reachable else the reloc never@739: // goes to the movq that loads the address and not the faulting instruction never@739: // which breaks the signal handler code never@739: duke@435: __ test32(rax, polling_page); duke@435: duke@435: __ ret(0); duke@435: } duke@435: duke@435: duke@435: int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { duke@435: AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), duke@435: relocInfo::poll_type); duke@435: duke@435: if (info != NULL) { duke@435: add_debug_info_for_branch(info); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: int offset = __ offset(); never@739: never@739: // NOTE: the requires that the polling page be reachable else the reloc never@739: // goes to the movq that loads the address and not the faulting instruction never@739: // which breaks the signal handler code never@739: duke@435: __ test32(rax, polling_page); duke@435: return offset; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { never@739: if (from_reg != to_reg) __ mov(to_reg, from_reg); duke@435: } duke@435: duke@435: void LIR_Assembler::swap_reg(Register a, Register b) { never@739: __ xchgptr(a, b); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { duke@435: assert(src->is_constant(), "should not call otherwise"); duke@435: assert(dest->is_register(), "should not call otherwise"); duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: duke@435: switch (c->type()) { duke@435: case T_INT: { duke@435: assert(patch_code == lir_patch_none, "no patching handled here"); duke@435: __ movl(dest->as_register(), c->as_jint()); duke@435: break; duke@435: } duke@435: duke@435: case T_LONG: { duke@435: assert(patch_code == lir_patch_none, "no patching handled here"); never@739: #ifdef _LP64 never@739: __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); never@739: #else never@739: __ movptr(dest->as_register_lo(), c->as_jint_lo()); never@739: __ movptr(dest->as_register_hi(), c->as_jint_hi()); never@739: #endif // _LP64 duke@435: break; duke@435: } duke@435: duke@435: case T_OBJECT: { duke@435: if (patch_code != lir_patch_none) { duke@435: jobject2reg_with_patching(dest->as_register(), info); duke@435: } else { duke@435: __ movoop(dest->as_register(), c->as_jobject()); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_FLOAT: { duke@435: if (dest->is_single_xmm()) { duke@435: if (c->is_zero_float()) { duke@435: __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); duke@435: } else { duke@435: __ movflt(dest->as_xmm_float_reg(), duke@435: InternalAddress(float_constant(c->as_jfloat()))); duke@435: } duke@435: } else { duke@435: assert(dest->is_single_fpu(), "must be"); duke@435: assert(dest->fpu_regnr() == 0, "dest must be TOS"); duke@435: if (c->is_zero_float()) { duke@435: __ fldz(); duke@435: } else if (c->is_one_float()) { duke@435: __ fld1(); duke@435: } else { duke@435: __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); duke@435: } duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_DOUBLE: { duke@435: if (dest->is_double_xmm()) { duke@435: if (c->is_zero_double()) { duke@435: __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); duke@435: } else { duke@435: __ movdbl(dest->as_xmm_double_reg(), duke@435: InternalAddress(double_constant(c->as_jdouble()))); duke@435: } duke@435: } else { duke@435: assert(dest->is_double_fpu(), "must be"); duke@435: assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); duke@435: if (c->is_zero_double()) { duke@435: __ fldz(); duke@435: } else if (c->is_one_double()) { duke@435: __ fld1(); duke@435: } else { duke@435: __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); duke@435: } duke@435: } duke@435: break; duke@435: } duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { duke@435: assert(src->is_constant(), "should not call otherwise"); duke@435: assert(dest->is_stack(), "should not call otherwise"); duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: duke@435: switch (c->type()) { duke@435: case T_INT: // fall through duke@435: case T_FLOAT: duke@435: __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); duke@435: break; duke@435: duke@435: case T_OBJECT: duke@435: __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); duke@435: break; duke@435: duke@435: case T_LONG: // fall through duke@435: case T_DOUBLE: never@739: #ifdef _LP64 never@739: __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), never@739: lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); never@739: #else never@739: __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), never@739: lo_word_offset_in_bytes), c->as_jint_lo_bits()); never@739: __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), never@739: hi_word_offset_in_bytes), c->as_jint_hi_bits()); never@739: #endif // _LP64 duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { duke@435: assert(src->is_constant(), "should not call otherwise"); duke@435: assert(dest->is_address(), "should not call otherwise"); duke@435: LIR_Const* c = src->as_constant_ptr(); duke@435: LIR_Address* addr = dest->as_address_ptr(); duke@435: never@739: int null_check_here = code_offset(); duke@435: switch (type) { duke@435: case T_INT: // fall through duke@435: case T_FLOAT: duke@435: __ movl(as_Address(addr), c->as_jint_bits()); duke@435: break; duke@435: duke@435: case T_OBJECT: // fall through duke@435: case T_ARRAY: duke@435: if (c->as_jobject() == NULL) { xlu@947: __ movptr(as_Address(addr), NULL_WORD); duke@435: } else { never@739: if (is_literal_address(addr)) { never@739: ShouldNotReachHere(); never@739: __ movoop(as_Address(addr, noreg), c->as_jobject()); never@739: } else { roland@1495: #ifdef _LP64 roland@1495: __ movoop(rscratch1, c->as_jobject()); roland@1495: null_check_here = code_offset(); roland@1495: __ movptr(as_Address_lo(addr), rscratch1); roland@1495: #else never@739: __ movoop(as_Address(addr), c->as_jobject()); roland@1495: #endif never@739: } duke@435: } duke@435: break; duke@435: duke@435: case T_LONG: // fall through duke@435: case T_DOUBLE: never@739: #ifdef _LP64 never@739: if (is_literal_address(addr)) { never@739: ShouldNotReachHere(); never@739: __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); never@739: } else { never@739: __ movptr(r10, (intptr_t)c->as_jlong_bits()); never@739: null_check_here = code_offset(); never@739: __ movptr(as_Address_lo(addr), r10); never@739: } never@739: #else never@739: // Always reachable in 32bit so this doesn't produce useless move literal never@739: __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); never@739: __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); never@739: #endif // _LP64 duke@435: break; duke@435: duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE: duke@435: __ movb(as_Address(addr), c->as_jint() & 0xFF); duke@435: break; duke@435: duke@435: case T_CHAR: // fall through duke@435: case T_SHORT: duke@435: __ movw(as_Address(addr), c->as_jint() & 0xFFFF); duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: }; never@739: never@739: if (info != NULL) { never@739: add_debug_info_for_null_check(null_check_here, info); never@739: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { duke@435: assert(src->is_register(), "should not call otherwise"); duke@435: assert(dest->is_register(), "should not call otherwise"); duke@435: duke@435: // move between cpu-registers duke@435: if (dest->is_single_cpu()) { never@739: #ifdef _LP64 never@739: if (src->type() == T_LONG) { never@739: // Can do LONG -> OBJECT never@739: move_regs(src->as_register_lo(), dest->as_register()); never@739: return; never@739: } never@739: #endif duke@435: assert(src->is_single_cpu(), "must match"); duke@435: if (src->type() == T_OBJECT) { duke@435: __ verify_oop(src->as_register()); duke@435: } duke@435: move_regs(src->as_register(), dest->as_register()); duke@435: duke@435: } else if (dest->is_double_cpu()) { never@739: #ifdef _LP64 never@739: if (src->type() == T_OBJECT || src->type() == T_ARRAY) { never@739: // Surprising to me but we can see move of a long to t_object never@739: __ verify_oop(src->as_register()); never@739: move_regs(src->as_register(), dest->as_register_lo()); never@739: return; never@739: } never@739: #endif duke@435: assert(src->is_double_cpu(), "must match"); duke@435: Register f_lo = src->as_register_lo(); duke@435: Register f_hi = src->as_register_hi(); duke@435: Register t_lo = dest->as_register_lo(); duke@435: Register t_hi = dest->as_register_hi(); never@739: #ifdef _LP64 never@739: assert(f_hi == f_lo, "must be same"); never@739: assert(t_hi == t_lo, "must be same"); never@739: move_regs(f_lo, t_lo); never@739: #else duke@435: assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); duke@435: never@739: duke@435: if (f_lo == t_hi && f_hi == t_lo) { duke@435: swap_reg(f_lo, f_hi); duke@435: } else if (f_hi == t_lo) { duke@435: assert(f_lo != t_hi, "overwriting register"); duke@435: move_regs(f_hi, t_hi); duke@435: move_regs(f_lo, t_lo); duke@435: } else { duke@435: assert(f_hi != t_lo, "overwriting register"); duke@435: move_regs(f_lo, t_lo); duke@435: move_regs(f_hi, t_hi); duke@435: } never@739: #endif // LP64 duke@435: duke@435: // special moves from fpu-register to xmm-register duke@435: // necessary for method results duke@435: } else if (src->is_single_xmm() && !dest->is_single_xmm()) { duke@435: __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); duke@435: __ fld_s(Address(rsp, 0)); duke@435: } else if (src->is_double_xmm() && !dest->is_double_xmm()) { duke@435: __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); duke@435: __ fld_d(Address(rsp, 0)); duke@435: } else if (dest->is_single_xmm() && !src->is_single_xmm()) { duke@435: __ fstp_s(Address(rsp, 0)); duke@435: __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); duke@435: } else if (dest->is_double_xmm() && !src->is_double_xmm()) { duke@435: __ fstp_d(Address(rsp, 0)); duke@435: __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); duke@435: duke@435: // move between xmm-registers duke@435: } else if (dest->is_single_xmm()) { duke@435: assert(src->is_single_xmm(), "must match"); duke@435: __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); duke@435: } else if (dest->is_double_xmm()) { duke@435: assert(src->is_double_xmm(), "must match"); duke@435: __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); duke@435: duke@435: // move between fpu-registers (no instruction necessary because of fpu-stack) duke@435: } else if (dest->is_single_fpu() || dest->is_double_fpu()) { duke@435: assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); duke@435: assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { duke@435: assert(src->is_register(), "should not call otherwise"); duke@435: assert(dest->is_stack(), "should not call otherwise"); duke@435: duke@435: if (src->is_single_cpu()) { duke@435: Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: if (type == T_OBJECT || type == T_ARRAY) { duke@435: __ verify_oop(src->as_register()); never@739: __ movptr (dst, src->as_register()); never@739: } else { never@739: __ movl (dst, src->as_register()); duke@435: } duke@435: duke@435: } else if (src->is_double_cpu()) { duke@435: Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); duke@435: Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); never@739: __ movptr (dstLO, src->as_register_lo()); never@739: NOT_LP64(__ movptr (dstHI, src->as_register_hi())); duke@435: duke@435: } else if (src->is_single_xmm()) { duke@435: Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: __ movflt(dst_addr, src->as_xmm_float_reg()); duke@435: duke@435: } else if (src->is_double_xmm()) { duke@435: Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); duke@435: __ movdbl(dst_addr, src->as_xmm_double_reg()); duke@435: duke@435: } else if (src->is_single_fpu()) { duke@435: assert(src->fpu_regnr() == 0, "argument must be on TOS"); duke@435: Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); duke@435: if (pop_fpu_stack) __ fstp_s (dst_addr); duke@435: else __ fst_s (dst_addr); duke@435: duke@435: } else if (src->is_double_fpu()) { duke@435: assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); duke@435: Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); duke@435: if (pop_fpu_stack) __ fstp_d (dst_addr); duke@435: else __ fst_d (dst_addr); duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { duke@435: LIR_Address* to_addr = dest->as_address_ptr(); duke@435: PatchingStub* patch = NULL; duke@435: duke@435: if (type == T_ARRAY || type == T_OBJECT) { duke@435: __ verify_oop(src->as_register()); duke@435: } duke@435: if (patch_code != lir_patch_none) { duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); never@739: Address toa = as_Address(to_addr); never@739: assert(toa.disp() != 0, "must have"); duke@435: } duke@435: if (info != NULL) { duke@435: add_debug_info_for_null_check_here(info); duke@435: } duke@435: duke@435: switch (type) { duke@435: case T_FLOAT: { duke@435: if (src->is_single_xmm()) { duke@435: __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); duke@435: } else { duke@435: assert(src->is_single_fpu(), "must be"); duke@435: assert(src->fpu_regnr() == 0, "argument must be on TOS"); duke@435: if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); duke@435: else __ fst_s (as_Address(to_addr)); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_DOUBLE: { duke@435: if (src->is_double_xmm()) { duke@435: __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); duke@435: } else { duke@435: assert(src->is_double_fpu(), "must be"); duke@435: assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); duke@435: if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); duke@435: else __ fst_d (as_Address(to_addr)); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_ADDRESS: // fall through duke@435: case T_ARRAY: // fall through duke@435: case T_OBJECT: // fall through never@739: #ifdef _LP64 never@739: __ movptr(as_Address(to_addr), src->as_register()); never@739: break; never@739: #endif // _LP64 duke@435: case T_INT: duke@435: __ movl(as_Address(to_addr), src->as_register()); duke@435: break; duke@435: duke@435: case T_LONG: { duke@435: Register from_lo = src->as_register_lo(); duke@435: Register from_hi = src->as_register_hi(); never@739: #ifdef _LP64 never@739: __ movptr(as_Address_lo(to_addr), from_lo); never@739: #else duke@435: Register base = to_addr->base()->as_register(); duke@435: Register index = noreg; duke@435: if (to_addr->index()->is_register()) { duke@435: index = to_addr->index()->as_register(); duke@435: } duke@435: if (base == from_lo || index == from_lo) { duke@435: assert(base != from_hi, "can't be"); duke@435: assert(index == noreg || (index != base && index != from_hi), "can't handle this"); duke@435: __ movl(as_Address_hi(to_addr), from_hi); duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, lir_patch_high, base, info); duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: patch_code = lir_patch_low; duke@435: } duke@435: __ movl(as_Address_lo(to_addr), from_lo); duke@435: } else { duke@435: assert(index == noreg || (index != base && index != from_lo), "can't handle this"); duke@435: __ movl(as_Address_lo(to_addr), from_lo); duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, lir_patch_low, base, info); duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: patch_code = lir_patch_high; duke@435: } duke@435: __ movl(as_Address_hi(to_addr), from_hi); duke@435: } never@739: #endif // _LP64 duke@435: break; duke@435: } duke@435: duke@435: case T_BYTE: // fall through duke@435: case T_BOOLEAN: { duke@435: Register src_reg = src->as_register(); duke@435: Address dst_addr = as_Address(to_addr); duke@435: assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); duke@435: __ movb(dst_addr, src_reg); duke@435: break; duke@435: } duke@435: duke@435: case T_CHAR: // fall through duke@435: case T_SHORT: duke@435: __ movw(as_Address(to_addr), src->as_register()); duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (patch_code != lir_patch_none) { duke@435: patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { duke@435: assert(src->is_stack(), "should not call otherwise"); duke@435: assert(dest->is_register(), "should not call otherwise"); duke@435: duke@435: if (dest->is_single_cpu()) { duke@435: if (type == T_ARRAY || type == T_OBJECT) { never@739: __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); duke@435: __ verify_oop(dest->as_register()); never@739: } else { never@739: __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); duke@435: } duke@435: duke@435: } else if (dest->is_double_cpu()) { duke@435: Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); duke@435: Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); never@739: __ movptr(dest->as_register_lo(), src_addr_LO); never@739: NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); duke@435: duke@435: } else if (dest->is_single_xmm()) { duke@435: Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); duke@435: __ movflt(dest->as_xmm_float_reg(), src_addr); duke@435: duke@435: } else if (dest->is_double_xmm()) { duke@435: Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); duke@435: __ movdbl(dest->as_xmm_double_reg(), src_addr); duke@435: duke@435: } else if (dest->is_single_fpu()) { duke@435: assert(dest->fpu_regnr() == 0, "dest must be TOS"); duke@435: Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); duke@435: __ fld_s(src_addr); duke@435: duke@435: } else if (dest->is_double_fpu()) { duke@435: assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); duke@435: Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); duke@435: __ fld_d(src_addr); duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { duke@435: if (src->is_single_stack()) { never@739: if (type == T_OBJECT || type == T_ARRAY) { never@739: __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); never@739: __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); never@739: } else { roland@1495: #ifndef _LP64 never@739: __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); never@739: __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); roland@1495: #else roland@1495: //no pushl on 64bits roland@1495: __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); roland@1495: __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); roland@1495: #endif never@739: } duke@435: duke@435: } else if (src->is_double_stack()) { never@739: #ifdef _LP64 never@739: __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); never@739: __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); never@739: #else duke@435: __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); never@739: // push and pop the part at src + wordSize, adding wordSize for the previous push never@756: __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); never@756: __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); duke@435: __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); never@739: #endif // _LP64 duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { duke@435: assert(src->is_address(), "should not call otherwise"); duke@435: assert(dest->is_register(), "should not call otherwise"); duke@435: duke@435: LIR_Address* addr = src->as_address_ptr(); duke@435: Address from_addr = as_Address(addr); duke@435: duke@435: switch (type) { duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE: // fall through duke@435: case T_CHAR: // fall through duke@435: case T_SHORT: duke@435: if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { duke@435: // on pre P6 processors we may get partial register stalls duke@435: // so blow away the value of to_rinfo before loading a duke@435: // partial word into it. Do it here so that it precedes duke@435: // the potential patch point below. never@739: __ xorptr(dest->as_register(), dest->as_register()); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: PatchingStub* patch = NULL; duke@435: if (patch_code != lir_patch_none) { duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); never@739: assert(from_addr.disp() != 0, "must have"); duke@435: } duke@435: if (info != NULL) { duke@435: add_debug_info_for_null_check_here(info); duke@435: } duke@435: duke@435: switch (type) { duke@435: case T_FLOAT: { duke@435: if (dest->is_single_xmm()) { duke@435: __ movflt(dest->as_xmm_float_reg(), from_addr); duke@435: } else { duke@435: assert(dest->is_single_fpu(), "must be"); duke@435: assert(dest->fpu_regnr() == 0, "dest must be TOS"); duke@435: __ fld_s(from_addr); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_DOUBLE: { duke@435: if (dest->is_double_xmm()) { duke@435: __ movdbl(dest->as_xmm_double_reg(), from_addr); duke@435: } else { duke@435: assert(dest->is_double_fpu(), "must be"); duke@435: assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); duke@435: __ fld_d(from_addr); duke@435: } duke@435: break; duke@435: } duke@435: duke@435: case T_ADDRESS: // fall through duke@435: case T_OBJECT: // fall through duke@435: case T_ARRAY: // fall through never@739: #ifdef _LP64 never@739: __ movptr(dest->as_register(), from_addr); never@739: break; never@739: #endif // _L64 duke@435: case T_INT: never@739: // %%% could this be a movl? this is safer but longer instruction never@739: __ movl2ptr(dest->as_register(), from_addr); duke@435: break; duke@435: duke@435: case T_LONG: { duke@435: Register to_lo = dest->as_register_lo(); duke@435: Register to_hi = dest->as_register_hi(); never@739: #ifdef _LP64 never@739: __ movptr(to_lo, as_Address_lo(addr)); never@739: #else duke@435: Register base = addr->base()->as_register(); duke@435: Register index = noreg; duke@435: if (addr->index()->is_register()) { duke@435: index = addr->index()->as_register(); duke@435: } duke@435: if ((base == to_lo && index == to_hi) || duke@435: (base == to_hi && index == to_lo)) { duke@435: // addresses with 2 registers are only formed as a result of duke@435: // array access so this code will never have to deal with duke@435: // patches or null checks. duke@435: assert(info == NULL && patch == NULL, "must be"); never@739: __ lea(to_hi, as_Address(addr)); duke@435: __ movl(to_lo, Address(to_hi, 0)); duke@435: __ movl(to_hi, Address(to_hi, BytesPerWord)); duke@435: } else if (base == to_lo || index == to_lo) { duke@435: assert(base != to_hi, "can't be"); duke@435: assert(index == noreg || (index != base && index != to_hi), "can't handle this"); duke@435: __ movl(to_hi, as_Address_hi(addr)); duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, lir_patch_high, base, info); duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: patch_code = lir_patch_low; duke@435: } duke@435: __ movl(to_lo, as_Address_lo(addr)); duke@435: } else { duke@435: assert(index == noreg || (index != base && index != to_lo), "can't handle this"); duke@435: __ movl(to_lo, as_Address_lo(addr)); duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, lir_patch_low, base, info); duke@435: patch = new PatchingStub(_masm, PatchingStub::access_field_id); duke@435: patch_code = lir_patch_high; duke@435: } duke@435: __ movl(to_hi, as_Address_hi(addr)); duke@435: } never@739: #endif // _LP64 duke@435: break; duke@435: } duke@435: duke@435: case T_BOOLEAN: // fall through duke@435: case T_BYTE: { duke@435: Register dest_reg = dest->as_register(); duke@435: assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); duke@435: if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { never@739: __ movsbl(dest_reg, from_addr); duke@435: } else { duke@435: __ movb(dest_reg, from_addr); duke@435: __ shll(dest_reg, 24); duke@435: __ sarl(dest_reg, 24); duke@435: } never@739: // These are unsigned so the zero extension on 64bit is just what we need duke@435: break; duke@435: } duke@435: duke@435: case T_CHAR: { duke@435: Register dest_reg = dest->as_register(); duke@435: assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); duke@435: if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { never@739: __ movzwl(dest_reg, from_addr); duke@435: } else { duke@435: __ movw(dest_reg, from_addr); duke@435: } never@739: // This is unsigned so the zero extension on 64bit is just what we need never@739: // __ movl2ptr(dest_reg, dest_reg); duke@435: break; duke@435: } duke@435: duke@435: case T_SHORT: { duke@435: Register dest_reg = dest->as_register(); duke@435: if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { never@739: __ movswl(dest_reg, from_addr); duke@435: } else { duke@435: __ movw(dest_reg, from_addr); duke@435: __ shll(dest_reg, 16); duke@435: __ sarl(dest_reg, 16); duke@435: } never@739: // Might not be needed in 64bit but certainly doesn't hurt (except for code size) never@739: __ movl2ptr(dest_reg, dest_reg); duke@435: break; duke@435: } duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (patch != NULL) { duke@435: patching_epilog(patch, patch_code, addr->base()->as_register(), info); duke@435: } duke@435: duke@435: if (type == T_ARRAY || type == T_OBJECT) { duke@435: __ verify_oop(dest->as_register()); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::prefetchr(LIR_Opr src) { duke@435: LIR_Address* addr = src->as_address_ptr(); duke@435: Address from_addr = as_Address(addr); duke@435: duke@435: if (VM_Version::supports_sse()) { duke@435: switch (ReadPrefetchInstr) { duke@435: case 0: duke@435: __ prefetchnta(from_addr); break; duke@435: case 1: duke@435: __ prefetcht0(from_addr); break; duke@435: case 2: duke@435: __ prefetcht2(from_addr); break; duke@435: default: duke@435: ShouldNotReachHere(); break; duke@435: } duke@435: } else if (VM_Version::supports_3dnow()) { duke@435: __ prefetchr(from_addr); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::prefetchw(LIR_Opr src) { duke@435: LIR_Address* addr = src->as_address_ptr(); duke@435: Address from_addr = as_Address(addr); duke@435: duke@435: if (VM_Version::supports_sse()) { duke@435: switch (AllocatePrefetchInstr) { duke@435: case 0: duke@435: __ prefetchnta(from_addr); break; duke@435: case 1: duke@435: __ prefetcht0(from_addr); break; duke@435: case 2: duke@435: __ prefetcht2(from_addr); break; duke@435: case 3: duke@435: __ prefetchw(from_addr); break; duke@435: default: duke@435: ShouldNotReachHere(); break; duke@435: } duke@435: } else if (VM_Version::supports_3dnow()) { duke@435: __ prefetchw(from_addr); duke@435: } duke@435: } duke@435: duke@435: duke@435: NEEDS_CLEANUP; // This could be static? duke@435: Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { kvn@464: int elem_size = type2aelembytes(type); duke@435: switch (elem_size) { duke@435: case 1: return Address::times_1; duke@435: case 2: return Address::times_2; duke@435: case 4: return Address::times_4; duke@435: case 8: return Address::times_8; duke@435: } duke@435: ShouldNotReachHere(); duke@435: return Address::no_scale; duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_op3(LIR_Op3* op) { duke@435: switch (op->code()) { duke@435: case lir_idiv: duke@435: case lir_irem: duke@435: arithmetic_idiv(op->code(), duke@435: op->in_opr1(), duke@435: op->in_opr2(), duke@435: op->in_opr3(), duke@435: op->result_opr(), duke@435: op->info()); duke@435: break; duke@435: default: ShouldNotReachHere(); break; duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { duke@435: #ifdef ASSERT duke@435: assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); duke@435: if (op->block() != NULL) _branch_target_blocks.append(op->block()); duke@435: if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); duke@435: #endif duke@435: duke@435: if (op->cond() == lir_cond_always) { duke@435: if (op->info() != NULL) add_debug_info_for_branch(op->info()); duke@435: __ jmp (*(op->label())); duke@435: } else { duke@435: Assembler::Condition acond = Assembler::zero; duke@435: if (op->code() == lir_cond_float_branch) { duke@435: assert(op->ublock() != NULL, "must have unordered successor"); duke@435: __ jcc(Assembler::parity, *(op->ublock()->label())); duke@435: switch(op->cond()) { duke@435: case lir_cond_equal: acond = Assembler::equal; break; duke@435: case lir_cond_notEqual: acond = Assembler::notEqual; break; duke@435: case lir_cond_less: acond = Assembler::below; break; duke@435: case lir_cond_lessEqual: acond = Assembler::belowEqual; break; duke@435: case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; duke@435: case lir_cond_greater: acond = Assembler::above; break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: switch (op->cond()) { duke@435: case lir_cond_equal: acond = Assembler::equal; break; duke@435: case lir_cond_notEqual: acond = Assembler::notEqual; break; duke@435: case lir_cond_less: acond = Assembler::less; break; duke@435: case lir_cond_lessEqual: acond = Assembler::lessEqual; break; duke@435: case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; duke@435: case lir_cond_greater: acond = Assembler::greater; break; duke@435: case lir_cond_belowEqual: acond = Assembler::belowEqual; break; duke@435: case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: __ jcc(acond,*(op->label())); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { duke@435: LIR_Opr src = op->in_opr(); duke@435: LIR_Opr dest = op->result_opr(); duke@435: duke@435: switch (op->bytecode()) { duke@435: case Bytecodes::_i2l: never@739: #ifdef _LP64 never@739: __ movl2ptr(dest->as_register_lo(), src->as_register()); never@739: #else duke@435: move_regs(src->as_register(), dest->as_register_lo()); duke@435: move_regs(src->as_register(), dest->as_register_hi()); duke@435: __ sarl(dest->as_register_hi(), 31); never@739: #endif // LP64 duke@435: break; duke@435: duke@435: case Bytecodes::_l2i: duke@435: move_regs(src->as_register_lo(), dest->as_register()); duke@435: break; duke@435: duke@435: case Bytecodes::_i2b: duke@435: move_regs(src->as_register(), dest->as_register()); duke@435: __ sign_extend_byte(dest->as_register()); duke@435: break; duke@435: duke@435: case Bytecodes::_i2c: duke@435: move_regs(src->as_register(), dest->as_register()); duke@435: __ andl(dest->as_register(), 0xFFFF); duke@435: break; duke@435: duke@435: case Bytecodes::_i2s: duke@435: move_regs(src->as_register(), dest->as_register()); duke@435: __ sign_extend_short(dest->as_register()); duke@435: break; duke@435: duke@435: duke@435: case Bytecodes::_f2d: duke@435: case Bytecodes::_d2f: duke@435: if (dest->is_single_xmm()) { duke@435: __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); duke@435: } else if (dest->is_double_xmm()) { duke@435: __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); duke@435: } else { duke@435: assert(src->fpu() == dest->fpu(), "register must be equal"); duke@435: // do nothing (float result is rounded later through spilling) duke@435: } duke@435: break; duke@435: duke@435: case Bytecodes::_i2f: duke@435: case Bytecodes::_i2d: duke@435: if (dest->is_single_xmm()) { never@739: __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); duke@435: } else if (dest->is_double_xmm()) { never@739: __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); duke@435: } else { duke@435: assert(dest->fpu() == 0, "result must be on TOS"); duke@435: __ movl(Address(rsp, 0), src->as_register()); duke@435: __ fild_s(Address(rsp, 0)); duke@435: } duke@435: break; duke@435: duke@435: case Bytecodes::_f2i: duke@435: case Bytecodes::_d2i: duke@435: if (src->is_single_xmm()) { never@739: __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); duke@435: } else if (src->is_double_xmm()) { never@739: __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); duke@435: } else { duke@435: assert(src->fpu() == 0, "input must be on TOS"); duke@435: __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); duke@435: __ fist_s(Address(rsp, 0)); duke@435: __ movl(dest->as_register(), Address(rsp, 0)); duke@435: __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); duke@435: } duke@435: duke@435: // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub duke@435: assert(op->stub() != NULL, "stub required"); duke@435: __ cmpl(dest->as_register(), 0x80000000); duke@435: __ jcc(Assembler::equal, *op->stub()->entry()); duke@435: __ bind(*op->stub()->continuation()); duke@435: break; duke@435: duke@435: case Bytecodes::_l2f: duke@435: case Bytecodes::_l2d: duke@435: assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); duke@435: assert(dest->fpu() == 0, "result must be on TOS"); duke@435: never@739: __ movptr(Address(rsp, 0), src->as_register_lo()); never@739: NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); duke@435: __ fild_d(Address(rsp, 0)); duke@435: // float result is rounded later through spilling duke@435: break; duke@435: duke@435: case Bytecodes::_f2l: duke@435: case Bytecodes::_d2l: duke@435: assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); duke@435: assert(src->fpu() == 0, "input must be on TOS"); never@739: assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); duke@435: duke@435: // instruction sequence too long to inline it here duke@435: { duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); duke@435: } duke@435: break; duke@435: duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { duke@435: if (op->init_check()) { duke@435: __ cmpl(Address(op->klass()->as_register(), duke@435: instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), duke@435: instanceKlass::fully_initialized); duke@435: add_debug_info_for_null_check_here(op->stub()->info()); duke@435: __ jcc(Assembler::notEqual, *op->stub()->entry()); duke@435: } duke@435: __ allocate_object(op->obj()->as_register(), duke@435: op->tmp1()->as_register(), duke@435: op->tmp2()->as_register(), duke@435: op->header_size(), duke@435: op->object_size(), duke@435: op->klass()->as_register(), duke@435: *op->stub()->entry()); duke@435: __ bind(*op->stub()->continuation()); duke@435: } duke@435: duke@435: void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { duke@435: if (UseSlowPath || duke@435: (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || duke@435: (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { duke@435: __ jmp(*op->stub()->entry()); duke@435: } else { duke@435: Register len = op->len()->as_register(); duke@435: Register tmp1 = op->tmp1()->as_register(); duke@435: Register tmp2 = op->tmp2()->as_register(); duke@435: Register tmp3 = op->tmp3()->as_register(); duke@435: if (len == tmp1) { duke@435: tmp1 = tmp3; duke@435: } else if (len == tmp2) { duke@435: tmp2 = tmp3; duke@435: } else if (len == tmp3) { duke@435: // everything is ok duke@435: } else { never@739: __ mov(tmp3, len); duke@435: } duke@435: __ allocate_array(op->obj()->as_register(), duke@435: len, duke@435: tmp1, duke@435: tmp2, duke@435: arrayOopDesc::header_size(op->type()), duke@435: array_element_size(op->type()), duke@435: op->klass()->as_register(), duke@435: *op->stub()->entry()); duke@435: } duke@435: __ bind(*op->stub()->continuation()); duke@435: } duke@435: duke@435: duke@435: duke@435: void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { duke@435: LIR_Code code = op->code(); duke@435: if (code == lir_store_check) { duke@435: Register value = op->object()->as_register(); duke@435: Register array = op->array()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register Rtmp1 = op->tmp3()->as_register(); duke@435: duke@435: CodeStub* stub = op->stub(); duke@435: Label done; never@739: __ cmpptr(value, (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, done); duke@435: add_debug_info_for_null_check_here(op->info_for_exception()); never@739: __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); never@739: __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); duke@435: duke@435: // get instance klass never@739: __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); jrose@1079: // perform the fast part of the checking logic jrose@1079: __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); jrose@1079: // call out-of-line instance of __ check_klass_subtype_slow_path(...): never@739: __ push(klass_RInfo); never@739: __ push(k_RInfo); duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); never@739: __ pop(klass_RInfo); never@739: __ pop(k_RInfo); never@739: // result is a boolean duke@435: __ cmpl(k_RInfo, 0); duke@435: __ jcc(Assembler::equal, *stub->entry()); duke@435: __ bind(done); duke@435: } else if (op->code() == lir_checkcast) { duke@435: // we always need a stub for the failure case. duke@435: CodeStub* stub = op->stub(); duke@435: Register obj = op->object()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register dst = op->result_opr()->as_register(); duke@435: ciKlass* k = op->klass(); duke@435: Register Rtmp1 = noreg; duke@435: duke@435: Label done; duke@435: if (obj == k_RInfo) { duke@435: k_RInfo = dst; duke@435: } else if (obj == klass_RInfo) { duke@435: klass_RInfo = dst; duke@435: } duke@435: if (k->is_loaded()) { duke@435: select_different_registers(obj, dst, k_RInfo, klass_RInfo); duke@435: } else { duke@435: Rtmp1 = op->tmp3()->as_register(); duke@435: select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); duke@435: } duke@435: duke@435: assert_different_registers(obj, k_RInfo, klass_RInfo); duke@435: if (!k->is_loaded()) { duke@435: jobject2reg_with_patching(k_RInfo, op->info_for_patch()); duke@435: } else { never@739: #ifdef _LP64 jrose@1424: __ movoop(k_RInfo, k->constant_encoding()); never@739: #else duke@435: k_RInfo = noreg; never@739: #endif // _LP64 duke@435: } duke@435: assert(obj != k_RInfo, "must be different"); never@739: __ cmpptr(obj, (int32_t)NULL_WORD); duke@435: if (op->profiled_method() != NULL) { duke@435: ciMethod* method = op->profiled_method(); duke@435: int bci = op->profiled_bci(); duke@435: duke@435: Label profile_done; duke@435: __ jcc(Assembler::notEqual, profile_done); duke@435: // Object is null; update methodDataOop duke@435: ciMethodData* md = method->method_data(); duke@435: if (md == NULL) { duke@435: bailout("out of memory building methodDataOop"); duke@435: return; duke@435: } duke@435: ciProfileData* data = md->bci_to_data(bci); duke@435: assert(data != NULL, "need data for checkcast"); duke@435: assert(data->is_BitData(), "need BitData for checkcast"); duke@435: Register mdo = klass_RInfo; jrose@1424: __ movoop(mdo, md->constant_encoding()); duke@435: Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); duke@435: int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); duke@435: __ orl(data_addr, header_bits); duke@435: __ jmp(done); duke@435: __ bind(profile_done); duke@435: } else { duke@435: __ jcc(Assembler::equal, done); duke@435: } duke@435: __ verify_oop(obj); duke@435: duke@435: if (op->fast_check()) { duke@435: // get object classo duke@435: // not a safepoint as obj null check happens earlier duke@435: if (k->is_loaded()) { never@739: #ifdef _LP64 never@739: __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); never@739: #else jrose@1424: __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); never@739: #endif // _LP64 duke@435: } else { never@739: __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); duke@435: duke@435: } duke@435: __ jcc(Assembler::notEqual, *stub->entry()); duke@435: __ bind(done); duke@435: } else { duke@435: // get object class duke@435: // not a safepoint as obj null check happens earlier never@739: __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); duke@435: if (k->is_loaded()) { duke@435: // See if we get an immediate positive hit never@739: #ifdef _LP64 never@739: __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); never@739: #else jrose@1424: __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); never@739: #endif // _LP64 duke@435: if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { duke@435: __ jcc(Assembler::notEqual, *stub->entry()); duke@435: } else { duke@435: // See if we get an immediate positive hit duke@435: __ jcc(Assembler::equal, done); duke@435: // check for self never@739: #ifdef _LP64 never@739: __ cmpptr(klass_RInfo, k_RInfo); never@739: #else jrose@1424: __ cmpoop(klass_RInfo, k->constant_encoding()); never@739: #endif // _LP64 duke@435: __ jcc(Assembler::equal, done); duke@435: never@739: __ push(klass_RInfo); never@739: #ifdef _LP64 never@739: __ push(k_RInfo); never@739: #else jrose@1424: __ pushoop(k->constant_encoding()); never@739: #endif // _LP64 duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); never@739: __ pop(klass_RInfo); never@739: __ pop(klass_RInfo); never@739: // result is a boolean duke@435: __ cmpl(klass_RInfo, 0); duke@435: __ jcc(Assembler::equal, *stub->entry()); duke@435: } duke@435: __ bind(done); duke@435: } else { jrose@1079: // perform the fast part of the checking logic jrose@1079: __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); jrose@1079: // call out-of-line instance of __ check_klass_subtype_slow_path(...): never@739: __ push(klass_RInfo); never@739: __ push(k_RInfo); duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); never@739: __ pop(klass_RInfo); never@739: __ pop(k_RInfo); never@739: // result is a boolean duke@435: __ cmpl(k_RInfo, 0); duke@435: __ jcc(Assembler::equal, *stub->entry()); duke@435: __ bind(done); duke@435: } duke@435: duke@435: } duke@435: if (dst != obj) { never@739: __ mov(dst, obj); duke@435: } duke@435: } else if (code == lir_instanceof) { duke@435: Register obj = op->object()->as_register(); duke@435: Register k_RInfo = op->tmp1()->as_register(); duke@435: Register klass_RInfo = op->tmp2()->as_register(); duke@435: Register dst = op->result_opr()->as_register(); duke@435: ciKlass* k = op->klass(); duke@435: duke@435: Label done; duke@435: Label zero; duke@435: Label one; duke@435: if (obj == k_RInfo) { duke@435: k_RInfo = klass_RInfo; duke@435: klass_RInfo = obj; duke@435: } duke@435: // patching may screw with our temporaries on sparc, duke@435: // so let's do it before loading the class duke@435: if (!k->is_loaded()) { duke@435: jobject2reg_with_patching(k_RInfo, op->info_for_patch()); never@739: } else { jrose@1424: LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); duke@435: } duke@435: assert(obj != k_RInfo, "must be different"); duke@435: duke@435: __ verify_oop(obj); duke@435: if (op->fast_check()) { never@739: __ cmpptr(obj, (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, zero); duke@435: // get object class duke@435: // not a safepoint as obj null check happens earlier never@739: if (LP64_ONLY(false &&) k->is_loaded()) { jrose@1424: NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); duke@435: k_RInfo = noreg; duke@435: } else { never@739: __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); duke@435: duke@435: } duke@435: __ jcc(Assembler::equal, one); duke@435: } else { duke@435: // get object class duke@435: // not a safepoint as obj null check happens earlier never@739: __ cmpptr(obj, (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::equal, zero); never@739: __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); never@739: never@739: #ifndef _LP64 duke@435: if (k->is_loaded()) { duke@435: // See if we get an immediate positive hit jrose@1424: __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); duke@435: __ jcc(Assembler::equal, one); duke@435: if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { duke@435: // check for self jrose@1424: __ cmpoop(klass_RInfo, k->constant_encoding()); duke@435: __ jcc(Assembler::equal, one); never@739: __ push(klass_RInfo); jrose@1424: __ pushoop(k->constant_encoding()); duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); never@739: __ pop(klass_RInfo); never@739: __ pop(dst); duke@435: __ jmp(done); duke@435: } jrose@1079: } jrose@1079: else // next block is unconditional if LP64: never@739: #endif // LP64 jrose@1079: { duke@435: assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); duke@435: jrose@1079: // perform the fast part of the checking logic jrose@1079: __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); jrose@1079: // call out-of-line instance of __ check_klass_subtype_slow_path(...): never@739: __ push(klass_RInfo); never@739: __ push(k_RInfo); duke@435: __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); never@739: __ pop(klass_RInfo); never@739: __ pop(dst); duke@435: __ jmp(done); duke@435: } duke@435: } duke@435: __ bind(zero); never@739: __ xorptr(dst, dst); duke@435: __ jmp(done); duke@435: __ bind(one); never@739: __ movptr(dst, 1); duke@435: __ bind(done); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { never@739: if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { duke@435: assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); duke@435: assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); duke@435: assert(op->new_value()->as_register_lo() == rbx, "wrong register"); duke@435: assert(op->new_value()->as_register_hi() == rcx, "wrong register"); duke@435: Register addr = op->addr()->as_register(); duke@435: if (os::is_MP()) { duke@435: __ lock(); duke@435: } never@739: NOT_LP64(__ cmpxchg8(Address(addr, 0))); never@739: never@739: } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { never@739: NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) never@739: Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); duke@435: Register newval = op->new_value()->as_register(); duke@435: Register cmpval = op->cmp_value()->as_register(); duke@435: assert(cmpval == rax, "wrong register"); duke@435: assert(newval != NULL, "new val must be register"); duke@435: assert(cmpval != newval, "cmp and new values must be in different registers"); duke@435: assert(cmpval != addr, "cmp and addr must be in different registers"); duke@435: assert(newval != addr, "new value and addr must be in different registers"); duke@435: if (os::is_MP()) { duke@435: __ lock(); duke@435: } never@739: if ( op->code() == lir_cas_obj) { never@739: __ cmpxchgptr(newval, Address(addr, 0)); never@739: } else if (op->code() == lir_cas_int) { never@739: __ cmpxchgl(newval, Address(addr, 0)); never@739: } else { never@739: LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); never@739: } never@739: #ifdef _LP64 never@739: } else if (op->code() == lir_cas_long) { never@739: Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); never@739: Register newval = op->new_value()->as_register_lo(); never@739: Register cmpval = op->cmp_value()->as_register_lo(); never@739: assert(cmpval == rax, "wrong register"); never@739: assert(newval != NULL, "new val must be register"); never@739: assert(cmpval != newval, "cmp and new values must be in different registers"); never@739: assert(cmpval != addr, "cmp and addr must be in different registers"); never@739: assert(newval != addr, "new value and addr must be in different registers"); never@739: if (os::is_MP()) { never@739: __ lock(); never@739: } never@739: __ cmpxchgq(newval, Address(addr, 0)); never@739: #endif // _LP64 duke@435: } else { duke@435: Unimplemented(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { duke@435: Assembler::Condition acond, ncond; duke@435: switch (condition) { duke@435: case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; duke@435: case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; duke@435: case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; duke@435: case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; duke@435: case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; duke@435: case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; duke@435: case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; duke@435: case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (opr1->is_cpu_register()) { duke@435: reg2reg(opr1, result); duke@435: } else if (opr1->is_stack()) { duke@435: stack2reg(opr1, result, result->type()); duke@435: } else if (opr1->is_constant()) { duke@435: const2reg(opr1, result, lir_patch_none, NULL); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (VM_Version::supports_cmov() && !opr2->is_constant()) { duke@435: // optimized version that does not require a branch duke@435: if (opr2->is_single_cpu()) { duke@435: assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); never@739: __ cmov(ncond, result->as_register(), opr2->as_register()); duke@435: } else if (opr2->is_double_cpu()) { duke@435: assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); duke@435: assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); never@739: __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); never@739: NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) duke@435: } else if (opr2->is_single_stack()) { duke@435: __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); duke@435: } else if (opr2->is_double_stack()) { never@739: __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); never@739: NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else { duke@435: Label skip; duke@435: __ jcc (acond, skip); duke@435: if (opr2->is_cpu_register()) { duke@435: reg2reg(opr2, result); duke@435: } else if (opr2->is_stack()) { duke@435: stack2reg(opr2, result, result->type()); duke@435: } else if (opr2->is_constant()) { duke@435: const2reg(opr2, result, lir_patch_none, NULL); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: __ bind(skip); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { duke@435: assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); duke@435: duke@435: if (left->is_single_cpu()) { duke@435: assert(left == dest, "left and dest must be equal"); duke@435: Register lreg = left->as_register(); duke@435: duke@435: if (right->is_single_cpu()) { duke@435: // cpu register - cpu register duke@435: Register rreg = right->as_register(); duke@435: switch (code) { duke@435: case lir_add: __ addl (lreg, rreg); break; duke@435: case lir_sub: __ subl (lreg, rreg); break; duke@435: case lir_mul: __ imull(lreg, rreg); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (right->is_stack()) { duke@435: // cpu register - stack duke@435: Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); duke@435: switch (code) { duke@435: case lir_add: __ addl(lreg, raddr); break; duke@435: case lir_sub: __ subl(lreg, raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (right->is_constant()) { duke@435: // cpu register - constant duke@435: jint c = right->as_constant_ptr()->as_jint(); duke@435: switch (code) { duke@435: case lir_add: { duke@435: __ increment(lreg, c); duke@435: break; duke@435: } duke@435: case lir_sub: { duke@435: __ decrement(lreg, c); duke@435: break; duke@435: } duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (left->is_double_cpu()) { duke@435: assert(left == dest, "left and dest must be equal"); duke@435: Register lreg_lo = left->as_register_lo(); duke@435: Register lreg_hi = left->as_register_hi(); duke@435: duke@435: if (right->is_double_cpu()) { duke@435: // cpu register - cpu register duke@435: Register rreg_lo = right->as_register_lo(); duke@435: Register rreg_hi = right->as_register_hi(); never@739: NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); never@739: LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); duke@435: switch (code) { duke@435: case lir_add: never@739: __ addptr(lreg_lo, rreg_lo); never@739: NOT_LP64(__ adcl(lreg_hi, rreg_hi)); duke@435: break; duke@435: case lir_sub: never@739: __ subptr(lreg_lo, rreg_lo); never@739: NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); duke@435: break; duke@435: case lir_mul: never@739: #ifdef _LP64 never@739: __ imulq(lreg_lo, rreg_lo); never@739: #else duke@435: assert(lreg_lo == rax && lreg_hi == rdx, "must be"); duke@435: __ imull(lreg_hi, rreg_lo); duke@435: __ imull(rreg_hi, lreg_lo); duke@435: __ addl (rreg_hi, lreg_hi); duke@435: __ mull (rreg_lo); duke@435: __ addl (lreg_hi, rreg_hi); never@739: #endif // _LP64 duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (right->is_constant()) { duke@435: // cpu register - constant never@739: #ifdef _LP64 never@739: jlong c = right->as_constant_ptr()->as_jlong_bits(); never@739: __ movptr(r10, (intptr_t) c); never@739: switch (code) { never@739: case lir_add: never@739: __ addptr(lreg_lo, r10); never@739: break; never@739: case lir_sub: never@739: __ subptr(lreg_lo, r10); never@739: break; never@739: default: never@739: ShouldNotReachHere(); never@739: } never@739: #else duke@435: jint c_lo = right->as_constant_ptr()->as_jint_lo(); duke@435: jint c_hi = right->as_constant_ptr()->as_jint_hi(); duke@435: switch (code) { duke@435: case lir_add: never@739: __ addptr(lreg_lo, c_lo); duke@435: __ adcl(lreg_hi, c_hi); duke@435: break; duke@435: case lir_sub: never@739: __ subptr(lreg_lo, c_lo); duke@435: __ sbbl(lreg_hi, c_hi); duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } never@739: #endif // _LP64 duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (left->is_single_xmm()) { duke@435: assert(left == dest, "left and dest must be equal"); duke@435: XMMRegister lreg = left->as_xmm_float_reg(); duke@435: duke@435: if (right->is_single_xmm()) { duke@435: XMMRegister rreg = right->as_xmm_float_reg(); duke@435: switch (code) { duke@435: case lir_add: __ addss(lreg, rreg); break; duke@435: case lir_sub: __ subss(lreg, rreg); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ mulss(lreg, rreg); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ divss(lreg, rreg); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Address raddr; duke@435: if (right->is_single_stack()) { duke@435: raddr = frame_map()->address_for_slot(right->single_stack_ix()); duke@435: } else if (right->is_constant()) { duke@435: // hack for now duke@435: raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: switch (code) { duke@435: case lir_add: __ addss(lreg, raddr); break; duke@435: case lir_sub: __ subss(lreg, raddr); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ mulss(lreg, raddr); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ divss(lreg, raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: } else if (left->is_double_xmm()) { duke@435: assert(left == dest, "left and dest must be equal"); duke@435: duke@435: XMMRegister lreg = left->as_xmm_double_reg(); duke@435: if (right->is_double_xmm()) { duke@435: XMMRegister rreg = right->as_xmm_double_reg(); duke@435: switch (code) { duke@435: case lir_add: __ addsd(lreg, rreg); break; duke@435: case lir_sub: __ subsd(lreg, rreg); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ mulsd(lreg, rreg); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ divsd(lreg, rreg); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Address raddr; duke@435: if (right->is_double_stack()) { duke@435: raddr = frame_map()->address_for_slot(right->double_stack_ix()); duke@435: } else if (right->is_constant()) { duke@435: // hack for now duke@435: raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: switch (code) { duke@435: case lir_add: __ addsd(lreg, raddr); break; duke@435: case lir_sub: __ subsd(lreg, raddr); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ mulsd(lreg, raddr); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ divsd(lreg, raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: } else if (left->is_single_fpu()) { duke@435: assert(dest->is_single_fpu(), "fpu stack allocation required"); duke@435: duke@435: if (right->is_single_fpu()) { duke@435: arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); duke@435: duke@435: } else { duke@435: assert(left->fpu_regnr() == 0, "left must be on TOS"); duke@435: assert(dest->fpu_regnr() == 0, "dest must be on TOS"); duke@435: duke@435: Address raddr; duke@435: if (right->is_single_stack()) { duke@435: raddr = frame_map()->address_for_slot(right->single_stack_ix()); duke@435: } else if (right->is_constant()) { duke@435: address const_addr = float_constant(right->as_jfloat()); duke@435: assert(const_addr != NULL, "incorrect float/double constant maintainance"); duke@435: // hack for now duke@435: raddr = __ as_Address(InternalAddress(const_addr)); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: switch (code) { duke@435: case lir_add: __ fadd_s(raddr); break; duke@435: case lir_sub: __ fsub_s(raddr); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ fmul_s(raddr); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ fdiv_s(raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: } else if (left->is_double_fpu()) { duke@435: assert(dest->is_double_fpu(), "fpu stack allocation required"); duke@435: duke@435: if (code == lir_mul_strictfp || code == lir_div_strictfp) { duke@435: // Double values require special handling for strictfp mul/div on x86 duke@435: __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); duke@435: __ fmulp(left->fpu_regnrLo() + 1); duke@435: } duke@435: duke@435: if (right->is_double_fpu()) { duke@435: arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); duke@435: duke@435: } else { duke@435: assert(left->fpu_regnrLo() == 0, "left must be on TOS"); duke@435: assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); duke@435: duke@435: Address raddr; duke@435: if (right->is_double_stack()) { duke@435: raddr = frame_map()->address_for_slot(right->double_stack_ix()); duke@435: } else if (right->is_constant()) { duke@435: // hack for now duke@435: raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: switch (code) { duke@435: case lir_add: __ fadd_d(raddr); break; duke@435: case lir_sub: __ fsub_d(raddr); break; duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: __ fmul_d(raddr); break; duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: __ fdiv_d(raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: if (code == lir_mul_strictfp || code == lir_div_strictfp) { duke@435: // Double values require special handling for strictfp mul/div on x86 duke@435: __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); duke@435: __ fmulp(dest->fpu_regnrLo() + 1); duke@435: } duke@435: duke@435: } else if (left->is_single_stack() || left->is_address()) { duke@435: assert(left == dest, "left and dest must be equal"); duke@435: duke@435: Address laddr; duke@435: if (left->is_single_stack()) { duke@435: laddr = frame_map()->address_for_slot(left->single_stack_ix()); duke@435: } else if (left->is_address()) { duke@435: laddr = as_Address(left->as_address_ptr()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: if (right->is_single_cpu()) { duke@435: Register rreg = right->as_register(); duke@435: switch (code) { duke@435: case lir_add: __ addl(laddr, rreg); break; duke@435: case lir_sub: __ subl(laddr, rreg); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else if (right->is_constant()) { duke@435: jint c = right->as_constant_ptr()->as_jint(); duke@435: switch (code) { duke@435: case lir_add: { never@739: __ incrementl(laddr, c); duke@435: break; duke@435: } duke@435: case lir_sub: { never@739: __ decrementl(laddr, c); duke@435: break; duke@435: } duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { duke@435: assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); duke@435: assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); duke@435: assert(left_index == 0 || right_index == 0, "either must be on top of stack"); duke@435: duke@435: bool left_is_tos = (left_index == 0); duke@435: bool dest_is_tos = (dest_index == 0); duke@435: int non_tos_index = (left_is_tos ? right_index : left_index); duke@435: duke@435: switch (code) { duke@435: case lir_add: duke@435: if (pop_fpu_stack) __ faddp(non_tos_index); duke@435: else if (dest_is_tos) __ fadd (non_tos_index); duke@435: else __ fadda(non_tos_index); duke@435: break; duke@435: duke@435: case lir_sub: duke@435: if (left_is_tos) { duke@435: if (pop_fpu_stack) __ fsubrp(non_tos_index); duke@435: else if (dest_is_tos) __ fsub (non_tos_index); duke@435: else __ fsubra(non_tos_index); duke@435: } else { duke@435: if (pop_fpu_stack) __ fsubp (non_tos_index); duke@435: else if (dest_is_tos) __ fsubr (non_tos_index); duke@435: else __ fsuba (non_tos_index); duke@435: } duke@435: break; duke@435: duke@435: case lir_mul_strictfp: // fall through duke@435: case lir_mul: duke@435: if (pop_fpu_stack) __ fmulp(non_tos_index); duke@435: else if (dest_is_tos) __ fmul (non_tos_index); duke@435: else __ fmula(non_tos_index); duke@435: break; duke@435: duke@435: case lir_div_strictfp: // fall through duke@435: case lir_div: duke@435: if (left_is_tos) { duke@435: if (pop_fpu_stack) __ fdivrp(non_tos_index); duke@435: else if (dest_is_tos) __ fdiv (non_tos_index); duke@435: else __ fdivra(non_tos_index); duke@435: } else { duke@435: if (pop_fpu_stack) __ fdivp (non_tos_index); duke@435: else if (dest_is_tos) __ fdivr (non_tos_index); duke@435: else __ fdiva (non_tos_index); duke@435: } duke@435: break; duke@435: duke@435: case lir_rem: duke@435: assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); duke@435: __ fremr(noreg); duke@435: break; duke@435: duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { duke@435: if (value->is_double_xmm()) { duke@435: switch(code) { duke@435: case lir_abs : duke@435: { duke@435: if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { duke@435: __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); duke@435: } duke@435: __ andpd(dest->as_xmm_double_reg(), duke@435: ExternalAddress((address)double_signmask_pool)); duke@435: } duke@435: break; duke@435: duke@435: case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; duke@435: // all other intrinsics are not available in the SSE instruction set, so FPU is used duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (value->is_double_fpu()) { duke@435: assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); duke@435: switch(code) { duke@435: case lir_log : __ flog() ; break; duke@435: case lir_log10 : __ flog10() ; break; duke@435: case lir_abs : __ fabs() ; break; duke@435: case lir_sqrt : __ fsqrt(); break; duke@435: case lir_sin : duke@435: // Should consider not saving rbx, if not necessary duke@435: __ trigfunc('s', op->as_Op2()->fpu_stack_size()); duke@435: break; duke@435: case lir_cos : duke@435: // Should consider not saving rbx, if not necessary duke@435: assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); duke@435: __ trigfunc('c', op->as_Op2()->fpu_stack_size()); duke@435: break; duke@435: case lir_tan : duke@435: // Should consider not saving rbx, if not necessary duke@435: __ trigfunc('t', op->as_Op2()->fpu_stack_size()); duke@435: break; duke@435: default : ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Unimplemented(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { duke@435: // assert(left->destroys_register(), "check"); duke@435: if (left->is_single_cpu()) { duke@435: Register reg = left->as_register(); duke@435: if (right->is_constant()) { duke@435: int val = right->as_constant_ptr()->as_jint(); duke@435: switch (code) { duke@435: case lir_logic_and: __ andl (reg, val); break; duke@435: case lir_logic_or: __ orl (reg, val); break; duke@435: case lir_logic_xor: __ xorl (reg, val); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else if (right->is_stack()) { duke@435: // added support for stack operands duke@435: Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); duke@435: switch (code) { duke@435: case lir_logic_and: __ andl (reg, raddr); break; duke@435: case lir_logic_or: __ orl (reg, raddr); break; duke@435: case lir_logic_xor: __ xorl (reg, raddr); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Register rright = right->as_register(); duke@435: switch (code) { never@739: case lir_logic_and: __ andptr (reg, rright); break; never@739: case lir_logic_or : __ orptr (reg, rright); break; never@739: case lir_logic_xor: __ xorptr (reg, rright); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: move_regs(reg, dst->as_register()); duke@435: } else { duke@435: Register l_lo = left->as_register_lo(); duke@435: Register l_hi = left->as_register_hi(); duke@435: if (right->is_constant()) { never@739: #ifdef _LP64 never@739: __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); never@739: switch (code) { never@739: case lir_logic_and: never@739: __ andq(l_lo, rscratch1); never@739: break; never@739: case lir_logic_or: never@739: __ orq(l_lo, rscratch1); never@739: break; never@739: case lir_logic_xor: never@739: __ xorq(l_lo, rscratch1); never@739: break; never@739: default: ShouldNotReachHere(); never@739: } never@739: #else duke@435: int r_lo = right->as_constant_ptr()->as_jint_lo(); duke@435: int r_hi = right->as_constant_ptr()->as_jint_hi(); duke@435: switch (code) { duke@435: case lir_logic_and: duke@435: __ andl(l_lo, r_lo); duke@435: __ andl(l_hi, r_hi); duke@435: break; duke@435: case lir_logic_or: duke@435: __ orl(l_lo, r_lo); duke@435: __ orl(l_hi, r_hi); duke@435: break; duke@435: case lir_logic_xor: duke@435: __ xorl(l_lo, r_lo); duke@435: __ xorl(l_hi, r_hi); duke@435: break; duke@435: default: ShouldNotReachHere(); duke@435: } never@739: #endif // _LP64 duke@435: } else { duke@435: Register r_lo = right->as_register_lo(); duke@435: Register r_hi = right->as_register_hi(); duke@435: assert(l_lo != r_hi, "overwriting registers"); duke@435: switch (code) { duke@435: case lir_logic_and: never@739: __ andptr(l_lo, r_lo); never@739: NOT_LP64(__ andptr(l_hi, r_hi);) duke@435: break; duke@435: case lir_logic_or: never@739: __ orptr(l_lo, r_lo); never@739: NOT_LP64(__ orptr(l_hi, r_hi);) duke@435: break; duke@435: case lir_logic_xor: never@739: __ xorptr(l_lo, r_lo); never@739: NOT_LP64(__ xorptr(l_hi, r_hi);) duke@435: break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: Register dst_lo = dst->as_register_lo(); duke@435: Register dst_hi = dst->as_register_hi(); duke@435: never@739: #ifdef _LP64 never@739: move_regs(l_lo, dst_lo); never@739: #else duke@435: if (dst_lo == l_hi) { duke@435: assert(dst_hi != l_lo, "overwriting registers"); duke@435: move_regs(l_hi, dst_hi); duke@435: move_regs(l_lo, dst_lo); duke@435: } else { duke@435: assert(dst_lo != l_hi, "overwriting registers"); duke@435: move_regs(l_lo, dst_lo); duke@435: move_regs(l_hi, dst_hi); duke@435: } never@739: #endif // _LP64 duke@435: } duke@435: } duke@435: duke@435: duke@435: // we assume that rax, and rdx can be overwritten duke@435: void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { duke@435: duke@435: assert(left->is_single_cpu(), "left must be register"); duke@435: assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); duke@435: assert(result->is_single_cpu(), "result must be register"); duke@435: duke@435: // assert(left->destroys_register(), "check"); duke@435: // assert(right->destroys_register(), "check"); duke@435: duke@435: Register lreg = left->as_register(); duke@435: Register dreg = result->as_register(); duke@435: duke@435: if (right->is_constant()) { duke@435: int divisor = right->as_constant_ptr()->as_jint(); duke@435: assert(divisor > 0 && is_power_of_2(divisor), "must be"); duke@435: if (code == lir_idiv) { duke@435: assert(lreg == rax, "must be rax,"); duke@435: assert(temp->as_register() == rdx, "tmp register must be rdx"); duke@435: __ cdql(); // sign extend into rdx:rax duke@435: if (divisor == 2) { duke@435: __ subl(lreg, rdx); duke@435: } else { duke@435: __ andl(rdx, divisor - 1); duke@435: __ addl(lreg, rdx); duke@435: } duke@435: __ sarl(lreg, log2_intptr(divisor)); duke@435: move_regs(lreg, dreg); duke@435: } else if (code == lir_irem) { duke@435: Label done; never@739: __ mov(dreg, lreg); duke@435: __ andl(dreg, 0x80000000 | (divisor - 1)); duke@435: __ jcc(Assembler::positive, done); duke@435: __ decrement(dreg); duke@435: __ orl(dreg, ~(divisor - 1)); duke@435: __ increment(dreg); duke@435: __ bind(done); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: Register rreg = right->as_register(); duke@435: assert(lreg == rax, "left register must be rax,"); duke@435: assert(rreg != rdx, "right register must not be rdx"); duke@435: assert(temp->as_register() == rdx, "tmp register must be rdx"); duke@435: duke@435: move_regs(lreg, rax); duke@435: duke@435: int idivl_offset = __ corrected_idivl(rreg); duke@435: add_debug_info_for_div0(idivl_offset, info); duke@435: if (code == lir_irem) { duke@435: move_regs(rdx, dreg); // result is in rdx duke@435: } else { duke@435: move_regs(rax, dreg); duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { duke@435: if (opr1->is_single_cpu()) { duke@435: Register reg1 = opr1->as_register(); duke@435: if (opr2->is_single_cpu()) { duke@435: // cpu register - cpu register never@739: if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { never@739: __ cmpptr(reg1, opr2->as_register()); never@739: } else { never@739: assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); never@739: __ cmpl(reg1, opr2->as_register()); never@739: } duke@435: } else if (opr2->is_stack()) { duke@435: // cpu register - stack never@739: if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { never@739: __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); never@739: } else { never@739: __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); never@739: } duke@435: } else if (opr2->is_constant()) { duke@435: // cpu register - constant duke@435: LIR_Const* c = opr2->as_constant_ptr(); duke@435: if (c->type() == T_INT) { duke@435: __ cmpl(reg1, c->as_jint()); never@739: } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { never@739: // In 64bit oops are single register duke@435: jobject o = c->as_jobject(); duke@435: if (o == NULL) { never@739: __ cmpptr(reg1, (int32_t)NULL_WORD); duke@435: } else { never@739: #ifdef _LP64 never@739: __ movoop(rscratch1, o); never@739: __ cmpptr(reg1, rscratch1); never@739: #else duke@435: __ cmpoop(reg1, c->as_jobject()); never@739: #endif // _LP64 duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: // cpu register - address duke@435: } else if (opr2->is_address()) { duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check_here(op->info()); duke@435: } duke@435: __ cmpl(reg1, as_Address(opr2->as_address_ptr())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if(opr1->is_double_cpu()) { duke@435: Register xlo = opr1->as_register_lo(); duke@435: Register xhi = opr1->as_register_hi(); duke@435: if (opr2->is_double_cpu()) { never@739: #ifdef _LP64 never@739: __ cmpptr(xlo, opr2->as_register_lo()); never@739: #else duke@435: // cpu register - cpu register duke@435: Register ylo = opr2->as_register_lo(); duke@435: Register yhi = opr2->as_register_hi(); duke@435: __ subl(xlo, ylo); duke@435: __ sbbl(xhi, yhi); duke@435: if (condition == lir_cond_equal || condition == lir_cond_notEqual) { duke@435: __ orl(xhi, xlo); duke@435: } never@739: #endif // _LP64 duke@435: } else if (opr2->is_constant()) { duke@435: // cpu register - constant 0 duke@435: assert(opr2->as_jlong() == (jlong)0, "only handles zero"); never@739: #ifdef _LP64 never@739: __ cmpptr(xlo, (int32_t)opr2->as_jlong()); never@739: #else duke@435: assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); duke@435: __ orl(xhi, xlo); never@739: #endif // _LP64 duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (opr1->is_single_xmm()) { duke@435: XMMRegister reg1 = opr1->as_xmm_float_reg(); duke@435: if (opr2->is_single_xmm()) { duke@435: // xmm register - xmm register duke@435: __ ucomiss(reg1, opr2->as_xmm_float_reg()); duke@435: } else if (opr2->is_stack()) { duke@435: // xmm register - stack duke@435: __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); duke@435: } else if (opr2->is_constant()) { duke@435: // xmm register - constant duke@435: __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); duke@435: } else if (opr2->is_address()) { duke@435: // xmm register - address duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check_here(op->info()); duke@435: } duke@435: __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (opr1->is_double_xmm()) { duke@435: XMMRegister reg1 = opr1->as_xmm_double_reg(); duke@435: if (opr2->is_double_xmm()) { duke@435: // xmm register - xmm register duke@435: __ ucomisd(reg1, opr2->as_xmm_double_reg()); duke@435: } else if (opr2->is_stack()) { duke@435: // xmm register - stack duke@435: __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); duke@435: } else if (opr2->is_constant()) { duke@435: // xmm register - constant duke@435: __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); duke@435: } else if (opr2->is_address()) { duke@435: // xmm register - address duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check_here(op->info()); duke@435: } duke@435: __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { duke@435: assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); duke@435: assert(opr2->is_fpu_register(), "both must be registers"); duke@435: __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); duke@435: duke@435: } else if (opr1->is_address() && opr2->is_constant()) { never@739: LIR_Const* c = opr2->as_constant_ptr(); never@739: #ifdef _LP64 never@739: if (c->type() == T_OBJECT || c->type() == T_ARRAY) { never@739: assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); never@739: __ movoop(rscratch1, c->as_jobject()); never@739: } never@739: #endif // LP64 duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check_here(op->info()); duke@435: } duke@435: // special case: address - constant duke@435: LIR_Address* addr = opr1->as_address_ptr(); duke@435: if (c->type() == T_INT) { duke@435: __ cmpl(as_Address(addr), c->as_jint()); never@739: } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { never@739: #ifdef _LP64 never@739: // %%% Make this explode if addr isn't reachable until we figure out a never@739: // better strategy by giving noreg as the temp for as_Address never@739: __ cmpptr(rscratch1, as_Address(addr, noreg)); never@739: #else duke@435: __ cmpoop(as_Address(addr), c->as_jobject()); never@739: #endif // _LP64 duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { duke@435: if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { duke@435: if (left->is_single_xmm()) { duke@435: assert(right->is_single_xmm(), "must match"); duke@435: __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); duke@435: } else if (left->is_double_xmm()) { duke@435: assert(right->is_double_xmm(), "must match"); duke@435: __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); duke@435: duke@435: } else { duke@435: assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); duke@435: assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); duke@435: duke@435: assert(left->fpu() == 0, "left must be on TOS"); duke@435: __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), duke@435: op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); duke@435: } duke@435: } else { duke@435: assert(code == lir_cmp_l2i, "check"); never@739: #ifdef _LP64 never@739: Register dest = dst->as_register(); never@739: __ xorptr(dest, dest); never@739: Label high, done; never@739: __ cmpptr(left->as_register_lo(), right->as_register_lo()); never@739: __ jcc(Assembler::equal, done); never@739: __ jcc(Assembler::greater, high); never@739: __ decrement(dest); never@739: __ jmp(done); never@739: __ bind(high); never@739: __ increment(dest); never@739: never@739: __ bind(done); never@739: never@739: #else duke@435: __ lcmp2int(left->as_register_hi(), duke@435: left->as_register_lo(), duke@435: right->as_register_hi(), duke@435: right->as_register_lo()); duke@435: move_regs(left->as_register_hi(), dst->as_register()); never@739: #endif // _LP64 duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::align_call(LIR_Code code) { duke@435: if (os::is_MP()) { duke@435: // make sure that the displacement word of the call ends up word aligned duke@435: int offset = __ offset(); duke@435: switch (code) { duke@435: case lir_static_call: duke@435: case lir_optvirtual_call: duke@435: offset += NativeCall::displacement_offset; duke@435: break; duke@435: case lir_icvirtual_call: duke@435: offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; duke@435: break; duke@435: case lir_virtual_call: // currently, sparc-specific for niagara duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: while (offset++ % BytesPerWord != 0) { duke@435: __ nop(); duke@435: } duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { duke@435: assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, duke@435: "must be aligned"); duke@435: __ call(AddressLiteral(entry, rtype)); duke@435: add_call_info(code_offset(), info); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { duke@435: RelocationHolder rh = virtual_call_Relocation::spec(pc()); duke@435: __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); duke@435: assert(!os::is_MP() || duke@435: (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, duke@435: "must be aligned"); duke@435: __ call(AddressLiteral(entry, rh)); duke@435: add_call_info(code_offset(), info); duke@435: } duke@435: duke@435: duke@435: /* Currently, vtable-dispatch is only enabled for sparc platforms */ duke@435: void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: void LIR_Assembler::emit_static_call_stub() { duke@435: address call_pc = __ pc(); duke@435: address stub = __ start_a_stub(call_stub_size); duke@435: if (stub == NULL) { duke@435: bailout("static call stub overflow"); duke@435: return; duke@435: } duke@435: duke@435: int start = __ offset(); duke@435: if (os::is_MP()) { duke@435: // make sure that the displacement word of the call ends up word aligned duke@435: int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; duke@435: while (offset++ % BytesPerWord != 0) { duke@435: __ nop(); duke@435: } duke@435: } duke@435: __ relocate(static_stub_Relocation::spec(call_pc)); duke@435: __ movoop(rbx, (jobject)NULL); duke@435: // must be set to -1 at code generation time duke@435: assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); never@739: // On 64bit this will die since it will take a movq & jmp, must be only a jmp never@739: __ jump(RuntimeAddress(__ pc())); duke@435: duke@435: assert(__ offset() - start <= call_stub_size, "stub too big") duke@435: __ end_a_stub(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { duke@435: assert(exceptionOop->as_register() == rax, "must match"); duke@435: assert(unwind || exceptionPC->as_register() == rdx, "must match"); duke@435: duke@435: // exception object is not added to oop map by LinearScan duke@435: // (LinearScan assumes that no oops are in fixed registers) duke@435: info->add_register_oop(exceptionOop); duke@435: Runtime1::StubID unwind_id; duke@435: duke@435: if (!unwind) { duke@435: // get current pc information duke@435: // pc is only needed if the method has an exception handler, the unwind code does not need it. duke@435: int pc_for_athrow_offset = __ offset(); duke@435: InternalAddress pc_for_athrow(__ pc()); duke@435: __ lea(exceptionPC->as_register(), pc_for_athrow); duke@435: add_call_info(pc_for_athrow_offset, info); // for exception handler duke@435: duke@435: __ verify_not_null_oop(rax); duke@435: // search an exception handler (rax: exception oop, rdx: throwing pc) duke@435: if (compilation()->has_fpu_code()) { duke@435: unwind_id = Runtime1::handle_exception_id; duke@435: } else { duke@435: unwind_id = Runtime1::handle_exception_nofpu_id; duke@435: } duke@435: } else { duke@435: unwind_id = Runtime1::unwind_exception_id; duke@435: } duke@435: __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); duke@435: duke@435: // enough room for two byte trap duke@435: __ nop(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { duke@435: duke@435: // optimized version for linear scan: duke@435: // * count must be already in ECX (guaranteed by LinearScan) duke@435: // * left and dest must be equal duke@435: // * tmp must be unused duke@435: assert(count->as_register() == SHIFT_count, "count must be in ECX"); duke@435: assert(left == dest, "left and dest must be equal"); duke@435: assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); duke@435: duke@435: if (left->is_single_cpu()) { duke@435: Register value = left->as_register(); duke@435: assert(value != SHIFT_count, "left cannot be ECX"); duke@435: duke@435: switch (code) { duke@435: case lir_shl: __ shll(value); break; duke@435: case lir_shr: __ sarl(value); break; duke@435: case lir_ushr: __ shrl(value); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else if (left->is_double_cpu()) { duke@435: Register lo = left->as_register_lo(); duke@435: Register hi = left->as_register_hi(); duke@435: assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); never@739: #ifdef _LP64 never@739: switch (code) { never@739: case lir_shl: __ shlptr(lo); break; never@739: case lir_shr: __ sarptr(lo); break; never@739: case lir_ushr: __ shrptr(lo); break; never@739: default: ShouldNotReachHere(); never@739: } never@739: #else duke@435: duke@435: switch (code) { duke@435: case lir_shl: __ lshl(hi, lo); break; duke@435: case lir_shr: __ lshr(hi, lo, true); break; duke@435: case lir_ushr: __ lshr(hi, lo, false); break; duke@435: default: ShouldNotReachHere(); duke@435: } never@739: #endif // LP64 duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { duke@435: if (dest->is_single_cpu()) { duke@435: // first move left into dest so that left is not destroyed by the shift duke@435: Register value = dest->as_register(); duke@435: count = count & 0x1F; // Java spec duke@435: duke@435: move_regs(left->as_register(), value); duke@435: switch (code) { duke@435: case lir_shl: __ shll(value, count); break; duke@435: case lir_shr: __ sarl(value, count); break; duke@435: case lir_ushr: __ shrl(value, count); break; duke@435: default: ShouldNotReachHere(); duke@435: } duke@435: } else if (dest->is_double_cpu()) { never@739: #ifndef _LP64 duke@435: Unimplemented(); never@739: #else never@739: // first move left into dest so that left is not destroyed by the shift never@739: Register value = dest->as_register_lo(); never@739: count = count & 0x1F; // Java spec never@739: never@739: move_regs(left->as_register_lo(), value); never@739: switch (code) { never@739: case lir_shl: __ shlptr(value, count); break; never@739: case lir_shr: __ sarptr(value, count); break; never@739: case lir_ushr: __ shrptr(value, count); break; never@739: default: ShouldNotReachHere(); never@739: } never@739: #endif // _LP64 duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { duke@435: assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); duke@435: int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; duke@435: assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); never@739: __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { duke@435: assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); duke@435: int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; duke@435: assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); never@739: __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { duke@435: assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); duke@435: int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; duke@435: assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); duke@435: __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); duke@435: } duke@435: duke@435: duke@435: // This code replaces a call to arraycopy; no exception may duke@435: // be thrown in this code, they must be thrown in the System.arraycopy duke@435: // activation frame; we could save some checks if this would not be the case duke@435: void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { duke@435: ciArrayKlass* default_type = op->expected_type(); duke@435: Register src = op->src()->as_register(); duke@435: Register dst = op->dst()->as_register(); duke@435: Register src_pos = op->src_pos()->as_register(); duke@435: Register dst_pos = op->dst_pos()->as_register(); duke@435: Register length = op->length()->as_register(); duke@435: Register tmp = op->tmp()->as_register(); duke@435: duke@435: CodeStub* stub = op->stub(); duke@435: int flags = op->flags(); duke@435: BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; duke@435: if (basic_type == T_ARRAY) basic_type = T_OBJECT; duke@435: duke@435: // if we don't know anything or it's an object array, just go through the generic arraycopy duke@435: if (default_type == NULL) { duke@435: Label done; duke@435: // save outgoing arguments on stack in case call to System.arraycopy is needed duke@435: // HACK ALERT. This code used to push the parameters in a hardwired fashion duke@435: // for interpreter calling conventions. Now we have to do it in new style conventions. duke@435: // For the moment until C1 gets the new register allocator I just force all the duke@435: // args to the right place (except the register args) and then on the back side duke@435: // reload the register args properly if we go slow path. Yuck duke@435: duke@435: // These are proper for the calling convention duke@435: duke@435: store_parameter(length, 2); duke@435: store_parameter(dst_pos, 1); duke@435: store_parameter(dst, 0); duke@435: duke@435: // these are just temporary placements until we need to reload duke@435: store_parameter(src_pos, 3); duke@435: store_parameter(src, 4); never@739: NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) never@739: never@739: address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); duke@435: duke@435: // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint never@739: #ifdef _LP64 never@739: // The arguments are in java calling convention so we can trivially shift them to C never@739: // convention never@739: assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); never@739: __ mov(c_rarg0, j_rarg0); never@739: assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); never@739: __ mov(c_rarg1, j_rarg1); never@739: assert_different_registers(c_rarg2, j_rarg3, j_rarg4); never@739: __ mov(c_rarg2, j_rarg2); never@739: assert_different_registers(c_rarg3, j_rarg4); never@739: __ mov(c_rarg3, j_rarg3); never@739: #ifdef _WIN64 never@739: // Allocate abi space for args but be sure to keep stack aligned never@739: __ subptr(rsp, 6*wordSize); never@739: store_parameter(j_rarg4, 4); never@739: __ call(RuntimeAddress(entry)); never@739: __ addptr(rsp, 6*wordSize); never@739: #else never@739: __ mov(c_rarg4, j_rarg4); never@739: __ call(RuntimeAddress(entry)); never@739: #endif // _WIN64 never@739: #else never@739: __ push(length); never@739: __ push(dst_pos); never@739: __ push(dst); never@739: __ push(src_pos); never@739: __ push(src); duke@435: __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack duke@435: never@739: #endif // _LP64 never@739: duke@435: __ cmpl(rax, 0); duke@435: __ jcc(Assembler::equal, *stub->continuation()); duke@435: duke@435: // Reload values from the stack so they are where the stub duke@435: // expects them. never@739: __ movptr (dst, Address(rsp, 0*BytesPerWord)); never@739: __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); never@739: __ movptr (length, Address(rsp, 2*BytesPerWord)); never@739: __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); never@739: __ movptr (src, Address(rsp, 4*BytesPerWord)); duke@435: __ jmp(*stub->entry()); duke@435: duke@435: __ bind(*stub->continuation()); duke@435: return; duke@435: } duke@435: duke@435: assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); duke@435: kvn@464: int elem_size = type2aelembytes(basic_type); duke@435: int shift_amount; duke@435: Address::ScaleFactor scale; duke@435: duke@435: switch (elem_size) { duke@435: case 1 : duke@435: shift_amount = 0; duke@435: scale = Address::times_1; duke@435: break; duke@435: case 2 : duke@435: shift_amount = 1; duke@435: scale = Address::times_2; duke@435: break; duke@435: case 4 : duke@435: shift_amount = 2; duke@435: scale = Address::times_4; duke@435: break; duke@435: case 8 : duke@435: shift_amount = 3; duke@435: scale = Address::times_8; duke@435: break; duke@435: default: duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); duke@435: Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); duke@435: Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); duke@435: Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); duke@435: never@739: // length and pos's are all sign extended at this point on 64bit never@739: duke@435: // test for NULL duke@435: if (flags & LIR_OpArrayCopy::src_null_check) { never@739: __ testptr(src, src); duke@435: __ jcc(Assembler::zero, *stub->entry()); duke@435: } duke@435: if (flags & LIR_OpArrayCopy::dst_null_check) { never@739: __ testptr(dst, dst); duke@435: __ jcc(Assembler::zero, *stub->entry()); duke@435: } duke@435: duke@435: // check if negative duke@435: if (flags & LIR_OpArrayCopy::src_pos_positive_check) { duke@435: __ testl(src_pos, src_pos); duke@435: __ jcc(Assembler::less, *stub->entry()); duke@435: } duke@435: if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { duke@435: __ testl(dst_pos, dst_pos); duke@435: __ jcc(Assembler::less, *stub->entry()); duke@435: } duke@435: if (flags & LIR_OpArrayCopy::length_positive_check) { duke@435: __ testl(length, length); duke@435: __ jcc(Assembler::less, *stub->entry()); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::src_range_check) { never@739: __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); duke@435: __ cmpl(tmp, src_length_addr); duke@435: __ jcc(Assembler::above, *stub->entry()); duke@435: } duke@435: if (flags & LIR_OpArrayCopy::dst_range_check) { never@739: __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); duke@435: __ cmpl(tmp, dst_length_addr); duke@435: __ jcc(Assembler::above, *stub->entry()); duke@435: } duke@435: duke@435: if (flags & LIR_OpArrayCopy::type_check) { never@739: __ movptr(tmp, src_klass_addr); never@739: __ cmpptr(tmp, dst_klass_addr); duke@435: __ jcc(Assembler::notEqual, *stub->entry()); duke@435: } duke@435: duke@435: #ifdef ASSERT duke@435: if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { duke@435: // Sanity check the known type with the incoming class. For the duke@435: // primitive case the types must match exactly with src.klass and duke@435: // dst.klass each exactly matching the default type. For the duke@435: // object array case, if no type check is needed then either the duke@435: // dst type is exactly the expected type and the src type is a duke@435: // subtype which we can't check or src is the same array as dst duke@435: // but not necessarily exactly of type default_type. duke@435: Label known_ok, halt; jrose@1424: __ movoop(tmp, default_type->constant_encoding()); duke@435: if (basic_type != T_OBJECT) { never@739: __ cmpptr(tmp, dst_klass_addr); duke@435: __ jcc(Assembler::notEqual, halt); never@739: __ cmpptr(tmp, src_klass_addr); duke@435: __ jcc(Assembler::equal, known_ok); duke@435: } else { never@739: __ cmpptr(tmp, dst_klass_addr); duke@435: __ jcc(Assembler::equal, known_ok); never@739: __ cmpptr(src, dst); duke@435: __ jcc(Assembler::equal, known_ok); duke@435: } duke@435: __ bind(halt); duke@435: __ stop("incorrect type information in arraycopy"); duke@435: __ bind(known_ok); duke@435: } duke@435: #endif duke@435: never@739: if (shift_amount > 0 && basic_type != T_OBJECT) { never@739: __ shlptr(length, shift_amount); never@739: } never@739: never@739: #ifdef _LP64 never@739: assert_different_registers(c_rarg0, dst, dst_pos, length); roland@1495: __ movl2ptr(src_pos, src_pos); //higher 32bits must be null never@739: __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); never@739: assert_different_registers(c_rarg1, length); roland@1495: __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null never@739: __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); never@739: __ mov(c_rarg2, length); never@739: never@739: #else never@739: __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); duke@435: store_parameter(tmp, 0); never@739: __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); duke@435: store_parameter(tmp, 1); duke@435: store_parameter(length, 2); never@739: #endif // _LP64 duke@435: if (basic_type == T_OBJECT) { duke@435: __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); duke@435: } else { duke@435: __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); duke@435: } duke@435: duke@435: __ bind(*stub->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_lock(LIR_OpLock* op) { duke@435: Register obj = op->obj_opr()->as_register(); // may not be an oop duke@435: Register hdr = op->hdr_opr()->as_register(); duke@435: Register lock = op->lock_opr()->as_register(); duke@435: if (!UseFastLocking) { duke@435: __ jmp(*op->stub()->entry()); duke@435: } else if (op->code() == lir_lock) { duke@435: Register scratch = noreg; duke@435: if (UseBiasedLocking) { duke@435: scratch = op->scratch_opr()->as_register(); duke@435: } duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: // add debug info for NullPointerException only if one is possible duke@435: int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); duke@435: if (op->info() != NULL) { duke@435: add_debug_info_for_null_check(null_check_offset, op->info()); duke@435: } duke@435: // done duke@435: } else if (op->code() == lir_unlock) { duke@435: assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); duke@435: __ unlock_object(hdr, obj, lock, *op->stub()->entry()); duke@435: } else { duke@435: Unimplemented(); duke@435: } duke@435: __ bind(*op->stub()->continuation()); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { duke@435: ciMethod* method = op->profiled_method(); duke@435: int bci = op->profiled_bci(); duke@435: duke@435: // Update counter for all call types duke@435: ciMethodData* md = method->method_data(); duke@435: if (md == NULL) { duke@435: bailout("out of memory building methodDataOop"); duke@435: return; duke@435: } duke@435: ciProfileData* data = md->bci_to_data(bci); duke@435: assert(data->is_CounterData(), "need CounterData for calls"); duke@435: assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); duke@435: Register mdo = op->mdo()->as_register(); jrose@1424: __ movoop(mdo, md->constant_encoding()); duke@435: Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); duke@435: Bytecodes::Code bc = method->java_code_at_bci(bci); duke@435: // Perform additional virtual call profiling for invokevirtual and duke@435: // invokeinterface bytecodes duke@435: if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && duke@435: Tier1ProfileVirtualCalls) { duke@435: assert(op->recv()->is_single_cpu(), "recv must be allocated"); duke@435: Register recv = op->recv()->as_register(); duke@435: assert_different_registers(mdo, recv); duke@435: assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); duke@435: ciKlass* known_klass = op->known_holder(); duke@435: if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { duke@435: // We know the type that will be seen at this call site; we can duke@435: // statically update the methodDataOop rather than needing to do duke@435: // dynamic tests on the receiver type duke@435: duke@435: // NOTE: we should probably put a lock around this search to duke@435: // avoid collisions by concurrent compilations duke@435: ciVirtualCallData* vc_data = (ciVirtualCallData*) data; duke@435: uint i; duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: ciKlass* receiver = vc_data->receiver(i); duke@435: if (known_klass->equals(receiver)) { duke@435: Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); duke@435: __ addl(data_addr, DataLayout::counter_increment); duke@435: return; duke@435: } duke@435: } duke@435: duke@435: // Receiver type not found in profile data; select an empty slot duke@435: duke@435: // Note that this is less efficient than it should be because it duke@435: // always does a write to the receiver part of the duke@435: // VirtualCallData rather than just the first time duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: ciKlass* receiver = vc_data->receiver(i); duke@435: if (receiver == NULL) { duke@435: Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); jrose@1424: __ movoop(recv_addr, known_klass->constant_encoding()); duke@435: Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); duke@435: __ addl(data_addr, DataLayout::counter_increment); duke@435: return; duke@435: } duke@435: } duke@435: } else { never@739: __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); duke@435: Label update_done; duke@435: uint i; duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: Label next_test; duke@435: // See if the receiver is receiver[n]. never@739: __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); duke@435: __ jcc(Assembler::notEqual, next_test); duke@435: Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); duke@435: __ addl(data_addr, DataLayout::counter_increment); duke@435: __ jmp(update_done); duke@435: __ bind(next_test); duke@435: } duke@435: duke@435: // Didn't find receiver; find next empty slot and fill it in duke@435: for (i = 0; i < VirtualCallData::row_limit(); i++) { duke@435: Label next_test; duke@435: Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); never@739: __ cmpptr(recv_addr, (int32_t)NULL_WORD); duke@435: __ jcc(Assembler::notEqual, next_test); never@739: __ movptr(recv_addr, recv); duke@435: __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); kvn@1641: __ jmp(update_done); duke@435: __ bind(next_test); duke@435: } kvn@1641: // Receiver did not match any saved receiver and there is no empty row for it. kvn@1641: // Increment total counter to indicate polimorphic case. kvn@1641: __ addl(counter_addr, DataLayout::counter_increment); duke@435: duke@435: __ bind(update_done); duke@435: } kvn@1641: } else { kvn@1641: // Static call kvn@1641: __ addl(counter_addr, DataLayout::counter_increment); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::emit_delay(LIR_OpDelay*) { duke@435: Unimplemented(); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { never@739: __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::align_backward_branch_target() { duke@435: __ align(BytesPerWord); duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { duke@435: if (left->is_single_cpu()) { duke@435: __ negl(left->as_register()); duke@435: move_regs(left->as_register(), dest->as_register()); duke@435: duke@435: } else if (left->is_double_cpu()) { duke@435: Register lo = left->as_register_lo(); never@739: #ifdef _LP64 never@739: Register dst = dest->as_register_lo(); never@739: __ movptr(dst, lo); never@739: __ negptr(dst); never@739: #else duke@435: Register hi = left->as_register_hi(); duke@435: __ lneg(hi, lo); duke@435: if (dest->as_register_lo() == hi) { duke@435: assert(dest->as_register_hi() != lo, "destroying register"); duke@435: move_regs(hi, dest->as_register_hi()); duke@435: move_regs(lo, dest->as_register_lo()); duke@435: } else { duke@435: move_regs(lo, dest->as_register_lo()); duke@435: move_regs(hi, dest->as_register_hi()); duke@435: } never@739: #endif // _LP64 duke@435: duke@435: } else if (dest->is_single_xmm()) { duke@435: if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { duke@435: __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); duke@435: } duke@435: __ xorps(dest->as_xmm_float_reg(), duke@435: ExternalAddress((address)float_signflip_pool)); duke@435: duke@435: } else if (dest->is_double_xmm()) { duke@435: if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { duke@435: __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); duke@435: } duke@435: __ xorpd(dest->as_xmm_double_reg(), duke@435: ExternalAddress((address)double_signflip_pool)); duke@435: duke@435: } else if (left->is_single_fpu() || left->is_double_fpu()) { duke@435: assert(left->fpu() == 0, "arg must be on TOS"); duke@435: assert(dest->fpu() == 0, "dest must be TOS"); duke@435: __ fchs(); duke@435: duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { duke@435: assert(addr->is_address() && dest->is_register(), "check"); never@739: Register reg; never@739: reg = dest->as_pointer_register(); never@739: __ lea(reg, as_Address(addr->as_address_ptr())); duke@435: } duke@435: duke@435: duke@435: duke@435: void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { duke@435: assert(!tmp->is_valid(), "don't need temporary"); duke@435: __ call(RuntimeAddress(dest)); duke@435: if (info != NULL) { duke@435: add_call_info_here(info); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { duke@435: assert(type == T_LONG, "only for volatile long fields"); duke@435: duke@435: if (info != NULL) { duke@435: add_debug_info_for_null_check_here(info); duke@435: } duke@435: duke@435: if (src->is_double_xmm()) { duke@435: if (dest->is_double_cpu()) { never@739: #ifdef _LP64 never@739: __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); never@739: #else never@739: __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); duke@435: __ psrlq(src->as_xmm_double_reg(), 32); never@739: __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); never@739: #endif // _LP64 duke@435: } else if (dest->is_double_stack()) { duke@435: __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); duke@435: } else if (dest->is_address()) { duke@435: __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (dest->is_double_xmm()) { duke@435: if (src->is_double_stack()) { duke@435: __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); duke@435: } else if (src->is_address()) { duke@435: __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (src->is_double_fpu()) { duke@435: assert(src->fpu_regnrLo() == 0, "must be TOS"); duke@435: if (dest->is_double_stack()) { duke@435: __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); duke@435: } else if (dest->is_address()) { duke@435: __ fistp_d(as_Address(dest->as_address_ptr())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: duke@435: } else if (dest->is_double_fpu()) { duke@435: assert(dest->fpu_regnrLo() == 0, "must be TOS"); duke@435: if (src->is_double_stack()) { duke@435: __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); duke@435: } else if (src->is_address()) { duke@435: __ fild_d(as_Address(src->as_address_ptr())); duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } else { duke@435: ShouldNotReachHere(); duke@435: } duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::membar() { never@739: // QQQ sparc TSO uses this, never@739: __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); duke@435: } duke@435: duke@435: void LIR_Assembler::membar_acquire() { duke@435: // No x86 machines currently require load fences duke@435: // __ load_fence(); duke@435: } duke@435: duke@435: void LIR_Assembler::membar_release() { duke@435: // No x86 machines currently require store fences duke@435: // __ store_fence(); duke@435: } duke@435: duke@435: void LIR_Assembler::get_thread(LIR_Opr result_reg) { duke@435: assert(result_reg->is_register(), "check"); never@739: #ifdef _LP64 never@739: // __ get_thread(result_reg->as_register_lo()); never@739: __ mov(result_reg->as_register(), r15_thread); never@739: #else duke@435: __ get_thread(result_reg->as_register()); never@739: #endif // _LP64 duke@435: } duke@435: duke@435: duke@435: void LIR_Assembler::peephole(LIR_List*) { duke@435: // do nothing for now duke@435: } duke@435: duke@435: duke@435: #undef __