twisti@4323: /* hseigel@5528: * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. twisti@4323: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. twisti@4323: * twisti@4323: * This code is free software; you can redistribute it and/or modify it twisti@4323: * under the terms of the GNU General Public License version 2 only, as twisti@4323: * published by the Free Software Foundation. twisti@4323: * twisti@4323: * This code is distributed in the hope that it will be useful, but WITHOUT twisti@4323: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or twisti@4323: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License twisti@4323: * version 2 for more details (a copy is included in the LICENSE file that twisti@4323: * accompanied this code). twisti@4323: * twisti@4323: * You should have received a copy of the GNU General Public License version twisti@4323: * 2 along with this work; if not, write to the Free Software Foundation, twisti@4323: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. twisti@4323: * twisti@4323: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA twisti@4323: * or visit www.oracle.com if you need additional information or have any twisti@4323: * questions. twisti@4323: * twisti@4323: */ twisti@4323: twisti@4323: #include "precompiled.hpp" twisti@4323: #include "asm/assembler.inline.hpp" twisti@4323: #include "compiler/disassembler.hpp" twisti@4323: #include "gc_interface/collectedHeap.inline.hpp" twisti@4323: #include "interpreter/interpreter.hpp" twisti@4323: #include "memory/cardTableModRefBS.hpp" twisti@4323: #include "memory/resourceArea.hpp" hseigel@5528: #include "memory/universe.hpp" twisti@4323: #include "prims/methodHandles.hpp" twisti@4323: #include "runtime/biasedLocking.hpp" twisti@4323: #include "runtime/interfaceSupport.hpp" twisti@4323: #include "runtime/objectMonitor.hpp" twisti@4323: #include "runtime/os.hpp" twisti@4323: #include "runtime/sharedRuntime.hpp" twisti@4323: #include "runtime/stubRoutines.hpp" jprovino@4542: #include "utilities/macros.hpp" jprovino@4542: #if INCLUDE_ALL_GCS twisti@4323: #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" twisti@4323: #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" twisti@4323: #include "gc_implementation/g1/heapRegion.hpp" jprovino@4542: #endif // INCLUDE_ALL_GCS twisti@4323: twisti@4323: #ifdef PRODUCT twisti@4323: #define BLOCK_COMMENT(str) /* nothing */ twisti@4323: #define STOP(error) stop(error) twisti@4323: #else twisti@4323: #define BLOCK_COMMENT(str) block_comment(str) twisti@4323: #define STOP(error) block_comment(error); stop(error) twisti@4323: #endif twisti@4323: twisti@4323: // Convert the raw encoding form into the form expected by the twisti@4323: // constructor for Address. twisti@4323: Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { twisti@4323: assert(scale == 0, "not supported"); twisti@4323: RelocationHolder rspec; twisti@4323: if (disp_reloc != relocInfo::none) { twisti@4323: rspec = Relocation::spec_simple(disp_reloc); twisti@4323: } twisti@4323: twisti@4323: Register rindex = as_Register(index); twisti@4323: if (rindex != G0) { twisti@4323: Address madr(as_Register(base), rindex); twisti@4323: madr._rspec = rspec; twisti@4323: return madr; twisti@4323: } else { twisti@4323: Address madr(as_Register(base), disp); twisti@4323: madr._rspec = rspec; twisti@4323: return madr; twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: Address Argument::address_in_frame() const { twisti@4323: // Warning: In LP64 mode disp will occupy more than 10 bits, but twisti@4323: // op codes such as ld or ldx, only access disp() to get twisti@4323: // their simm13 argument. twisti@4323: int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; twisti@4323: if (is_in()) twisti@4323: return Address(FP, disp); // In argument. twisti@4323: else twisti@4323: return Address(SP, disp); // Out argument. twisti@4323: } twisti@4323: twisti@4323: static const char* argumentNames[][2] = { twisti@4323: {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, twisti@4323: {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, twisti@4323: {"A(n>9)","P(n>9)"} twisti@4323: }; twisti@4323: twisti@4323: const char* Argument::name() const { twisti@4323: int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; twisti@4323: int num = number(); twisti@4323: if (num >= nofArgs) num = nofArgs - 1; twisti@4323: return argumentNames[num][is_in() ? 1 : 0]; twisti@4323: } twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // On RISC, there's no benefit to verifying instruction boundaries. twisti@4323: bool AbstractAssembler::pd_check_instruction_mark() { return false; } twisti@4323: #endif twisti@4323: twisti@4323: // Patch instruction inst at offset inst_pos to refer to dest_pos twisti@4323: // and return the resulting instruction. twisti@4323: // We should have pcs, not offsets, but since all is relative, it will work out twisti@4323: // OK. twisti@4323: int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) { twisti@4323: int m; // mask for displacement field twisti@4323: int v; // new value for displacement field twisti@4323: const int word_aligned_ones = -4; twisti@4323: switch (inv_op(inst)) { twisti@4323: default: ShouldNotReachHere(); twisti@4323: case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; twisti@4323: case branch_op: twisti@4323: switch (inv_op2(inst)) { twisti@4323: case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; twisti@4323: case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; twisti@4323: case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; twisti@4323: case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; twisti@4323: case bpr_op2: { twisti@4323: if (is_cbcond(inst)) { twisti@4323: m = wdisp10(word_aligned_ones, 0); twisti@4323: v = wdisp10(dest_pos, inst_pos); twisti@4323: } else { twisti@4323: m = wdisp16(word_aligned_ones, 0); twisti@4323: v = wdisp16(dest_pos, inst_pos); twisti@4323: } twisti@4323: break; twisti@4323: } twisti@4323: default: ShouldNotReachHere(); twisti@4323: } twisti@4323: } twisti@4323: return inst & ~m | v; twisti@4323: } twisti@4323: twisti@4323: // Return the offset of the branch destionation of instruction inst twisti@4323: // at offset pos. twisti@4323: // Should have pcs, but since all is relative, it works out. twisti@4323: int MacroAssembler::branch_destination(int inst, int pos) { twisti@4323: int r; twisti@4323: switch (inv_op(inst)) { twisti@4323: default: ShouldNotReachHere(); twisti@4323: case call_op: r = inv_wdisp(inst, pos, 30); break; twisti@4323: case branch_op: twisti@4323: switch (inv_op2(inst)) { twisti@4323: case fbp_op2: r = inv_wdisp( inst, pos, 19); break; twisti@4323: case bp_op2: r = inv_wdisp( inst, pos, 19); break; twisti@4323: case fb_op2: r = inv_wdisp( inst, pos, 22); break; twisti@4323: case br_op2: r = inv_wdisp( inst, pos, 22); break; twisti@4323: case bpr_op2: { twisti@4323: if (is_cbcond(inst)) { twisti@4323: r = inv_wdisp10(inst, pos); twisti@4323: } else { twisti@4323: r = inv_wdisp16(inst, pos); twisti@4323: } twisti@4323: break; twisti@4323: } twisti@4323: default: ShouldNotReachHere(); twisti@4323: } twisti@4323: } twisti@4323: return r; twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::null_check(Register reg, int offset) { twisti@4323: if (needs_explicit_null_check((intptr_t)offset)) { twisti@4323: // provoke OS NULL exception if reg = NULL by twisti@4323: // accessing M[reg] w/o changing any registers twisti@4323: ld_ptr(reg, 0, G0); twisti@4323: } twisti@4323: else { twisti@4323: // nothing to do, (later) access of M[reg + offset] twisti@4323: // will provoke OS NULL exception if reg = NULL twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Ring buffer jumps twisti@4323: twisti@4323: #ifndef PRODUCT twisti@4323: void MacroAssembler::ret( bool trace ) { if (trace) { twisti@4323: mov(I7, O7); // traceable register twisti@4323: JMP(O7, 2 * BytesPerInstWord); twisti@4323: } else { twisti@4323: jmpl( I7, 2 * BytesPerInstWord, G0 ); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); twisti@4323: else jmpl( O7, 2 * BytesPerInstWord, G0 ); } twisti@4323: #endif /* PRODUCT */ twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { twisti@4323: assert_not_delayed(); twisti@4323: // This can only be traceable if r1 & r2 are visible after a window save twisti@4323: if (TraceJumps) { twisti@4323: #ifndef PRODUCT twisti@4323: save_frame(0); twisti@4323: verify_thread(); twisti@4323: ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); twisti@4323: add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); twisti@4323: sll(O0, exact_log2(4*sizeof(intptr_t)), O2); twisti@4323: add(O2, O1, O1); twisti@4323: twisti@4323: add(r1->after_save(), r2->after_save(), O2); twisti@4323: set((intptr_t)file, O3); twisti@4323: set(line, O4); twisti@4323: Label L; twisti@4323: // get nearby pc, store jmp target twisti@4323: call(L, relocInfo::none); // No relocation for call to pc+0x8 twisti@4323: delayed()->st(O2, O1, 0); twisti@4323: bind(L); twisti@4323: twisti@4323: // store nearby pc twisti@4323: st(O7, O1, sizeof(intptr_t)); twisti@4323: // store file twisti@4323: st(O3, O1, 2*sizeof(intptr_t)); twisti@4323: // store line twisti@4323: st(O4, O1, 3*sizeof(intptr_t)); twisti@4323: add(O0, 1, O0); twisti@4323: and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); twisti@4323: st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); twisti@4323: restore(); twisti@4323: #endif /* PRODUCT */ twisti@4323: } twisti@4323: jmpl(r1, r2, G0); twisti@4323: } twisti@4323: void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { twisti@4323: assert_not_delayed(); twisti@4323: // This can only be traceable if r1 is visible after a window save twisti@4323: if (TraceJumps) { twisti@4323: #ifndef PRODUCT twisti@4323: save_frame(0); twisti@4323: verify_thread(); twisti@4323: ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); twisti@4323: add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); twisti@4323: sll(O0, exact_log2(4*sizeof(intptr_t)), O2); twisti@4323: add(O2, O1, O1); twisti@4323: twisti@4323: add(r1->after_save(), offset, O2); twisti@4323: set((intptr_t)file, O3); twisti@4323: set(line, O4); twisti@4323: Label L; twisti@4323: // get nearby pc, store jmp target twisti@4323: call(L, relocInfo::none); // No relocation for call to pc+0x8 twisti@4323: delayed()->st(O2, O1, 0); twisti@4323: bind(L); twisti@4323: twisti@4323: // store nearby pc twisti@4323: st(O7, O1, sizeof(intptr_t)); twisti@4323: // store file twisti@4323: st(O3, O1, 2*sizeof(intptr_t)); twisti@4323: // store line twisti@4323: st(O4, O1, 3*sizeof(intptr_t)); twisti@4323: add(O0, 1, O0); twisti@4323: and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); twisti@4323: st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); twisti@4323: restore(); twisti@4323: #endif /* PRODUCT */ twisti@4323: } twisti@4323: jmp(r1, offset); twisti@4323: } twisti@4323: twisti@4323: // This code sequence is relocatable to any address, even on LP64. twisti@4323: void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { twisti@4323: assert_not_delayed(); twisti@4323: // Force fixed length sethi because NativeJump and NativeFarCall don't handle twisti@4323: // variable length instruction streams. twisti@4323: patchable_sethi(addrlit, temp); twisti@4323: Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. twisti@4323: if (TraceJumps) { twisti@4323: #ifndef PRODUCT twisti@4323: // Must do the add here so relocation can find the remainder of the twisti@4323: // value to be relocated. twisti@4323: add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); twisti@4323: save_frame(0); twisti@4323: verify_thread(); twisti@4323: ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); twisti@4323: add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); twisti@4323: sll(O0, exact_log2(4*sizeof(intptr_t)), O2); twisti@4323: add(O2, O1, O1); twisti@4323: twisti@4323: set((intptr_t)file, O3); twisti@4323: set(line, O4); twisti@4323: Label L; twisti@4323: twisti@4323: // get nearby pc, store jmp target twisti@4323: call(L, relocInfo::none); // No relocation for call to pc+0x8 twisti@4323: delayed()->st(a.base()->after_save(), O1, 0); twisti@4323: bind(L); twisti@4323: twisti@4323: // store nearby pc twisti@4323: st(O7, O1, sizeof(intptr_t)); twisti@4323: // store file twisti@4323: st(O3, O1, 2*sizeof(intptr_t)); twisti@4323: // store line twisti@4323: st(O4, O1, 3*sizeof(intptr_t)); twisti@4323: add(O0, 1, O0); twisti@4323: and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); twisti@4323: st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); twisti@4323: restore(); twisti@4323: jmpl(a.base(), G0, d); twisti@4323: #else twisti@4323: jmpl(a.base(), a.disp(), d); twisti@4323: #endif /* PRODUCT */ twisti@4323: } else { twisti@4323: jmpl(a.base(), a.disp(), d); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { twisti@4323: jumpl(addrlit, temp, G0, offset, file, line); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // Conditional breakpoint (for assertion checks in assembly code) twisti@4323: void MacroAssembler::breakpoint_trap(Condition c, CC cc) { twisti@4323: trap(c, cc, G0, ST_RESERVED_FOR_USER_0); twisti@4323: } twisti@4323: twisti@4323: // We want to use ST_BREAKPOINT here, but the debugger is confused by it. twisti@4323: void MacroAssembler::breakpoint_trap() { twisti@4323: trap(ST_RESERVED_FOR_USER_0); twisti@4323: } twisti@4323: twisti@4323: // Write serialization page so VM thread can do a pseudo remote membar twisti@4323: // We use the current thread pointer to calculate a thread specific twisti@4323: // offset to write to within the page. This minimizes bus traffic twisti@4323: // due to cache line collision. twisti@4323: void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { twisti@4323: srl(thread, os::get_serialize_page_shift_count(), tmp2); twisti@4323: if (Assembler::is_simm13(os::vm_page_size())) { twisti@4323: and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); twisti@4323: } twisti@4323: else { twisti@4323: set((os::vm_page_size() - sizeof(int)), tmp1); twisti@4323: and3(tmp2, tmp1, tmp2); twisti@4323: } twisti@4323: set(os::get_memory_serialize_page(), tmp1); twisti@4323: st(G0, tmp1, tmp2); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::enter() { twisti@4323: Unimplemented(); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::leave() { twisti@4323: Unimplemented(); twisti@4323: } twisti@4323: twisti@4323: // Calls to C land twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // a hook for debugging twisti@4323: static Thread* reinitialize_thread() { twisti@4323: return ThreadLocalStorage::thread(); twisti@4323: } twisti@4323: #else twisti@4323: #define reinitialize_thread ThreadLocalStorage::thread twisti@4323: #endif twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: address last_get_thread = NULL; twisti@4323: #endif twisti@4323: twisti@4323: // call this when G2_thread is not known to be valid twisti@4323: void MacroAssembler::get_thread() { twisti@4323: save_frame(0); // to avoid clobbering O0 twisti@4323: mov(G1, L0); // avoid clobbering G1 twisti@4323: mov(G5_method, L1); // avoid clobbering G5 twisti@4323: mov(G3, L2); // avoid clobbering G3 also twisti@4323: mov(G4, L5); // avoid clobbering G4 twisti@4323: #ifdef ASSERT twisti@4323: AddressLiteral last_get_thread_addrlit(&last_get_thread); twisti@4323: set(last_get_thread_addrlit, L3); morris@5283: rdpc(L4); morris@5283: inc(L4, 3 * BytesPerInstWord); // skip rdpc + inc + st_ptr to point L4 at call st_ptr(L4, L3, 0); twisti@4323: #endif twisti@4323: call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); twisti@4323: delayed()->nop(); twisti@4323: mov(L0, G1); twisti@4323: mov(L1, G5_method); twisti@4323: mov(L2, G3); twisti@4323: mov(L5, G4); twisti@4323: restore(O0, 0, G2_thread); twisti@4323: } twisti@4323: twisti@4323: static Thread* verify_thread_subroutine(Thread* gthread_value) { twisti@4323: Thread* correct_value = ThreadLocalStorage::thread(); twisti@4323: guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); twisti@4323: return correct_value; twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::verify_thread() { twisti@4323: if (VerifyThread) { twisti@4323: // NOTE: this chops off the heads of the 64-bit O registers. twisti@4323: #ifdef CC_INTERP twisti@4323: save_frame(0); twisti@4323: #else twisti@4323: // make sure G2_thread contains the right value twisti@4323: save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) twisti@4323: mov(G1, L1); // avoid clobbering G1 twisti@4323: // G2 saved below twisti@4323: mov(G3, L3); // avoid clobbering G3 twisti@4323: mov(G4, L4); // avoid clobbering G4 twisti@4323: mov(G5_method, L5); // avoid clobbering G5_method twisti@4323: #endif /* CC_INTERP */ twisti@4323: #if defined(COMPILER2) && !defined(_LP64) twisti@4323: // Save & restore possible 64-bit Long arguments in G-regs twisti@4323: srlx(G1,32,L0); twisti@4323: srlx(G4,32,L6); twisti@4323: #endif twisti@4323: call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); twisti@4323: delayed()->mov(G2_thread, O0); twisti@4323: twisti@4323: mov(L1, G1); // Restore G1 twisti@4323: // G2 restored below twisti@4323: mov(L3, G3); // restore G3 twisti@4323: mov(L4, G4); // restore G4 twisti@4323: mov(L5, G5_method); // restore G5_method twisti@4323: #if defined(COMPILER2) && !defined(_LP64) twisti@4323: // Save & restore possible 64-bit Long arguments in G-regs twisti@4323: sllx(L0,32,G2); // Move old high G1 bits high in G2 twisti@4323: srl(G1, 0,G1); // Clear current high G1 bits twisti@4323: or3 (G1,G2,G1); // Recover 64-bit G1 twisti@4323: sllx(L6,32,G2); // Move old high G4 bits high in G2 twisti@4323: srl(G4, 0,G4); // Clear current high G4 bits twisti@4323: or3 (G4,G2,G4); // Recover 64-bit G4 twisti@4323: #endif twisti@4323: restore(O0, 0, G2_thread); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::save_thread(const Register thread_cache) { twisti@4323: verify_thread(); twisti@4323: if (thread_cache->is_valid()) { twisti@4323: assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); twisti@4323: mov(G2_thread, thread_cache); twisti@4323: } twisti@4323: if (VerifyThread) { twisti@4323: // smash G2_thread, as if the VM were about to anyway twisti@4323: set(0x67676767, G2_thread); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::restore_thread(const Register thread_cache) { twisti@4323: if (thread_cache->is_valid()) { twisti@4323: assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); twisti@4323: mov(thread_cache, G2_thread); twisti@4323: verify_thread(); twisti@4323: } else { twisti@4323: // do it the slow way twisti@4323: get_thread(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // %%% maybe get rid of [re]set_last_Java_frame twisti@4323: void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { twisti@4323: assert_not_delayed(); twisti@4323: Address flags(G2_thread, JavaThread::frame_anchor_offset() + twisti@4323: JavaFrameAnchor::flags_offset()); twisti@4323: Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); twisti@4323: twisti@4323: // Always set last_Java_pc and flags first because once last_Java_sp is visible twisti@4323: // has_last_Java_frame is true and users will look at the rest of the fields. twisti@4323: // (Note: flags should always be zero before we get here so doesn't need to be set.) twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // Verify that flags was zeroed on return to Java twisti@4323: Label PcOk; twisti@4323: save_frame(0); // to avoid clobbering O0 twisti@4323: ld_ptr(pc_addr, L0); twisti@4323: br_null_short(L0, Assembler::pt, PcOk); twisti@4323: STOP("last_Java_pc not zeroed before leaving Java"); twisti@4323: bind(PcOk); twisti@4323: twisti@4323: // Verify that flags was zeroed on return to Java twisti@4323: Label FlagsOk; twisti@4323: ld(flags, L0); twisti@4323: tst(L0); twisti@4323: br(Assembler::zero, false, Assembler::pt, FlagsOk); twisti@4323: delayed() -> restore(); twisti@4323: STOP("flags not zeroed before leaving Java"); twisti@4323: bind(FlagsOk); twisti@4323: #endif /* ASSERT */ twisti@4323: // twisti@4323: // When returning from calling out from Java mode the frame anchor's last_Java_pc twisti@4323: // will always be set to NULL. It is set here so that if we are doing a call to twisti@4323: // native (not VM) that we capture the known pc and don't have to rely on the twisti@4323: // native call having a standard frame linkage where we can find the pc. twisti@4323: twisti@4323: if (last_Java_pc->is_valid()) { twisti@4323: st_ptr(last_Java_pc, pc_addr); twisti@4323: } twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: #ifdef ASSERT twisti@4323: // Make sure that we have an odd stack twisti@4323: Label StackOk; twisti@4323: andcc(last_java_sp, 0x01, G0); twisti@4323: br(Assembler::notZero, false, Assembler::pt, StackOk); twisti@4323: delayed()->nop(); twisti@4323: STOP("Stack Not Biased in set_last_Java_frame"); twisti@4323: bind(StackOk); twisti@4323: #endif // ASSERT twisti@4323: assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); twisti@4323: add( last_java_sp, STACK_BIAS, G4_scratch ); twisti@4323: st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); twisti@4323: #else twisti@4323: st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); twisti@4323: #endif // _LP64 twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::reset_last_Java_frame(void) { twisti@4323: assert_not_delayed(); twisti@4323: twisti@4323: Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); twisti@4323: Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); twisti@4323: Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // check that it WAS previously set twisti@4323: #ifdef CC_INTERP twisti@4323: save_frame(0); twisti@4323: #else twisti@4323: save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof twisti@4323: #endif /* CC_INTERP */ twisti@4323: ld_ptr(sp_addr, L0); twisti@4323: tst(L0); twisti@4323: breakpoint_trap(Assembler::zero, Assembler::ptr_cc); twisti@4323: restore(); twisti@4323: #endif // ASSERT twisti@4323: twisti@4323: st_ptr(G0, sp_addr); twisti@4323: // Always return last_Java_pc to zero twisti@4323: st_ptr(G0, pc_addr); twisti@4323: // Always null flags after return to Java twisti@4323: st(G0, flags); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_base( twisti@4323: Register oop_result, twisti@4323: Register thread_cache, twisti@4323: Register last_java_sp, twisti@4323: address entry_point, twisti@4323: int number_of_arguments, twisti@4323: bool check_exceptions) twisti@4323: { twisti@4323: assert_not_delayed(); twisti@4323: twisti@4323: // determine last_java_sp register twisti@4323: if (!last_java_sp->is_valid()) { twisti@4323: last_java_sp = SP; twisti@4323: } twisti@4323: // debugging support twisti@4323: assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); twisti@4323: twisti@4323: // 64-bit last_java_sp is biased! twisti@4323: set_last_Java_frame(last_java_sp, noreg); twisti@4323: if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early twisti@4323: save_thread(thread_cache); twisti@4323: // do the call twisti@4323: call(entry_point, relocInfo::runtime_call_type); twisti@4323: if (!VerifyThread) twisti@4323: delayed()->mov(G2_thread, O0); // pass thread as first argument twisti@4323: else twisti@4323: delayed()->nop(); // (thread already passed) twisti@4323: restore_thread(thread_cache); twisti@4323: reset_last_Java_frame(); twisti@4323: twisti@4323: // check for pending exceptions. use Gtemp as scratch register. twisti@4323: if (check_exceptions) { twisti@4323: check_and_forward_exception(Gtemp); twisti@4323: } twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: set(badHeapWordVal, G3); twisti@4323: set(badHeapWordVal, G4); twisti@4323: set(badHeapWordVal, G5); twisti@4323: #endif twisti@4323: twisti@4323: // get oop result if there is one and reset the value in the thread twisti@4323: if (oop_result->is_valid()) { twisti@4323: get_vm_result(oop_result); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::check_and_forward_exception(Register scratch_reg) twisti@4323: { twisti@4323: Label L; twisti@4323: twisti@4323: check_and_handle_popframe(scratch_reg); twisti@4323: check_and_handle_earlyret(scratch_reg); twisti@4323: twisti@4323: Address exception_addr(G2_thread, Thread::pending_exception_offset()); twisti@4323: ld_ptr(exception_addr, scratch_reg); twisti@4323: br_null_short(scratch_reg, pt, L); twisti@4323: // we use O7 linkage so that forward_exception_entry has the issuing PC twisti@4323: call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); twisti@4323: delayed()->nop(); twisti@4323: bind(L); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { twisti@4323: call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: call_VM(oop_result, entry_point, 1, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); twisti@4323: call_VM(oop_result, entry_point, 2, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); twisti@4323: mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); twisti@4323: call_VM(oop_result, entry_point, 3, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: // Note: The following call_VM overloadings are useful when a "save" twisti@4323: // has already been performed by a stub, and the last Java frame is twisti@4323: // the previous one. In that case, last_java_sp must be passed as FP twisti@4323: // instead of SP. twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { twisti@4323: call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); twisti@4323: call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { twisti@4323: // O0 is reserved for the thread twisti@4323: mov(arg_1, O1); twisti@4323: mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); twisti@4323: mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); twisti@4323: call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { twisti@4323: assert_not_delayed(); twisti@4323: save_thread(thread_cache); twisti@4323: // do the call twisti@4323: call(entry_point, relocInfo::runtime_call_type); twisti@4323: delayed()->nop(); twisti@4323: restore_thread(thread_cache); twisti@4323: #ifdef ASSERT twisti@4323: set(badHeapWordVal, G3); twisti@4323: set(badHeapWordVal, G4); twisti@4323: set(badHeapWordVal, G5); twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { twisti@4323: call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { twisti@4323: mov(arg_1, O0); twisti@4323: call_VM_leaf(thread_cache, entry_point, 1); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { twisti@4323: mov(arg_1, O0); twisti@4323: mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); twisti@4323: call_VM_leaf(thread_cache, entry_point, 2); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { twisti@4323: mov(arg_1, O0); twisti@4323: mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); twisti@4323: mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); twisti@4323: call_VM_leaf(thread_cache, entry_point, 3); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::get_vm_result(Register oop_result) { twisti@4323: verify_thread(); twisti@4323: Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); twisti@4323: ld_ptr( vm_result_addr, oop_result); twisti@4323: st_ptr(G0, vm_result_addr); twisti@4323: verify_oop(oop_result); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::get_vm_result_2(Register metadata_result) { twisti@4323: verify_thread(); twisti@4323: Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); twisti@4323: ld_ptr(vm_result_addr_2, metadata_result); twisti@4323: st_ptr(G0, vm_result_addr_2); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // We require that C code which does not return a value in vm_result will twisti@4323: // leave it undisturbed. twisti@4323: void MacroAssembler::set_vm_result(Register oop_result) { twisti@4323: verify_thread(); twisti@4323: Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); twisti@4323: verify_oop(oop_result); twisti@4323: twisti@4323: # ifdef ASSERT twisti@4323: // Check that we are not overwriting any other oop. twisti@4323: #ifdef CC_INTERP twisti@4323: save_frame(0); twisti@4323: #else twisti@4323: save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof twisti@4323: #endif /* CC_INTERP */ twisti@4323: ld_ptr(vm_result_addr, L0); twisti@4323: tst(L0); twisti@4323: restore(); twisti@4323: breakpoint_trap(notZero, Assembler::ptr_cc); twisti@4323: // } twisti@4323: # endif twisti@4323: twisti@4323: st_ptr(oop_result, vm_result_addr); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::ic_call(address entry, bool emit_delay) { twisti@4323: RelocationHolder rspec = virtual_call_Relocation::spec(pc()); twisti@4323: patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg); twisti@4323: relocate(rspec); twisti@4323: call(entry, relocInfo::none); twisti@4323: if (emit_delay) { twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::card_table_write(jbyte* byte_map_base, twisti@4323: Register tmp, Register obj) { twisti@4323: #ifdef _LP64 twisti@4323: srlx(obj, CardTableModRefBS::card_shift, obj); twisti@4323: #else twisti@4323: srl(obj, CardTableModRefBS::card_shift, obj); twisti@4323: #endif twisti@4323: assert(tmp != obj, "need separate temp reg"); twisti@4323: set((address) byte_map_base, tmp); twisti@4323: stb(G0, tmp, obj); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { twisti@4323: address save_pc; twisti@4323: int shiftcnt; twisti@4323: #ifdef _LP64 twisti@4323: # ifdef CHECK_DELAY twisti@4323: assert_not_delayed((char*) "cannot put two instructions in delay slot"); twisti@4323: # endif twisti@4323: v9_dep(); twisti@4323: save_pc = pc(); twisti@4323: twisti@4323: int msb32 = (int) (addrlit.value() >> 32); twisti@4323: int lsb32 = (int) (addrlit.value()); twisti@4323: twisti@4323: if (msb32 == 0 && lsb32 >= 0) { twisti@4323: Assembler::sethi(lsb32, d, addrlit.rspec()); twisti@4323: } twisti@4323: else if (msb32 == -1) { twisti@4323: Assembler::sethi(~lsb32, d, addrlit.rspec()); twisti@4323: xor3(d, ~low10(~0), d); twisti@4323: } twisti@4323: else { twisti@4323: Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits twisti@4323: if (msb32 & 0x3ff) // Any bits? twisti@4323: or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 twisti@4323: if (lsb32 & 0xFFFFFC00) { // done? twisti@4323: if ((lsb32 >> 20) & 0xfff) { // Any bits set? twisti@4323: sllx(d, 12, d); // Make room for next 12 bits twisti@4323: or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 twisti@4323: shiftcnt = 0; // We already shifted twisti@4323: } twisti@4323: else twisti@4323: shiftcnt = 12; twisti@4323: if ((lsb32 >> 10) & 0x3ff) { twisti@4323: sllx(d, shiftcnt + 10, d); // Make room for last 10 bits twisti@4323: or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 twisti@4323: shiftcnt = 0; twisti@4323: } twisti@4323: else twisti@4323: shiftcnt = 10; twisti@4323: sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd twisti@4323: } twisti@4323: else twisti@4323: sllx(d, 32, d); twisti@4323: } twisti@4323: // Pad out the instruction sequence so it can be patched later. twisti@4323: if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && twisti@4323: addrlit.rtype() != relocInfo::runtime_call_type)) { twisti@4323: while (pc() < (save_pc + (7 * BytesPerInstWord))) twisti@4323: nop(); twisti@4323: } twisti@4323: #else twisti@4323: Assembler::sethi(addrlit.value(), d, addrlit.rspec()); twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { twisti@4323: internal_sethi(addrlit, d, false); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { twisti@4323: internal_sethi(addrlit, d, true); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: int MacroAssembler::insts_for_sethi(address a, bool worst_case) { twisti@4323: #ifdef _LP64 twisti@4323: if (worst_case) return 7; twisti@4323: intptr_t iaddr = (intptr_t) a; twisti@4323: int msb32 = (int) (iaddr >> 32); twisti@4323: int lsb32 = (int) (iaddr); twisti@4323: int count; twisti@4323: if (msb32 == 0 && lsb32 >= 0) twisti@4323: count = 1; twisti@4323: else if (msb32 == -1) twisti@4323: count = 2; twisti@4323: else { twisti@4323: count = 2; twisti@4323: if (msb32 & 0x3ff) twisti@4323: count++; twisti@4323: if (lsb32 & 0xFFFFFC00 ) { twisti@4323: if ((lsb32 >> 20) & 0xfff) count += 2; twisti@4323: if ((lsb32 >> 10) & 0x3ff) count += 2; twisti@4323: } twisti@4323: } twisti@4323: return count; twisti@4323: #else twisti@4323: return 1; twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: int MacroAssembler::worst_case_insts_for_set() { twisti@4323: return insts_for_sethi(NULL, true) + 1; twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // Keep in sync with MacroAssembler::insts_for_internal_set twisti@4323: void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { twisti@4323: intptr_t value = addrlit.value(); twisti@4323: twisti@4323: if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { twisti@4323: // can optimize twisti@4323: if (-4096 <= value && value <= 4095) { twisti@4323: or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) twisti@4323: return; twisti@4323: } twisti@4323: if (inv_hi22(hi22(value)) == value) { twisti@4323: sethi(addrlit, d); twisti@4323: return; twisti@4323: } twisti@4323: } twisti@4323: assert_not_delayed((char*) "cannot put two instructions in delay slot"); twisti@4323: internal_sethi(addrlit, d, ForceRelocatable); twisti@4323: if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { twisti@4323: add(d, addrlit.low10(), d, addrlit.rspec()); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Keep in sync with MacroAssembler::internal_set twisti@4323: int MacroAssembler::insts_for_internal_set(intptr_t value) { twisti@4323: // can optimize twisti@4323: if (-4096 <= value && value <= 4095) { twisti@4323: return 1; twisti@4323: } twisti@4323: if (inv_hi22(hi22(value)) == value) { twisti@4323: return insts_for_sethi((address) value); twisti@4323: } twisti@4323: int count = insts_for_sethi((address) value); twisti@4323: AddressLiteral al(value); twisti@4323: if (al.low10() != 0) { twisti@4323: count++; twisti@4323: } twisti@4323: return count; twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::set(const AddressLiteral& al, Register d) { twisti@4323: internal_set(al, d, false); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::set(intptr_t value, Register d) { twisti@4323: AddressLiteral al(value); twisti@4323: internal_set(al, d, false); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { twisti@4323: AddressLiteral al(addr, rspec); twisti@4323: internal_set(al, d, false); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { twisti@4323: internal_set(al, d, true); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::patchable_set(intptr_t value, Register d) { twisti@4323: AddressLiteral al(value); twisti@4323: internal_set(al, d, true); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::set64(jlong value, Register d, Register tmp) { twisti@4323: assert_not_delayed(); twisti@4323: v9_dep(); twisti@4323: twisti@4323: int hi = (int)(value >> 32); twisti@4323: int lo = (int)(value & ~0); twisti@4323: // (Matcher::isSimpleConstant64 knows about the following optimizations.) twisti@4323: if (Assembler::is_simm13(lo) && value == lo) { twisti@4323: or3(G0, lo, d); twisti@4323: } else if (hi == 0) { twisti@4323: Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 twisti@4323: if (low10(lo) != 0) twisti@4323: or3(d, low10(lo), d); twisti@4323: } twisti@4323: else if (hi == -1) { twisti@4323: Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 twisti@4323: xor3(d, low10(lo) ^ ~low10(~0), d); twisti@4323: } twisti@4323: else if (lo == 0) { twisti@4323: if (Assembler::is_simm13(hi)) { twisti@4323: or3(G0, hi, d); twisti@4323: } else { twisti@4323: Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 twisti@4323: if (low10(hi) != 0) twisti@4323: or3(d, low10(hi), d); twisti@4323: } twisti@4323: sllx(d, 32, d); twisti@4323: } twisti@4323: else { twisti@4323: Assembler::sethi(hi, tmp); twisti@4323: Assembler::sethi(lo, d); // macro assembler version sign-extends twisti@4323: if (low10(hi) != 0) twisti@4323: or3 (tmp, low10(hi), tmp); twisti@4323: if (low10(lo) != 0) twisti@4323: or3 ( d, low10(lo), d); twisti@4323: sllx(tmp, 32, tmp); twisti@4323: or3 (d, tmp, d); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: int MacroAssembler::insts_for_set64(jlong value) { twisti@4323: v9_dep(); twisti@4323: twisti@4323: int hi = (int) (value >> 32); twisti@4323: int lo = (int) (value & ~0); twisti@4323: int count = 0; twisti@4323: twisti@4323: // (Matcher::isSimpleConstant64 knows about the following optimizations.) twisti@4323: if (Assembler::is_simm13(lo) && value == lo) { twisti@4323: count++; twisti@4323: } else if (hi == 0) { twisti@4323: count++; twisti@4323: if (low10(lo) != 0) twisti@4323: count++; twisti@4323: } twisti@4323: else if (hi == -1) { twisti@4323: count += 2; twisti@4323: } twisti@4323: else if (lo == 0) { twisti@4323: if (Assembler::is_simm13(hi)) { twisti@4323: count++; twisti@4323: } else { twisti@4323: count++; twisti@4323: if (low10(hi) != 0) twisti@4323: count++; twisti@4323: } twisti@4323: count++; twisti@4323: } twisti@4323: else { twisti@4323: count += 2; twisti@4323: if (low10(hi) != 0) twisti@4323: count++; twisti@4323: if (low10(lo) != 0) twisti@4323: count++; twisti@4323: count += 2; twisti@4323: } twisti@4323: return count; twisti@4323: } twisti@4323: twisti@4323: // compute size in bytes of sparc frame, given twisti@4323: // number of extraWords twisti@4323: int MacroAssembler::total_frame_size_in_bytes(int extraWords) { twisti@4323: twisti@4323: int nWords = frame::memory_parameter_word_sp_offset; twisti@4323: twisti@4323: nWords += extraWords; twisti@4323: twisti@4323: if (nWords & 1) ++nWords; // round up to double-word twisti@4323: twisti@4323: return nWords * BytesPerWord; twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // save_frame: given number of "extra" words in frame, twisti@4323: // issue approp. save instruction (p 200, v8 manual) twisti@4323: twisti@4323: void MacroAssembler::save_frame(int extraWords) { twisti@4323: int delta = -total_frame_size_in_bytes(extraWords); twisti@4323: if (is_simm13(delta)) { twisti@4323: save(SP, delta, SP); twisti@4323: } else { twisti@4323: set(delta, G3_scratch); twisti@4323: save(SP, G3_scratch, SP); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::save_frame_c1(int size_in_bytes) { twisti@4323: if (is_simm13(-size_in_bytes)) { twisti@4323: save(SP, -size_in_bytes, SP); twisti@4323: } else { twisti@4323: set(-size_in_bytes, G3_scratch); twisti@4323: save(SP, G3_scratch, SP); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::save_frame_and_mov(int extraWords, twisti@4323: Register s1, Register d1, twisti@4323: Register s2, Register d2) { twisti@4323: assert_not_delayed(); twisti@4323: twisti@4323: // The trick here is to use precisely the same memory word twisti@4323: // that trap handlers also use to save the register. twisti@4323: // This word cannot be used for any other purpose, but twisti@4323: // it works fine to save the register's value, whether or not twisti@4323: // an interrupt flushes register windows at any given moment! twisti@4323: Address s1_addr; twisti@4323: if (s1->is_valid() && (s1->is_in() || s1->is_local())) { twisti@4323: s1_addr = s1->address_in_saved_window(); twisti@4323: st_ptr(s1, s1_addr); twisti@4323: } twisti@4323: twisti@4323: Address s2_addr; twisti@4323: if (s2->is_valid() && (s2->is_in() || s2->is_local())) { twisti@4323: s2_addr = s2->address_in_saved_window(); twisti@4323: st_ptr(s2, s2_addr); twisti@4323: } twisti@4323: twisti@4323: save_frame(extraWords); twisti@4323: twisti@4323: if (s1_addr.base() == SP) { twisti@4323: ld_ptr(s1_addr.after_save(), d1); twisti@4323: } else if (s1->is_valid()) { twisti@4323: mov(s1->after_save(), d1); twisti@4323: } twisti@4323: twisti@4323: if (s2_addr.base() == SP) { twisti@4323: ld_ptr(s2_addr.after_save(), d2); twisti@4323: } else if (s2->is_valid()) { twisti@4323: mov(s2->after_save(), d2); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) { twisti@4323: assert(oop_recorder() != NULL, "this assembler needs a Recorder"); twisti@4323: int index = oop_recorder()->allocate_metadata_index(obj); twisti@4323: RelocationHolder rspec = metadata_Relocation::spec(index); twisti@4323: return AddressLiteral((address)obj, rspec); twisti@4323: } twisti@4323: twisti@4323: AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) { twisti@4323: assert(oop_recorder() != NULL, "this assembler needs a Recorder"); twisti@4323: int index = oop_recorder()->find_index(obj); twisti@4323: RelocationHolder rspec = metadata_Relocation::spec(index); twisti@4323: return AddressLiteral((address)obj, rspec); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { twisti@4323: assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4323: assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); twisti@4323: int oop_index = oop_recorder()->find_index(obj); twisti@4323: return AddressLiteral(obj, oop_Relocation::spec(oop_index)); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::set_narrow_oop(jobject obj, Register d) { twisti@4323: assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4323: int oop_index = oop_recorder()->find_index(obj); twisti@4323: RelocationHolder rspec = oop_Relocation::spec(oop_index); twisti@4323: twisti@4323: assert_not_delayed(); twisti@4323: // Relocation with special format (see relocInfo_sparc.hpp). twisti@4323: relocate(rspec, 1); twisti@4323: // Assembler::sethi(0x3fffff, d); twisti@4412: emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); twisti@4323: // Don't add relocation for 'add'. Do patching during 'sethi' processing. twisti@4323: add(d, 0x3ff, d); twisti@4323: twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::set_narrow_klass(Klass* k, Register d) { twisti@4323: assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); twisti@4323: int klass_index = oop_recorder()->find_index(k); twisti@4323: RelocationHolder rspec = metadata_Relocation::spec(klass_index); hseigel@5528: narrowOop encoded_k = Klass::encode_klass(k); twisti@4323: twisti@4323: assert_not_delayed(); twisti@4323: // Relocation with special format (see relocInfo_sparc.hpp). twisti@4323: relocate(rspec, 1); twisti@4323: // Assembler::sethi(encoded_k, d); twisti@4412: emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) ); twisti@4323: // Don't add relocation for 'add'. Do patching during 'sethi' processing. twisti@4323: add(d, low10(encoded_k), d); twisti@4323: twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::align(int modulus) { twisti@4323: while (offset() % modulus != 0) nop(); twisti@4323: } twisti@4323: twisti@4323: void RegistersForDebugging::print(outputStream* s) { twisti@4323: FlagSetting fs(Debugging, true); twisti@4323: int j; twisti@4323: for (j = 0; j < 8; ++j) { twisti@4323: if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); } twisti@4323: else { s->print( "fp = " ); os::print_location(s, i[j]); } twisti@4323: } twisti@4323: s->cr(); twisti@4323: twisti@4323: for (j = 0; j < 8; ++j) { twisti@4323: s->print("l%d = ", j); os::print_location(s, l[j]); twisti@4323: } twisti@4323: s->cr(); twisti@4323: twisti@4323: for (j = 0; j < 8; ++j) { twisti@4323: if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); } twisti@4323: else { s->print( "sp = " ); os::print_location(s, o[j]); } twisti@4323: } twisti@4323: s->cr(); twisti@4323: twisti@4323: for (j = 0; j < 8; ++j) { twisti@4323: s->print("g%d = ", j); os::print_location(s, g[j]); twisti@4323: } twisti@4323: s->cr(); twisti@4323: twisti@4323: // print out floats with compression twisti@4323: for (j = 0; j < 32; ) { twisti@4323: jfloat val = f[j]; twisti@4323: int last = j; twisti@4323: for ( ; last+1 < 32; ++last ) { twisti@4323: char b1[1024], b2[1024]; twisti@4323: sprintf(b1, "%f", val); twisti@4323: sprintf(b2, "%f", f[last+1]); twisti@4323: if (strcmp(b1, b2)) twisti@4323: break; twisti@4323: } twisti@4323: s->print("f%d", j); twisti@4323: if ( j != last ) s->print(" - f%d", last); twisti@4323: s->print(" = %f", val); twisti@4323: s->fill_to(25); twisti@4323: s->print_cr(" (0x%x)", val); twisti@4323: j = last + 1; twisti@4323: } twisti@4323: s->cr(); twisti@4323: twisti@4323: // and doubles (evens only) twisti@4323: for (j = 0; j < 32; ) { twisti@4323: jdouble val = d[j]; twisti@4323: int last = j; twisti@4323: for ( ; last+1 < 32; ++last ) { twisti@4323: char b1[1024], b2[1024]; twisti@4323: sprintf(b1, "%f", val); twisti@4323: sprintf(b2, "%f", d[last+1]); twisti@4323: if (strcmp(b1, b2)) twisti@4323: break; twisti@4323: } twisti@4323: s->print("d%d", 2 * j); twisti@4323: if ( j != last ) s->print(" - d%d", last); twisti@4323: s->print(" = %f", val); twisti@4323: s->fill_to(30); twisti@4323: s->print("(0x%x)", *(int*)&val); twisti@4323: s->fill_to(42); twisti@4323: s->print_cr("(0x%x)", *(1 + (int*)&val)); twisti@4323: j = last + 1; twisti@4323: } twisti@4323: s->cr(); twisti@4323: } twisti@4323: twisti@4323: void RegistersForDebugging::save_registers(MacroAssembler* a) { twisti@4323: a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); morris@5283: a->flushw(); twisti@4323: int i; twisti@4323: for (i = 0; i < 8; ++i) { twisti@4323: a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); twisti@4323: a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); twisti@4323: a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); twisti@4323: a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); twisti@4323: } twisti@4323: for (i = 0; i < 32; ++i) { twisti@4323: a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); twisti@4323: } morris@5283: for (i = 0; i < 64; i += 2) { twisti@4323: a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { twisti@4323: for (int i = 1; i < 8; ++i) { twisti@4323: a->ld_ptr(r, g_offset(i), as_gRegister(i)); twisti@4323: } twisti@4323: for (int j = 0; j < 32; ++j) { twisti@4323: a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); twisti@4323: } morris@5283: for (int k = 0; k < 64; k += 2) { twisti@4323: a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack twisti@4323: void MacroAssembler::push_fTOS() { twisti@4323: // %%%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: // pops double TOS element from CPU stack and pushes on FPU stack twisti@4323: void MacroAssembler::pop_fTOS() { twisti@4323: // %%%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::empty_FPU_stack() { twisti@4323: // %%%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { twisti@4323: // plausibility check for oops twisti@4323: if (!VerifyOops) return; twisti@4323: twisti@4323: if (reg == G0) return; // always NULL, which is always an oop twisti@4323: twisti@4323: BLOCK_COMMENT("verify_oop {"); twisti@4323: char buffer[64]; twisti@4323: #ifdef COMPILER1 twisti@4323: if (CommentedAssembly) { twisti@4323: snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); twisti@4323: block_comment(buffer); twisti@4323: } twisti@4323: #endif twisti@4323: roland@4767: const char* real_msg = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("%s at offset %d (%s:%d)", msg, offset(), file, line); roland@4767: real_msg = code_string(ss.as_string()); roland@4767: } twisti@4323: twisti@4323: // Call indirectly to solve generation ordering problem twisti@4323: AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); twisti@4323: twisti@4323: // Make some space on stack above the current register window. twisti@4323: // Enough to hold 8 64-bit registers. twisti@4323: add(SP,-8*8,SP); twisti@4323: twisti@4323: // Save some 64-bit registers; a normal 'save' chops the heads off twisti@4323: // of 64-bit longs in the 32-bit build. twisti@4323: stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); twisti@4323: stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); twisti@4323: mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed twisti@4323: stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); twisti@4323: twisti@4323: // Size of set() should stay the same twisti@4323: patchable_set((intptr_t)real_msg, O1); twisti@4323: // Load address to call to into O7 twisti@4323: load_ptr_contents(a, O7); twisti@4323: // Register call to verify_oop_subroutine twisti@4323: callr(O7, G0); twisti@4323: delayed()->nop(); twisti@4323: // recover frame size twisti@4323: add(SP, 8*8,SP); twisti@4323: BLOCK_COMMENT("} verify_oop"); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { twisti@4323: // plausibility check for oops twisti@4323: if (!VerifyOops) return; twisti@4323: roland@4767: const char* real_msg = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); roland@4767: real_msg = code_string(ss.as_string()); roland@4767: } twisti@4323: twisti@4323: // Call indirectly to solve generation ordering problem twisti@4323: AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); twisti@4323: twisti@4323: // Make some space on stack above the current register window. twisti@4323: // Enough to hold 8 64-bit registers. twisti@4323: add(SP,-8*8,SP); twisti@4323: twisti@4323: // Save some 64-bit registers; a normal 'save' chops the heads off twisti@4323: // of 64-bit longs in the 32-bit build. twisti@4323: stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); twisti@4323: stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); twisti@4323: ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed twisti@4323: stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); twisti@4323: twisti@4323: // Size of set() should stay the same twisti@4323: patchable_set((intptr_t)real_msg, O1); twisti@4323: // Load address to call to into O7 twisti@4323: load_ptr_contents(a, O7); twisti@4323: // Register call to verify_oop_subroutine twisti@4323: callr(O7, G0); twisti@4323: delayed()->nop(); twisti@4323: // recover frame size twisti@4323: add(SP, 8*8,SP); twisti@4323: } twisti@4323: twisti@4323: // side-door communication with signalHandler in os_solaris.cpp twisti@4323: address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; twisti@4323: twisti@4323: // This macro is expanded just once; it creates shared code. Contract: twisti@4323: // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY twisti@4323: // registers, including flags. May not use a register 'save', as this blows twisti@4323: // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' twisti@4323: // call. twisti@4323: void MacroAssembler::verify_oop_subroutine() { twisti@4323: // Leaf call; no frame. twisti@4323: Label succeed, fail, null_or_fail; twisti@4323: twisti@4323: // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). twisti@4323: // O0 is now the oop to be checked. O7 is the return address. twisti@4323: Register O0_obj = O0; twisti@4323: twisti@4323: // Save some more registers for temps. twisti@4323: stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); twisti@4323: stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); twisti@4323: stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); twisti@4323: stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); twisti@4323: twisti@4323: // Save flags twisti@4323: Register O5_save_flags = O5; twisti@4323: rdccr( O5_save_flags ); twisti@4323: twisti@4323: { // count number of verifies twisti@4323: Register O2_adr = O2; twisti@4323: Register O3_accum = O3; twisti@4323: inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum); twisti@4323: } twisti@4323: twisti@4323: Register O2_mask = O2; twisti@4323: Register O3_bits = O3; twisti@4323: Register O4_temp = O4; twisti@4323: twisti@4323: // mark lower end of faulting range twisti@4323: assert(_verify_oop_implicit_branch[0] == NULL, "set once"); twisti@4323: _verify_oop_implicit_branch[0] = pc(); twisti@4323: twisti@4323: // We can't check the mark oop because it could be in the process of twisti@4323: // locking or unlocking while this is running. twisti@4323: set(Universe::verify_oop_mask (), O2_mask); twisti@4323: set(Universe::verify_oop_bits (), O3_bits); twisti@4323: twisti@4323: // assert((obj & oop_mask) == oop_bits); twisti@4323: and3(O0_obj, O2_mask, O4_temp); twisti@4323: cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail); twisti@4323: twisti@4323: if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { twisti@4323: // the null_or_fail case is useless; must test for null separately twisti@4323: br_null_short(O0_obj, pn, succeed); twisti@4323: } twisti@4323: twisti@4323: // Check the Klass* of this object for being in the right area of memory. twisti@4323: // Cannot do the load in the delay above slot in case O0 is null twisti@4323: load_klass(O0_obj, O0_obj); twisti@4323: // assert((klass != NULL) twisti@4323: br_null_short(O0_obj, pn, fail); twisti@4323: twisti@4323: wrccr( O5_save_flags ); // Restore CCR's twisti@4323: twisti@4323: // mark upper end of faulting range twisti@4323: _verify_oop_implicit_branch[1] = pc(); twisti@4323: twisti@4323: //----------------------- twisti@4323: // all tests pass twisti@4323: bind(succeed); twisti@4323: twisti@4323: // Restore prior 64-bit registers twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); twisti@4323: ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); twisti@4323: twisti@4323: retl(); // Leaf return; restore prior O7 in delay slot twisti@4323: delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); twisti@4323: twisti@4323: //----------------------- twisti@4323: bind(null_or_fail); // nulls are less common but OK twisti@4323: br_null(O0_obj, false, pt, succeed); twisti@4323: delayed()->wrccr( O5_save_flags ); // Restore CCR's twisti@4323: twisti@4323: //----------------------- twisti@4323: // report failure: twisti@4323: bind(fail); twisti@4323: _verify_oop_implicit_branch[2] = pc(); twisti@4323: twisti@4323: wrccr( O5_save_flags ); // Restore CCR's twisti@4323: twisti@4323: save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); twisti@4323: twisti@4323: // stop_subroutine expects message pointer in I1. twisti@4323: mov(I1, O1); twisti@4323: twisti@4323: // Restore prior 64-bit registers twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); twisti@4323: ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); twisti@4323: twisti@4323: // factor long stop-sequence into subroutine to save space twisti@4323: assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); twisti@4323: twisti@4323: // call indirectly to solve generation ordering problem twisti@4323: AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address()); twisti@4323: load_ptr_contents(al, O5); twisti@4323: jmpl(O5, 0, O7); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::stop(const char* msg) { twisti@4323: // save frame first to get O7 for return address twisti@4323: // add one word to size in case struct is odd number of words long twisti@4323: // It must be doubleword-aligned for storing doubles into it. twisti@4323: twisti@4323: save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); twisti@4323: twisti@4323: // stop_subroutine expects message pointer in I1. twisti@4323: // Size of set() should stay the same twisti@4323: patchable_set((intptr_t)msg, O1); twisti@4323: twisti@4323: // factor long stop-sequence into subroutine to save space twisti@4323: assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); twisti@4323: twisti@4323: // call indirectly to solve generation ordering problem twisti@4323: AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address()); twisti@4323: load_ptr_contents(a, O5); twisti@4323: jmpl(O5, 0, O7); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: breakpoint_trap(); // make stop actually stop rather than writing twisti@4323: // unnoticeable results in the output files. twisti@4323: twisti@4323: // restore(); done in callee to save space! twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::warn(const char* msg) { twisti@4323: save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); twisti@4323: RegistersForDebugging::save_registers(this); twisti@4323: mov(O0, L0); twisti@4323: // Size of set() should stay the same twisti@4323: patchable_set((intptr_t)msg, O0); twisti@4323: call( CAST_FROM_FN_PTR(address, warning) ); twisti@4323: delayed()->nop(); twisti@4323: // ret(); twisti@4323: // delayed()->restore(); twisti@4323: RegistersForDebugging::restore_registers(this, L0); twisti@4323: restore(); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::untested(const char* what) { twisti@4323: // We must be able to turn interactive prompting off twisti@4323: // in order to run automated test scripts on the VM twisti@4323: // Use the flag ShowMessageBoxOnError twisti@4323: roland@4767: const char* b = NULL; roland@4767: { roland@4767: ResourceMark rm; roland@4767: stringStream ss; roland@4767: ss.print("untested: %s", what); roland@4767: b = code_string(ss.as_string()); roland@4767: } twisti@4323: if (ShowMessageBoxOnError) { STOP(b); } twisti@4323: else { warn(b); } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::stop_subroutine() { twisti@4323: RegistersForDebugging::save_registers(this); twisti@4323: twisti@4323: // for the sake of the debugger, stick a PC on the current frame twisti@4323: // (this assumes that the caller has performed an extra "save") twisti@4323: mov(I7, L7); twisti@4323: add(O7, -7 * BytesPerInt, I7); twisti@4323: twisti@4323: save_frame(); // one more save to free up another O7 register twisti@4323: mov(I0, O1); // addr of reg save area twisti@4323: twisti@4323: // We expect pointer to message in I1. Caller must set it up in O1 twisti@4323: mov(I1, O0); // get msg twisti@4323: call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: restore(); twisti@4323: twisti@4323: RegistersForDebugging::restore_registers(this, O0); twisti@4323: twisti@4323: save_frame(0); twisti@4323: call(CAST_FROM_FN_PTR(address,breakpoint)); twisti@4323: delayed()->nop(); twisti@4323: restore(); twisti@4323: twisti@4323: mov(L7, I7); twisti@4323: retl(); twisti@4323: delayed()->restore(); // see stop above twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { twisti@4323: if ( ShowMessageBoxOnError ) { twisti@4323: JavaThread* thread = JavaThread::current(); twisti@4323: JavaThreadState saved_state = thread->thread_state(); twisti@4323: thread->set_thread_state(_thread_in_vm); twisti@4323: { twisti@4323: // In order to get locks work, we need to fake a in_VM state twisti@4323: ttyLocker ttyl; twisti@4323: ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); twisti@4323: if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { twisti@4323: BytecodeCounter::print(); twisti@4323: } twisti@4323: if (os::message_box(msg, "Execution stopped, print registers?")) twisti@4323: regs->print(::tty); twisti@4323: } twisti@4323: BREAKPOINT; twisti@4323: ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); twisti@4323: } twisti@4323: else { twisti@4323: ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); twisti@4323: } twisti@4323: assert(false, err_msg("DEBUG MESSAGE: %s", msg)); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { twisti@4323: subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? twisti@4323: Label no_extras; twisti@4323: br( negative, true, pt, no_extras ); // if neg, clear reg twisti@4323: delayed()->set(0, Rresult); // annuled, so only if taken twisti@4323: bind( no_extras ); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { twisti@4323: #ifdef _LP64 twisti@4323: add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); twisti@4323: #else twisti@4323: add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); twisti@4323: #endif twisti@4323: bclr(1, Rresult); twisti@4323: sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { twisti@4323: calc_frame_size(Rextra_words, Rresult); twisti@4323: neg(Rresult); twisti@4323: save(SP, Rresult, SP); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // --------------------------------------------------------- twisti@4323: Assembler::RCondition cond2rcond(Assembler::Condition c) { twisti@4323: switch (c) { twisti@4323: /*case zero: */ twisti@4323: case Assembler::equal: return Assembler::rc_z; twisti@4323: case Assembler::lessEqual: return Assembler::rc_lez; twisti@4323: case Assembler::less: return Assembler::rc_lz; twisti@4323: /*case notZero:*/ twisti@4323: case Assembler::notEqual: return Assembler::rc_nz; twisti@4323: case Assembler::greater: return Assembler::rc_gz; twisti@4323: case Assembler::greaterEqual: return Assembler::rc_gez; twisti@4323: } twisti@4323: ShouldNotReachHere(); twisti@4323: return Assembler::rc_z; twisti@4323: } twisti@4323: twisti@4323: // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS twisti@4323: void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) { twisti@4323: tst(s1); twisti@4323: br (c, a, p, L); twisti@4323: } twisti@4323: twisti@4323: // Compares a pointer register with zero and branches on null. twisti@4323: // Does a test & branch on 32-bit systems and a register-branch on 64-bit. twisti@4323: void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { twisti@4323: assert_not_delayed(); twisti@4323: #ifdef _LP64 twisti@4323: bpr( rc_z, a, p, s1, L ); twisti@4323: #else twisti@4323: tst(s1); twisti@4323: br ( zero, a, p, L ); twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { twisti@4323: assert_not_delayed(); twisti@4323: #ifdef _LP64 twisti@4323: bpr( rc_nz, a, p, s1, L ); twisti@4323: #else twisti@4323: tst(s1); twisti@4323: br ( notZero, a, p, L ); twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: // Compare registers and branch with nop in delay slot or cbcond without delay slot. twisti@4323: twisti@4323: // Compare integer (32 bit) values (icc only). twisti@4323: void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c, twisti@4323: Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (use_cbcond(L)) { twisti@4323: Assembler::cbcond(c, icc, s1, s2, L); twisti@4323: } else { twisti@4323: cmp(s1, s2); twisti@4323: br(c, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Compare integer (32 bit) values (icc only). twisti@4323: void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, twisti@4323: Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (is_simm(simm13a,5) && use_cbcond(L)) { twisti@4323: Assembler::cbcond(c, icc, s1, simm13a, L); twisti@4323: } else { twisti@4323: cmp(s1, simm13a); twisti@4323: br(c, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Branch that tests xcc in LP64 and icc in !LP64 twisti@4323: void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c, twisti@4323: Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (use_cbcond(L)) { twisti@4323: Assembler::cbcond(c, ptr_cc, s1, s2, L); twisti@4323: } else { twisti@4323: cmp(s1, s2); twisti@4323: brx(c, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Branch that tests xcc in LP64 and icc in !LP64 twisti@4323: void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, twisti@4323: Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (is_simm(simm13a,5) && use_cbcond(L)) { twisti@4323: Assembler::cbcond(c, ptr_cc, s1, simm13a, L); twisti@4323: } else { twisti@4323: cmp(s1, simm13a); twisti@4323: brx(c, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Short branch version for compares a pointer with zero. twisti@4323: twisti@4323: void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (use_cbcond(L)) { twisti@4323: Assembler::cbcond(zero, ptr_cc, s1, 0, L); twisti@4323: return; twisti@4323: } twisti@4323: br_null(s1, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) { twisti@4323: assert_not_delayed(); twisti@4323: if (use_cbcond(L)) { twisti@4323: Assembler::cbcond(notZero, ptr_cc, s1, 0, L); twisti@4323: return; twisti@4323: } twisti@4323: br_notnull(s1, false, p, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: // Unconditional short branch twisti@4323: void MacroAssembler::ba_short(Label& L) { twisti@4323: if (use_cbcond(L)) { twisti@4323: Assembler::cbcond(equal, icc, G0, G0, L); twisti@4323: return; twisti@4323: } twisti@4323: br(always, false, pt, L); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: // instruction sequences factored across compiler & interpreter twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, twisti@4323: Register Rb_hi, Register Rb_low, twisti@4323: Register Rresult) { twisti@4323: twisti@4323: Label check_low_parts, done; twisti@4323: twisti@4323: cmp(Ra_hi, Rb_hi ); // compare hi parts twisti@4323: br(equal, true, pt, check_low_parts); twisti@4323: delayed()->cmp(Ra_low, Rb_low); // test low parts twisti@4323: twisti@4323: // And, with an unsigned comparison, it does not matter if the numbers twisti@4323: // are negative or not. twisti@4323: // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. twisti@4323: // The second one is bigger (unsignedly). twisti@4323: twisti@4323: // Other notes: The first move in each triplet can be unconditional twisti@4323: // (and therefore probably prefetchable). twisti@4323: // And the equals case for the high part does not need testing, twisti@4323: // since that triplet is reached only after finding the high halves differ. twisti@4323: morris@5283: mov(-1, Rresult); morris@5283: ba(done); morris@5283: delayed()->movcc(greater, false, icc, 1, Rresult); morris@5283: morris@5283: bind(check_low_parts); morris@5283: morris@5283: mov( -1, Rresult); morris@5283: movcc(equal, false, icc, 0, Rresult); morris@5283: movcc(greaterUnsigned, false, icc, 1, Rresult); morris@5283: morris@5283: bind(done); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::lneg( Register Rhi, Register Rlow ) { twisti@4323: subcc( G0, Rlow, Rlow ); twisti@4323: subc( G0, Rhi, Rhi ); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::lshl( Register Rin_high, Register Rin_low, twisti@4323: Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, twisti@4323: Register Rtemp ) { twisti@4323: twisti@4323: twisti@4323: Register Ralt_count = Rtemp; twisti@4323: Register Rxfer_bits = Rtemp; twisti@4323: twisti@4323: assert( Ralt_count != Rin_high twisti@4323: && Ralt_count != Rin_low twisti@4323: && Ralt_count != Rcount twisti@4323: && Rxfer_bits != Rin_low twisti@4323: && Rxfer_bits != Rin_high twisti@4323: && Rxfer_bits != Rcount twisti@4323: && Rxfer_bits != Rout_low twisti@4323: && Rout_low != Rin_high, twisti@4323: "register alias checks"); twisti@4323: twisti@4323: Label big_shift, done; twisti@4323: twisti@4323: // This code can be optimized to use the 64 bit shifts in V9. twisti@4323: // Here we use the 32 bit shifts. twisti@4323: twisti@4323: and3( Rcount, 0x3f, Rcount); // take least significant 6 bits twisti@4323: subcc(Rcount, 31, Ralt_count); twisti@4323: br(greater, true, pn, big_shift); twisti@4323: delayed()->dec(Ralt_count); twisti@4323: twisti@4323: // shift < 32 bits, Ralt_count = Rcount-31 twisti@4323: twisti@4323: // We get the transfer bits by shifting right by 32-count the low twisti@4323: // register. This is done by shifting right by 31-count and then by one twisti@4323: // more to take care of the special (rare) case where count is zero twisti@4323: // (shifting by 32 would not work). twisti@4323: twisti@4323: neg(Ralt_count); twisti@4323: twisti@4323: // The order of the next two instructions is critical in the case where twisti@4323: // Rin and Rout are the same and should not be reversed. twisti@4323: twisti@4323: srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count twisti@4323: if (Rcount != Rout_low) { twisti@4323: sll(Rin_low, Rcount, Rout_low); // low half twisti@4323: } twisti@4323: sll(Rin_high, Rcount, Rout_high); twisti@4323: if (Rcount == Rout_low) { twisti@4323: sll(Rin_low, Rcount, Rout_low); // low half twisti@4323: } twisti@4323: srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more twisti@4323: ba(done); twisti@4323: delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low twisti@4323: twisti@4323: // shift >= 32 bits, Ralt_count = Rcount-32 twisti@4323: bind(big_shift); twisti@4323: sll(Rin_low, Ralt_count, Rout_high ); twisti@4323: clr(Rout_low); twisti@4323: twisti@4323: bind(done); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::lshr( Register Rin_high, Register Rin_low, twisti@4323: Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, twisti@4323: Register Rtemp ) { twisti@4323: twisti@4323: Register Ralt_count = Rtemp; twisti@4323: Register Rxfer_bits = Rtemp; twisti@4323: twisti@4323: assert( Ralt_count != Rin_high twisti@4323: && Ralt_count != Rin_low twisti@4323: && Ralt_count != Rcount twisti@4323: && Rxfer_bits != Rin_low twisti@4323: && Rxfer_bits != Rin_high twisti@4323: && Rxfer_bits != Rcount twisti@4323: && Rxfer_bits != Rout_high twisti@4323: && Rout_high != Rin_low, twisti@4323: "register alias checks"); twisti@4323: twisti@4323: Label big_shift, done; twisti@4323: twisti@4323: // This code can be optimized to use the 64 bit shifts in V9. twisti@4323: // Here we use the 32 bit shifts. twisti@4323: twisti@4323: and3( Rcount, 0x3f, Rcount); // take least significant 6 bits twisti@4323: subcc(Rcount, 31, Ralt_count); twisti@4323: br(greater, true, pn, big_shift); twisti@4323: delayed()->dec(Ralt_count); twisti@4323: twisti@4323: // shift < 32 bits, Ralt_count = Rcount-31 twisti@4323: twisti@4323: // We get the transfer bits by shifting left by 32-count the high twisti@4323: // register. This is done by shifting left by 31-count and then by one twisti@4323: // more to take care of the special (rare) case where count is zero twisti@4323: // (shifting by 32 would not work). twisti@4323: twisti@4323: neg(Ralt_count); twisti@4323: if (Rcount != Rout_low) { twisti@4323: srl(Rin_low, Rcount, Rout_low); twisti@4323: } twisti@4323: twisti@4323: // The order of the next two instructions is critical in the case where twisti@4323: // Rin and Rout are the same and should not be reversed. twisti@4323: twisti@4323: sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count twisti@4323: sra(Rin_high, Rcount, Rout_high ); // high half twisti@4323: sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more twisti@4323: if (Rcount == Rout_low) { twisti@4323: srl(Rin_low, Rcount, Rout_low); twisti@4323: } twisti@4323: ba(done); twisti@4323: delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high twisti@4323: twisti@4323: // shift >= 32 bits, Ralt_count = Rcount-32 twisti@4323: bind(big_shift); twisti@4323: twisti@4323: sra(Rin_high, Ralt_count, Rout_low); twisti@4323: sra(Rin_high, 31, Rout_high); // sign into hi twisti@4323: twisti@4323: bind( done ); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::lushr( Register Rin_high, Register Rin_low, twisti@4323: Register Rcount, twisti@4323: Register Rout_high, Register Rout_low, twisti@4323: Register Rtemp ) { twisti@4323: twisti@4323: Register Ralt_count = Rtemp; twisti@4323: Register Rxfer_bits = Rtemp; twisti@4323: twisti@4323: assert( Ralt_count != Rin_high twisti@4323: && Ralt_count != Rin_low twisti@4323: && Ralt_count != Rcount twisti@4323: && Rxfer_bits != Rin_low twisti@4323: && Rxfer_bits != Rin_high twisti@4323: && Rxfer_bits != Rcount twisti@4323: && Rxfer_bits != Rout_high twisti@4323: && Rout_high != Rin_low, twisti@4323: "register alias checks"); twisti@4323: twisti@4323: Label big_shift, done; twisti@4323: twisti@4323: // This code can be optimized to use the 64 bit shifts in V9. twisti@4323: // Here we use the 32 bit shifts. twisti@4323: twisti@4323: and3( Rcount, 0x3f, Rcount); // take least significant 6 bits twisti@4323: subcc(Rcount, 31, Ralt_count); twisti@4323: br(greater, true, pn, big_shift); twisti@4323: delayed()->dec(Ralt_count); twisti@4323: twisti@4323: // shift < 32 bits, Ralt_count = Rcount-31 twisti@4323: twisti@4323: // We get the transfer bits by shifting left by 32-count the high twisti@4323: // register. This is done by shifting left by 31-count and then by one twisti@4323: // more to take care of the special (rare) case where count is zero twisti@4323: // (shifting by 32 would not work). twisti@4323: twisti@4323: neg(Ralt_count); twisti@4323: if (Rcount != Rout_low) { twisti@4323: srl(Rin_low, Rcount, Rout_low); twisti@4323: } twisti@4323: twisti@4323: // The order of the next two instructions is critical in the case where twisti@4323: // Rin and Rout are the same and should not be reversed. twisti@4323: twisti@4323: sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count twisti@4323: srl(Rin_high, Rcount, Rout_high ); // high half twisti@4323: sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more twisti@4323: if (Rcount == Rout_low) { twisti@4323: srl(Rin_low, Rcount, Rout_low); twisti@4323: } twisti@4323: ba(done); twisti@4323: delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high twisti@4323: twisti@4323: // shift >= 32 bits, Ralt_count = Rcount-32 twisti@4323: bind(big_shift); twisti@4323: twisti@4323: srl(Rin_high, Ralt_count, Rout_low); twisti@4323: clr(Rout_high); twisti@4323: twisti@4323: bind( done ); twisti@4323: } twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { twisti@4323: cmp(Ra, Rb); twisti@4323: mov(-1, Rresult); twisti@4323: movcc(equal, false, xcc, 0, Rresult); twisti@4323: movcc(greater, false, xcc, 1, Rresult); twisti@4323: } twisti@4323: #endif twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) { twisti@4323: switch (size_in_bytes) { twisti@4323: case 8: ld_long(src, dst); break; twisti@4323: case 4: ld( src, dst); break; twisti@4323: case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break; twisti@4323: case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break; twisti@4323: default: ShouldNotReachHere(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) { twisti@4323: switch (size_in_bytes) { twisti@4323: case 8: st_long(src, dst); break; twisti@4323: case 4: st( src, dst); break; twisti@4323: case 2: sth( src, dst); break; twisti@4323: case 1: stb( src, dst); break; twisti@4323: default: ShouldNotReachHere(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::float_cmp( bool is_float, int unordered_result, twisti@4323: FloatRegister Fa, FloatRegister Fb, twisti@4323: Register Rresult) { morris@5283: if (is_float) { morris@5283: fcmp(FloatRegisterImpl::S, fcc0, Fa, Fb); twisti@4323: } else { morris@5283: fcmp(FloatRegisterImpl::D, fcc0, Fa, Fb); morris@5283: } morris@5283: morris@5283: if (unordered_result == 1) { morris@5283: mov( -1, Rresult); morris@5283: movcc(f_equal, true, fcc0, 0, Rresult); morris@5283: movcc(f_unorderedOrGreater, true, fcc0, 1, Rresult); morris@5283: } else { morris@5283: mov( -1, Rresult); morris@5283: movcc(f_equal, true, fcc0, 0, Rresult); morris@5283: movcc(f_greater, true, fcc0, 1, Rresult); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::save_all_globals_into_locals() { twisti@4323: mov(G1,L1); twisti@4323: mov(G2,L2); twisti@4323: mov(G3,L3); twisti@4323: mov(G4,L4); twisti@4323: mov(G5,L5); twisti@4323: mov(G6,L6); twisti@4323: mov(G7,L7); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::restore_globals_from_locals() { twisti@4323: mov(L1,G1); twisti@4323: mov(L2,G2); twisti@4323: mov(L3,G3); twisti@4323: mov(L4,G4); twisti@4323: mov(L5,G5); twisti@4323: mov(L6,G6); twisti@4323: mov(L7,G7); twisti@4323: } twisti@4323: twisti@4323: RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, twisti@4323: Register tmp, twisti@4323: int offset) { twisti@4323: intptr_t value = *delayed_value_addr; twisti@4323: if (value != 0) twisti@4323: return RegisterOrConstant(value + offset); twisti@4323: twisti@4323: // load indirectly to solve generation ordering problem twisti@4323: AddressLiteral a(delayed_value_addr); twisti@4323: load_ptr_contents(a, tmp); twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: tst(tmp); twisti@4323: breakpoint_trap(zero, xcc); twisti@4323: #endif twisti@4323: twisti@4323: if (offset != 0) twisti@4323: add(tmp, offset, tmp); twisti@4323: twisti@4323: return RegisterOrConstant(tmp); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { twisti@4323: assert(d.register_or_noreg() != G0, "lost side effect"); twisti@4323: if ((s2.is_constant() && s2.as_constant() == 0) || twisti@4323: (s2.is_register() && s2.as_register() == G0)) { twisti@4323: // Do nothing, just move value. twisti@4323: if (s1.is_register()) { twisti@4323: if (d.is_constant()) d = temp; twisti@4323: mov(s1.as_register(), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: return s1; twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: if (s1.is_register()) { twisti@4323: assert_different_registers(s1.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: if (s2.is_register()) { twisti@4323: assert_different_registers(s2.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: set(s1.as_constant(), temp); twisti@4323: andn(temp, s2.as_register(), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: intptr_t res = s1.as_constant() & ~s2.as_constant(); twisti@4323: return res; twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { twisti@4323: assert(d.register_or_noreg() != G0, "lost side effect"); twisti@4323: if ((s2.is_constant() && s2.as_constant() == 0) || twisti@4323: (s2.is_register() && s2.as_register() == G0)) { twisti@4323: // Do nothing, just move value. twisti@4323: if (s1.is_register()) { twisti@4323: if (d.is_constant()) d = temp; twisti@4323: mov(s1.as_register(), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: return s1; twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: if (s1.is_register()) { twisti@4323: assert_different_registers(s1.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: if (s2.is_register()) { twisti@4323: assert_different_registers(s2.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: intptr_t res = s1.as_constant() + s2.as_constant(); twisti@4323: return res; twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { twisti@4323: assert(d.register_or_noreg() != G0, "lost side effect"); twisti@4323: if (!is_simm13(s2.constant_or_zero())) twisti@4323: s2 = (s2.as_constant() & 0xFF); twisti@4323: if ((s2.is_constant() && s2.as_constant() == 0) || twisti@4323: (s2.is_register() && s2.as_register() == G0)) { twisti@4323: // Do nothing, just move value. twisti@4323: if (s1.is_register()) { twisti@4323: if (d.is_constant()) d = temp; twisti@4323: mov(s1.as_register(), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: return s1; twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: if (s1.is_register()) { twisti@4323: assert_different_registers(s1.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: if (s2.is_register()) { twisti@4323: assert_different_registers(s2.as_register(), temp); twisti@4323: if (d.is_constant()) d = temp; twisti@4323: set(s1.as_constant(), temp); twisti@4323: sll_ptr(temp, s2.as_register(), d.as_register()); twisti@4323: return d; twisti@4323: } else { twisti@4323: intptr_t res = s1.as_constant() << s2.as_constant(); twisti@4323: return res; twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // Look up the method for a megamorphic invokeinterface call. twisti@4323: // The target method is determined by . twisti@4323: // The receiver klass is in recv_klass. twisti@4323: // On success, the result will be in method_result, and execution falls through. twisti@4323: // On failure, execution transfers to the given label. twisti@4323: void MacroAssembler::lookup_interface_method(Register recv_klass, twisti@4323: Register intf_klass, twisti@4323: RegisterOrConstant itable_index, twisti@4323: Register method_result, twisti@4323: Register scan_temp, twisti@4323: Register sethi_temp, twisti@4323: Label& L_no_such_interface) { twisti@4323: assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); twisti@4323: assert(itable_index.is_constant() || itable_index.as_register() == method_result, twisti@4323: "caller must use same register for non-constant itable index as for method"); twisti@4323: twisti@4323: Label L_no_such_interface_restore; twisti@4323: bool did_save = false; twisti@4323: if (scan_temp == noreg || sethi_temp == noreg) { twisti@4323: Register recv_2 = recv_klass->is_global() ? recv_klass : L0; twisti@4323: Register intf_2 = intf_klass->is_global() ? intf_klass : L1; twisti@4323: assert(method_result->is_global(), "must be able to return value"); twisti@4323: scan_temp = L2; twisti@4323: sethi_temp = L3; twisti@4323: save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2); twisti@4323: recv_klass = recv_2; twisti@4323: intf_klass = intf_2; twisti@4323: did_save = true; twisti@4323: } twisti@4323: twisti@4323: // Compute start of first itableOffsetEntry (which is at the end of the vtable) twisti@4323: int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; twisti@4323: int scan_step = itableOffsetEntry::size() * wordSize; twisti@4323: int vte_size = vtableEntry::size() * wordSize; twisti@4323: twisti@4323: lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp); twisti@4323: // %%% We should store the aligned, prescaled offset in the klassoop. twisti@4323: // Then the next several instructions would fold away. twisti@4323: twisti@4323: int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); twisti@4323: int itb_offset = vtable_base; twisti@4323: if (round_to_unit != 0) { twisti@4323: // hoist first instruction of round_to(scan_temp, BytesPerLong): twisti@4323: itb_offset += round_to_unit - wordSize; twisti@4323: } twisti@4323: int itb_scale = exact_log2(vtableEntry::size() * wordSize); twisti@4323: sll(scan_temp, itb_scale, scan_temp); twisti@4323: add(scan_temp, itb_offset, scan_temp); twisti@4323: if (round_to_unit != 0) { twisti@4323: // Round up to align_object_offset boundary twisti@4323: // see code for InstanceKlass::start_of_itable! twisti@4323: // Was: round_to(scan_temp, BytesPerLong); twisti@4323: // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); twisti@4323: and3(scan_temp, -round_to_unit, scan_temp); twisti@4323: } twisti@4323: add(recv_klass, scan_temp, scan_temp); twisti@4323: twisti@4323: // Adjust recv_klass by scaled itable_index, so we can free itable_index. twisti@4323: RegisterOrConstant itable_offset = itable_index; twisti@4323: itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset); twisti@4323: itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset); twisti@4323: add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass); twisti@4323: twisti@4323: // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { twisti@4323: // if (scan->interface() == intf) { twisti@4323: // result = (klass + scan->offset() + itable_index); twisti@4323: // } twisti@4323: // } twisti@4323: Label L_search, L_found_method; twisti@4323: twisti@4323: for (int peel = 1; peel >= 0; peel--) { twisti@4323: // %%%% Could load both offset and interface in one ldx, if they were twisti@4323: // in the opposite order. This would save a load. twisti@4323: ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); twisti@4323: twisti@4323: // Check that this entry is non-null. A null entry means that twisti@4323: // the receiver class doesn't implement the interface, and wasn't the twisti@4323: // same as when the caller was compiled. twisti@4323: bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface); twisti@4323: delayed()->cmp(method_result, intf_klass); twisti@4323: twisti@4323: if (peel) { twisti@4323: brx(Assembler::equal, false, Assembler::pt, L_found_method); twisti@4323: } else { twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, L_search); twisti@4323: // (invert the test to fall through to found_method...) twisti@4323: } twisti@4323: delayed()->add(scan_temp, scan_step, scan_temp); twisti@4323: twisti@4323: if (!peel) break; twisti@4323: twisti@4323: bind(L_search); twisti@4323: } twisti@4323: twisti@4323: bind(L_found_method); twisti@4323: twisti@4323: // Got a hit. twisti@4323: int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); twisti@4323: // scan_temp[-scan_step] points to the vtable offset we need twisti@4323: ito_offset -= scan_step; twisti@4323: lduw(scan_temp, ito_offset, scan_temp); twisti@4323: ld_ptr(recv_klass, scan_temp, method_result); twisti@4323: twisti@4323: if (did_save) { twisti@4323: Label L_done; twisti@4323: ba(L_done); twisti@4323: delayed()->restore(); twisti@4323: twisti@4323: bind(L_no_such_interface_restore); twisti@4323: ba(L_no_such_interface); twisti@4323: delayed()->restore(); twisti@4323: twisti@4323: bind(L_done); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // virtual method calling twisti@4323: void MacroAssembler::lookup_virtual_method(Register recv_klass, twisti@4323: RegisterOrConstant vtable_index, twisti@4323: Register method_result) { twisti@4323: assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg()); twisti@4323: Register sethi_temp = method_result; twisti@4323: const int base = (InstanceKlass::vtable_start_offset() * wordSize + twisti@4323: // method pointer offset within the vtable entry: twisti@4323: vtableEntry::method_offset_in_bytes()); twisti@4323: RegisterOrConstant vtable_offset = vtable_index; twisti@4323: // Each of the following three lines potentially generates an instruction. twisti@4323: // But the total number of address formation instructions will always be twisti@4323: // at most two, and will often be zero. In any case, it will be optimal. twisti@4323: // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x). twisti@4323: // If vtable_index is a constant, we will have at most (set B+X<is_global()) sub_2 = L0; twisti@4323: if (!sup_2->is_global()) sup_2 = L1; twisti@4323: bool did_save = false; twisti@4323: if (temp_reg == noreg || temp2_reg == noreg) { twisti@4323: temp_reg = L2; twisti@4323: temp2_reg = L3; twisti@4323: save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); twisti@4323: sub_klass = sub_2; twisti@4323: super_klass = sup_2; twisti@4323: did_save = true; twisti@4323: } twisti@4323: Label L_failure, L_pop_to_failure, L_pop_to_success; twisti@4323: check_klass_subtype_fast_path(sub_klass, super_klass, twisti@4323: temp_reg, temp2_reg, twisti@4323: (did_save ? &L_pop_to_success : &L_success), twisti@4323: (did_save ? &L_pop_to_failure : &L_failure), NULL); twisti@4323: twisti@4323: if (!did_save) twisti@4323: save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); twisti@4323: check_klass_subtype_slow_path(sub_2, sup_2, twisti@4323: L2, L3, L4, L5, twisti@4323: NULL, &L_pop_to_failure); twisti@4323: twisti@4323: // on success: twisti@4323: bind(L_pop_to_success); twisti@4323: restore(); twisti@4323: ba_short(L_success); twisti@4323: twisti@4323: // on failure: twisti@4323: bind(L_pop_to_failure); twisti@4323: restore(); twisti@4323: bind(L_failure); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, twisti@4323: Register super_klass, twisti@4323: Register temp_reg, twisti@4323: Register temp2_reg, twisti@4323: Label* L_success, twisti@4323: Label* L_failure, twisti@4323: Label* L_slow_path, twisti@4323: RegisterOrConstant super_check_offset) { twisti@4323: int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); twisti@4323: int sco_offset = in_bytes(Klass::super_check_offset_offset()); twisti@4323: twisti@4323: bool must_load_sco = (super_check_offset.constant_or_zero() == -1); twisti@4323: bool need_slow_path = (must_load_sco || twisti@4323: super_check_offset.constant_or_zero() == sco_offset); twisti@4323: twisti@4323: assert_different_registers(sub_klass, super_klass, temp_reg); twisti@4323: if (super_check_offset.is_register()) { twisti@4323: assert_different_registers(sub_klass, super_klass, temp_reg, twisti@4323: super_check_offset.as_register()); twisti@4323: } else if (must_load_sco) { twisti@4323: assert(temp2_reg != noreg, "supply either a temp or a register offset"); twisti@4323: } twisti@4323: twisti@4323: Label L_fallthrough; twisti@4323: int label_nulls = 0; twisti@4323: if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } twisti@4323: if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } twisti@4323: if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } twisti@4323: assert(label_nulls <= 1 || twisti@4323: (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), twisti@4323: "at most one NULL in the batch, usually"); twisti@4323: twisti@4323: // If the pointers are equal, we are done (e.g., String[] elements). twisti@4323: // This self-check enables sharing of secondary supertype arrays among twisti@4323: // non-primary types such as array-of-interface. Otherwise, each such twisti@4323: // type would need its own customized SSA. twisti@4323: // We move this check to the front of the fast path because many twisti@4323: // type checks are in fact trivially successful in this manner, twisti@4323: // so we get a nicely predicted branch right at the start of the check. twisti@4323: cmp(super_klass, sub_klass); twisti@4323: brx(Assembler::equal, false, Assembler::pn, *L_success); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: // Check the supertype display: twisti@4323: if (must_load_sco) { twisti@4323: // The super check offset is always positive... twisti@4323: lduw(super_klass, sco_offset, temp2_reg); twisti@4323: super_check_offset = RegisterOrConstant(temp2_reg); twisti@4323: // super_check_offset is register. twisti@4323: assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register()); twisti@4323: } twisti@4323: ld_ptr(sub_klass, super_check_offset, temp_reg); twisti@4323: cmp(super_klass, temp_reg); twisti@4323: twisti@4323: // This check has worked decisively for primary supers. twisti@4323: // Secondary supers are sought in the super_cache ('super_cache_addr'). twisti@4323: // (Secondary supers are interfaces and very deeply nested subtypes.) twisti@4323: // This works in the same check above because of a tricky aliasing twisti@4323: // between the super_cache and the primary super display elements. twisti@4323: // (The 'super_check_addr' can address either, as the case requires.) twisti@4323: // Note that the cache is updated below if it does not help us find twisti@4323: // what we need immediately. twisti@4323: // So if it was a primary super, we can just fail immediately. twisti@4323: // Otherwise, it's the slow path for us (no success at this point). twisti@4323: twisti@4323: // Hacked ba(), which may only be used just before L_fallthrough. twisti@4323: #define FINAL_JUMP(label) \ twisti@4323: if (&(label) != &L_fallthrough) { \ twisti@4323: ba(label); delayed()->nop(); \ twisti@4323: } twisti@4323: twisti@4323: if (super_check_offset.is_register()) { twisti@4323: brx(Assembler::equal, false, Assembler::pn, *L_success); twisti@4323: delayed()->cmp(super_check_offset.as_register(), sc_offset); twisti@4323: twisti@4323: if (L_failure == &L_fallthrough) { twisti@4323: brx(Assembler::equal, false, Assembler::pt, *L_slow_path); twisti@4323: delayed()->nop(); twisti@4323: } else { twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, *L_failure); twisti@4323: delayed()->nop(); twisti@4323: FINAL_JUMP(*L_slow_path); twisti@4323: } twisti@4323: } else if (super_check_offset.as_constant() == sc_offset) { twisti@4323: // Need a slow path; fast failure is impossible. twisti@4323: if (L_slow_path == &L_fallthrough) { twisti@4323: brx(Assembler::equal, false, Assembler::pt, *L_success); twisti@4323: delayed()->nop(); twisti@4323: } else { twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); twisti@4323: delayed()->nop(); twisti@4323: FINAL_JUMP(*L_success); twisti@4323: } twisti@4323: } else { twisti@4323: // No slow path; it's a fast decision. twisti@4323: if (L_failure == &L_fallthrough) { twisti@4323: brx(Assembler::equal, false, Assembler::pt, *L_success); twisti@4323: delayed()->nop(); twisti@4323: } else { twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, *L_failure); twisti@4323: delayed()->nop(); twisti@4323: FINAL_JUMP(*L_success); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: bind(L_fallthrough); twisti@4323: twisti@4323: #undef FINAL_JUMP twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, twisti@4323: Register super_klass, twisti@4323: Register count_temp, twisti@4323: Register scan_temp, twisti@4323: Register scratch_reg, twisti@4323: Register coop_reg, twisti@4323: Label* L_success, twisti@4323: Label* L_failure) { twisti@4323: assert_different_registers(sub_klass, super_klass, twisti@4323: count_temp, scan_temp, scratch_reg, coop_reg); twisti@4323: twisti@4323: Label L_fallthrough, L_loop; twisti@4323: int label_nulls = 0; twisti@4323: if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } twisti@4323: if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } twisti@4323: assert(label_nulls <= 1, "at most one NULL in the batch"); twisti@4323: twisti@4323: // a couple of useful fields in sub_klass: twisti@4323: int ss_offset = in_bytes(Klass::secondary_supers_offset()); twisti@4323: int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); twisti@4323: twisti@4323: // Do a linear scan of the secondary super-klass chain. twisti@4323: // This code is rarely used, so simplicity is a virtue here. twisti@4323: twisti@4323: #ifndef PRODUCT twisti@4323: int* pst_counter = &SharedRuntime::_partial_subtype_ctr; twisti@4323: inc_counter((address) pst_counter, count_temp, scan_temp); twisti@4323: #endif twisti@4323: twisti@4323: // We will consult the secondary-super array. twisti@4323: ld_ptr(sub_klass, ss_offset, scan_temp); twisti@4323: twisti@4323: Register search_key = super_klass; twisti@4323: twisti@4323: // Load the array length. (Positive movl does right thing on LP64.) twisti@4323: lduw(scan_temp, Array::length_offset_in_bytes(), count_temp); twisti@4323: twisti@4323: // Check for empty secondary super list twisti@4323: tst(count_temp); twisti@4323: twisti@4323: // In the array of super classes elements are pointer sized. twisti@4323: int element_size = wordSize; twisti@4323: twisti@4323: // Top of search loop twisti@4323: bind(L_loop); twisti@4323: br(Assembler::equal, false, Assembler::pn, *L_failure); twisti@4323: delayed()->add(scan_temp, element_size, scan_temp); twisti@4323: twisti@4323: // Skip the array header in all array accesses. twisti@4323: int elem_offset = Array::base_offset_in_bytes(); twisti@4323: elem_offset -= element_size; // the scan pointer was pre-incremented also twisti@4323: twisti@4323: // Load next super to check twisti@4323: ld_ptr( scan_temp, elem_offset, scratch_reg ); twisti@4323: twisti@4323: // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list twisti@4323: cmp(scratch_reg, search_key); twisti@4323: twisti@4323: // A miss means we are NOT a subtype and need to keep looping twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, L_loop); twisti@4323: delayed()->deccc(count_temp); // decrement trip counter in delay slot twisti@4323: twisti@4323: // Success. Cache the super we found and proceed in triumph. twisti@4323: st_ptr(super_klass, sub_klass, sc_offset); twisti@4323: twisti@4323: if (L_success != &L_fallthrough) { twisti@4323: ba(*L_success); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: bind(L_fallthrough); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot, twisti@4323: Register temp_reg, twisti@4323: int extra_slot_offset) { twisti@4323: // cf. TemplateTable::prepare_invoke(), if (load_receiver). twisti@4323: int stackElementSize = Interpreter::stackElementSize; twisti@4323: int offset = extra_slot_offset * stackElementSize; twisti@4323: if (arg_slot.is_constant()) { twisti@4323: offset += arg_slot.as_constant() * stackElementSize; twisti@4323: return offset; twisti@4323: } else { twisti@4323: assert(temp_reg != noreg, "must specify"); twisti@4323: sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg); twisti@4323: if (offset != 0) twisti@4323: add(temp_reg, offset, temp_reg); twisti@4323: return temp_reg; twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, twisti@4323: Register temp_reg, twisti@4323: int extra_slot_offset) { twisti@4323: return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset)); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, twisti@4323: Register temp_reg, twisti@4323: Label& done, Label* slow_case, twisti@4323: BiasedLockingCounters* counters) { twisti@4323: assert(UseBiasedLocking, "why call this otherwise?"); twisti@4323: twisti@4323: if (PrintBiasedLockingStatistics) { twisti@4323: assert_different_registers(obj_reg, mark_reg, temp_reg, O7); twisti@4323: if (counters == NULL) twisti@4323: counters = BiasedLocking::counters(); twisti@4323: } twisti@4323: twisti@4323: Label cas_label; twisti@4323: twisti@4323: // Biased locking twisti@4323: // See whether the lock is currently biased toward our thread and twisti@4323: // whether the epoch is still valid twisti@4323: // Note that the runtime guarantees sufficient alignment of JavaThread twisti@4323: // pointers to allow age to be placed into low bits twisti@4323: assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); twisti@4323: and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); twisti@4323: cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label); twisti@4323: twisti@4323: load_klass(obj_reg, temp_reg); twisti@4323: ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); twisti@4323: or3(G2_thread, temp_reg, temp_reg); twisti@4323: xor3(mark_reg, temp_reg, temp_reg); twisti@4323: andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); twisti@4323: if (counters != NULL) { twisti@4323: cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); twisti@4323: // Reload mark_reg as we may need it later twisti@4323: ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); twisti@4323: } twisti@4323: brx(Assembler::equal, true, Assembler::pt, done); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: Label try_revoke_bias; twisti@4323: Label try_rebias; twisti@4323: Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); twisti@4323: assert(mark_addr.disp() == 0, "cas must take a zero displacement"); twisti@4323: twisti@4323: // At this point we know that the header has the bias pattern and twisti@4323: // that we are not the bias owner in the current epoch. We need to twisti@4323: // figure out more details about the state of the header in order to twisti@4323: // know what operations can be legally performed on the object's twisti@4323: // header. twisti@4323: twisti@4323: // If the low three bits in the xor result aren't clear, that means twisti@4323: // the prototype header is no longer biased and we have to revoke twisti@4323: // the bias on this object. twisti@4323: btst(markOopDesc::biased_lock_mask_in_place, temp_reg); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); twisti@4323: twisti@4323: // Biasing is still enabled for this data type. See whether the twisti@4323: // epoch of the current bias is still valid, meaning that the epoch twisti@4323: // bits of the mark word are equal to the epoch bits of the twisti@4323: // prototype header. (Note that the prototype header's epoch bits twisti@4323: // only change at a safepoint.) If not, attempt to rebias the object twisti@4323: // toward the current thread. Note that we must be absolutely sure twisti@4323: // that the current epoch is invalid in order to do this because twisti@4323: // otherwise the manipulations it performs on the mark word are twisti@4323: // illegal. twisti@4323: delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, try_rebias); twisti@4323: twisti@4323: // The epoch of the current bias is still valid but we know nothing twisti@4323: // about the owner; it might be set or it might be clear. Try to twisti@4323: // acquire the bias of the object using an atomic operation. If this twisti@4323: // fails we will go in to the runtime to revoke the object's bias. twisti@4323: // Note that we first construct the presumed unbiased header so we twisti@4323: // don't accidentally blow away another thread's valid bias. twisti@4323: delayed()->and3(mark_reg, twisti@4323: markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, twisti@4323: mark_reg); twisti@4323: or3(G2_thread, mark_reg, temp_reg); morris@5283: cas_ptr(mark_addr.base(), mark_reg, temp_reg); twisti@4323: // If the biasing toward our thread failed, this means that twisti@4323: // another thread succeeded in biasing it toward itself and we twisti@4323: // need to revoke that bias. The revocation will occur in the twisti@4323: // interpreter runtime in the slow case. twisti@4323: cmp(mark_reg, temp_reg); twisti@4323: if (counters != NULL) { twisti@4323: cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); twisti@4323: } twisti@4323: if (slow_case != NULL) { twisti@4323: brx(Assembler::notEqual, true, Assembler::pn, *slow_case); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: ba_short(done); twisti@4323: twisti@4323: bind(try_rebias); twisti@4323: // At this point we know the epoch has expired, meaning that the twisti@4323: // current "bias owner", if any, is actually invalid. Under these twisti@4323: // circumstances _only_, we are allowed to use the current header's twisti@4323: // value as the comparison value when doing the cas to acquire the twisti@4323: // bias in the current epoch. In other words, we allow transfer of twisti@4323: // the bias from one thread to another directly in this situation. twisti@4323: // twisti@4323: // FIXME: due to a lack of registers we currently blow away the age twisti@4323: // bits in this situation. Should attempt to preserve them. twisti@4323: load_klass(obj_reg, temp_reg); twisti@4323: ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); twisti@4323: or3(G2_thread, temp_reg, temp_reg); morris@5283: cas_ptr(mark_addr.base(), mark_reg, temp_reg); twisti@4323: // If the biasing toward our thread failed, this means that twisti@4323: // another thread succeeded in biasing it toward itself and we twisti@4323: // need to revoke that bias. The revocation will occur in the twisti@4323: // interpreter runtime in the slow case. twisti@4323: cmp(mark_reg, temp_reg); twisti@4323: if (counters != NULL) { twisti@4323: cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); twisti@4323: } twisti@4323: if (slow_case != NULL) { twisti@4323: brx(Assembler::notEqual, true, Assembler::pn, *slow_case); twisti@4323: delayed()->nop(); twisti@4323: } twisti@4323: ba_short(done); twisti@4323: twisti@4323: bind(try_revoke_bias); twisti@4323: // The prototype mark in the klass doesn't have the bias bit set any twisti@4323: // more, indicating that objects of this data type are not supposed twisti@4323: // to be biased any more. We are going to try to reset the mark of twisti@4323: // this object to the prototype value and fall through to the twisti@4323: // CAS-based locking scheme. Note that if our CAS fails, it means twisti@4323: // that another thread raced us for the privilege of revoking the twisti@4323: // bias of this particular object, so it's okay to continue in the twisti@4323: // normal locking code. twisti@4323: // twisti@4323: // FIXME: due to a lack of registers we currently blow away the age twisti@4323: // bits in this situation. Should attempt to preserve them. twisti@4323: load_klass(obj_reg, temp_reg); twisti@4323: ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); morris@5283: cas_ptr(mark_addr.base(), mark_reg, temp_reg); twisti@4323: // Fall through to the normal CAS-based lock, because no matter what twisti@4323: // the result of the above CAS, some thread must have succeeded in twisti@4323: // removing the bias bit from the object's header. twisti@4323: if (counters != NULL) { twisti@4323: cmp(mark_reg, temp_reg); twisti@4323: cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); twisti@4323: } twisti@4323: twisti@4323: bind(cas_label); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, twisti@4323: bool allow_delay_slot_filling) { twisti@4323: // Check for biased locking unlock case, which is a no-op twisti@4323: // Note: we do not have to check the thread ID for two reasons. twisti@4323: // First, the interpreter checks for IllegalMonitorStateException at twisti@4323: // a higher level. Second, if the bias was revoked while we held the twisti@4323: // lock, the object could not be rebiased toward another thread, so twisti@4323: // the bias bit would be clear. twisti@4323: ld_ptr(mark_addr, temp_reg); twisti@4323: and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); twisti@4323: cmp(temp_reg, markOopDesc::biased_lock_pattern); twisti@4323: brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); twisti@4323: delayed(); twisti@4323: if (!allow_delay_slot_filling) { twisti@4323: nop(); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // compiler_lock_object() and compiler_unlock_object() are direct transliterations twisti@4323: // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. twisti@4323: // The code could be tightened up considerably. twisti@4323: // twisti@4323: // box->dhw disposition - post-conditions at DONE_LABEL. twisti@4323: // - Successful inflated lock: box->dhw != 0. twisti@4323: // Any non-zero value suffices. twisti@4323: // Consider G2_thread, rsp, boxReg, or unused_mark() twisti@4323: // - Successful Stack-lock: box->dhw == mark. twisti@4323: // box->dhw must contain the displaced mark word value twisti@4323: // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. twisti@4323: // The slow-path fast_enter() and slow_enter() operators twisti@4323: // are responsible for setting box->dhw = NonZero (typically ::unused_mark). twisti@4323: // - Biased: box->dhw is undefined twisti@4323: // twisti@4323: // SPARC refworkload performance - specifically jetstream and scimark - are twisti@4323: // extremely sensitive to the size of the code emitted by compiler_lock_object twisti@4323: // and compiler_unlock_object. Critically, the key factor is code size, not path twisti@4323: // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the twisti@4323: // effect). twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, twisti@4323: Register Rbox, Register Rscratch, twisti@4323: BiasedLockingCounters* counters, twisti@4323: bool try_bias) { twisti@4323: Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); twisti@4323: twisti@4323: verify_oop(Roop); twisti@4323: Label done ; twisti@4323: twisti@4323: if (counters != NULL) { twisti@4323: inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); twisti@4323: } twisti@4323: twisti@4323: if (EmitSync & 1) { twisti@4323: mov(3, Rscratch); twisti@4323: st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: cmp(SP, G0); twisti@4323: return ; twisti@4323: } twisti@4323: twisti@4323: if (EmitSync & 2) { twisti@4323: twisti@4323: // Fetch object's markword twisti@4323: ld_ptr(mark_addr, Rmark); twisti@4323: twisti@4323: if (try_bias) { twisti@4323: biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); twisti@4323: } twisti@4323: twisti@4323: // Save Rbox in Rscratch to be used for the cas operation twisti@4323: mov(Rbox, Rscratch); twisti@4323: twisti@4323: // set Rmark to markOop | markOopDesc::unlocked_value twisti@4323: or3(Rmark, markOopDesc::unlocked_value, Rmark); twisti@4323: twisti@4323: // Initialize the box. (Must happen before we update the object mark!) twisti@4323: st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: twisti@4323: // compare object markOop with Rmark and if equal exchange Rscratch with object markOop twisti@4323: assert(mark_addr.disp() == 0, "cas must take a zero displacement"); morris@5283: cas_ptr(mark_addr.base(), Rmark, Rscratch); twisti@4323: twisti@4323: // if compare/exchange succeeded we found an unlocked object and we now have locked it twisti@4323: // hence we are done twisti@4323: cmp(Rmark, Rscratch); twisti@4323: #ifdef _LP64 twisti@4323: sub(Rscratch, STACK_BIAS, Rscratch); twisti@4323: #endif twisti@4323: brx(Assembler::equal, false, Assembler::pt, done); twisti@4323: delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot twisti@4323: twisti@4323: // we did not find an unlocked object so see if this is a recursive case twisti@4323: // sub(Rscratch, SP, Rscratch); twisti@4323: assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); twisti@4323: andcc(Rscratch, 0xfffff003, Rscratch); twisti@4323: st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: bind (done); twisti@4323: return ; twisti@4323: } twisti@4323: twisti@4323: Label Egress ; twisti@4323: twisti@4323: if (EmitSync & 256) { twisti@4323: Label IsInflated ; twisti@4323: twisti@4323: ld_ptr(mark_addr, Rmark); // fetch obj->mark twisti@4323: // Triage: biased, stack-locked, neutral, inflated twisti@4323: if (try_bias) { twisti@4323: biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); twisti@4323: // Invariant: if control reaches this point in the emitted stream twisti@4323: // then Rmark has not been modified. twisti@4323: } twisti@4323: twisti@4323: // Store mark into displaced mark field in the on-stack basic-lock "box" twisti@4323: // Critically, this must happen before the CAS twisti@4323: // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. twisti@4323: st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: andcc(Rmark, 2, G0); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, IsInflated); twisti@4323: delayed()-> twisti@4323: twisti@4323: // Try stack-lock acquisition. twisti@4323: // Beware: the 1st instruction is in a delay slot twisti@4323: mov(Rbox, Rscratch); twisti@4323: or3(Rmark, markOopDesc::unlocked_value, Rmark); twisti@4323: assert(mark_addr.disp() == 0, "cas must take a zero displacement"); morris@5283: cas_ptr(mark_addr.base(), Rmark, Rscratch); twisti@4323: cmp(Rmark, Rscratch); twisti@4323: brx(Assembler::equal, false, Assembler::pt, done); twisti@4323: delayed()->sub(Rscratch, SP, Rscratch); twisti@4323: twisti@4323: // Stack-lock attempt failed - check for recursive stack-lock. twisti@4323: // See the comments below about how we might remove this case. twisti@4323: #ifdef _LP64 twisti@4323: sub(Rscratch, STACK_BIAS, Rscratch); twisti@4323: #endif twisti@4323: assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); twisti@4323: andcc(Rscratch, 0xfffff003, Rscratch); twisti@4323: br(Assembler::always, false, Assembler::pt, done); twisti@4323: delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: twisti@4323: bind(IsInflated); twisti@4323: if (EmitSync & 64) { twisti@4323: // If m->owner != null goto IsLocked twisti@4323: // Pessimistic form: Test-and-CAS vs CAS twisti@4323: // The optimistic form avoids RTS->RTO cache line upgrades. twisti@4323: ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); twisti@4323: andcc(Rscratch, Rscratch, G0); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, done); twisti@4323: delayed()->nop(); twisti@4323: // m->owner == null : it's unlocked. twisti@4323: } twisti@4323: twisti@4323: // Try to CAS m->owner from null to Self twisti@4323: // Invariant: if we acquire the lock then _recursions should be 0. twisti@4323: add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); twisti@4323: mov(G2_thread, Rscratch); morris@5283: cas_ptr(Rmark, G0, Rscratch); twisti@4323: cmp(Rscratch, G0); twisti@4323: // Intentional fall-through into done twisti@4323: } else { twisti@4323: // Aggressively avoid the Store-before-CAS penalty twisti@4323: // Defer the store into box->dhw until after the CAS twisti@4323: Label IsInflated, Recursive ; twisti@4323: twisti@4323: // Anticipate CAS -- Avoid RTS->RTO upgrade twisti@4323: // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); twisti@4323: twisti@4323: ld_ptr(mark_addr, Rmark); // fetch obj->mark twisti@4323: // Triage: biased, stack-locked, neutral, inflated twisti@4323: twisti@4323: if (try_bias) { twisti@4323: biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); twisti@4323: // Invariant: if control reaches this point in the emitted stream twisti@4323: // then Rmark has not been modified. twisti@4323: } twisti@4323: andcc(Rmark, 2, G0); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, IsInflated); twisti@4323: delayed()-> // Beware - dangling delay-slot twisti@4323: twisti@4323: // Try stack-lock acquisition. twisti@4323: // Transiently install BUSY (0) encoding in the mark word. twisti@4323: // if the CAS of 0 into the mark was successful then we execute: twisti@4323: // ST box->dhw = mark -- save fetched mark in on-stack basiclock box twisti@4323: // ST obj->mark = box -- overwrite transient 0 value twisti@4323: // This presumes TSO, of course. twisti@4323: twisti@4323: mov(0, Rscratch); twisti@4323: or3(Rmark, markOopDesc::unlocked_value, Rmark); twisti@4323: assert(mark_addr.disp() == 0, "cas must take a zero displacement"); morris@5283: cas_ptr(mark_addr.base(), Rmark, Rscratch); twisti@4323: // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); twisti@4323: cmp(Rscratch, Rmark); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, Recursive); twisti@4323: delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: if (counters != NULL) { twisti@4323: cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); twisti@4323: } twisti@4323: ba(done); twisti@4323: delayed()->st_ptr(Rbox, mark_addr); twisti@4323: twisti@4323: bind(Recursive); twisti@4323: // Stack-lock attempt failed - check for recursive stack-lock. twisti@4323: // Tests show that we can remove the recursive case with no impact twisti@4323: // on refworkload 0.83. If we need to reduce the size of the code twisti@4323: // emitted by compiler_lock_object() the recursive case is perfect twisti@4323: // candidate. twisti@4323: // twisti@4323: // A more extreme idea is to always inflate on stack-lock recursion. twisti@4323: // This lets us eliminate the recursive checks in compiler_lock_object twisti@4323: // and compiler_unlock_object and the (box->dhw == 0) encoding. twisti@4323: // A brief experiment - requiring changes to synchronizer.cpp, interpreter, twisti@4323: // and showed a performance *increase*. In the same experiment I eliminated twisti@4323: // the fast-path stack-lock code from the interpreter and always passed twisti@4323: // control to the "slow" operators in synchronizer.cpp. twisti@4323: morris@5283: // RScratch contains the fetched obj->mark value from the failed CAS. twisti@4323: #ifdef _LP64 twisti@4323: sub(Rscratch, STACK_BIAS, Rscratch); twisti@4323: #endif twisti@4323: sub(Rscratch, SP, Rscratch); twisti@4323: assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); twisti@4323: andcc(Rscratch, 0xfffff003, Rscratch); twisti@4323: if (counters != NULL) { twisti@4323: // Accounting needs the Rscratch register twisti@4323: st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); twisti@4323: ba_short(done); twisti@4323: } else { twisti@4323: ba(done); twisti@4323: delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: } twisti@4323: twisti@4323: bind (IsInflated); twisti@4323: if (EmitSync & 64) { twisti@4323: // If m->owner != null goto IsLocked twisti@4323: // Test-and-CAS vs CAS twisti@4323: // Pessimistic form avoids futile (doomed) CAS attempts twisti@4323: // The optimistic form avoids RTS->RTO cache line upgrades. twisti@4323: ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); twisti@4323: andcc(Rscratch, Rscratch, G0); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, done); twisti@4323: delayed()->nop(); twisti@4323: // m->owner == null : it's unlocked. twisti@4323: } twisti@4323: twisti@4323: // Try to CAS m->owner from null to Self twisti@4323: // Invariant: if we acquire the lock then _recursions should be 0. twisti@4323: add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); twisti@4323: mov(G2_thread, Rscratch); morris@5283: cas_ptr(Rmark, G0, Rscratch); twisti@4323: cmp(Rscratch, G0); twisti@4323: // ST box->displaced_header = NonZero. twisti@4323: // Any non-zero value suffices: twisti@4323: // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. twisti@4323: st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); twisti@4323: // Intentional fall-through into done twisti@4323: } twisti@4323: twisti@4323: bind (done); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, twisti@4323: Register Rbox, Register Rscratch, twisti@4323: bool try_bias) { twisti@4323: Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); twisti@4323: twisti@4323: Label done ; twisti@4323: twisti@4323: if (EmitSync & 4) { twisti@4323: cmp(SP, G0); twisti@4323: return ; twisti@4323: } twisti@4323: twisti@4323: if (EmitSync & 8) { twisti@4323: if (try_bias) { twisti@4323: biased_locking_exit(mark_addr, Rscratch, done); twisti@4323: } twisti@4323: twisti@4323: // Test first if it is a fast recursive unlock twisti@4323: ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); twisti@4323: br_null_short(Rmark, Assembler::pt, done); twisti@4323: twisti@4323: // Check if it is still a light weight lock, this is is true if we see twisti@4323: // the stack address of the basicLock in the markOop of the object twisti@4323: assert(mark_addr.disp() == 0, "cas must take a zero displacement"); morris@5283: cas_ptr(mark_addr.base(), Rbox, Rmark); twisti@4323: ba(done); twisti@4323: delayed()->cmp(Rbox, Rmark); twisti@4323: bind(done); twisti@4323: return ; twisti@4323: } twisti@4323: twisti@4323: // Beware ... If the aggregate size of the code emitted by CLO and CUO is twisti@4323: // is too large performance rolls abruptly off a cliff. twisti@4323: // This could be related to inlining policies, code cache management, or twisti@4323: // I$ effects. twisti@4323: Label LStacked ; twisti@4323: twisti@4323: if (try_bias) { twisti@4323: // TODO: eliminate redundant LDs of obj->mark twisti@4323: biased_locking_exit(mark_addr, Rscratch, done); twisti@4323: } twisti@4323: twisti@4323: ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark); twisti@4323: ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); twisti@4323: andcc(Rscratch, Rscratch, G0); twisti@4323: brx(Assembler::zero, false, Assembler::pn, done); twisti@4323: delayed()->nop(); // consider: relocate fetch of mark, above, into this DS twisti@4323: andcc(Rmark, 2, G0); twisti@4323: brx(Assembler::zero, false, Assembler::pt, LStacked); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: // It's inflated twisti@4323: // Conceptually we need a #loadstore|#storestore "release" MEMBAR before twisti@4323: // the ST of 0 into _owner which releases the lock. This prevents loads twisti@4323: // and stores within the critical section from reordering (floating) twisti@4323: // past the store that releases the lock. But TSO is a strong memory model twisti@4323: // and that particular flavor of barrier is a noop, so we can safely elide it. twisti@4323: // Note that we use 1-0 locking by default for the inflated case. We twisti@4323: // close the resultant (and rare) race by having contented threads in twisti@4323: // monitorenter periodically poll _owner. twisti@4323: ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); twisti@4323: ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox); twisti@4323: xor3(Rscratch, G2_thread, Rscratch); twisti@4323: orcc(Rbox, Rscratch, Rbox); twisti@4323: brx(Assembler::notZero, false, Assembler::pn, done); twisti@4323: delayed()-> twisti@4323: ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch); twisti@4323: ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox); twisti@4323: orcc(Rbox, Rscratch, G0); twisti@4323: if (EmitSync & 65536) { twisti@4323: Label LSucc ; twisti@4323: brx(Assembler::notZero, false, Assembler::pn, LSucc); twisti@4323: delayed()->nop(); twisti@4323: ba(done); twisti@4323: delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); twisti@4323: twisti@4323: bind(LSucc); twisti@4323: st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); twisti@4323: if (os::is_MP()) { membar (StoreLoad); } twisti@4323: ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch); twisti@4323: andcc(Rscratch, Rscratch, G0); twisti@4323: brx(Assembler::notZero, false, Assembler::pt, done); twisti@4323: delayed()->andcc(G0, G0, G0); twisti@4323: add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); twisti@4323: mov(G2_thread, Rscratch); morris@5283: cas_ptr(Rmark, G0, Rscratch); twisti@4323: // invert icc.zf and goto done twisti@4323: br_notnull(Rscratch, false, Assembler::pt, done); twisti@4323: delayed()->cmp(G0, G0); twisti@4323: ba(done); twisti@4323: delayed()->cmp(G0, 1); twisti@4323: } else { twisti@4323: brx(Assembler::notZero, false, Assembler::pn, done); twisti@4323: delayed()->nop(); twisti@4323: ba(done); twisti@4323: delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); twisti@4323: } twisti@4323: twisti@4323: bind (LStacked); twisti@4323: // Consider: we could replace the expensive CAS in the exit twisti@4323: // path with a simple ST of the displaced mark value fetched from twisti@4323: // the on-stack basiclock box. That admits a race where a thread T2 twisti@4323: // in the slow lock path -- inflating with monitor M -- could race a twisti@4323: // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. twisti@4323: // More precisely T1 in the stack-lock unlock path could "stomp" the twisti@4323: // inflated mark value M installed by T2, resulting in an orphan twisti@4323: // object monitor M and T2 becoming stranded. We can remedy that situation twisti@4323: // by having T2 periodically poll the object's mark word using timed wait twisti@4323: // operations. If T2 discovers that a stomp has occurred it vacates twisti@4323: // the monitor M and wakes any other threads stranded on the now-orphan M. twisti@4323: // In addition the monitor scavenger, which performs deflation, twisti@4323: // would also need to check for orpan monitors and stranded threads. twisti@4323: // twisti@4323: // Finally, inflation is also used when T2 needs to assign a hashCode twisti@4323: // to O and O is stack-locked by T1. The "stomp" race could cause twisti@4323: // an assigned hashCode value to be lost. We can avoid that condition twisti@4323: // and provide the necessary hashCode stability invariants by ensuring twisti@4323: // that hashCode generation is idempotent between copying GCs. twisti@4323: // For example we could compute the hashCode of an object O as twisti@4323: // O's heap address XOR some high quality RNG value that is refreshed twisti@4323: // at GC-time. The monitor scavenger would install the hashCode twisti@4323: // found in any orphan monitors. Again, the mechanism admits a twisti@4323: // lost-update "stomp" WAW race but detects and recovers as needed. twisti@4323: // twisti@4323: // A prototype implementation showed excellent results, although twisti@4323: // the scavenger and timeout code was rather involved. twisti@4323: morris@5283: cas_ptr(mark_addr.base(), Rbox, Rscratch); twisti@4323: cmp(Rbox, Rscratch); twisti@4323: // Intentional fall through into done ... twisti@4323: twisti@4323: bind(done); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::print_CPU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::verify_FPU(int stack_depth, const char* s) { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::push_IU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::pop_IU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::push_FPU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::pop_FPU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::push_CPU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::pop_CPU_state() { twisti@4323: // %%%%% need to implement this twisti@4323: } twisti@4323: twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::verify_tlab() { twisti@4323: #ifdef ASSERT twisti@4323: if (UseTLAB && VerifyOops) { twisti@4323: Label next, next2, ok; twisti@4323: Register t1 = L0; twisti@4323: Register t2 = L1; twisti@4323: Register t3 = L2; twisti@4323: twisti@4323: save_frame(0); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); twisti@4323: or3(t1, t2, t3); twisti@4323: cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next); twisti@4323: STOP("assert(top >= start)"); twisti@4323: should_not_reach_here(); twisti@4323: twisti@4323: bind(next); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); twisti@4323: or3(t3, t2, t3); twisti@4323: cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2); twisti@4323: STOP("assert(top <= end)"); twisti@4323: should_not_reach_here(); twisti@4323: twisti@4323: bind(next2); twisti@4323: and3(t3, MinObjAlignmentInBytesMask, t3); twisti@4323: cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok); twisti@4323: STOP("assert(aligned)"); twisti@4323: should_not_reach_here(); twisti@4323: twisti@4323: bind(ok); twisti@4323: restore(); twisti@4323: } twisti@4323: #endif twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::eden_allocate( twisti@4323: Register obj, // result: pointer to object after successful allocation twisti@4323: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise twisti@4323: int con_size_in_bytes, // object size in bytes if known at compile time twisti@4323: Register t1, // temp register twisti@4323: Register t2, // temp register twisti@4323: Label& slow_case // continuation point if fast allocation fails twisti@4323: ){ twisti@4323: // make sure arguments make sense twisti@4323: assert_different_registers(obj, var_size_in_bytes, t1, t2); twisti@4323: assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); twisti@4323: assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); twisti@4323: twisti@4323: if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { twisti@4323: // No allocation in the shared eden. morris@5281: ba(slow_case); morris@5281: delayed()->nop(); twisti@4323: } else { twisti@4323: // get eden boundaries twisti@4323: // note: we need both top & top_addr! twisti@4323: const Register top_addr = t1; twisti@4323: const Register end = t2; twisti@4323: twisti@4323: CollectedHeap* ch = Universe::heap(); twisti@4323: set((intx)ch->top_addr(), top_addr); twisti@4323: intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); twisti@4323: ld_ptr(top_addr, delta, end); twisti@4323: ld_ptr(top_addr, 0, obj); twisti@4323: twisti@4323: // try to allocate twisti@4323: Label retry; twisti@4323: bind(retry); twisti@4323: #ifdef ASSERT twisti@4323: // make sure eden top is properly aligned twisti@4323: { twisti@4323: Label L; twisti@4323: btst(MinObjAlignmentInBytesMask, obj); twisti@4323: br(Assembler::zero, false, Assembler::pt, L); twisti@4323: delayed()->nop(); twisti@4323: STOP("eden top is not properly aligned"); twisti@4323: bind(L); twisti@4323: } twisti@4323: #endif // ASSERT twisti@4323: const Register free = end; twisti@4323: sub(end, obj, free); // compute amount of free space twisti@4323: if (var_size_in_bytes->is_valid()) { twisti@4323: // size is unknown at compile time twisti@4323: cmp(free, var_size_in_bytes); twisti@4323: br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case twisti@4323: delayed()->add(obj, var_size_in_bytes, end); twisti@4323: } else { twisti@4323: // size is known at compile time twisti@4323: cmp(free, con_size_in_bytes); twisti@4323: br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case twisti@4323: delayed()->add(obj, con_size_in_bytes, end); twisti@4323: } twisti@4323: // Compare obj with the value at top_addr; if still equal, swap the value of twisti@4323: // end with the value at top_addr. If not equal, read the value at top_addr twisti@4323: // into end. morris@5283: cas_ptr(top_addr, obj, end); twisti@4323: // if someone beat us on the allocation, try again, otherwise continue twisti@4323: cmp(obj, end); twisti@4323: brx(Assembler::notEqual, false, Assembler::pn, retry); twisti@4323: delayed()->mov(end, obj); // nop if successfull since obj == end twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // make sure eden top is properly aligned twisti@4323: { twisti@4323: Label L; twisti@4323: const Register top_addr = t1; twisti@4323: twisti@4323: set((intx)ch->top_addr(), top_addr); twisti@4323: ld_ptr(top_addr, 0, top_addr); twisti@4323: btst(MinObjAlignmentInBytesMask, top_addr); twisti@4323: br(Assembler::zero, false, Assembler::pt, L); twisti@4323: delayed()->nop(); twisti@4323: STOP("eden top is not properly aligned"); twisti@4323: bind(L); twisti@4323: } twisti@4323: #endif // ASSERT twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::tlab_allocate( twisti@4323: Register obj, // result: pointer to object after successful allocation twisti@4323: Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise twisti@4323: int con_size_in_bytes, // object size in bytes if known at compile time twisti@4323: Register t1, // temp register twisti@4323: Label& slow_case // continuation point if fast allocation fails twisti@4323: ){ twisti@4323: // make sure arguments make sense twisti@4323: assert_different_registers(obj, var_size_in_bytes, t1); twisti@4323: assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); twisti@4323: assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); twisti@4323: twisti@4323: const Register free = t1; twisti@4323: twisti@4323: verify_tlab(); twisti@4323: twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); twisti@4323: twisti@4323: // calculate amount of free space twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); twisti@4323: sub(free, obj, free); twisti@4323: twisti@4323: Label done; twisti@4323: if (var_size_in_bytes == noreg) { twisti@4323: cmp(free, con_size_in_bytes); twisti@4323: } else { twisti@4323: cmp(free, var_size_in_bytes); twisti@4323: } twisti@4323: br(Assembler::less, false, Assembler::pn, slow_case); twisti@4323: // calculate the new top pointer twisti@4323: if (var_size_in_bytes == noreg) { twisti@4323: delayed()->add(obj, con_size_in_bytes, free); twisti@4323: } else { twisti@4323: delayed()->add(obj, var_size_in_bytes, free); twisti@4323: } twisti@4323: twisti@4323: bind(done); twisti@4323: twisti@4323: #ifdef ASSERT twisti@4323: // make sure new free pointer is properly aligned twisti@4323: { twisti@4323: Label L; twisti@4323: btst(MinObjAlignmentInBytesMask, free); twisti@4323: br(Assembler::zero, false, Assembler::pt, L); twisti@4323: delayed()->nop(); twisti@4323: STOP("updated TLAB free is not properly aligned"); twisti@4323: bind(L); twisti@4323: } twisti@4323: #endif // ASSERT twisti@4323: twisti@4323: // update the tlab top pointer twisti@4323: st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); twisti@4323: verify_tlab(); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { twisti@4323: Register top = O0; twisti@4323: Register t1 = G1; twisti@4323: Register t2 = G3; twisti@4323: Register t3 = O1; twisti@4323: assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); twisti@4323: Label do_refill, discard_tlab; twisti@4323: twisti@4323: if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { twisti@4323: // No allocation in the shared eden. twisti@4323: ba_short(slow_case); twisti@4323: } twisti@4323: twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); twisti@4323: twisti@4323: // calculate amount of free space twisti@4323: sub(t1, top, t1); twisti@4323: srl_ptr(t1, LogHeapWordSize, t1); twisti@4323: twisti@4323: // Retain tlab and allocate object in shared space if twisti@4323: // the amount free in the tlab is too large to discard. twisti@4323: cmp(t1, t2); twisti@4323: brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); twisti@4323: twisti@4323: // increment waste limit to prevent getting stuck on this slow path twisti@4323: delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); twisti@4323: st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); twisti@4323: if (TLABStats) { twisti@4323: // increment number of slow_allocations twisti@4323: ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); twisti@4323: add(t2, 1, t2); twisti@4323: stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); twisti@4323: } twisti@4323: ba_short(try_eden); twisti@4323: twisti@4323: bind(discard_tlab); twisti@4323: if (TLABStats) { twisti@4323: // increment number of refills twisti@4323: ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); twisti@4323: add(t2, 1, t2); twisti@4323: stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); twisti@4323: // accumulate wastage twisti@4323: ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); twisti@4323: add(t2, t1, t2); twisti@4323: stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); twisti@4323: } twisti@4323: twisti@4323: // if tlab is currently allocated (top or end != null) then twisti@4323: // fill [top, end + alignment_reserve) with array object twisti@4323: br_null_short(top, Assembler::pn, do_refill); twisti@4323: twisti@4323: set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); twisti@4323: st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word twisti@4323: // set klass to intArrayKlass twisti@4323: sub(t1, typeArrayOopDesc::header_size(T_INT), t1); twisti@4323: add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); twisti@4323: sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); twisti@4323: st(t1, top, arrayOopDesc::length_offset_in_bytes()); twisti@4323: set((intptr_t)Universe::intArrayKlassObj_addr(), t2); twisti@4323: ld_ptr(t2, 0, t2); twisti@4323: // store klass last. concurrent gcs assumes klass length is valid if twisti@4323: // klass field is not null. twisti@4323: store_klass(t2, top); twisti@4323: verify_oop(top); twisti@4323: twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1); twisti@4323: sub(top, t1, t1); // size of tlab's allocated portion twisti@4323: incr_allocated_bytes(t1, t2, t3); twisti@4323: twisti@4323: // refill the tlab with an eden allocation twisti@4323: bind(do_refill); twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); twisti@4323: sll_ptr(t1, LogHeapWordSize, t1); twisti@4323: // allocate new tlab, address returned in top twisti@4323: eden_allocate(top, t1, 0, t2, t3, slow_case); twisti@4323: twisti@4323: st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); twisti@4323: st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); twisti@4323: #ifdef ASSERT twisti@4323: // check that tlab_size (t1) is still valid twisti@4323: { twisti@4323: Label ok; twisti@4323: ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); twisti@4323: sll_ptr(t2, LogHeapWordSize, t2); twisti@4323: cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok); twisti@4323: STOP("assert(t1 == tlab_size)"); twisti@4323: should_not_reach_here(); twisti@4323: twisti@4323: bind(ok); twisti@4323: } twisti@4323: #endif // ASSERT twisti@4323: add(top, t1, top); // t1 is tlab_size twisti@4323: sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); twisti@4323: st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); twisti@4323: verify_tlab(); twisti@4323: ba_short(retry); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, twisti@4323: Register t1, Register t2) { twisti@4323: // Bump total bytes allocated by this thread twisti@4323: assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch twisti@4323: assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2); twisti@4323: // v8 support has gone the way of the dodo twisti@4323: ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1); twisti@4323: add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1); twisti@4323: stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset())); twisti@4323: } twisti@4323: twisti@4323: Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { twisti@4323: switch (cond) { twisti@4323: // Note some conditions are synonyms for others twisti@4323: case Assembler::never: return Assembler::always; twisti@4323: case Assembler::zero: return Assembler::notZero; twisti@4323: case Assembler::lessEqual: return Assembler::greater; twisti@4323: case Assembler::less: return Assembler::greaterEqual; twisti@4323: case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; twisti@4323: case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; twisti@4323: case Assembler::negative: return Assembler::positive; twisti@4323: case Assembler::overflowSet: return Assembler::overflowClear; twisti@4323: case Assembler::always: return Assembler::never; twisti@4323: case Assembler::notZero: return Assembler::zero; twisti@4323: case Assembler::greater: return Assembler::lessEqual; twisti@4323: case Assembler::greaterEqual: return Assembler::less; twisti@4323: case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; twisti@4323: case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; twisti@4323: case Assembler::positive: return Assembler::negative; twisti@4323: case Assembler::overflowClear: return Assembler::overflowSet; twisti@4323: } twisti@4323: twisti@4323: ShouldNotReachHere(); return Assembler::overflowClear; twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, twisti@4323: Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { twisti@4323: Condition negated_cond = negate_condition(cond); twisti@4323: Label L; twisti@4323: brx(negated_cond, false, Assembler::pt, L); twisti@4323: delayed()->nop(); twisti@4323: inc_counter(counter_ptr, Rtmp1, Rtmp2); twisti@4323: bind(L); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { twisti@4323: AddressLiteral addrlit(counter_addr); twisti@4323: sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. twisti@4323: Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. twisti@4323: ld(addr, Rtmp2); twisti@4323: inc(Rtmp2); twisti@4323: st(Rtmp2, addr); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { twisti@4323: inc_counter((address) counter_addr, Rtmp1, Rtmp2); twisti@4323: } twisti@4323: twisti@4323: SkipIfEqual::SkipIfEqual( twisti@4323: MacroAssembler* masm, Register temp, const bool* flag_addr, twisti@4323: Assembler::Condition condition) { twisti@4323: _masm = masm; twisti@4323: AddressLiteral flag(flag_addr); twisti@4323: _masm->sethi(flag, temp); twisti@4323: _masm->ldub(temp, flag.low10(), temp); twisti@4323: _masm->tst(temp); twisti@4323: _masm->br(condition, false, Assembler::pt, _label); twisti@4323: _masm->delayed()->nop(); twisti@4323: } twisti@4323: twisti@4323: SkipIfEqual::~SkipIfEqual() { twisti@4323: _masm->bind(_label); twisti@4323: } twisti@4323: twisti@4323: twisti@4323: // Writes to stack successive pages until offset reached to check for twisti@4323: // stack overflow + shadow pages. This clobbers tsp and scratch. twisti@4323: void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, twisti@4323: Register Rscratch) { twisti@4323: // Use stack pointer in temp stack pointer twisti@4323: mov(SP, Rtsp); twisti@4323: twisti@4323: // Bang stack for total size given plus stack shadow page size. twisti@4323: // Bang one page at a time because a large size can overflow yellow and twisti@4323: // red zones (the bang will fail but stack overflow handling can't tell that twisti@4323: // it was a stack overflow bang vs a regular segv). twisti@4323: int offset = os::vm_page_size(); twisti@4323: Register Roffset = Rscratch; twisti@4323: twisti@4323: Label loop; twisti@4323: bind(loop); twisti@4323: set((-offset)+STACK_BIAS, Rscratch); twisti@4323: st(G0, Rtsp, Rscratch); twisti@4323: set(offset, Roffset); twisti@4323: sub(Rsize, Roffset, Rsize); twisti@4323: cmp(Rsize, G0); twisti@4323: br(Assembler::greater, false, Assembler::pn, loop); twisti@4323: delayed()->sub(Rtsp, Roffset, Rtsp); twisti@4323: twisti@4323: // Bang down shadow pages too. twisti@4323: // The -1 because we already subtracted 1 page. twisti@4323: for (int i = 0; i< StackShadowPages-1; i++) { twisti@4323: set((-i*offset)+STACK_BIAS, Rscratch); twisti@4323: st(G0, Rtsp, Rscratch); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: /////////////////////////////////////////////////////////////////////////////////// jprovino@4542: #if INCLUDE_ALL_GCS twisti@4323: twisti@4323: static address satb_log_enqueue_with_frame = NULL; twisti@4323: static u_char* satb_log_enqueue_with_frame_end = NULL; twisti@4323: twisti@4323: static address satb_log_enqueue_frameless = NULL; twisti@4323: static u_char* satb_log_enqueue_frameless_end = NULL; twisti@4323: twisti@4323: static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? twisti@4323: twisti@4323: static void generate_satb_log_enqueue(bool with_frame) { twisti@4323: BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); twisti@4323: CodeBuffer buf(bb); twisti@4323: MacroAssembler masm(&buf); twisti@4323: twisti@4323: #define __ masm. twisti@4323: twisti@4323: address start = __ pc(); twisti@4323: Register pre_val; twisti@4323: twisti@4323: Label refill, restart; twisti@4323: if (with_frame) { twisti@4323: __ save_frame(0); twisti@4323: pre_val = I0; // Was O0 before the save. twisti@4323: } else { twisti@4323: pre_val = O0; twisti@4323: } twisti@4323: twisti@4323: int satb_q_index_byte_offset = twisti@4323: in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_index()); twisti@4323: twisti@4323: int satb_q_buf_byte_offset = twisti@4323: in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_buf()); twisti@4323: twisti@4323: assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && twisti@4323: in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), twisti@4323: "check sizes in assembly below"); twisti@4323: twisti@4323: __ bind(restart); twisti@4323: twisti@4323: // Load the index into the SATB buffer. PtrQueue::_index is a size_t twisti@4323: // so ld_ptr is appropriate. twisti@4323: __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0); twisti@4323: twisti@4323: // index == 0? twisti@4323: __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); twisti@4323: twisti@4323: __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); twisti@4323: __ sub(L0, oopSize, L0); twisti@4323: twisti@4323: __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0 twisti@4323: if (!with_frame) { twisti@4323: // Use return-from-leaf twisti@4323: __ retl(); twisti@4323: __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); twisti@4323: } else { twisti@4323: // Not delayed. twisti@4323: __ st_ptr(L0, G2_thread, satb_q_index_byte_offset); twisti@4323: } twisti@4323: if (with_frame) { twisti@4323: __ ret(); twisti@4323: __ delayed()->restore(); twisti@4323: } twisti@4323: __ bind(refill); twisti@4323: twisti@4323: address handle_zero = twisti@4323: CAST_FROM_FN_PTR(address, twisti@4323: &SATBMarkQueueSet::handle_zero_index_for_thread); twisti@4323: // This should be rare enough that we can afford to save all the twisti@4323: // scratch registers that the calling context might be using. twisti@4323: __ mov(G1_scratch, L0); twisti@4323: __ mov(G3_scratch, L1); twisti@4323: __ mov(G4, L2); twisti@4323: // We need the value of O0 above (for the write into the buffer), so we twisti@4323: // save and restore it. twisti@4323: __ mov(O0, L3); twisti@4323: // Since the call will overwrite O7, we save and restore that, as well. twisti@4323: __ mov(O7, L4); twisti@4323: __ call_VM_leaf(L5, handle_zero, G2_thread); twisti@4323: __ mov(L0, G1_scratch); twisti@4323: __ mov(L1, G3_scratch); twisti@4323: __ mov(L2, G4); twisti@4323: __ mov(L3, O0); twisti@4323: __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); twisti@4323: __ delayed()->mov(L4, O7); twisti@4323: twisti@4323: if (with_frame) { twisti@4323: satb_log_enqueue_with_frame = start; twisti@4323: satb_log_enqueue_with_frame_end = __ pc(); twisti@4323: } else { twisti@4323: satb_log_enqueue_frameless = start; twisti@4323: satb_log_enqueue_frameless_end = __ pc(); twisti@4323: } twisti@4323: twisti@4323: #undef __ twisti@4323: } twisti@4323: twisti@4323: static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { twisti@4323: if (with_frame) { twisti@4323: if (satb_log_enqueue_with_frame == 0) { twisti@4323: generate_satb_log_enqueue(with_frame); twisti@4323: assert(satb_log_enqueue_with_frame != 0, "postcondition."); twisti@4323: if (G1SATBPrintStubs) { twisti@4323: tty->print_cr("Generated with-frame satb enqueue:"); twisti@4323: Disassembler::decode((u_char*)satb_log_enqueue_with_frame, twisti@4323: satb_log_enqueue_with_frame_end, twisti@4323: tty); twisti@4323: } twisti@4323: } twisti@4323: } else { twisti@4323: if (satb_log_enqueue_frameless == 0) { twisti@4323: generate_satb_log_enqueue(with_frame); twisti@4323: assert(satb_log_enqueue_frameless != 0, "postcondition."); twisti@4323: if (G1SATBPrintStubs) { twisti@4323: tty->print_cr("Generated frameless satb enqueue:"); twisti@4323: Disassembler::decode((u_char*)satb_log_enqueue_frameless, twisti@4323: satb_log_enqueue_frameless_end, twisti@4323: tty); twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::g1_write_barrier_pre(Register obj, twisti@4323: Register index, twisti@4323: int offset, twisti@4323: Register pre_val, twisti@4323: Register tmp, twisti@4323: bool preserve_o_regs) { twisti@4323: Label filtered; twisti@4323: twisti@4323: if (obj == noreg) { twisti@4323: // We are not loading the previous value so make twisti@4323: // sure that we don't trash the value in pre_val twisti@4323: // with the code below. twisti@4323: assert_different_registers(pre_val, tmp); twisti@4323: } else { twisti@4323: // We will be loading the previous value twisti@4323: // in this code so... twisti@4323: assert(offset == 0 || index == noreg, "choose one"); twisti@4323: assert(pre_val == noreg, "check this code"); twisti@4323: } twisti@4323: twisti@4323: // Is marking active? twisti@4323: if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { twisti@4323: ld(G2, twisti@4323: in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_active()), twisti@4323: tmp); twisti@4323: } else { twisti@4323: guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, twisti@4323: "Assumption"); twisti@4323: ldsb(G2, twisti@4323: in_bytes(JavaThread::satb_mark_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_active()), twisti@4323: tmp); twisti@4323: } twisti@4323: twisti@4323: // Is marking active? twisti@4323: cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); twisti@4323: twisti@4323: // Do we need to load the previous value? twisti@4323: if (obj != noreg) { twisti@4323: // Load the previous value... twisti@4323: if (index == noreg) { twisti@4323: if (Assembler::is_simm13(offset)) { twisti@4323: load_heap_oop(obj, offset, tmp); twisti@4323: } else { twisti@4323: set(offset, tmp); twisti@4323: load_heap_oop(obj, tmp, tmp); twisti@4323: } twisti@4323: } else { twisti@4323: load_heap_oop(obj, index, tmp); twisti@4323: } twisti@4323: // Previous value has been loaded into tmp twisti@4323: pre_val = tmp; twisti@4323: } twisti@4323: twisti@4323: assert(pre_val != noreg, "must have a real register"); twisti@4323: twisti@4323: // Is the previous value null? twisti@4323: cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered); twisti@4323: twisti@4323: // OK, it's not filtered, so we'll need to call enqueue. In the normal twisti@4323: // case, pre_val will be a scratch G-reg, but there are some cases in twisti@4323: // which it's an O-reg. In the first case, do a normal call. In the twisti@4323: // latter, do a save here and call the frameless version. twisti@4323: twisti@4323: guarantee(pre_val->is_global() || pre_val->is_out(), twisti@4323: "Or we need to think harder."); twisti@4323: twisti@4323: if (pre_val->is_global() && !preserve_o_regs) { twisti@4323: generate_satb_log_enqueue_if_necessary(true); // with frame twisti@4323: twisti@4323: call(satb_log_enqueue_with_frame); twisti@4323: delayed()->mov(pre_val, O0); twisti@4323: } else { twisti@4323: generate_satb_log_enqueue_if_necessary(false); // frameless twisti@4323: twisti@4323: save_frame(0); twisti@4323: call(satb_log_enqueue_frameless); twisti@4323: delayed()->mov(pre_val->after_save(), O0); twisti@4323: restore(); twisti@4323: } twisti@4323: twisti@4323: bind(filtered); twisti@4323: } twisti@4323: twisti@4323: static address dirty_card_log_enqueue = 0; twisti@4323: static u_char* dirty_card_log_enqueue_end = 0; twisti@4323: twisti@4323: // This gets to assume that o0 contains the object address. twisti@4323: static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { twisti@4323: BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); twisti@4323: CodeBuffer buf(bb); twisti@4323: MacroAssembler masm(&buf); twisti@4323: #define __ masm. twisti@4323: address start = __ pc(); twisti@4323: twisti@4323: Label not_already_dirty, restart, refill; twisti@4323: twisti@4323: #ifdef _LP64 twisti@4323: __ srlx(O0, CardTableModRefBS::card_shift, O0); twisti@4323: #else twisti@4323: __ srl(O0, CardTableModRefBS::card_shift, O0); twisti@4323: #endif twisti@4323: AddressLiteral addrlit(byte_map_base); twisti@4323: __ set(addrlit, O1); // O1 := twisti@4323: __ ldub(O0, O1, O2); // O2 := [O0 + O1] twisti@4323: twisti@4323: assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code"); twisti@4323: __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty); twisti@4323: twisti@4323: // We didn't take the branch, so we're already dirty: return. twisti@4323: // Use return-from-leaf twisti@4323: __ retl(); twisti@4323: __ delayed()->nop(); twisti@4323: twisti@4323: // Not dirty. twisti@4323: __ bind(not_already_dirty); twisti@4323: twisti@4323: // Get O0 + O1 into a reg by itself twisti@4323: __ add(O0, O1, O3); twisti@4323: twisti@4323: // First, dirty it. twisti@4323: __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). twisti@4323: twisti@4323: int dirty_card_q_index_byte_offset = twisti@4323: in_bytes(JavaThread::dirty_card_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_index()); twisti@4323: int dirty_card_q_buf_byte_offset = twisti@4323: in_bytes(JavaThread::dirty_card_queue_offset() + twisti@4323: PtrQueue::byte_offset_of_buf()); twisti@4323: __ bind(restart); twisti@4323: twisti@4323: // Load the index into the update buffer. PtrQueue::_index is twisti@4323: // a size_t so ld_ptr is appropriate here. twisti@4323: __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); twisti@4323: twisti@4323: // index == 0? twisti@4323: __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); twisti@4323: twisti@4323: __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); twisti@4323: __ sub(L0, oopSize, L0); twisti@4323: twisti@4323: __ st_ptr(O3, L1, L0); // [_buf + index] := I0 twisti@4323: // Use return-from-leaf twisti@4323: __ retl(); twisti@4323: __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); twisti@4323: twisti@4323: __ bind(refill); twisti@4323: address handle_zero = twisti@4323: CAST_FROM_FN_PTR(address, twisti@4323: &DirtyCardQueueSet::handle_zero_index_for_thread); twisti@4323: // This should be rare enough that we can afford to save all the twisti@4323: // scratch registers that the calling context might be using. twisti@4323: __ mov(G1_scratch, L3); twisti@4323: __ mov(G3_scratch, L5); twisti@4323: // We need the value of O3 above (for the write into the buffer), so we twisti@4323: // save and restore it. twisti@4323: __ mov(O3, L6); twisti@4323: // Since the call will overwrite O7, we save and restore that, as well. twisti@4323: __ mov(O7, L4); twisti@4323: twisti@4323: __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); twisti@4323: __ mov(L3, G1_scratch); twisti@4323: __ mov(L5, G3_scratch); twisti@4323: __ mov(L6, O3); twisti@4323: __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); twisti@4323: __ delayed()->mov(L4, O7); twisti@4323: twisti@4323: dirty_card_log_enqueue = start; twisti@4323: dirty_card_log_enqueue_end = __ pc(); twisti@4323: // XXX Should have a guarantee here about not going off the end! twisti@4323: // Does it already do so? Do an experiment... twisti@4323: twisti@4323: #undef __ twisti@4323: twisti@4323: } twisti@4323: twisti@4323: static inline void twisti@4323: generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { twisti@4323: if (dirty_card_log_enqueue == 0) { twisti@4323: generate_dirty_card_log_enqueue(byte_map_base); twisti@4323: assert(dirty_card_log_enqueue != 0, "postcondition."); twisti@4323: if (G1SATBPrintStubs) { twisti@4323: tty->print_cr("Generated dirty_card enqueue:"); twisti@4323: Disassembler::decode((u_char*)dirty_card_log_enqueue, twisti@4323: dirty_card_log_enqueue_end, twisti@4323: tty); twisti@4323: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { twisti@4323: twisti@4323: Label filtered; twisti@4323: MacroAssembler* post_filter_masm = this; twisti@4323: twisti@4323: if (new_val == G0) return; twisti@4323: twisti@4323: G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); twisti@4323: assert(bs->kind() == BarrierSet::G1SATBCT || twisti@4323: bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); twisti@4323: twisti@4323: if (G1RSBarrierRegionFilter) { twisti@4323: xor3(store_addr, new_val, tmp); twisti@4323: #ifdef _LP64 twisti@4323: srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); twisti@4323: #else twisti@4323: srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); twisti@4323: #endif twisti@4323: twisti@4323: // XXX Should I predict this taken or not? Does it matter? twisti@4323: cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); twisti@4323: } twisti@4323: twisti@4323: // If the "store_addr" register is an "in" or "local" register, move it to twisti@4323: // a scratch reg so we can pass it as an argument. twisti@4323: bool use_scr = !(store_addr->is_global() || store_addr->is_out()); twisti@4323: // Pick a scratch register different from "tmp". twisti@4323: Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); twisti@4323: // Make sure we use up the delay slot! twisti@4323: if (use_scr) { twisti@4323: post_filter_masm->mov(store_addr, scr); twisti@4323: } else { twisti@4323: post_filter_masm->nop(); twisti@4323: } twisti@4323: generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); twisti@4323: save_frame(0); twisti@4323: call(dirty_card_log_enqueue); twisti@4323: if (use_scr) { twisti@4323: delayed()->mov(scr, O0); twisti@4323: } else { twisti@4323: delayed()->mov(store_addr->after_save(), O0); twisti@4323: } twisti@4323: restore(); twisti@4323: twisti@4323: bind(filtered); twisti@4323: } twisti@4323: jprovino@4542: #endif // INCLUDE_ALL_GCS twisti@4323: /////////////////////////////////////////////////////////////////////////////////// twisti@4323: twisti@4323: void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { twisti@4323: // If we're writing constant NULL, we can skip the write barrier. twisti@4323: if (new_val == G0) return; twisti@4323: CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); twisti@4323: assert(bs->kind() == BarrierSet::CardTableModRef || twisti@4323: bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); twisti@4323: card_table_write(bs->byte_map_base, tmp, store_addr); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::load_klass(Register src_oop, Register klass) { twisti@4323: // The number of bytes in this code is used by twisti@4323: // MachCallDynamicJavaNode::ret_addr_offset() twisti@4323: // if this changes, change that. ehelin@5694: if (UseCompressedClassPointers) { twisti@4323: lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); twisti@4323: decode_klass_not_null(klass); twisti@4323: } else { twisti@4323: ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_klass(Register klass, Register dst_oop) { ehelin@5694: if (UseCompressedClassPointers) { twisti@4323: assert(dst_oop != klass, "not enough registers"); twisti@4323: encode_klass_not_null(klass); twisti@4323: st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); twisti@4323: } else { twisti@4323: st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_klass_gap(Register s, Register d) { ehelin@5694: if (UseCompressedClassPointers) { twisti@4323: assert(s != d, "not enough registers"); twisti@4323: st(s, d, oopDesc::klass_gap_offset_in_bytes()); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::load_heap_oop(const Address& s, Register d) { twisti@4323: if (UseCompressedOops) { twisti@4323: lduw(s, d); twisti@4323: decode_heap_oop(d); twisti@4323: } else { twisti@4323: ld_ptr(s, d); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { twisti@4323: if (UseCompressedOops) { twisti@4323: lduw(s1, s2, d); twisti@4323: decode_heap_oop(d, d); twisti@4323: } else { twisti@4323: ld_ptr(s1, s2, d); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { twisti@4323: if (UseCompressedOops) { twisti@4323: lduw(s1, simm13a, d); twisti@4323: decode_heap_oop(d, d); twisti@4323: } else { twisti@4323: ld_ptr(s1, simm13a, d); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) { twisti@4323: if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d); twisti@4323: else load_heap_oop(s1, s2.as_register(), d); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { twisti@4323: if (UseCompressedOops) { twisti@4323: assert(s1 != d && s2 != d, "not enough registers"); twisti@4323: encode_heap_oop(d); twisti@4323: st(d, s1, s2); twisti@4323: } else { twisti@4323: st_ptr(d, s1, s2); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { twisti@4323: if (UseCompressedOops) { twisti@4323: assert(s1 != d, "not enough registers"); twisti@4323: encode_heap_oop(d); twisti@4323: st(d, s1, simm13a); twisti@4323: } else { twisti@4323: st_ptr(d, s1, simm13a); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { twisti@4323: if (UseCompressedOops) { twisti@4323: assert(a.base() != d, "not enough registers"); twisti@4323: encode_heap_oop(d); twisti@4323: st(d, a, offset); twisti@4323: } else { twisti@4323: st_ptr(d, a, offset); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::encode_heap_oop(Register src, Register dst) { twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: verify_oop(src); twisti@4323: if (Universe::narrow_oop_base() == NULL) { twisti@4323: srlx(src, LogMinObjAlignmentInBytes, dst); twisti@4323: return; twisti@4323: } twisti@4323: Label done; twisti@4323: if (src == dst) { twisti@4323: // optimize for frequent case src == dst twisti@4323: bpr(rc_nz, true, Assembler::pt, src, done); twisti@4323: delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken twisti@4323: bind(done); twisti@4323: srlx(src, LogMinObjAlignmentInBytes, dst); twisti@4323: } else { twisti@4323: bpr(rc_z, false, Assembler::pn, src, done); twisti@4323: delayed() -> mov(G0, dst); twisti@4323: // could be moved before branch, and annulate delay, twisti@4323: // but may add some unneeded work decoding null twisti@4323: sub(src, G6_heapbase, dst); twisti@4323: srlx(dst, LogMinObjAlignmentInBytes, dst); twisti@4323: bind(done); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: twisti@4323: void MacroAssembler::encode_heap_oop_not_null(Register r) { twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: verify_oop(r); twisti@4323: if (Universe::narrow_oop_base() != NULL) twisti@4323: sub(r, G6_heapbase, r); twisti@4323: srlx(r, LogMinObjAlignmentInBytes, r); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: verify_oop(src); twisti@4323: if (Universe::narrow_oop_base() == NULL) { twisti@4323: srlx(src, LogMinObjAlignmentInBytes, dst); twisti@4323: } else { twisti@4323: sub(src, G6_heapbase, dst); twisti@4323: srlx(dst, LogMinObjAlignmentInBytes, dst); twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Same algorithm as oops.inline.hpp decode_heap_oop. twisti@4323: void MacroAssembler::decode_heap_oop(Register src, Register dst) { twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: sllx(src, LogMinObjAlignmentInBytes, dst); twisti@4323: if (Universe::narrow_oop_base() != NULL) { twisti@4323: Label done; twisti@4323: bpr(rc_nz, true, Assembler::pt, dst, done); twisti@4323: delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken twisti@4323: bind(done); twisti@4323: } twisti@4323: verify_oop(dst); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::decode_heap_oop_not_null(Register r) { twisti@4323: // Do not add assert code to this unless you change vtableStubs_sparc.cpp twisti@4323: // pd_code_size_limit. twisti@4323: // Also do not verify_oop as this is called by verify_oop. twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (Universe::heap() != NULL, "java heap should be initialized"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: sllx(r, LogMinObjAlignmentInBytes, r); twisti@4323: if (Universe::narrow_oop_base() != NULL) twisti@4323: add(r, G6_heapbase, r); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { twisti@4323: // Do not add assert code to this unless you change vtableStubs_sparc.cpp twisti@4323: // pd_code_size_limit. twisti@4323: // Also do not verify_oop as this is called by verify_oop. twisti@4323: assert (UseCompressedOops, "must be compressed"); twisti@4323: assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); twisti@4323: sllx(src, LogMinObjAlignmentInBytes, dst); twisti@4323: if (Universe::narrow_oop_base() != NULL) twisti@4323: add(dst, G6_heapbase, dst); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::encode_klass_not_null(Register r) { ehelin@5694: assert (UseCompressedClassPointers, "must be compressed"); hseigel@5528: assert(Universe::narrow_klass_base() != NULL, "narrow_klass_base should be initialized"); hseigel@5528: assert(r != G6_heapbase, "bad register choice"); hseigel@5528: set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); hseigel@5528: sub(r, G6_heapbase, r); hseigel@5528: if (Universe::narrow_klass_shift() != 0) { hseigel@5528: assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); hseigel@5528: srlx(r, LogKlassAlignmentInBytes, r); hseigel@5528: } hseigel@5528: reinit_heapbase(); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::encode_klass_not_null(Register src, Register dst) { hseigel@5528: if (src == dst) { hseigel@5528: encode_klass_not_null(src); twisti@4323: } else { ehelin@5694: assert (UseCompressedClassPointers, "must be compressed"); hseigel@5528: assert(Universe::narrow_klass_base() != NULL, "narrow_klass_base should be initialized"); hseigel@5528: set((intptr_t)Universe::narrow_klass_base(), dst); hseigel@5528: sub(src, dst, dst); hseigel@5528: if (Universe::narrow_klass_shift() != 0) { hseigel@5528: srlx(dst, LogKlassAlignmentInBytes, dst); hseigel@5528: } twisti@4323: } twisti@4323: } twisti@4323: hseigel@5528: // Function instr_size_for_decode_klass_not_null() counts the instructions hseigel@5528: // generated by decode_klass_not_null() and reinit_heapbase(). Hence, if hseigel@5528: // the instructions they generate change, then this method needs to be updated. hseigel@5528: int MacroAssembler::instr_size_for_decode_klass_not_null() { ehelin@5694: assert (UseCompressedClassPointers, "only for compressed klass ptrs"); hseigel@5528: // set + add + set hseigel@5528: int num_instrs = insts_for_internal_set((intptr_t)Universe::narrow_klass_base()) + 1 + hseigel@5528: insts_for_internal_set((intptr_t)Universe::narrow_ptrs_base()); hseigel@5528: if (Universe::narrow_klass_shift() == 0) { hseigel@5528: return num_instrs * BytesPerInstWord; hseigel@5528: } else { // sllx hseigel@5528: return (num_instrs + 1) * BytesPerInstWord; hseigel@5528: } hseigel@5528: } hseigel@5528: hseigel@5528: // !!! If the instructions that get generated here change then function hseigel@5528: // instr_size_for_decode_klass_not_null() needs to get updated. twisti@4323: void MacroAssembler::decode_klass_not_null(Register r) { twisti@4323: // Do not add assert code to this unless you change vtableStubs_sparc.cpp twisti@4323: // pd_code_size_limit. ehelin@5694: assert (UseCompressedClassPointers, "must be compressed"); hseigel@5528: assert(Universe::narrow_klass_base() != NULL, "narrow_klass_base should be initialized"); hseigel@5528: assert(r != G6_heapbase, "bad register choice"); hseigel@5528: set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); hseigel@5528: if (Universe::narrow_klass_shift() != 0) hseigel@5528: sllx(r, LogKlassAlignmentInBytes, r); hseigel@5528: add(r, G6_heapbase, r); hseigel@5528: reinit_heapbase(); twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::decode_klass_not_null(Register src, Register dst) { hseigel@5528: if (src == dst) { hseigel@5528: decode_klass_not_null(src); hseigel@5528: } else { hseigel@5528: // Do not add assert code to this unless you change vtableStubs_sparc.cpp hseigel@5528: // pd_code_size_limit. ehelin@5694: assert (UseCompressedClassPointers, "must be compressed"); hseigel@5528: assert(Universe::narrow_klass_base() != NULL, "narrow_klass_base should be initialized"); hseigel@5528: if (Universe::narrow_klass_shift() != 0) { hseigel@5528: assert((src != G6_heapbase) && (dst != G6_heapbase), "bad register choice"); hseigel@5528: set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); hseigel@5528: sllx(src, LogKlassAlignmentInBytes, dst); hseigel@5528: add(dst, G6_heapbase, dst); hseigel@5528: reinit_heapbase(); hseigel@5528: } else { hseigel@5528: set((intptr_t)Universe::narrow_klass_base(), dst); hseigel@5528: add(src, dst, dst); hseigel@5528: } hseigel@5528: } twisti@4323: } twisti@4323: twisti@4323: void MacroAssembler::reinit_heapbase() { ehelin@5694: if (UseCompressedOops || UseCompressedClassPointers) { hseigel@5528: if (Universe::heap() != NULL) { hseigel@5528: set((intptr_t)Universe::narrow_ptrs_base(), G6_heapbase); hseigel@5528: } else { hseigel@5528: AddressLiteral base(Universe::narrow_ptrs_base_addr()); hseigel@5528: load_ptr_contents(base, G6_heapbase); hseigel@5528: } twisti@4323: } twisti@4323: } twisti@4323: twisti@4323: // Compare char[] arrays aligned to 4 bytes. twisti@4323: void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, twisti@4323: Register limit, Register result, twisti@4323: Register chr1, Register chr2, Label& Ldone) { twisti@4323: Label Lvector, Lloop; twisti@4323: assert(chr1 == result, "should be the same"); twisti@4323: twisti@4323: // Note: limit contains number of bytes (2*char_elements) != 0. twisti@4323: andcc(limit, 0x2, chr1); // trailing character ? twisti@4323: br(Assembler::zero, false, Assembler::pt, Lvector); twisti@4323: delayed()->nop(); twisti@4323: twisti@4323: // compare the trailing char twisti@4323: sub(limit, sizeof(jchar), limit); twisti@4323: lduh(ary1, limit, chr1); twisti@4323: lduh(ary2, limit, chr2); twisti@4323: cmp(chr1, chr2); twisti@4323: br(Assembler::notEqual, true, Assembler::pt, Ldone); twisti@4323: delayed()->mov(G0, result); // not equal twisti@4323: twisti@4323: // only one char ? twisti@4323: cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); twisti@4323: delayed()->add(G0, 1, result); // zero-length arrays are equal twisti@4323: twisti@4323: // word by word compare, dont't need alignment check twisti@4323: bind(Lvector); twisti@4323: // Shift ary1 and ary2 to the end of the arrays, negate limit twisti@4323: add(ary1, limit, ary1); twisti@4323: add(ary2, limit, ary2); twisti@4323: neg(limit, limit); twisti@4323: twisti@4323: lduw(ary1, limit, chr1); twisti@4323: bind(Lloop); twisti@4323: lduw(ary2, limit, chr2); twisti@4323: cmp(chr1, chr2); twisti@4323: br(Assembler::notEqual, true, Assembler::pt, Ldone); twisti@4323: delayed()->mov(G0, result); // not equal twisti@4323: inccc(limit, 2*sizeof(jchar)); twisti@4323: // annul LDUW if branch is not taken to prevent access past end of array twisti@4323: br(Assembler::notZero, true, Assembler::pt, Lloop); twisti@4323: delayed()->lduw(ary1, limit, chr1); // hoisted twisti@4323: twisti@4323: // Caller should set it: twisti@4323: // add(G0, 1, result); // equals twisti@4323: } twisti@4323: twisti@4323: // Use BIS for zeroing (count is in bytes). twisti@4323: void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) { twisti@4323: assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing"); twisti@4323: Register end = count; twisti@4323: int cache_line_size = VM_Version::prefetch_data_size(); twisti@4323: // Minimum count when BIS zeroing can be used since twisti@4323: // it needs membar which is expensive. twisti@4323: int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit); twisti@4323: twisti@4323: Label small_loop; twisti@4323: // Check if count is negative (dead code) or zero. twisti@4323: // Note, count uses 64bit in 64 bit VM. twisti@4323: cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone); twisti@4323: twisti@4323: // Use BIS zeroing only for big arrays since it requires membar. twisti@4323: if (Assembler::is_simm13(block_zero_size)) { // < 4096 twisti@4323: cmp(count, block_zero_size); twisti@4323: } else { twisti@4323: set(block_zero_size, temp); twisti@4323: cmp(count, temp); twisti@4323: } twisti@4323: br(Assembler::lessUnsigned, false, Assembler::pt, small_loop); twisti@4323: delayed()->add(to, count, end); twisti@4323: twisti@4323: // Note: size is >= three (32 bytes) cache lines. twisti@4323: twisti@4323: // Clean the beginning of space up to next cache line. twisti@4323: for (int offs = 0; offs < cache_line_size; offs += 8) { twisti@4323: stx(G0, to, offs); twisti@4323: } twisti@4323: twisti@4323: // align to next cache line twisti@4323: add(to, cache_line_size, to); twisti@4323: and3(to, -cache_line_size, to); twisti@4323: twisti@4323: // Note: size left >= two (32 bytes) cache lines. twisti@4323: twisti@4323: // BIS should not be used to zero tail (64 bytes) twisti@4323: // to avoid zeroing a header of the following object. twisti@4323: sub(end, (cache_line_size*2)-8, end); twisti@4323: twisti@4323: Label bis_loop; twisti@4323: bind(bis_loop); twisti@4323: stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); twisti@4323: add(to, cache_line_size, to); twisti@4323: cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop); twisti@4323: twisti@4323: // BIS needs membar. twisti@4323: membar(Assembler::StoreLoad); twisti@4323: twisti@4323: add(end, (cache_line_size*2)-8, end); // restore end twisti@4323: cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone); twisti@4323: twisti@4323: // Clean the tail. twisti@4323: bind(small_loop); twisti@4323: stx(G0, to, 0); twisti@4323: add(to, 8, to); twisti@4323: cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop); twisti@4323: nop(); // Separate short branches twisti@4323: }