twisti@4318: /*
drchase@5353:  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
twisti@4318:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@4318:  *
twisti@4318:  * This code is free software; you can redistribute it and/or modify it
twisti@4318:  * under the terms of the GNU General Public License version 2 only, as
twisti@4318:  * published by the Free Software Foundation.
twisti@4318:  *
twisti@4318:  * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@4318:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@4318:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
twisti@4318:  * version 2 for more details (a copy is included in the LICENSE file that
twisti@4318:  * accompanied this code).
twisti@4318:  *
twisti@4318:  * You should have received a copy of the GNU General Public License version
twisti@4318:  * 2 along with this work; if not, write to the Free Software Foundation,
twisti@4318:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@4318:  *
twisti@4318:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
twisti@4318:  * or visit www.oracle.com if you need additional information or have any
twisti@4318:  * questions.
twisti@4318:  *
twisti@4318:  */
twisti@4318: 
twisti@4318: #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@4318: #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@4318: 
twisti@4318: #include "asm/assembler.hpp"
jprovino@4542: #include "utilities/macros.hpp"
twisti@4318: 
twisti@4318: 
twisti@4318: // MacroAssembler extends Assembler by frequently used macros.
twisti@4318: //
twisti@4318: // Instructions for which a 'better' code sequence exists depending
twisti@4318: // on arguments should also go in here.
twisti@4318: 
twisti@4318: class MacroAssembler: public Assembler {
twisti@4318:   friend class LIR_Assembler;
twisti@4318:   friend class Runtime1;      // as_Address()
twisti@4318: 
twisti@4318:  protected:
twisti@4318: 
twisti@4318:   Address as_Address(AddressLiteral adr);
twisti@4318:   Address as_Address(ArrayAddress adr);
twisti@4318: 
twisti@4318:   // Support for VM calls
twisti@4318:   //
twisti@4318:   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
twisti@4318:   // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@4318:   // additional registers when doing a VM call).
twisti@4318: #ifdef CC_INTERP
twisti@4318:   // c++ interpreter never wants to use interp_masm version of call_VM
twisti@4318:   #define VIRTUAL
twisti@4318: #else
twisti@4318:   #define VIRTUAL virtual
twisti@4318: #endif
twisti@4318: 
twisti@4318:   VIRTUAL void call_VM_leaf_base(
twisti@4318:     address entry_point,               // the entry point
twisti@4318:     int     number_of_arguments        // the number of arguments to pop after the call
twisti@4318:   );
twisti@4318: 
twisti@4318:   // This is the base routine called by the different versions of call_VM. The interpreter
twisti@4318:   // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@4318:   // additional registers when doing a VM call).
twisti@4318:   //
twisti@4318:   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
twisti@4318:   // returns the register which contains the thread upon return. If a thread register has been
twisti@4318:   // specified, the return value will correspond to that register. If no last_java_sp is specified
twisti@4318:   // (noreg) than rsp will be used instead.
twisti@4318:   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
twisti@4318:     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
twisti@4318:     Register java_thread,              // the thread if computed before     ; use noreg otherwise
twisti@4318:     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
twisti@4318:     address  entry_point,              // the entry point
twisti@4318:     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
twisti@4318:     bool     check_exceptions          // whether to check for pending exceptions after return
twisti@4318:   );
twisti@4318: 
twisti@4318:   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
twisti@4318:   // The implementation is only non-empty for the InterpreterMacroAssembler,
twisti@4318:   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
twisti@4318:   virtual void check_and_handle_popframe(Register java_thread);
twisti@4318:   virtual void check_and_handle_earlyret(Register java_thread);
twisti@4318: 
twisti@4318:   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
twisti@4318: 
twisti@4318:   // helpers for FPU flag access
twisti@4318:   // tmp is a temporary register, if none is available use noreg
twisti@4318:   void save_rax   (Register tmp);
twisti@4318:   void restore_rax(Register tmp);
twisti@4318: 
twisti@4318:  public:
twisti@4318:   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
twisti@4318: 
twisti@4318:   // Support for NULL-checks
twisti@4318:   //
twisti@4318:   // Generates code that causes a NULL OS exception if the content of reg is NULL.
twisti@4318:   // If the accessed location is M[reg + offset] and the offset is known, provide the
twisti@4318:   // offset. No explicit code generation is needed if the offset is within a certain
twisti@4318:   // range (0 <= offset <= page_size).
twisti@4318: 
twisti@4318:   void null_check(Register reg, int offset = -1);
twisti@4318:   static bool needs_explicit_null_check(intptr_t offset);
twisti@4318: 
twisti@4318:   // Required platform-specific helpers for Label::patch_instructions.
twisti@4318:   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
twisti@4318:   void pd_patch_instruction(address branch, address target) {
twisti@4318:     unsigned char op = branch[0];
twisti@4318:     assert(op == 0xE8 /* call */ ||
twisti@4318:         op == 0xE9 /* jmp */ ||
twisti@4318:         op == 0xEB /* short jmp */ ||
twisti@4318:         (op & 0xF0) == 0x70 /* short jcc */ ||
twisti@4318:         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
twisti@4318:         "Invalid opcode at patch point");
twisti@4318: 
twisti@4318:     if (op == 0xEB || (op & 0xF0) == 0x70) {
twisti@4318:       // short offset operators (jmp and jcc)
twisti@4318:       char* disp = (char*) &branch[1];
twisti@4318:       int imm8 = target - (address) &disp[1];
twisti@4318:       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
twisti@4318:       *disp = imm8;
twisti@4318:     } else {
twisti@4318:       int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
twisti@4318:       int imm32 = target - (address) &disp[1];
twisti@4318:       *disp = imm32;
twisti@4318:     }
twisti@4318:   }
twisti@4318: 
twisti@4318:   // The following 4 methods return the offset of the appropriate move instruction
twisti@4318: 
twisti@4318:   // Support for fast byte/short loading with zero extension (depending on particular CPU)
twisti@4318:   int load_unsigned_byte(Register dst, Address src);
twisti@4318:   int load_unsigned_short(Register dst, Address src);
twisti@4318: 
twisti@4318:   // Support for fast byte/short loading with sign extension (depending on particular CPU)
twisti@4318:   int load_signed_byte(Register dst, Address src);
twisti@4318:   int load_signed_short(Register dst, Address src);
twisti@4318: 
twisti@4318:   // Support for sign-extension (hi:lo = extend_sign(lo))
twisti@4318:   void extend_sign(Register hi, Register lo);
twisti@4318: 
twisti@4318:   // Load and store values by size and signed-ness
twisti@4318:   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
twisti@4318:   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
twisti@4318: 
twisti@4318:   // Support for inc/dec with optimal instruction selection depending on value
twisti@4318: 
twisti@4318:   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
twisti@4318:   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
twisti@4318: 
twisti@4318:   void decrementl(Address dst, int value = 1);
twisti@4318:   void decrementl(Register reg, int value = 1);
twisti@4318: 
twisti@4318:   void decrementq(Register reg, int value = 1);
twisti@4318:   void decrementq(Address dst, int value = 1);
twisti@4318: 
twisti@4318:   void incrementl(Address dst, int value = 1);
twisti@4318:   void incrementl(Register reg, int value = 1);
twisti@4318: 
twisti@4318:   void incrementq(Register reg, int value = 1);
twisti@4318:   void incrementq(Address dst, int value = 1);
twisti@4318: 
twisti@4318: 
twisti@4318:   // Support optimal SSE move instructions.
twisti@4318:   void movflt(XMMRegister dst, XMMRegister src) {
twisti@4318:     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
twisti@4318:     else                       { movss (dst, src); return; }
twisti@4318:   }
twisti@4318:   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
twisti@4318:   void movflt(XMMRegister dst, AddressLiteral src);
twisti@4318:   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
twisti@4318: 
twisti@4318:   void movdbl(XMMRegister dst, XMMRegister src) {
twisti@4318:     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
twisti@4318:     else                       { movsd (dst, src); return; }
twisti@4318:   }
twisti@4318: 
twisti@4318:   void movdbl(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void movdbl(XMMRegister dst, Address src) {
twisti@4318:     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
twisti@4318:     else                         { movlpd(dst, src); return; }
twisti@4318:   }
twisti@4318:   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
twisti@4318: 
twisti@4318:   void incrementl(AddressLiteral dst);
twisti@4318:   void incrementl(ArrayAddress dst);
twisti@4318: 
twisti@4318:   // Alignment
twisti@4318:   void align(int modulus);
twisti@4318: 
twisti@4318:   // A 5 byte nop that is safe for patching (see patch_verified_entry)
twisti@4318:   void fat_nop();
twisti@4318: 
twisti@4318:   // Stack frame creation/removal
twisti@4318:   void enter();
twisti@4318:   void leave();
twisti@4318: 
twisti@4318:   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
twisti@4318:   // The pointer will be loaded into the thread register.
twisti@4318:   void get_thread(Register thread);
twisti@4318: 
twisti@4318: 
twisti@4318:   // Support for VM calls
twisti@4318:   //
twisti@4318:   // It is imperative that all calls into the VM are handled via the call_VM macros.
twisti@4318:   // They make sure that the stack linkage is setup correctly. call_VM's correspond
twisti@4318:   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
twisti@4318: 
twisti@4318: 
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                address entry_point,
twisti@4318:                bool check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1,
twisti@4318:                bool check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1, Register arg_2,
twisti@4318:                bool check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1, Register arg_2, Register arg_3,
twisti@4318:                bool check_exceptions = true);
twisti@4318: 
twisti@4318:   // Overloadings with last_Java_sp
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                Register last_java_sp,
twisti@4318:                address entry_point,
twisti@4318:                int number_of_arguments = 0,
twisti@4318:                bool check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                Register last_java_sp,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1, bool
twisti@4318:                check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                Register last_java_sp,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1, Register arg_2,
twisti@4318:                bool check_exceptions = true);
twisti@4318:   void call_VM(Register oop_result,
twisti@4318:                Register last_java_sp,
twisti@4318:                address entry_point,
twisti@4318:                Register arg_1, Register arg_2, Register arg_3,
twisti@4318:                bool check_exceptions = true);
twisti@4318: 
twisti@4318:   void get_vm_result  (Register oop_result, Register thread);
twisti@4318:   void get_vm_result_2(Register metadata_result, Register thread);
twisti@4318: 
twisti@4318:   // These always tightly bind to MacroAssembler::call_VM_base
twisti@4318:   // bypassing the virtual implementation
twisti@4318:   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
twisti@4318:   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
twisti@4318:   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
twisti@4318:   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
twisti@4318:   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
twisti@4318: 
twisti@4318:   void call_VM_leaf(address entry_point,
twisti@4318:                     int number_of_arguments = 0);
twisti@4318:   void call_VM_leaf(address entry_point,
twisti@4318:                     Register arg_1);
twisti@4318:   void call_VM_leaf(address entry_point,
twisti@4318:                     Register arg_1, Register arg_2);
twisti@4318:   void call_VM_leaf(address entry_point,
twisti@4318:                     Register arg_1, Register arg_2, Register arg_3);
twisti@4318: 
twisti@4318:   // These always tightly bind to MacroAssembler::call_VM_leaf_base
twisti@4318:   // bypassing the virtual implementation
twisti@4318:   void super_call_VM_leaf(address entry_point);
twisti@4318:   void super_call_VM_leaf(address entry_point, Register arg_1);
twisti@4318:   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
twisti@4318:   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
twisti@4318:   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
twisti@4318: 
twisti@4318:   // last Java Frame (fills frame anchor)
twisti@4318:   void set_last_Java_frame(Register thread,
twisti@4318:                            Register last_java_sp,
twisti@4318:                            Register last_java_fp,
twisti@4318:                            address last_java_pc);
twisti@4318: 
twisti@4318:   // thread in the default location (r15_thread on 64bit)
twisti@4318:   void set_last_Java_frame(Register last_java_sp,
twisti@4318:                            Register last_java_fp,
twisti@4318:                            address last_java_pc);
twisti@4318: 
twisti@4318:   void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
twisti@4318: 
twisti@4318:   // thread in the default location (r15_thread on 64bit)
twisti@4318:   void reset_last_Java_frame(bool clear_fp, bool clear_pc);
twisti@4318: 
twisti@4318:   // Stores
twisti@4318:   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
twisti@4318:   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
twisti@4318: 
jprovino@4542: #if INCLUDE_ALL_GCS
twisti@4318: 
twisti@4318:   void g1_write_barrier_pre(Register obj,
twisti@4318:                             Register pre_val,
twisti@4318:                             Register thread,
twisti@4318:                             Register tmp,
twisti@4318:                             bool tosca_live,
twisti@4318:                             bool expand_call);
twisti@4318: 
twisti@4318:   void g1_write_barrier_post(Register store_addr,
twisti@4318:                              Register new_val,
twisti@4318:                              Register thread,
twisti@4318:                              Register tmp,
twisti@4318:                              Register tmp2);
twisti@4318: 
jprovino@4542: #endif // INCLUDE_ALL_GCS
twisti@4318: 
twisti@4318:   // split store_check(Register obj) to enhance instruction interleaving
twisti@4318:   void store_check_part_1(Register obj);
twisti@4318:   void store_check_part_2(Register obj);
twisti@4318: 
twisti@4318:   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
twisti@4318:   void c2bool(Register x);
twisti@4318: 
twisti@4318:   // C++ bool manipulation
twisti@4318: 
twisti@4318:   void movbool(Register dst, Address src);
twisti@4318:   void movbool(Address dst, bool boolconst);
twisti@4318:   void movbool(Address dst, Register src);
twisti@4318:   void testbool(Register dst);
twisti@4318: 
twisti@4318:   // oop manipulations
twisti@4318:   void load_klass(Register dst, Register src);
twisti@4318:   void store_klass(Register dst, Register src);
twisti@4318: 
twisti@4318:   void load_heap_oop(Register dst, Address src);
twisti@4318:   void load_heap_oop_not_null(Register dst, Address src);
twisti@4318:   void store_heap_oop(Address dst, Register src);
twisti@4318:   void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
twisti@4318: 
twisti@4318:   // Used for storing NULL. All other oop constants should be
twisti@4318:   // stored using routines that take a jobject.
twisti@4318:   void store_heap_oop_null(Address dst);
twisti@4318: 
twisti@4318:   void load_prototype_header(Register dst, Register src);
twisti@4318: 
twisti@4318: #ifdef _LP64
twisti@4318:   void store_klass_gap(Register dst, Register src);
twisti@4318: 
twisti@4318:   // This dummy is to prevent a call to store_heap_oop from
twisti@4318:   // converting a zero (like NULL) into a Register by giving
twisti@4318:   // the compiler two choices it can't resolve
twisti@4318: 
twisti@4318:   void store_heap_oop(Address dst, void* dummy);
twisti@4318: 
twisti@4318:   void encode_heap_oop(Register r);
twisti@4318:   void decode_heap_oop(Register r);
twisti@4318:   void encode_heap_oop_not_null(Register r);
twisti@4318:   void decode_heap_oop_not_null(Register r);
twisti@4318:   void encode_heap_oop_not_null(Register dst, Register src);
twisti@4318:   void decode_heap_oop_not_null(Register dst, Register src);
twisti@4318: 
twisti@4318:   void set_narrow_oop(Register dst, jobject obj);
twisti@4318:   void set_narrow_oop(Address dst, jobject obj);
twisti@4318:   void cmp_narrow_oop(Register dst, jobject obj);
twisti@4318:   void cmp_narrow_oop(Address dst, jobject obj);
twisti@4318: 
twisti@4318:   void encode_klass_not_null(Register r);
twisti@4318:   void decode_klass_not_null(Register r);
twisti@4318:   void encode_klass_not_null(Register dst, Register src);
twisti@4318:   void decode_klass_not_null(Register dst, Register src);
twisti@4318:   void set_narrow_klass(Register dst, Klass* k);
twisti@4318:   void set_narrow_klass(Address dst, Klass* k);
twisti@4318:   void cmp_narrow_klass(Register dst, Klass* k);
twisti@4318:   void cmp_narrow_klass(Address dst, Klass* k);
twisti@4318: 
hseigel@5528:   // Returns the byte size of the instructions generated by decode_klass_not_null()
hseigel@5528:   // when compressed klass pointers are being used.
hseigel@5528:   static int instr_size_for_decode_klass_not_null();
hseigel@5528: 
twisti@4318:   // if heap base register is used - reinit it with the correct value
twisti@4318:   void reinit_heapbase();
twisti@4318: 
twisti@4318:   DEBUG_ONLY(void verify_heapbase(const char* msg);)
twisti@4318: 
twisti@4318: #endif // _LP64
twisti@4318: 
twisti@4318:   // Int division/remainder for Java
twisti@4318:   // (as idivl, but checks for special case as described in JVM spec.)
twisti@4318:   // returns idivl instruction offset for implicit exception handling
twisti@4318:   int corrected_idivl(Register reg);
twisti@4318: 
twisti@4318:   // Long division/remainder for Java
twisti@4318:   // (as idivq, but checks for special case as described in JVM spec.)
twisti@4318:   // returns idivq instruction offset for implicit exception handling
twisti@4318:   int corrected_idivq(Register reg);
twisti@4318: 
twisti@4318:   void int3();
twisti@4318: 
twisti@4318:   // Long operation macros for a 32bit cpu
twisti@4318:   // Long negation for Java
twisti@4318:   void lneg(Register hi, Register lo);
twisti@4318: 
twisti@4318:   // Long multiplication for Java
twisti@4318:   // (destroys contents of eax, ebx, ecx and edx)
twisti@4318:   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
twisti@4318: 
twisti@4318:   // Long shifts for Java
twisti@4318:   // (semantics as described in JVM spec.)
twisti@4318:   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
twisti@4318:   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
twisti@4318: 
twisti@4318:   // Long compare for Java
twisti@4318:   // (semantics as described in JVM spec.)
twisti@4318:   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
twisti@4318: 
twisti@4318: 
twisti@4318:   // misc
twisti@4318: 
twisti@4318:   // Sign extension
twisti@4318:   void sign_extend_short(Register reg);
twisti@4318:   void sign_extend_byte(Register reg);
twisti@4318: 
twisti@4318:   // Division by power of 2, rounding towards 0
twisti@4318:   void division_with_shift(Register reg, int shift_value);
twisti@4318: 
twisti@4318:   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
twisti@4318:   //
twisti@4318:   // CF (corresponds to C0) if x < y
twisti@4318:   // PF (corresponds to C2) if unordered
twisti@4318:   // ZF (corresponds to C3) if x = y
twisti@4318:   //
twisti@4318:   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@4318:   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
twisti@4318:   void fcmp(Register tmp);
twisti@4318:   // Variant of the above which allows y to be further down the stack
twisti@4318:   // and which only pops x and y if specified. If pop_right is
twisti@4318:   // specified then pop_left must also be specified.
twisti@4318:   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
twisti@4318: 
twisti@4318:   // Floating-point comparison for Java
twisti@4318:   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
twisti@4318:   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@4318:   // (semantics as described in JVM spec.)
twisti@4318:   void fcmp2int(Register dst, bool unordered_is_less);
twisti@4318:   // Variant of the above which allows y to be further down the stack
twisti@4318:   // and which only pops x and y if specified. If pop_right is
twisti@4318:   // specified then pop_left must also be specified.
twisti@4318:   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
twisti@4318: 
twisti@4318:   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
twisti@4318:   // tmp is a temporary register, if none is available use noreg
twisti@4318:   void fremr(Register tmp);
twisti@4318: 
twisti@4318: 
twisti@4318:   // same as fcmp2int, but using SSE2
twisti@4318:   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@4318:   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@4318: 
twisti@4318:   // Inlined sin/cos generator for Java; must not use CPU instruction
twisti@4318:   // directly on Intel as it does not have high enough precision
twisti@4318:   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
twisti@4318:   // number of FPU stack slots in use; all but the topmost will
twisti@4318:   // require saving if a slow case is necessary. Assumes argument is
twisti@4318:   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
twisti@4318:   // this code.
twisti@4318:   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
twisti@4318: 
twisti@4318:   // branch to L if FPU flag C2 is set/not set
twisti@4318:   // tmp is a temporary register, if none is available use noreg
twisti@4318:   void jC2 (Register tmp, Label& L);
twisti@4318:   void jnC2(Register tmp, Label& L);
twisti@4318: 
twisti@4318:   // Pop ST (ffree & fincstp combined)
twisti@4318:   void fpop();
twisti@4318: 
twisti@4318:   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
twisti@4318:   void push_fTOS();
twisti@4318: 
twisti@4318:   // pops double TOS element from CPU stack and pushes on FPU stack
twisti@4318:   void pop_fTOS();
twisti@4318: 
twisti@4318:   void empty_FPU_stack();
twisti@4318: 
twisti@4318:   void push_IU_state();
twisti@4318:   void pop_IU_state();
twisti@4318: 
twisti@4318:   void push_FPU_state();
twisti@4318:   void pop_FPU_state();
twisti@4318: 
twisti@4318:   void push_CPU_state();
twisti@4318:   void pop_CPU_state();
twisti@4318: 
twisti@4318:   // Round up to a power of two
twisti@4318:   void round_to(Register reg, int modulus);
twisti@4318: 
twisti@4318:   // Callee saved registers handling
twisti@4318:   void push_callee_saved_registers();
twisti@4318:   void pop_callee_saved_registers();
twisti@4318: 
twisti@4318:   // allocation
twisti@4318:   void eden_allocate(
twisti@4318:     Register obj,                      // result: pointer to object after successful allocation
twisti@4318:     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
twisti@4318:     int      con_size_in_bytes,        // object size in bytes if   known at compile time
twisti@4318:     Register t1,                       // temp register
twisti@4318:     Label&   slow_case                 // continuation point if fast allocation fails
twisti@4318:   );
twisti@4318:   void tlab_allocate(
twisti@4318:     Register obj,                      // result: pointer to object after successful allocation
twisti@4318:     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
twisti@4318:     int      con_size_in_bytes,        // object size in bytes if   known at compile time
twisti@4318:     Register t1,                       // temp register
twisti@4318:     Register t2,                       // temp register
twisti@4318:     Label&   slow_case                 // continuation point if fast allocation fails
twisti@4318:   );
twisti@4318:   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
twisti@4318:   void incr_allocated_bytes(Register thread,
twisti@4318:                             Register var_size_in_bytes, int con_size_in_bytes,
twisti@4318:                             Register t1 = noreg);
twisti@4318: 
twisti@4318:   // interface method calling
twisti@4318:   void lookup_interface_method(Register recv_klass,
twisti@4318:                                Register intf_klass,
twisti@4318:                                RegisterOrConstant itable_index,
twisti@4318:                                Register method_result,
twisti@4318:                                Register scan_temp,
twisti@4318:                                Label& no_such_interface);
twisti@4318: 
twisti@4318:   // virtual method calling
twisti@4318:   void lookup_virtual_method(Register recv_klass,
twisti@4318:                              RegisterOrConstant vtable_index,
twisti@4318:                              Register method_result);
twisti@4318: 
twisti@4318:   // Test sub_klass against super_klass, with fast and slow paths.
twisti@4318: 
twisti@4318:   // The fast path produces a tri-state answer: yes / no / maybe-slow.
twisti@4318:   // One of the three labels can be NULL, meaning take the fall-through.
twisti@4318:   // If super_check_offset is -1, the value is loaded up from super_klass.
twisti@4318:   // No registers are killed, except temp_reg.
twisti@4318:   void check_klass_subtype_fast_path(Register sub_klass,
twisti@4318:                                      Register super_klass,
twisti@4318:                                      Register temp_reg,
twisti@4318:                                      Label* L_success,
twisti@4318:                                      Label* L_failure,
twisti@4318:                                      Label* L_slow_path,
twisti@4318:                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
twisti@4318: 
twisti@4318:   // The rest of the type check; must be wired to a corresponding fast path.
twisti@4318:   // It does not repeat the fast path logic, so don't use it standalone.
twisti@4318:   // The temp_reg and temp2_reg can be noreg, if no temps are available.
twisti@4318:   // Updates the sub's secondary super cache as necessary.
twisti@4318:   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
twisti@4318:   void check_klass_subtype_slow_path(Register sub_klass,
twisti@4318:                                      Register super_klass,
twisti@4318:                                      Register temp_reg,
twisti@4318:                                      Register temp2_reg,
twisti@4318:                                      Label* L_success,
twisti@4318:                                      Label* L_failure,
twisti@4318:                                      bool set_cond_codes = false);
twisti@4318: 
twisti@4318:   // Simplified, combined version, good for typical uses.
twisti@4318:   // Falls through on failure.
twisti@4318:   void check_klass_subtype(Register sub_klass,
twisti@4318:                            Register super_klass,
twisti@4318:                            Register temp_reg,
twisti@4318:                            Label& L_success);
twisti@4318: 
twisti@4318:   // method handles (JSR 292)
twisti@4318:   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
twisti@4318: 
twisti@4318:   //----
twisti@4318:   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
twisti@4318: 
twisti@4318:   // Debugging
twisti@4318: 
twisti@4318:   // only if +VerifyOops
twisti@4318:   // TODO: Make these macros with file and line like sparc version!
twisti@4318:   void verify_oop(Register reg, const char* s = "broken oop");
twisti@4318:   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
twisti@4318: 
twisti@4318:   // TODO: verify method and klass metadata (compare against vptr?)
twisti@4318:   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
twisti@4318:   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
twisti@4318: 
twisti@4318: #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
twisti@4318: #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
twisti@4318: 
twisti@4318:   // only if +VerifyFPU
twisti@4318:   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
twisti@4318: 
kvn@4873:   // Verify or restore cpu control state after JNI call
kvn@4873:   void restore_cpu_control_state_after_jni();
kvn@4873: 
twisti@4318:   // prints msg, dumps registers and stops execution
twisti@4318:   void stop(const char* msg);
twisti@4318: 
twisti@4318:   // prints msg and continues
twisti@4318:   void warn(const char* msg);
twisti@4318: 
twisti@4318:   // dumps registers and other state
twisti@4318:   void print_state();
twisti@4318: 
twisti@4318:   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
twisti@4318:   static void debug64(char* msg, int64_t pc, int64_t regs[]);
twisti@4318:   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
twisti@4318:   static void print_state64(int64_t pc, int64_t regs[]);
twisti@4318: 
twisti@4318:   void os_breakpoint();
twisti@4318: 
twisti@4318:   void untested()                                { stop("untested"); }
twisti@4318: 
twisti@4318:   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
twisti@4318: 
twisti@4318:   void should_not_reach_here()                   { stop("should not reach here"); }
twisti@4318: 
twisti@4318:   void print_CPU_state();
twisti@4318: 
twisti@4318:   // Stack overflow checking
twisti@4318:   void bang_stack_with_offset(int offset) {
twisti@4318:     // stack grows down, caller passes positive offset
twisti@4318:     assert(offset > 0, "must bang with negative offset");
twisti@4318:     movl(Address(rsp, (-offset)), rax);
twisti@4318:   }
twisti@4318: 
twisti@4318:   // Writes to stack successive pages until offset reached to check for
twisti@4318:   // stack overflow + shadow pages.  Also, clobbers tmp
twisti@4318:   void bang_stack_size(Register size, Register tmp);
twisti@4318: 
twisti@4318:   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
twisti@4318:                                                 Register tmp,
twisti@4318:                                                 int offset);
twisti@4318: 
twisti@4318:   // Support for serializing memory accesses between threads
twisti@4318:   void serialize_memory(Register thread, Register tmp);
twisti@4318: 
twisti@4318:   void verify_tlab();
twisti@4318: 
twisti@4318:   // Biased locking support
twisti@4318:   // lock_reg and obj_reg must be loaded up with the appropriate values.
twisti@4318:   // swap_reg must be rax, and is killed.
twisti@4318:   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
twisti@4318:   // be killed; if not supplied, push/pop will be used internally to
twisti@4318:   // allocate a temporary (inefficient, avoid if possible).
twisti@4318:   // Optional slow case is for implementations (interpreter and C1) which branch to
twisti@4318:   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
twisti@4318:   // Returns offset of first potentially-faulting instruction for null
twisti@4318:   // check info (currently consumed only by C1). If
twisti@4318:   // swap_reg_contains_mark is true then returns -1 as it is assumed
twisti@4318:   // the calling code has already passed any potential faults.
twisti@4318:   int biased_locking_enter(Register lock_reg, Register obj_reg,
twisti@4318:                            Register swap_reg, Register tmp_reg,
twisti@4318:                            bool swap_reg_contains_mark,
twisti@4318:                            Label& done, Label* slow_case = NULL,
twisti@4318:                            BiasedLockingCounters* counters = NULL);
twisti@4318:   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
twisti@4318: 
twisti@4318: 
twisti@4318:   Condition negate_condition(Condition cond);
twisti@4318: 
twisti@4318:   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
twisti@4318:   // operands. In general the names are modified to avoid hiding the instruction in Assembler
twisti@4318:   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
twisti@4318:   // here in MacroAssembler. The major exception to this rule is call
twisti@4318: 
twisti@4318:   // Arithmetics
twisti@4318: 
twisti@4318: 
twisti@4318:   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
twisti@4318:   void addptr(Address dst, Register src);
twisti@4318: 
twisti@4318:   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
twisti@4318:   void addptr(Register dst, int32_t src);
twisti@4318:   void addptr(Register dst, Register src);
twisti@4318:   void addptr(Register dst, RegisterOrConstant src) {
twisti@4318:     if (src.is_constant()) addptr(dst, (int) src.as_constant());
twisti@4318:     else                   addptr(dst,       src.as_register());
twisti@4318:   }
twisti@4318: 
twisti@4318:   void andptr(Register dst, int32_t src);
twisti@4318:   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
twisti@4318: 
twisti@4318:   void cmp8(AddressLiteral src1, int imm);
twisti@4318: 
twisti@4318:   // renamed to drag out the casting of address to int32_t/intptr_t
twisti@4318:   void cmp32(Register src1, int32_t imm);
twisti@4318: 
twisti@4318:   void cmp32(AddressLiteral src1, int32_t imm);
twisti@4318:   // compare reg - mem, or reg - &mem
twisti@4318:   void cmp32(Register src1, AddressLiteral src2);
twisti@4318: 
twisti@4318:   void cmp32(Register src1, Address src2);
twisti@4318: 
twisti@4318: #ifndef _LP64
twisti@4318:   void cmpklass(Address dst, Metadata* obj);
twisti@4318:   void cmpklass(Register dst, Metadata* obj);
twisti@4318:   void cmpoop(Address dst, jobject obj);
twisti@4318:   void cmpoop(Register dst, jobject obj);
twisti@4318: #endif // _LP64
twisti@4318: 
twisti@4318:   // NOTE src2 must be the lval. This is NOT an mem-mem compare
twisti@4318:   void cmpptr(Address src1, AddressLiteral src2);
twisti@4318: 
twisti@4318:   void cmpptr(Register src1, AddressLiteral src2);
twisti@4318: 
twisti@4318:   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@4318:   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@4318:   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@4318: 
twisti@4318:   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@4318:   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@4318: 
twisti@4318:   // cmp64 to avoild hiding cmpq
twisti@4318:   void cmp64(Register src1, AddressLiteral src);
twisti@4318: 
twisti@4318:   void cmpxchgptr(Register reg, Address adr);
twisti@4318: 
twisti@4318:   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
twisti@4318: 
twisti@4318: 
twisti@4318:   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
twisti@4318: 
twisti@4318: 
twisti@4318:   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
twisti@4318: 
twisti@4318:   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
twisti@4318: 
twisti@4318:   void shlptr(Register dst, int32_t shift);
twisti@4318:   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
twisti@4318: 
twisti@4318:   void shrptr(Register dst, int32_t shift);
twisti@4318:   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
twisti@4318: 
twisti@4318:   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
twisti@4318:   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
twisti@4318: 
twisti@4318:   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@4318: 
twisti@4318:   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@4318:   void subptr(Register dst, int32_t src);
twisti@4318:   // Force generation of a 4 byte immediate value even if it fits into 8bit
twisti@4318:   void subptr_imm32(Register dst, int32_t src);
twisti@4318:   void subptr(Register dst, Register src);
twisti@4318:   void subptr(Register dst, RegisterOrConstant src) {
twisti@4318:     if (src.is_constant()) subptr(dst, (int) src.as_constant());
twisti@4318:     else                   subptr(dst,       src.as_register());
twisti@4318:   }
twisti@4318: 
twisti@4318:   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@4318:   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@4318: 
twisti@4318:   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@4318:   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@4318: 
twisti@4318:   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
twisti@4318: 
twisti@4318: 
twisti@4318: 
twisti@4318:   // Helper functions for statistics gathering.
twisti@4318:   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
twisti@4318:   void cond_inc32(Condition cond, AddressLiteral counter_addr);
twisti@4318:   // Unconditional atomic increment.
twisti@4318:   void atomic_incl(AddressLiteral counter_addr);
twisti@4318: 
twisti@4318:   void lea(Register dst, AddressLiteral adr);
twisti@4318:   void lea(Address dst, AddressLiteral adr);
twisti@4318:   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
twisti@4318: 
twisti@4318:   void leal32(Register dst, Address src) { leal(dst, src); }
twisti@4318: 
twisti@4318:   // Import other testl() methods from the parent class or else
twisti@4318:   // they will be hidden by the following overriding declaration.
twisti@4318:   using Assembler::testl;
twisti@4318:   void testl(Register dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@4318:   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@4318:   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@4318: 
twisti@4318:   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
twisti@4318:   void testptr(Register src1, Register src2);
twisti@4318: 
twisti@4318:   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@4318:   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@4318: 
twisti@4318:   // Calls
twisti@4318: 
twisti@4318:   void call(Label& L, relocInfo::relocType rtype);
twisti@4318:   void call(Register entry);
twisti@4318: 
twisti@4318:   // NOTE: this call tranfers to the effective address of entry NOT
twisti@4318:   // the address contained by entry. This is because this is more natural
twisti@4318:   // for jumps/calls.
twisti@4318:   void call(AddressLiteral entry);
twisti@4318: 
twisti@4318:   // Emit the CompiledIC call idiom
twisti@4318:   void ic_call(address entry);
twisti@4318: 
twisti@4318:   // Jumps
twisti@4318: 
twisti@4318:   // NOTE: these jumps tranfer to the effective address of dst NOT
twisti@4318:   // the address contained by dst. This is because this is more natural
twisti@4318:   // for jumps/calls.
twisti@4318:   void jump(AddressLiteral dst);
twisti@4318:   void jump_cc(Condition cc, AddressLiteral dst);
twisti@4318: 
twisti@4318:   // 32bit can do a case table jump in one instruction but we no longer allow the base
twisti@4318:   // to be installed in the Address class. This jump will tranfers to the address
twisti@4318:   // contained in the location described by entry (not the address of entry)
twisti@4318:   void jump(ArrayAddress entry);
twisti@4318: 
twisti@4318:   // Floating
twisti@4318: 
twisti@4318:   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
twisti@4318:   void andpd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
twisti@4318:   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
twisti@4318:   void andps(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
twisti@4318:   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
twisti@4318:   void comiss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
twisti@4318:   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
twisti@4318:   void comisd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void fadd_s(Address src)        { Assembler::fadd_s(src); }
twisti@4318:   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
twisti@4318: 
twisti@4318:   void fldcw(Address src) { Assembler::fldcw(src); }
twisti@4318:   void fldcw(AddressLiteral src);
twisti@4318: 
twisti@4318:   void fld_s(int index)   { Assembler::fld_s(index); }
twisti@4318:   void fld_s(Address src) { Assembler::fld_s(src); }
twisti@4318:   void fld_s(AddressLiteral src);
twisti@4318: 
twisti@4318:   void fld_d(Address src) { Assembler::fld_d(src); }
twisti@4318:   void fld_d(AddressLiteral src);
twisti@4318: 
twisti@4318:   void fld_x(Address src) { Assembler::fld_x(src); }
twisti@4318:   void fld_x(AddressLiteral src);
twisti@4318: 
twisti@4318:   void fmul_s(Address src)        { Assembler::fmul_s(src); }
twisti@4318:   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
twisti@4318: 
twisti@4318:   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
twisti@4318:   void ldmxcsr(AddressLiteral src);
twisti@4318: 
twisti@4318:   // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
twisti@4318:   // all corner cases and may result in NaN and require fallback to a
twisti@4318:   // runtime call.
twisti@4318:   void fast_pow();
twisti@4318:   void fast_exp();
twisti@4318:   void increase_precision();
twisti@4318:   void restore_precision();
twisti@4318: 
twisti@4318:   // computes exp(x). Fallback to runtime call included.
twisti@4318:   void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
twisti@4318:   // computes pow(x,y). Fallback to runtime call included.
twisti@4318:   void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
twisti@4318: 
twisti@4318: private:
twisti@4318: 
twisti@4318:   // call runtime as a fallback for trig functions and pow/exp.
twisti@4318:   void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
twisti@4318: 
twisti@4318:   // computes 2^(Ylog2X); Ylog2X in ST(0)
twisti@4318:   void pow_exp_core_encoding();
twisti@4318: 
twisti@4318:   // computes pow(x,y) or exp(x). Fallback to runtime call included.
twisti@4318:   void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
twisti@4318: 
twisti@4318:   // these are private because users should be doing movflt/movdbl
twisti@4318: 
twisti@4318:   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
twisti@4318:   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@4318:   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
twisti@4318:   void movss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
twisti@4318:   void movlpd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318: public:
twisti@4318: 
twisti@4318:   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
twisti@4318:   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
twisti@4318:   void addsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
twisti@4318:   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
twisti@4318:   void addss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
twisti@4318:   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
twisti@4318:   void divsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
twisti@4318:   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
twisti@4318:   void divss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // Move Unaligned Double Quadword
twisti@4318:   void movdqu(Address     dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
twisti@4318:   void movdqu(XMMRegister dst, Address src)       { Assembler::movdqu(dst, src); }
twisti@4318:   void movdqu(XMMRegister dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
twisti@4318:   void movdqu(XMMRegister dst, AddressLiteral src);
twisti@4318: 
drchase@5353:   // Move Aligned Double Quadword
drchase@5353:   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
drchase@5353:   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
drchase@5353:   void movdqa(XMMRegister dst, AddressLiteral src);
drchase@5353: 
twisti@4318:   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@4318:   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
twisti@4318:   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
twisti@4318:   void movsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
twisti@4318:   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
twisti@4318:   void mulsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
twisti@4318:   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
twisti@4318:   void mulss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
twisti@4318:   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
twisti@4318:   void sqrtsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
twisti@4318:   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
twisti@4318:   void sqrtss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
twisti@4318:   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
twisti@4318:   void subsd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
twisti@4318:   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
twisti@4318:   void subss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
twisti@4318:   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
twisti@4318:   void ucomiss(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
twisti@4318:   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
twisti@4318:   void ucomisd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
twisti@4318:   void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
twisti@4318:   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
twisti@4318:   void xorpd(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
twisti@4318:   void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
twisti@4318:   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
twisti@4318:   void xorps(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // Shuffle Bytes
twisti@4318:   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
twisti@4318:   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
twisti@4318:   void pshufb(XMMRegister dst, AddressLiteral src);
twisti@4318:   // AVX 3-operands instructions
twisti@4318: 
twisti@4318:   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
twisti@4318:   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
twisti@4318:   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
twisti@4318:   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
twisti@4318:   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
twisti@4318:   void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandpd(dst, nds, src, vector256); }
twisti@4318:   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@4318: 
twisti@4318:   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
twisti@4318:   void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandps(dst, nds, src, vector256); }
twisti@4318:   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@4318: 
twisti@4318:   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
twisti@4318:   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
twisti@4318:   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
twisti@4318:   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
twisti@4318:   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
twisti@4318:   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
twisti@4318:   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
twisti@4318:   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
twisti@4318:   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
twisti@4318:   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
twisti@4318:   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
twisti@4318:   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
twisti@4318:   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@4318: 
twisti@4318:   // AVX Vector instructions
twisti@4318: 
twisti@4318:   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
twisti@4318:   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
twisti@4318:   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@4318: 
twisti@4318:   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
twisti@4318:   void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
twisti@4318:   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@4318: 
twisti@4318:   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
twisti@4318:     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
twisti@4318:       Assembler::vpxor(dst, nds, src, vector256);
twisti@4318:     else
twisti@4318:       Assembler::vxorpd(dst, nds, src, vector256);
twisti@4318:   }
twisti@4318:   void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
twisti@4318:     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
twisti@4318:       Assembler::vpxor(dst, nds, src, vector256);
twisti@4318:     else
twisti@4318:       Assembler::vxorpd(dst, nds, src, vector256);
twisti@4318:   }
twisti@4318: 
kvn@4413:   // Simple version for AVX2 256bit vectors
kvn@4413:   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
kvn@4413:   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
kvn@4413: 
twisti@4318:   // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
twisti@4318:   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
twisti@4318:     if (UseAVX > 1) // vinserti128h is available only in AVX2
twisti@4318:       Assembler::vinserti128h(dst, nds, src);
twisti@4318:     else
twisti@4318:       Assembler::vinsertf128h(dst, nds, src);
twisti@4318:   }
twisti@4318: 
drchase@5353:   // Carry-Less Multiplication Quadword
drchase@5353:   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@5353:     // 0x00 - multiply lower 64 bits [0:63]
drchase@5353:     Assembler::vpclmulqdq(dst, nds, src, 0x00);
drchase@5353:   }
drchase@5353:   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@5353:     // 0x11 - multiply upper 64 bits [64:127]
drchase@5353:     Assembler::vpclmulqdq(dst, nds, src, 0x11);
drchase@5353:   }
drchase@5353: 
twisti@4318:   // Data
twisti@4318: 
twisti@4318:   void cmov32( Condition cc, Register dst, Address  src);
twisti@4318:   void cmov32( Condition cc, Register dst, Register src);
twisti@4318: 
twisti@4318:   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
twisti@4318: 
twisti@4318:   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@4318:   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@4318: 
twisti@4318:   void movoop(Register dst, jobject obj);
twisti@4318:   void movoop(Address dst, jobject obj);
twisti@4318: 
twisti@4318:   void mov_metadata(Register dst, Metadata* obj);
twisti@4318:   void mov_metadata(Address dst, Metadata* obj);
twisti@4318: 
twisti@4318:   void movptr(ArrayAddress dst, Register src);
twisti@4318:   // can this do an lea?
twisti@4318:   void movptr(Register dst, ArrayAddress src);
twisti@4318: 
twisti@4318:   void movptr(Register dst, Address src);
twisti@4318: 
twisti@4318:   void movptr(Register dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   void movptr(Register dst, intptr_t src);
twisti@4318:   void movptr(Register dst, Register src);
twisti@4318:   void movptr(Address dst, intptr_t src);
twisti@4318: 
twisti@4318:   void movptr(Address dst, Register src);
twisti@4318: 
twisti@4318:   void movptr(Register dst, RegisterOrConstant src) {
twisti@4318:     if (src.is_constant()) movptr(dst, src.as_constant());
twisti@4318:     else                   movptr(dst, src.as_register());
twisti@4318:   }
twisti@4318: 
twisti@4318: #ifdef _LP64
twisti@4318:   // Generally the next two are only used for moving NULL
twisti@4318:   // Although there are situations in initializing the mark word where
twisti@4318:   // they could be used. They are dangerous.
twisti@4318: 
twisti@4318:   // They only exist on LP64 so that int32_t and intptr_t are not the same
twisti@4318:   // and we have ambiguous declarations.
twisti@4318: 
twisti@4318:   void movptr(Address dst, int32_t imm32);
twisti@4318:   void movptr(Register dst, int32_t imm32);
twisti@4318: #endif // _LP64
twisti@4318: 
twisti@4318:   // to avoid hiding movl
twisti@4318:   void mov32(AddressLiteral dst, Register src);
twisti@4318:   void mov32(Register dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // to avoid hiding movb
twisti@4318:   void movbyte(ArrayAddress dst, int src);
twisti@4318: 
twisti@4318:   // Import other mov() methods from the parent class or else
twisti@4318:   // they will be hidden by the following overriding declaration.
twisti@4318:   using Assembler::movdl;
twisti@4318:   using Assembler::movq;
twisti@4318:   void movdl(XMMRegister dst, AddressLiteral src);
twisti@4318:   void movq(XMMRegister dst, AddressLiteral src);
twisti@4318: 
twisti@4318:   // Can push value or effective address
twisti@4318:   void pushptr(AddressLiteral src);
twisti@4318: 
twisti@4318:   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
twisti@4318:   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
twisti@4318: 
twisti@4318:   void pushoop(jobject obj);
twisti@4318:   void pushklass(Metadata* obj);
twisti@4318: 
twisti@4318:   // sign extend as need a l to ptr sized element
twisti@4318:   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
twisti@4318:   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
twisti@4318: 
twisti@4318:   // C2 compiled method's prolog code.
twisti@4318:   void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
twisti@4318: 
kvn@4410:   // clear memory of size 'cnt' qwords, starting at 'base'.
kvn@4410:   void clear_mem(Register base, Register cnt, Register rtmp);
kvn@4410: 
twisti@4318:   // IndexOf strings.
twisti@4318:   // Small strings are loaded through stack if they cross page boundary.
twisti@4318:   void string_indexof(Register str1, Register str2,
twisti@4318:                       Register cnt1, Register cnt2,
twisti@4318:                       int int_cnt2,  Register result,
twisti@4318:                       XMMRegister vec, Register tmp);
twisti@4318: 
twisti@4318:   // IndexOf for constant substrings with size >= 8 elements
twisti@4318:   // which don't need to be loaded through stack.
twisti@4318:   void string_indexofC8(Register str1, Register str2,
twisti@4318:                       Register cnt1, Register cnt2,
twisti@4318:                       int int_cnt2,  Register result,
twisti@4318:                       XMMRegister vec, Register tmp);
twisti@4318: 
twisti@4318:     // Smallest code: we don't need to load through stack,
twisti@4318:     // check string tail.
twisti@4318: 
twisti@4318:   // Compare strings.
twisti@4318:   void string_compare(Register str1, Register str2,
twisti@4318:                       Register cnt1, Register cnt2, Register result,
twisti@4318:                       XMMRegister vec1);
twisti@4318: 
twisti@4318:   // Compare char[] arrays.
twisti@4318:   void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
twisti@4318:                           Register limit, Register result, Register chr,
twisti@4318:                           XMMRegister vec1, XMMRegister vec2);
twisti@4318: 
twisti@4318:   // Fill primitive arrays
twisti@4318:   void generate_fill(BasicType t, bool aligned,
twisti@4318:                      Register to, Register value, Register count,
twisti@4318:                      Register rtmp, XMMRegister xtmp);
twisti@4318: 
kvn@4479:   void encode_iso_array(Register src, Register dst, Register len,
kvn@4479:                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
kvn@4479:                         XMMRegister tmp4, Register tmp5, Register result);
kvn@4479: 
drchase@5353:   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
drchase@5353:   void update_byte_crc32(Register crc, Register val, Register table);
drchase@5353:   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
drchase@5353:   // Fold 128-bit data chunk
drchase@5353:   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
drchase@5353:   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
drchase@5353:   // Fold 8-bit data
drchase@5353:   void fold_8bit_crc32(Register crc, Register table, Register tmp);
drchase@5353:   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
drchase@5353: 
twisti@4318: #undef VIRTUAL
twisti@4318: 
twisti@4318: };
twisti@4318: 
twisti@4318: /**
twisti@4318:  * class SkipIfEqual:
twisti@4318:  *
twisti@4318:  * Instantiating this class will result in assembly code being output that will
twisti@4318:  * jump around any code emitted between the creation of the instance and it's
twisti@4318:  * automatic destruction at the end of a scope block, depending on the value of
twisti@4318:  * the flag passed to the constructor, which will be checked at run-time.
twisti@4318:  */
twisti@4318: class SkipIfEqual {
twisti@4318:  private:
twisti@4318:   MacroAssembler* _masm;
twisti@4318:   Label _label;
twisti@4318: 
twisti@4318:  public:
twisti@4318:    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
twisti@4318:    ~SkipIfEqual();
twisti@4318: };
twisti@4318: 
twisti@4318: #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP