aoqi@0: /* aoqi@0: * Copyright (c) 2005, 2013, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@1: /* aoqi@1: * This file has been modified by Loongson Technology in 2015. These aoqi@1: * modifications are Copyright (c) 2015 Loongson Technology, and are made aoqi@1: * available on the same license terms set forth above. aoqi@1: */ aoqi@1: aoqi@0: #include "precompiled.hpp" aoqi@0: #include "c1/c1_CFGPrinter.hpp" aoqi@0: #include "c1/c1_CodeStubs.hpp" aoqi@0: #include "c1/c1_Compilation.hpp" aoqi@0: #include "c1/c1_FrameMap.hpp" aoqi@0: #include "c1/c1_IR.hpp" aoqi@0: #include "c1/c1_LIRGenerator.hpp" aoqi@0: #include "c1/c1_LinearScan.hpp" aoqi@0: #include "c1/c1_ValueStack.hpp" aoqi@0: #include "utilities/bitMap.inline.hpp" aoqi@0: #ifdef TARGET_ARCH_x86 aoqi@0: # include "vmreg_x86.inline.hpp" aoqi@0: #endif aoqi@1: #ifdef TARGET_ARCH_mips aoqi@1: # include "vmreg_mips.inline.hpp" aoqi@1: #endif aoqi@0: #ifdef TARGET_ARCH_sparc aoqi@0: # include "vmreg_sparc.inline.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_zero aoqi@0: # include "vmreg_zero.inline.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_arm aoqi@0: # include "vmreg_arm.inline.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_ppc aoqi@0: # include "vmreg_ppc.inline.hpp" aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: aoqi@0: static LinearScanStatistic _stat_before_alloc; aoqi@0: static LinearScanStatistic _stat_after_asign; aoqi@0: static LinearScanStatistic _stat_final; aoqi@0: aoqi@0: static LinearScanTimers _total_timer; aoqi@0: aoqi@0: // helper macro for short definition of timer aoqi@0: #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); aoqi@0: aoqi@0: // helper macro for short definition of trace-output inside code aoqi@0: #define TRACE_LINEAR_SCAN(level, code) \ aoqi@0: if (TraceLinearScanLevel >= level) { \ aoqi@0: code; \ aoqi@0: } aoqi@0: aoqi@0: #else aoqi@0: aoqi@0: #define TIME_LINEAR_SCAN(timer_name) aoqi@0: #define TRACE_LINEAR_SCAN(level, code) aoqi@0: aoqi@0: #endif aoqi@0: aoqi@0: // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words aoqi@0: #ifdef _LP64 aoqi@0: static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1}; aoqi@0: #else aoqi@0: static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1}; aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: // Implementation of LinearScan aoqi@0: aoqi@0: LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) aoqi@0: : _compilation(ir->compilation()) aoqi@0: , _ir(ir) aoqi@0: , _gen(gen) aoqi@0: , _frame_map(frame_map) aoqi@0: , _num_virtual_regs(gen->max_virtual_register_number()) aoqi@0: , _has_fpu_registers(false) aoqi@0: , _num_calls(-1) aoqi@0: , _max_spills(0) aoqi@0: , _unused_spill_slot(-1) aoqi@0: , _intervals(0) // initialized later with correct length aoqi@0: , _new_intervals_from_allocation(new IntervalList()) aoqi@0: , _sorted_intervals(NULL) aoqi@0: , _needs_full_resort(false) aoqi@0: , _lir_ops(0) // initialized later with correct length aoqi@0: , _block_of_op(0) // initialized later with correct length aoqi@0: , _has_info(0) aoqi@0: , _has_call(0) aoqi@0: , _scope_value_cache(0) // initialized later with correct length aoqi@0: , _interval_in_loop(0, 0) // initialized later with correct length aoqi@0: , _cached_blocks(*ir->linear_scan_order()) aoqi@0: #ifdef X86 aoqi@0: , _fpu_stack_allocator(NULL) aoqi@0: #endif aoqi@0: { aoqi@0: assert(this->ir() != NULL, "check if valid"); aoqi@0: assert(this->compilation() != NULL, "check if valid"); aoqi@0: assert(this->gen() != NULL, "check if valid"); aoqi@0: assert(this->frame_map() != NULL, "check if valid"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** functions for converting LIR-Operands to register numbers aoqi@0: // aoqi@0: // Emulate a flat register file comprising physical integer registers, aoqi@0: // physical floating-point registers and virtual registers, in that order. aoqi@0: // Virtual registers already have appropriate numbers, since V0 is aoqi@0: // the number of physical registers. aoqi@0: // Returns -1 for hi word if opr is a single word operand. aoqi@0: // aoqi@0: // Note: the inverse operation (calculating an operand for register numbers) aoqi@0: // is done in calc_operand_for_interval() aoqi@0: aoqi@0: int LinearScan::reg_num(LIR_Opr opr) { aoqi@0: assert(opr->is_register(), "should not call this otherwise"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); aoqi@0: return opr->vreg_number(); aoqi@0: } else if (opr->is_single_cpu()) { aoqi@0: return opr->cpu_regnr(); aoqi@0: } else if (opr->is_double_cpu()) { aoqi@0: return opr->cpu_regnrLo(); aoqi@0: #ifdef X86 aoqi@0: } else if (opr->is_single_xmm()) { aoqi@0: return opr->fpu_regnr() + pd_first_xmm_reg; aoqi@0: } else if (opr->is_double_xmm()) { aoqi@0: return opr->fpu_regnrLo() + pd_first_xmm_reg; aoqi@0: #endif aoqi@0: } else if (opr->is_single_fpu()) { aoqi@0: return opr->fpu_regnr() + pd_first_fpu_reg; aoqi@0: } else if (opr->is_double_fpu()) { aoqi@0: return opr->fpu_regnrLo() + pd_first_fpu_reg; aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: return -1; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int LinearScan::reg_numHi(LIR_Opr opr) { aoqi@0: assert(opr->is_register(), "should not call this otherwise"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: return -1; aoqi@0: } else if (opr->is_single_cpu()) { aoqi@0: return -1; aoqi@0: } else if (opr->is_double_cpu()) { aoqi@0: return opr->cpu_regnrHi(); aoqi@0: #ifdef X86 aoqi@0: } else if (opr->is_single_xmm()) { aoqi@0: return -1; aoqi@0: } else if (opr->is_double_xmm()) { aoqi@0: return -1; aoqi@0: #endif aoqi@0: } else if (opr->is_single_fpu()) { aoqi@0: return -1; aoqi@0: } else if (opr->is_double_fpu()) { aoqi@0: return opr->fpu_regnrHi() + pd_first_fpu_reg; aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: return -1; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** functions for classification of intervals aoqi@0: aoqi@0: bool LinearScan::is_precolored_interval(const Interval* i) { aoqi@0: return i->reg_num() < LinearScan::nof_regs; aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_virtual_interval(const Interval* i) { aoqi@0: return i->reg_num() >= LIR_OprDesc::vreg_base; aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_precolored_cpu_interval(const Interval* i) { aoqi@0: return i->reg_num() < LinearScan::nof_cpu_regs; aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_virtual_cpu_interval(const Interval* i) { aoqi@0: #if defined(__SOFTFP__) || defined(E500V2) aoqi@0: return i->reg_num() >= LIR_OprDesc::vreg_base; aoqi@0: #else aoqi@0: return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); aoqi@0: #endif // __SOFTFP__ or E500V2 aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_precolored_fpu_interval(const Interval* i) { aoqi@0: return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_virtual_fpu_interval(const Interval* i) { aoqi@0: #if defined(__SOFTFP__) || defined(E500V2) aoqi@0: return false; aoqi@0: #else aoqi@0: return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); aoqi@0: #endif // __SOFTFP__ or E500V2 aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_in_fpu_register(const Interval* i) { aoqi@0: // fixed intervals not needed for FPU stack allocation aoqi@0: return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; aoqi@0: } aoqi@0: aoqi@0: bool LinearScan::is_oop_interval(const Interval* i) { aoqi@0: // fixed intervals never contain oops aoqi@0: return i->reg_num() >= nof_regs && i->type() == T_OBJECT; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** General helper functions aoqi@0: aoqi@0: // compute next unused stack index that can be used for spilling aoqi@0: int LinearScan::allocate_spill_slot(bool double_word) { aoqi@0: int spill_slot; aoqi@0: if (double_word) { aoqi@0: if ((_max_spills & 1) == 1) { aoqi@0: // alignment of double-word values aoqi@0: // the hole because of the alignment is filled with the next single-word value aoqi@0: assert(_unused_spill_slot == -1, "wasting a spill slot"); aoqi@0: _unused_spill_slot = _max_spills; aoqi@0: _max_spills++; aoqi@0: } aoqi@0: spill_slot = _max_spills; aoqi@0: _max_spills += 2; aoqi@0: aoqi@0: } else if (_unused_spill_slot != -1) { aoqi@0: // re-use hole that was the result of a previous double-word alignment aoqi@0: spill_slot = _unused_spill_slot; aoqi@0: _unused_spill_slot = -1; aoqi@0: aoqi@0: } else { aoqi@0: spill_slot = _max_spills; aoqi@0: _max_spills++; aoqi@0: } aoqi@0: aoqi@0: int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); aoqi@0: aoqi@0: // the class OopMapValue uses only 11 bits for storing the name of the aoqi@0: // oop location. So a stack slot bigger than 2^11 leads to an overflow aoqi@0: // that is not reported in product builds. Prevent this by checking the aoqi@0: // spill slot here (altough this value and the later used location name aoqi@0: // are slightly different) aoqi@0: if (result > 2000) { aoqi@0: bailout("too many stack slots used"); aoqi@0: } aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: void LinearScan::assign_spill_slot(Interval* it) { aoqi@0: // assign the canonical spill slot of the parent (if a part of the interval aoqi@0: // is already spilled) or allocate a new spill slot aoqi@0: if (it->canonical_spill_slot() >= 0) { aoqi@0: it->assign_reg(it->canonical_spill_slot()); aoqi@0: } else { aoqi@0: int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); aoqi@0: it->set_canonical_spill_slot(spill); aoqi@0: it->assign_reg(spill); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::propagate_spill_slots() { aoqi@0: if (!frame_map()->finalize_frame(max_spills())) { aoqi@0: bailout("frame too large"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // create a new interval with a predefined reg_num aoqi@0: // (only used for parent intervals that are created during the building phase) aoqi@0: Interval* LinearScan::create_interval(int reg_num) { aoqi@0: assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); aoqi@0: aoqi@0: Interval* interval = new Interval(reg_num); aoqi@0: _intervals.at_put(reg_num, interval); aoqi@0: aoqi@0: // assign register number for precolored intervals aoqi@0: if (reg_num < LIR_OprDesc::vreg_base) { aoqi@0: interval->assign_reg(reg_num); aoqi@0: } aoqi@0: return interval; aoqi@0: } aoqi@0: aoqi@0: // assign a new reg_num to the interval and append it to the list of intervals aoqi@0: // (only used for child intervals that are created during register allocation) aoqi@0: void LinearScan::append_interval(Interval* it) { aoqi@0: it->set_reg_num(_intervals.length()); aoqi@0: _intervals.append(it); aoqi@0: _new_intervals_from_allocation->append(it); aoqi@0: } aoqi@0: aoqi@0: // copy the vreg-flags if an interval is split aoqi@0: void LinearScan::copy_register_flags(Interval* from, Interval* to) { aoqi@0: if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { aoqi@0: gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); aoqi@0: } aoqi@0: if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { aoqi@0: gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); aoqi@0: } aoqi@0: aoqi@0: // Note: do not copy the must_start_in_memory flag because it is not necessary for child aoqi@0: // intervals (only the very beginning of the interval must be in memory) aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** spill move optimization aoqi@0: // eliminate moves from register to stack if stack slot is known to be correct aoqi@0: aoqi@0: // called during building of intervals aoqi@0: void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { aoqi@0: assert(interval->is_split_parent(), "can only be called for split parents"); aoqi@0: aoqi@0: switch (interval->spill_state()) { aoqi@0: case noDefinitionFound: aoqi@0: assert(interval->spill_definition_pos() == -1, "must no be set before"); aoqi@0: interval->set_spill_definition_pos(def_pos); aoqi@0: interval->set_spill_state(oneDefinitionFound); aoqi@0: break; aoqi@0: aoqi@0: case oneDefinitionFound: aoqi@0: assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); aoqi@0: if (def_pos < interval->spill_definition_pos() - 2) { aoqi@0: // second definition found, so no spill optimization possible for this interval aoqi@0: interval->set_spill_state(noOptimization); aoqi@0: } else { aoqi@0: // two consecutive definitions (because of two-operand LIR form) aoqi@0: assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); aoqi@0: } aoqi@0: break; aoqi@0: aoqi@0: case noOptimization: aoqi@0: // nothing to do aoqi@0: break; aoqi@0: aoqi@0: default: aoqi@0: assert(false, "other states not allowed at this time"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // called during register allocation aoqi@0: void LinearScan::change_spill_state(Interval* interval, int spill_pos) { aoqi@0: switch (interval->spill_state()) { aoqi@0: case oneDefinitionFound: { aoqi@0: int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); aoqi@0: int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); aoqi@0: aoqi@0: if (def_loop_depth < spill_loop_depth) { aoqi@0: // the loop depth of the spilling position is higher then the loop depth aoqi@0: // at the definition of the interval -> move write to memory out of loop aoqi@0: // by storing at definitin of the interval aoqi@0: interval->set_spill_state(storeAtDefinition); aoqi@0: } else { aoqi@0: // the interval is currently spilled only once, so for now there is no aoqi@0: // reason to store the interval at the definition aoqi@0: interval->set_spill_state(oneMoveInserted); aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: aoqi@0: case oneMoveInserted: { aoqi@0: // the interval is spilled more then once, so it is better to store it to aoqi@0: // memory at the definition aoqi@0: interval->set_spill_state(storeAtDefinition); aoqi@0: break; aoqi@0: } aoqi@0: aoqi@0: case storeAtDefinition: aoqi@0: case startInMemory: aoqi@0: case noOptimization: aoqi@0: case noDefinitionFound: aoqi@0: // nothing to do aoqi@0: break; aoqi@0: aoqi@0: default: aoqi@0: assert(false, "other states not allowed at this time"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: bool LinearScan::must_store_at_definition(const Interval* i) { aoqi@0: return i->is_split_parent() && i->spill_state() == storeAtDefinition; aoqi@0: } aoqi@0: aoqi@0: // called once before asignment of register numbers aoqi@0: void LinearScan::eliminate_spill_moves() { aoqi@0: TIME_LINEAR_SCAN(timer_eliminate_spill_moves); aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); aoqi@0: aoqi@0: // collect all intervals that must be stored after their definion. aoqi@0: // the list is sorted by Interval::spill_definition_pos aoqi@0: Interval* interval; aoqi@0: Interval* temp_list; aoqi@0: create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: Interval* prev = NULL; aoqi@0: Interval* temp = interval; aoqi@0: while (temp != Interval::end()) { aoqi@0: assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); aoqi@0: if (prev != NULL) { aoqi@0: assert(temp->from() >= prev->from(), "intervals not sorted"); aoqi@0: assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); aoqi@0: } aoqi@0: aoqi@0: assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); aoqi@0: assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); aoqi@0: assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); aoqi@0: aoqi@0: temp = temp->next(); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: LIR_InsertionBuffer insertion_buffer; aoqi@0: int num_blocks = block_count(); aoqi@0: for (int i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: int num_inst = instructions->length(); aoqi@0: bool has_new = false; aoqi@0: aoqi@0: // iterate all instructions of the block. skip the first because it is always a label aoqi@0: for (int j = 1; j < num_inst; j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: int op_id = op->id(); aoqi@0: aoqi@0: if (op_id == -1) { aoqi@0: // remove move from register to stack if the stack slot is guaranteed to be correct. aoqi@0: // only moves that have been inserted by LinearScan can be removed. aoqi@0: assert(op->code() == lir_move, "only moves can have a op_id of -1"); aoqi@0: assert(op->as_Op1() != NULL, "move must be LIR_Op1"); aoqi@0: assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); aoqi@0: aoqi@0: LIR_Op1* op1 = (LIR_Op1*)op; aoqi@0: Interval* interval = interval_at(op1->result_opr()->vreg_number()); aoqi@0: aoqi@0: if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { aoqi@0: // move target is a stack slot that is always correct, so eliminate instruction aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); aoqi@0: instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // insert move from register to stack just after the beginning of the interval aoqi@0: assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); aoqi@0: assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); aoqi@0: aoqi@0: while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { aoqi@0: if (!has_new) { aoqi@0: // prepare insertion buffer (appended when all instructions of the block are processed) aoqi@0: insertion_buffer.init(block->lir()); aoqi@0: has_new = true; aoqi@0: } aoqi@0: aoqi@0: LIR_Opr from_opr = operand_for_interval(interval); aoqi@0: LIR_Opr to_opr = canonical_spill_opr(interval); aoqi@0: assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); aoqi@0: assert(to_opr->is_stack(), "to operand must be a stack slot"); aoqi@0: aoqi@0: insertion_buffer.move(j, from_opr, to_opr); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); aoqi@0: aoqi@0: interval = interval->next(); aoqi@0: } aoqi@0: } aoqi@0: } // end of instruction iteration aoqi@0: aoqi@0: if (has_new) { aoqi@0: block->lir()->append(&insertion_buffer); aoqi@0: } aoqi@0: } // end of block iteration aoqi@0: aoqi@0: assert(interval == Interval::end(), "missed an interval"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 1: number all instructions in all blocks aoqi@0: // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. aoqi@0: aoqi@0: void LinearScan::number_instructions() { aoqi@0: { aoqi@0: // dummy-timer to measure the cost of the timer itself aoqi@0: // (this time is then subtracted from all other timers to get the real value) aoqi@0: TIME_LINEAR_SCAN(timer_do_nothing); aoqi@0: } aoqi@0: TIME_LINEAR_SCAN(timer_number_instructions); aoqi@0: aoqi@0: // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. aoqi@0: int num_blocks = block_count(); aoqi@0: int num_instructions = 0; aoqi@0: int i; aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: num_instructions += block_at(i)->lir()->instructions_list()->length(); aoqi@0: } aoqi@0: aoqi@0: // initialize with correct length aoqi@0: _lir_ops = LIR_OpArray(num_instructions); aoqi@0: _block_of_op = BlockBeginArray(num_instructions); aoqi@0: aoqi@0: int op_id = 0; aoqi@0: int idx = 0; aoqi@0: aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: block->set_first_lir_instruction_id(op_id); aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: int num_inst = instructions->length(); aoqi@0: for (int j = 0; j < num_inst; j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: op->set_id(op_id); aoqi@0: aoqi@0: _lir_ops.at_put(idx, op); aoqi@0: _block_of_op.at_put(idx, block); aoqi@0: assert(lir_op_with_id(op_id) == op, "must match"); aoqi@0: aoqi@0: idx++; aoqi@0: op_id += 2; // numbering of lir_ops by two aoqi@0: } aoqi@0: block->set_last_lir_instruction_id(op_id - 2); aoqi@0: } aoqi@0: assert(idx == num_instructions, "must match"); aoqi@0: assert(idx * 2 == op_id, "must match"); aoqi@0: aoqi@0: _has_call = BitMap(num_instructions); _has_call.clear(); aoqi@0: _has_info = BitMap(num_instructions); _has_info.clear(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 2: compute local live sets separately for each block aoqi@0: // (sets live_gen and live_kill for each block) aoqi@0: aoqi@0: void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { aoqi@0: LIR_Opr opr = value->operand(); aoqi@0: Constant* con = value->as_Constant(); aoqi@0: aoqi@0: // check some asumptions about debug information aoqi@0: assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); aoqi@0: assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); aoqi@0: assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); aoqi@0: aoqi@0: if ((con == NULL || con->is_pinned()) && opr->is_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: int reg = opr->vreg_number(); aoqi@0: if (!live_kill.at(reg)) { aoqi@0: live_gen.set_bit(reg); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::compute_local_live_sets() { aoqi@0: TIME_LINEAR_SCAN(timer_compute_local_live_sets); aoqi@0: aoqi@0: int num_blocks = block_count(); aoqi@0: int live_size = live_set_size(); aoqi@0: bool local_has_fpu_registers = false; aoqi@0: int local_num_calls = 0; aoqi@0: LIR_OpVisitState visitor; aoqi@0: aoqi@0: BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); aoqi@0: local_interval_in_loop.clear(); aoqi@0: aoqi@0: // iterate all blocks aoqi@0: for (int i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: aoqi@0: BitMap live_gen(live_size); live_gen.clear(); aoqi@0: BitMap live_kill(live_size); live_kill.clear(); aoqi@0: aoqi@0: if (block->is_set(BlockBegin::exception_entry_flag)) { aoqi@0: // Phi functions at the begin of an exception handler are aoqi@0: // implicitly defined (= killed) at the beginning of the block. aoqi@0: for_each_phi_fun(block, phi, aoqi@0: live_kill.set_bit(phi->operand()->vreg_number()) aoqi@0: ); aoqi@0: } aoqi@0: aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: int num_inst = instructions->length(); aoqi@0: aoqi@0: // iterate all instructions of the block. skip the first because it is always a label aoqi@0: assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); aoqi@0: for (int j = 1; j < num_inst; j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: aoqi@0: // visit operation to collect all operands aoqi@0: visitor.visit(op); aoqi@0: aoqi@0: if (visitor.has_call()) { aoqi@0: _has_call.set_bit(op->id() >> 1); aoqi@0: local_num_calls++; aoqi@0: } aoqi@0: if (visitor.info_count() > 0) { aoqi@0: _has_info.set_bit(op->id() >> 1); aoqi@0: } aoqi@0: aoqi@0: // iterate input operands of instruction aoqi@0: int k, n, reg; aoqi@0: n = visitor.opr_count(LIR_OpVisitState::inputMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: reg = opr->vreg_number(); aoqi@0: if (!live_kill.at(reg)) { aoqi@0: live_gen.set_bit(reg); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); aoqi@0: } aoqi@0: if (block->loop_index() >= 0) { aoqi@0: local_interval_in_loop.set_bit(reg, block->loop_index()); aoqi@0: } aoqi@0: local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // fixed intervals are never live at block boundaries, so aoqi@0: // they need not be processed in live sets. aoqi@0: // this is checked by these assertions to be sure about it. aoqi@0: // the entry block may have incoming values in registers, which is ok. aoqi@0: if (!opr->is_virtual_register() && block != ir()->start()) { aoqi@0: reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: assert(live_kill.at(reg), "using fixed register that is not defined in this block"); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: assert(live_kill.at(reg), "using fixed register that is not defined in this block"); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: // Add uses of live locals from interpreter's point of view for proper debug information generation aoqi@0: n = visitor.info_count(); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: CodeEmitInfo* info = visitor.info_at(k); aoqi@0: ValueStack* stack = info->stack(); aoqi@0: for_each_state_value(stack, value, aoqi@0: set_live_gen_kill(value, op, live_gen, live_kill) aoqi@0: ); aoqi@0: } aoqi@0: aoqi@0: // iterate temp operands of instruction aoqi@0: n = visitor.opr_count(LIR_OpVisitState::tempMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: reg = opr->vreg_number(); aoqi@0: live_kill.set_bit(reg); aoqi@0: if (block->loop_index() >= 0) { aoqi@0: local_interval_in_loop.set_bit(reg, block->loop_index()); aoqi@0: } aoqi@0: local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // fixed intervals are never live at block boundaries, so aoqi@0: // they need not be processed in live sets aoqi@0: // process them only in debug mode so that this can be checked aoqi@0: if (!opr->is_virtual_register()) { aoqi@0: reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: live_kill.set_bit(reg_num(opr)); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: live_kill.set_bit(reg); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: // iterate output operands of instruction aoqi@0: n = visitor.opr_count(LIR_OpVisitState::outputMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: reg = opr->vreg_number(); aoqi@0: live_kill.set_bit(reg); aoqi@0: if (block->loop_index() >= 0) { aoqi@0: local_interval_in_loop.set_bit(reg, block->loop_index()); aoqi@0: } aoqi@0: local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // fixed intervals are never live at block boundaries, so aoqi@0: // they need not be processed in live sets aoqi@0: // process them only in debug mode so that this can be checked aoqi@0: if (!opr->is_virtual_register()) { aoqi@0: reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: live_kill.set_bit(reg_num(opr)); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: live_kill.set_bit(reg); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: } // end of instruction iteration aoqi@0: aoqi@0: block->set_live_gen (live_gen); aoqi@0: block->set_live_kill(live_kill); aoqi@0: block->set_live_in (BitMap(live_size)); block->live_in().clear(); aoqi@0: block->set_live_out (BitMap(live_size)); block->live_out().clear(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); aoqi@0: } // end of block iteration aoqi@0: aoqi@0: // propagate local calculated information into LinearScan object aoqi@0: _has_fpu_registers = local_has_fpu_registers; aoqi@0: compilation()->set_has_fpu_code(local_has_fpu_registers); aoqi@0: aoqi@0: _num_calls = local_num_calls; aoqi@0: _interval_in_loop = local_interval_in_loop; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 3: perform a backward dataflow analysis to compute global live sets aoqi@0: // (sets live_in and live_out for each block) aoqi@0: aoqi@0: void LinearScan::compute_global_live_sets() { aoqi@0: TIME_LINEAR_SCAN(timer_compute_global_live_sets); aoqi@0: aoqi@0: int num_blocks = block_count(); aoqi@0: bool change_occurred; aoqi@0: bool change_occurred_in_block; aoqi@0: int iteration_count = 0; aoqi@0: BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations aoqi@0: aoqi@0: // Perform a backward dataflow analysis to compute live_out and live_in for each block. aoqi@0: // The loop is executed until a fixpoint is reached (no changes in an iteration) aoqi@0: // Exception handlers must be processed because not all live values are aoqi@0: // present in the state array, e.g. because of global value numbering aoqi@0: do { aoqi@0: change_occurred = false; aoqi@0: aoqi@0: // iterate all blocks in reverse order aoqi@0: for (int i = num_blocks - 1; i >= 0; i--) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: aoqi@0: change_occurred_in_block = false; aoqi@0: aoqi@0: // live_out(block) is the union of live_in(sux), for successors sux of block aoqi@0: int n = block->number_of_sux(); aoqi@0: int e = block->number_of_exception_handlers(); aoqi@0: if (n + e > 0) { aoqi@0: // block has successors aoqi@0: if (n > 0) { aoqi@0: live_out.set_from(block->sux_at(0)->live_in()); aoqi@0: for (int j = 1; j < n; j++) { aoqi@0: live_out.set_union(block->sux_at(j)->live_in()); aoqi@0: } aoqi@0: } else { aoqi@0: live_out.clear(); aoqi@0: } aoqi@0: for (int j = 0; j < e; j++) { aoqi@0: live_out.set_union(block->exception_handler_at(j)->live_in()); aoqi@0: } aoqi@0: aoqi@0: if (!block->live_out().is_same(live_out)) { aoqi@0: // A change occurred. Swap the old and new live out sets to avoid copying. aoqi@0: BitMap temp = block->live_out(); aoqi@0: block->set_live_out(live_out); aoqi@0: live_out = temp; aoqi@0: aoqi@0: change_occurred = true; aoqi@0: change_occurred_in_block = true; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (iteration_count == 0 || change_occurred_in_block) { aoqi@0: // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) aoqi@0: // note: live_in has to be computed only in first iteration or if live_out has changed! aoqi@0: BitMap live_in = block->live_in(); aoqi@0: live_in.set_from(block->live_out()); aoqi@0: live_in.set_difference(block->live_kill()); aoqi@0: live_in.set_union(block->live_gen()); aoqi@0: } aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: if (TraceLinearScanLevel >= 4) { aoqi@0: char c = ' '; aoqi@0: if (iteration_count == 0 || change_occurred_in_block) { aoqi@0: c = '*'; aoqi@0: } aoqi@0: tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); aoqi@0: tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: iteration_count++; aoqi@0: aoqi@0: if (change_occurred && iteration_count > 50) { aoqi@0: BAILOUT("too many iterations in compute_global_live_sets"); aoqi@0: } aoqi@0: } while (change_occurred); aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // check that fixed intervals are not live at block boundaries aoqi@0: // (live set must be empty at fixed intervals) aoqi@0: for (int i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { aoqi@0: assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); aoqi@0: assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); aoqi@0: assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // check that the live_in set of the first block is empty aoqi@0: BitMap live_in_args(ir()->start()->live_in().size()); aoqi@0: live_in_args.clear(); aoqi@0: if (!ir()->start()->live_in().is_same(live_in_args)) { aoqi@0: #ifdef ASSERT aoqi@0: tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); aoqi@0: tty->print_cr("affected registers:"); aoqi@0: print_bitmap(ir()->start()->live_in()); aoqi@0: aoqi@0: // print some additional information to simplify debugging aoqi@0: for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { aoqi@0: if (ir()->start()->live_in().at(i)) { aoqi@0: Instruction* instr = gen()->instruction_for_vreg(i); aoqi@0: tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); aoqi@0: aoqi@0: for (int j = 0; j < num_blocks; j++) { aoqi@0: BlockBegin* block = block_at(j); aoqi@0: if (block->live_gen().at(i)) { aoqi@0: tty->print_cr(" used in block B%d", block->block_id()); aoqi@0: } aoqi@0: if (block->live_kill().at(i)) { aoqi@0: tty->print_cr(" defined in block B%d", block->block_id()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #endif aoqi@0: // when this fails, virtual registers are used before they are defined. aoqi@0: assert(false, "live_in set of first block must be empty"); aoqi@0: // bailout of if this occurs in product mode. aoqi@0: bailout("live_in set of first block not empty"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 4: build intervals aoqi@0: // (fills the list _intervals) aoqi@0: aoqi@0: void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { aoqi@0: assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); aoqi@0: LIR_Opr opr = value->operand(); aoqi@0: Constant* con = value->as_Constant(); aoqi@0: aoqi@0: if ((con == NULL || con->is_pinned()) && opr->is_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: add_use(opr, from, to, use_kind); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); aoqi@0: assert(opr->is_register(), "should not be called otherwise"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); aoqi@0: aoqi@0: } else { aoqi@0: int reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: add_def(reg, def_pos, use_kind, opr->type_register()); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: add_def(reg, def_pos, use_kind, opr->type_register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); aoqi@0: assert(opr->is_register(), "should not be called otherwise"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); aoqi@0: aoqi@0: } else { aoqi@0: int reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: add_use(reg, from, to, use_kind, opr->type_register()); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: add_use(reg, from, to, use_kind, opr->type_register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); aoqi@0: assert(opr->is_register(), "should not be called otherwise"); aoqi@0: aoqi@0: if (opr->is_virtual_register()) { aoqi@0: assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); aoqi@0: add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); aoqi@0: aoqi@0: } else { aoqi@0: int reg = reg_num(opr); aoqi@0: if (is_processed_reg_num(reg)) { aoqi@0: add_temp(reg, temp_pos, use_kind, opr->type_register()); aoqi@0: } aoqi@0: reg = reg_numHi(opr); aoqi@0: if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { aoqi@0: add_temp(reg, temp_pos, use_kind, opr->type_register()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { aoqi@0: Interval* interval = interval_at(reg_num); aoqi@0: if (interval != NULL) { aoqi@0: assert(interval->reg_num() == reg_num, "wrong interval"); aoqi@0: aoqi@0: if (type != T_ILLEGAL) { aoqi@0: interval->set_type(type); aoqi@0: } aoqi@0: aoqi@0: Range* r = interval->first(); aoqi@0: if (r->from() <= def_pos) { aoqi@0: // Update the starting point (when a range is first created for a use, its aoqi@0: // start is the beginning of the current block until a def is encountered.) aoqi@0: r->set_from(def_pos); aoqi@0: interval->add_use_pos(def_pos, use_kind); aoqi@0: aoqi@0: } else { aoqi@0: // Dead value - make vacuous interval aoqi@0: // also add use_kind for dead intervals aoqi@0: interval->add_range(def_pos, def_pos + 1); aoqi@0: interval->add_use_pos(def_pos, use_kind); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // Dead value - make vacuous interval aoqi@0: // also add use_kind for dead intervals aoqi@0: interval = create_interval(reg_num); aoqi@0: if (type != T_ILLEGAL) { aoqi@0: interval->set_type(type); aoqi@0: } aoqi@0: aoqi@0: interval->add_range(def_pos, def_pos + 1); aoqi@0: interval->add_use_pos(def_pos, use_kind); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); aoqi@0: } aoqi@0: aoqi@0: change_spill_definition_pos(interval, def_pos); aoqi@0: if (use_kind == noUse && interval->spill_state() <= startInMemory) { aoqi@0: // detection of method-parameters and roundfp-results aoqi@0: // TODO: move this directly to position where use-kind is computed aoqi@0: interval->set_spill_state(startInMemory); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { aoqi@0: Interval* interval = interval_at(reg_num); aoqi@0: if (interval == NULL) { aoqi@0: interval = create_interval(reg_num); aoqi@0: } aoqi@0: assert(interval->reg_num() == reg_num, "wrong interval"); aoqi@0: aoqi@0: if (type != T_ILLEGAL) { aoqi@0: interval->set_type(type); aoqi@0: } aoqi@0: aoqi@0: interval->add_range(from, to); aoqi@0: interval->add_use_pos(to, use_kind); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { aoqi@0: Interval* interval = interval_at(reg_num); aoqi@0: if (interval == NULL) { aoqi@0: interval = create_interval(reg_num); aoqi@0: } aoqi@0: assert(interval->reg_num() == reg_num, "wrong interval"); aoqi@0: aoqi@0: if (type != T_ILLEGAL) { aoqi@0: interval->set_type(type); aoqi@0: } aoqi@0: aoqi@0: interval->add_range(temp_pos, temp_pos + 1); aoqi@0: interval->add_use_pos(temp_pos, use_kind); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // the results of this functions are used for optimizing spilling and reloading aoqi@0: // if the functions return shouldHaveRegister and the interval is spilled, aoqi@0: // it is not reloaded to a register. aoqi@0: IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { aoqi@0: if (op->code() == lir_move) { aoqi@0: assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: LIR_Opr res = move->result_opr(); aoqi@0: bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); aoqi@0: aoqi@0: if (result_in_memory) { aoqi@0: // Begin of an interval with must_start_in_memory set. aoqi@0: // This interval will always get a stack slot first, so return noUse. aoqi@0: return noUse; aoqi@0: aoqi@0: } else if (move->in_opr()->is_stack()) { aoqi@0: // method argument (condition must be equal to handle_method_arguments) aoqi@0: return noUse; aoqi@0: aoqi@0: } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { aoqi@0: // Move from register to register aoqi@0: if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { aoqi@0: // special handling of phi-function moves inside osr-entry blocks aoqi@0: // input operand must have a register instead of output operand (leads to better register allocation) aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (opr->is_virtual() && aoqi@0: gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { aoqi@0: // result is a stack-slot, so prevent immediate reloading aoqi@0: return noUse; aoqi@0: } aoqi@0: aoqi@0: // all other operands require a register aoqi@0: return mustHaveRegister; aoqi@0: } aoqi@0: aoqi@0: IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { aoqi@0: if (op->code() == lir_move) { aoqi@0: assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: LIR_Opr res = move->result_opr(); aoqi@0: bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); aoqi@0: aoqi@0: if (result_in_memory) { aoqi@0: // Move to an interval with must_start_in_memory set. aoqi@0: // To avoid moves from stack to stack (not allowed) force the input operand to a register aoqi@0: return mustHaveRegister; aoqi@0: aoqi@0: } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { aoqi@0: // Move from register to register aoqi@0: if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { aoqi@0: // special handling of phi-function moves inside osr-entry blocks aoqi@0: // input operand must have a register instead of output operand (leads to better register allocation) aoqi@0: return mustHaveRegister; aoqi@0: } aoqi@0: aoqi@0: // The input operand is not forced to a register (moves from stack to register are allowed), aoqi@0: // but it is faster if the input operand is in a register aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef X86 aoqi@0: if (op->code() == lir_cmove) { aoqi@0: // conditional moves can handle stack operands aoqi@0: assert(op->result_opr()->is_register(), "result must always be in a register"); aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: aoqi@0: // optimizations for second input operand of arithmehtic operations on Intel aoqi@0: // this operand is allowed to be on the stack in some cases aoqi@0: BasicType opr_type = opr->type_register(); aoqi@0: if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { aoqi@0: if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) { aoqi@0: // SSE float instruction (T_DOUBLE only supported with SSE2) aoqi@0: switch (op->code()) { aoqi@0: case lir_cmp: aoqi@0: case lir_add: aoqi@0: case lir_sub: aoqi@0: case lir_mul: aoqi@0: case lir_div: aoqi@0: { aoqi@0: assert(op->as_Op2() != NULL, "must be LIR_Op2"); aoqi@0: LIR_Op2* op2 = (LIR_Op2*)op; aoqi@0: if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { aoqi@0: assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } else { aoqi@0: // FPU stack float instruction aoqi@0: switch (op->code()) { aoqi@0: case lir_add: aoqi@0: case lir_sub: aoqi@0: case lir_mul: aoqi@0: case lir_div: aoqi@0: { aoqi@0: assert(op->as_Op2() != NULL, "must be LIR_Op2"); aoqi@0: LIR_Op2* op2 = (LIR_Op2*)op; aoqi@0: if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { aoqi@0: assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: // We want to sometimes use logical operations on pointers, in particular in GC barriers. aoqi@0: // Since 64bit logical operations do not current support operands on stack, we have to make sure aoqi@0: // T_OBJECT doesn't get spilled along with T_LONG. aoqi@0: } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) { aoqi@0: // integer instruction (note: long operands must always be in register) aoqi@0: switch (op->code()) { aoqi@0: case lir_cmp: aoqi@0: case lir_add: aoqi@0: case lir_sub: aoqi@0: case lir_logic_and: aoqi@0: case lir_logic_or: aoqi@0: case lir_logic_xor: aoqi@0: { aoqi@0: assert(op->as_Op2() != NULL, "must be LIR_Op2"); aoqi@0: LIR_Op2* op2 = (LIR_Op2*)op; aoqi@0: if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { aoqi@0: assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); aoqi@0: return shouldHaveRegister; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: #endif // X86 aoqi@0: aoqi@0: // all other operands require a register aoqi@0: return mustHaveRegister; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::handle_method_arguments(LIR_Op* op) { aoqi@0: // special handling for method arguments (moves from stack to virtual register): aoqi@0: // the interval gets no register assigned, but the stack slot. aoqi@0: // it is split before the first use by the register allocator. aoqi@0: aoqi@0: if (op->code() == lir_move) { aoqi@0: assert(op->as_Op1() != NULL, "must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: aoqi@0: if (move->in_opr()->is_stack()) { aoqi@0: #ifdef ASSERT aoqi@0: int arg_size = compilation()->method()->arg_size(); aoqi@0: LIR_Opr o = move->in_opr(); aoqi@0: if (o->is_single_stack()) { aoqi@0: assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); aoqi@0: } else if (o->is_double_stack()) { aoqi@0: assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: aoqi@0: assert(move->id() > 0, "invalid id"); aoqi@0: assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); aoqi@0: assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); aoqi@0: #endif aoqi@0: aoqi@0: Interval* interval = interval_at(reg_num(move->result_opr())); aoqi@0: aoqi@0: int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); aoqi@0: interval->set_canonical_spill_slot(stack_slot); aoqi@0: interval->assign_reg(stack_slot); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::handle_doubleword_moves(LIR_Op* op) { aoqi@0: // special handling for doubleword move from memory to register: aoqi@0: // in this case the registers of the input address and the result aoqi@0: // registers must not overlap -> add a temp range for the input registers aoqi@0: if (op->code() == lir_move) { aoqi@0: assert(op->as_Op1() != NULL, "must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: aoqi@0: if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { aoqi@0: LIR_Address* address = move->in_opr()->as_address_ptr(); aoqi@0: if (address != NULL) { aoqi@0: if (address->base()->is_valid()) { aoqi@0: add_temp(address->base(), op->id(), noUse); aoqi@0: } aoqi@0: if (address->index()->is_valid()) { aoqi@0: add_temp(address->index(), op->id(), noUse); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::add_register_hints(LIR_Op* op) { aoqi@0: switch (op->code()) { aoqi@0: case lir_move: // fall through aoqi@0: case lir_convert: { aoqi@0: assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: aoqi@0: LIR_Opr move_from = move->in_opr(); aoqi@0: LIR_Opr move_to = move->result_opr(); aoqi@0: aoqi@0: if (move_to->is_register() && move_from->is_register()) { aoqi@0: Interval* from = interval_at(reg_num(move_from)); aoqi@0: Interval* to = interval_at(reg_num(move_to)); aoqi@0: if (from != NULL && to != NULL) { aoqi@0: to->set_register_hint(from); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); aoqi@0: } aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: case lir_cmove: { aoqi@0: assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); aoqi@0: LIR_Op2* cmove = (LIR_Op2*)op; aoqi@0: aoqi@0: LIR_Opr move_from = cmove->in_opr1(); aoqi@0: LIR_Opr move_to = cmove->result_opr(); aoqi@0: aoqi@0: if (move_to->is_register() && move_from->is_register()) { aoqi@0: Interval* from = interval_at(reg_num(move_from)); aoqi@0: Interval* to = interval_at(reg_num(move_to)); aoqi@0: if (from != NULL && to != NULL) { aoqi@0: to->set_register_hint(from); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); aoqi@0: } aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::build_intervals() { aoqi@0: TIME_LINEAR_SCAN(timer_build_intervals); aoqi@0: aoqi@0: // initialize interval list with expected number of intervals aoqi@0: // (32 is added to have some space for split children without having to resize the list) aoqi@0: _intervals = IntervalList(num_virtual_regs() + 32); aoqi@0: // initialize all slots that are used by build_intervals aoqi@0: _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); aoqi@0: aoqi@0: // create a list with all caller-save registers (cpu, fpu, xmm) aoqi@0: // when an instruction is a call, a temp range is created for all these registers aoqi@0: int num_caller_save_registers = 0; aoqi@0: int caller_save_registers[LinearScan::nof_regs]; aoqi@0: aoqi@0: int i; aoqi@0: for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) { aoqi@0: LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); aoqi@0: assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); aoqi@0: assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); aoqi@0: caller_save_registers[num_caller_save_registers++] = reg_num(opr); aoqi@0: } aoqi@0: aoqi@0: // temp ranges for fpu registers are only created when the method has aoqi@0: // virtual fpu operands. Otherwise no allocation for fpu registers is aoqi@0: // perfomed and so the temp ranges would be useless aoqi@0: if (has_fpu_registers()) { aoqi@0: #ifdef X86 aoqi@0: if (UseSSE < 2) { aoqi@0: #endif aoqi@0: for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { aoqi@0: LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); aoqi@0: assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); aoqi@0: assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); aoqi@0: caller_save_registers[num_caller_save_registers++] = reg_num(opr); aoqi@0: } aoqi@0: #ifdef X86 aoqi@0: } aoqi@0: if (UseSSE > 0) { aoqi@0: for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) { aoqi@0: LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); aoqi@0: assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); aoqi@0: assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); aoqi@0: caller_save_registers[num_caller_save_registers++] = reg_num(opr); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); aoqi@0: aoqi@0: aoqi@0: LIR_OpVisitState visitor; aoqi@0: aoqi@0: // iterate all blocks in reverse order aoqi@0: for (i = block_count() - 1; i >= 0; i--) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: int block_from = block->first_lir_instruction_id(); aoqi@0: int block_to = block->last_lir_instruction_id(); aoqi@0: aoqi@0: assert(block_from == instructions->at(0)->id(), "must be"); aoqi@0: assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); aoqi@0: aoqi@0: // Update intervals for registers live at the end of this block; aoqi@0: BitMap live = block->live_out(); aoqi@0: int size = (int)live.size(); aoqi@0: for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { aoqi@0: assert(live.at(number), "should not stop here otherwise"); aoqi@0: assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); aoqi@0: aoqi@0: add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); aoqi@0: aoqi@0: // add special use positions for loop-end blocks when the aoqi@0: // interval is used anywhere inside this loop. It's possible aoqi@0: // that the block was part of a non-natural loop, so it might aoqi@0: // have an invalid loop index. aoqi@0: if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && aoqi@0: block->loop_index() != -1 && aoqi@0: is_interval_in_loop(number, block->loop_index())) { aoqi@0: interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // iterate all instructions of the block in reverse order. aoqi@0: // skip the first instruction because it is always a label aoqi@0: // definitions of intervals are processed before uses aoqi@0: assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); aoqi@0: for (int j = instructions->length() - 1; j >= 1; j--) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: int op_id = op->id(); aoqi@0: aoqi@0: // visit operation to collect all operands aoqi@0: visitor.visit(op); aoqi@0: aoqi@0: // add a temp range for each register if operation destroys caller-save registers aoqi@0: if (visitor.has_call()) { aoqi@0: for (int k = 0; k < num_caller_save_registers; k++) { aoqi@0: add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); aoqi@0: } aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); aoqi@0: } aoqi@0: aoqi@0: // Add any platform dependent temps aoqi@0: pd_add_temps(op); aoqi@0: aoqi@0: // visit definitions (output and temp operands) aoqi@0: int k, n; aoqi@0: n = visitor.opr_count(LIR_OpVisitState::outputMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: add_def(opr, op_id, use_kind_of_output_operand(op, opr)); aoqi@0: } aoqi@0: aoqi@0: n = visitor.opr_count(LIR_OpVisitState::tempMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: add_temp(opr, op_id, mustHaveRegister); aoqi@0: } aoqi@0: aoqi@0: // visit uses (input operands) aoqi@0: n = visitor.opr_count(LIR_OpVisitState::inputMode); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); aoqi@0: assert(opr->is_register(), "visitor should only return register operands"); aoqi@0: add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); aoqi@0: } aoqi@0: aoqi@0: // Add uses of live locals from interpreter's point of view for proper aoqi@0: // debug information generation aoqi@0: // Treat these operands as temp values (if the life range is extended aoqi@0: // to a call site, the value would be in a register at the call otherwise) aoqi@0: n = visitor.info_count(); aoqi@0: for (k = 0; k < n; k++) { aoqi@0: CodeEmitInfo* info = visitor.info_at(k); aoqi@0: ValueStack* stack = info->stack(); aoqi@0: for_each_state_value(stack, value, aoqi@0: add_use(value, block_from, op_id + 1, noUse); aoqi@0: ); aoqi@0: } aoqi@0: aoqi@0: // special steps for some instructions (especially moves) aoqi@0: handle_method_arguments(op); aoqi@0: handle_doubleword_moves(op); aoqi@0: add_register_hints(op); aoqi@0: aoqi@0: } // end of instruction iteration aoqi@0: } // end of block iteration aoqi@0: aoqi@0: aoqi@0: // add the range [0, 1[ to all fixed intervals aoqi@0: // -> the register allocator need not handle unhandled fixed intervals aoqi@0: for (int n = 0; n < LinearScan::nof_regs; n++) { aoqi@0: Interval* interval = interval_at(n); aoqi@0: if (interval != NULL) { aoqi@0: interval->add_range(0, 1); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 5: actual register allocation aoqi@0: aoqi@0: int LinearScan::interval_cmp(Interval** a, Interval** b) { aoqi@0: if (*a != NULL) { aoqi@0: if (*b != NULL) { aoqi@0: return (*a)->from() - (*b)->from(); aoqi@0: } else { aoqi@0: return -1; aoqi@0: } aoqi@0: } else { aoqi@0: if (*b != NULL) { aoqi@0: return 1; aoqi@0: } else { aoqi@0: return 0; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: bool LinearScan::is_sorted(IntervalArray* intervals) { aoqi@0: int from = -1; aoqi@0: int i, j; aoqi@0: for (i = 0; i < intervals->length(); i ++) { aoqi@0: Interval* it = intervals->at(i); aoqi@0: if (it != NULL) { aoqi@0: if (from > it->from()) { aoqi@0: assert(false, ""); aoqi@0: return false; aoqi@0: } aoqi@0: from = it->from(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // check in both directions if sorted list and unsorted list contain same intervals aoqi@0: for (i = 0; i < interval_count(); i++) { aoqi@0: if (interval_at(i) != NULL) { aoqi@0: int num_found = 0; aoqi@0: for (j = 0; j < intervals->length(); j++) { aoqi@0: if (interval_at(i) == intervals->at(j)) { aoqi@0: num_found++; aoqi@0: } aoqi@0: } aoqi@0: assert(num_found == 1, "lists do not contain same intervals"); aoqi@0: } aoqi@0: } aoqi@0: for (j = 0; j < intervals->length(); j++) { aoqi@0: int num_found = 0; aoqi@0: for (i = 0; i < interval_count(); i++) { aoqi@0: if (interval_at(i) == intervals->at(j)) { aoqi@0: num_found++; aoqi@0: } aoqi@0: } aoqi@0: assert(num_found == 1, "lists do not contain same intervals"); aoqi@0: } aoqi@0: aoqi@0: return true; aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { aoqi@0: if (*prev != NULL) { aoqi@0: (*prev)->set_next(interval); aoqi@0: } else { aoqi@0: *first = interval; aoqi@0: } aoqi@0: *prev = interval; aoqi@0: } aoqi@0: aoqi@0: void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { aoqi@0: assert(is_sorted(_sorted_intervals), "interval list is not sorted"); aoqi@0: aoqi@0: *list1 = *list2 = Interval::end(); aoqi@0: aoqi@0: Interval* list1_prev = NULL; aoqi@0: Interval* list2_prev = NULL; aoqi@0: Interval* v; aoqi@0: aoqi@0: const int n = _sorted_intervals->length(); aoqi@0: for (int i = 0; i < n; i++) { aoqi@0: v = _sorted_intervals->at(i); aoqi@0: if (v == NULL) continue; aoqi@0: aoqi@0: if (is_list1(v)) { aoqi@0: add_to_list(list1, &list1_prev, v); aoqi@0: } else if (is_list2 == NULL || is_list2(v)) { aoqi@0: add_to_list(list2, &list2_prev, v); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (list1_prev != NULL) list1_prev->set_next(Interval::end()); aoqi@0: if (list2_prev != NULL) list2_prev->set_next(Interval::end()); aoqi@0: aoqi@0: assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); aoqi@0: assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::sort_intervals_before_allocation() { aoqi@0: TIME_LINEAR_SCAN(timer_sort_intervals_before); aoqi@0: aoqi@0: if (_needs_full_resort) { aoqi@0: // There is no known reason why this should occur but just in case... aoqi@0: assert(false, "should never occur"); aoqi@0: // Re-sort existing interval list because an Interval::from() has changed aoqi@0: _sorted_intervals->sort(interval_cmp); aoqi@0: _needs_full_resort = false; aoqi@0: } aoqi@0: aoqi@0: IntervalList* unsorted_list = &_intervals; aoqi@0: int unsorted_len = unsorted_list->length(); aoqi@0: int sorted_len = 0; aoqi@0: int unsorted_idx; aoqi@0: int sorted_idx = 0; aoqi@0: int sorted_from_max = -1; aoqi@0: aoqi@0: // calc number of items for sorted list (sorted list must not contain NULL values) aoqi@0: for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { aoqi@0: if (unsorted_list->at(unsorted_idx) != NULL) { aoqi@0: sorted_len++; aoqi@0: } aoqi@0: } aoqi@0: IntervalArray* sorted_list = new IntervalArray(sorted_len); aoqi@0: aoqi@0: // special sorting algorithm: the original interval-list is almost sorted, aoqi@0: // only some intervals are swapped. So this is much faster than a complete QuickSort aoqi@0: for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { aoqi@0: Interval* cur_interval = unsorted_list->at(unsorted_idx); aoqi@0: aoqi@0: if (cur_interval != NULL) { aoqi@0: int cur_from = cur_interval->from(); aoqi@0: aoqi@0: if (sorted_from_max <= cur_from) { aoqi@0: sorted_list->at_put(sorted_idx++, cur_interval); aoqi@0: sorted_from_max = cur_interval->from(); aoqi@0: } else { aoqi@0: // the asumption that the intervals are already sorted failed, aoqi@0: // so this interval must be sorted in manually aoqi@0: int j; aoqi@0: for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { aoqi@0: sorted_list->at_put(j + 1, sorted_list->at(j)); aoqi@0: } aoqi@0: sorted_list->at_put(j + 1, cur_interval); aoqi@0: sorted_idx++; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: _sorted_intervals = sorted_list; aoqi@0: assert(is_sorted(_sorted_intervals), "intervals unsorted"); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::sort_intervals_after_allocation() { aoqi@0: TIME_LINEAR_SCAN(timer_sort_intervals_after); aoqi@0: aoqi@0: if (_needs_full_resort) { aoqi@0: // Re-sort existing interval list because an Interval::from() has changed aoqi@0: _sorted_intervals->sort(interval_cmp); aoqi@0: _needs_full_resort = false; aoqi@0: } aoqi@0: aoqi@0: IntervalArray* old_list = _sorted_intervals; aoqi@0: IntervalList* new_list = _new_intervals_from_allocation; aoqi@0: int old_len = old_list->length(); aoqi@0: int new_len = new_list->length(); aoqi@0: aoqi@0: if (new_len == 0) { aoqi@0: // no intervals have been added during allocation, so sorted list is already up to date aoqi@0: assert(is_sorted(_sorted_intervals), "intervals unsorted"); aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: // conventional sort-algorithm for new intervals aoqi@0: new_list->sort(interval_cmp); aoqi@0: aoqi@0: // merge old and new list (both already sorted) into one combined list aoqi@0: IntervalArray* combined_list = new IntervalArray(old_len + new_len); aoqi@0: int old_idx = 0; aoqi@0: int new_idx = 0; aoqi@0: aoqi@0: while (old_idx + new_idx < old_len + new_len) { aoqi@0: if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { aoqi@0: combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); aoqi@0: old_idx++; aoqi@0: } else { aoqi@0: combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); aoqi@0: new_idx++; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: _sorted_intervals = combined_list; aoqi@0: assert(is_sorted(_sorted_intervals), "intervals unsorted"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::allocate_registers() { aoqi@0: TIME_LINEAR_SCAN(timer_allocate_registers); aoqi@0: aoqi@0: Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; aoqi@0: Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; aoqi@0: aoqi@0: create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval); aoqi@0: if (has_fpu_registers()) { aoqi@0: create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); aoqi@0: #ifdef ASSERT aoqi@0: } else { aoqi@0: // fpu register allocation is omitted because no virtual fpu registers are present aoqi@0: // just check this again... aoqi@0: create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); aoqi@0: assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval"); aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: // allocate cpu registers aoqi@0: LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); aoqi@0: cpu_lsw.walk(); aoqi@0: cpu_lsw.finish_allocation(); aoqi@0: aoqi@0: if (has_fpu_registers()) { aoqi@0: // allocate fpu registers aoqi@0: LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); aoqi@0: fpu_lsw.walk(); aoqi@0: fpu_lsw.finish_allocation(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 6: resolve data flow aoqi@0: // (insert moves at edges between blocks if intervals have been split) aoqi@0: aoqi@0: // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode aoqi@0: // instead of returning NULL aoqi@0: Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { aoqi@0: Interval* result = interval->split_child_at_op_id(op_id, mode); aoqi@0: if (result != NULL) { aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: assert(false, "must find an interval, but do a clean bailout in product mode"); aoqi@0: result = new Interval(LIR_OprDesc::vreg_base); aoqi@0: result->assign_reg(0); aoqi@0: result->set_type(T_INT); aoqi@0: BAILOUT_("LinearScan: interval is NULL", result); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { aoqi@0: assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); aoqi@0: assert(interval_at(reg_num) != NULL, "no interval found"); aoqi@0: aoqi@0: return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); aoqi@0: } aoqi@0: aoqi@0: Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { aoqi@0: assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); aoqi@0: assert(interval_at(reg_num) != NULL, "no interval found"); aoqi@0: aoqi@0: return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); aoqi@0: } aoqi@0: aoqi@0: Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { aoqi@0: assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); aoqi@0: assert(interval_at(reg_num) != NULL, "no interval found"); aoqi@0: aoqi@0: return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { aoqi@0: DEBUG_ONLY(move_resolver.check_empty()); aoqi@0: aoqi@0: const int num_regs = num_virtual_regs(); aoqi@0: const int size = live_set_size(); aoqi@0: const BitMap live_at_edge = to_block->live_in(); aoqi@0: aoqi@0: // visit all registers where the live_at_edge bit is set aoqi@0: for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { aoqi@0: assert(r < num_regs, "live information set for not exisiting interval"); aoqi@0: assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); aoqi@0: aoqi@0: Interval* from_interval = interval_at_block_end(from_block, r); aoqi@0: Interval* to_interval = interval_at_block_begin(to_block, r); aoqi@0: aoqi@0: if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { aoqi@0: // need to insert move instruction aoqi@0: move_resolver.add_mapping(from_interval, to_interval); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { aoqi@0: if (from_block->number_of_sux() <= 1) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); aoqi@0: aoqi@0: LIR_OpList* instructions = from_block->lir()->instructions_list(); aoqi@0: LIR_OpBranch* branch = instructions->last()->as_OpBranch(); aoqi@0: if (branch != NULL) { aoqi@0: // insert moves before branch aoqi@0: assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); aoqi@0: move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); aoqi@0: } else { aoqi@0: move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); aoqi@0: #ifdef ASSERT aoqi@0: assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); aoqi@0: aoqi@0: // because the number of predecessor edges matches the number of aoqi@0: // successor edges, blocks which are reached by switch statements aoqi@0: // may have be more than one predecessor but it will be guaranteed aoqi@0: // that all predecessors will be the same. aoqi@0: for (int i = 0; i < to_block->number_of_preds(); i++) { aoqi@0: assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: move_resolver.set_insert_position(to_block->lir(), 0); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split aoqi@0: void LinearScan::resolve_data_flow() { aoqi@0: TIME_LINEAR_SCAN(timer_resolve_data_flow); aoqi@0: aoqi@0: int num_blocks = block_count(); aoqi@0: MoveResolver move_resolver(this); aoqi@0: BitMap block_completed(num_blocks); block_completed.clear(); aoqi@0: BitMap already_resolved(num_blocks); already_resolved.clear(); aoqi@0: aoqi@0: int i; aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: aoqi@0: // check if block has only one predecessor and only one successor aoqi@0: if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: assert(instructions->at(0)->code() == lir_label, "block must start with label"); aoqi@0: assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); aoqi@0: assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); aoqi@0: aoqi@0: // check if block is empty (only label and branch) aoqi@0: if (instructions->length() == 2) { aoqi@0: BlockBegin* pred = block->pred_at(0); aoqi@0: BlockBegin* sux = block->sux_at(0); aoqi@0: aoqi@0: // prevent optimization of two consecutive blocks aoqi@0: if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); aoqi@0: block_completed.set_bit(block->linear_scan_number()); aoqi@0: aoqi@0: // directly resolve between pred and sux (without looking at the empty block between) aoqi@0: resolve_collect_mappings(pred, sux, move_resolver); aoqi@0: if (move_resolver.has_mappings()) { aoqi@0: move_resolver.set_insert_position(block->lir(), 0); aoqi@0: move_resolver.resolve_and_append_moves(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: if (!block_completed.at(i)) { aoqi@0: BlockBegin* from_block = block_at(i); aoqi@0: already_resolved.set_from(block_completed); aoqi@0: aoqi@0: int num_sux = from_block->number_of_sux(); aoqi@0: for (int s = 0; s < num_sux; s++) { aoqi@0: BlockBegin* to_block = from_block->sux_at(s); aoqi@0: aoqi@0: // check for duplicate edges between the same blocks (can happen with switch blocks) aoqi@0: if (!already_resolved.at(to_block->linear_scan_number())) { aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); aoqi@0: already_resolved.set_bit(to_block->linear_scan_number()); aoqi@0: aoqi@0: // collect all intervals that have been split between from_block and to_block aoqi@0: resolve_collect_mappings(from_block, to_block, move_resolver); aoqi@0: if (move_resolver.has_mappings()) { aoqi@0: resolve_find_insert_pos(from_block, to_block, move_resolver); aoqi@0: move_resolver.resolve_and_append_moves(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { aoqi@0: if (interval_at(reg_num) == NULL) { aoqi@0: // if a phi function is never used, no interval is created -> ignore this aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: Interval* interval = interval_at_block_begin(block, reg_num); aoqi@0: int reg = interval->assigned_reg(); aoqi@0: int regHi = interval->assigned_regHi(); aoqi@0: aoqi@0: if ((reg < nof_regs && interval->always_in_memory()) || aoqi@0: (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { aoqi@0: // the interval is split to get a short range that is located on the stack aoqi@0: // in the following two cases: aoqi@0: // * the interval started in memory (e.g. method parameter), but is currently in a register aoqi@0: // this is an optimization for exception handling that reduces the number of moves that aoqi@0: // are necessary for resolving the states when an exception uses this exception handler aoqi@0: // * the interval would be on the fpu stack at the begin of the exception handler aoqi@0: // this is not allowed because of the complicated fpu stack handling on Intel aoqi@0: aoqi@0: // range that will be spilled to memory aoqi@0: int from_op_id = block->first_lir_instruction_id(); aoqi@0: int to_op_id = from_op_id + 1; // short live range of length 1 aoqi@0: assert(interval->from() <= from_op_id && interval->to() >= to_op_id, aoqi@0: "no split allowed between exception entry and first instruction"); aoqi@0: aoqi@0: if (interval->from() != from_op_id) { aoqi@0: // the part before from_op_id is unchanged aoqi@0: interval = interval->split(from_op_id); aoqi@0: interval->assign_reg(reg, regHi); aoqi@0: append_interval(interval); aoqi@0: } else { aoqi@0: _needs_full_resort = true; aoqi@0: } aoqi@0: assert(interval->from() == from_op_id, "must be true now"); aoqi@0: aoqi@0: Interval* spilled_part = interval; aoqi@0: if (interval->to() != to_op_id) { aoqi@0: // the part after to_op_id is unchanged aoqi@0: spilled_part = interval->split_from_start(to_op_id); aoqi@0: append_interval(spilled_part); aoqi@0: move_resolver.add_mapping(spilled_part, interval); aoqi@0: } aoqi@0: assign_spill_slot(spilled_part); aoqi@0: aoqi@0: assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { aoqi@0: assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); aoqi@0: DEBUG_ONLY(move_resolver.check_empty()); aoqi@0: aoqi@0: // visit all registers where the live_in bit is set aoqi@0: int size = live_set_size(); aoqi@0: for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { aoqi@0: resolve_exception_entry(block, r, move_resolver); aoqi@0: } aoqi@0: aoqi@0: // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately aoqi@0: for_each_phi_fun(block, phi, aoqi@0: resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) aoqi@0: ); aoqi@0: aoqi@0: if (move_resolver.has_mappings()) { aoqi@0: // insert moves after first instruction aoqi@0: move_resolver.set_insert_position(block->lir(), 0); aoqi@0: move_resolver.resolve_and_append_moves(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { aoqi@0: if (interval_at(reg_num) == NULL) { aoqi@0: // if a phi function is never used, no interval is created -> ignore this aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: // the computation of to_interval is equal to resolve_collect_mappings, aoqi@0: // but from_interval is more complicated because of phi functions aoqi@0: BlockBegin* to_block = handler->entry_block(); aoqi@0: Interval* to_interval = interval_at_block_begin(to_block, reg_num); aoqi@0: aoqi@0: if (phi != NULL) { aoqi@0: // phi function of the exception entry block aoqi@0: // no moves are created for this phi function in the LIR_Generator, so the aoqi@0: // interval at the throwing instruction must be searched using the operands aoqi@0: // of the phi function aoqi@0: Value from_value = phi->operand_at(handler->phi_operand()); aoqi@0: aoqi@0: // with phi functions it can happen that the same from_value is used in aoqi@0: // multiple mappings, so notify move-resolver that this is allowed aoqi@0: move_resolver.set_multiple_reads_allowed(); aoqi@0: aoqi@0: Constant* con = from_value->as_Constant(); aoqi@0: if (con != NULL && !con->is_pinned()) { aoqi@0: // unpinned constants may have no register, so add mapping from constant to interval aoqi@0: move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); aoqi@0: } else { aoqi@0: // search split child at the throwing op_id aoqi@0: Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); aoqi@0: move_resolver.add_mapping(from_interval, to_interval); aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // no phi function, so use reg_num also for from_interval aoqi@0: // search split child at the throwing op_id aoqi@0: Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); aoqi@0: if (from_interval != to_interval) { aoqi@0: // optimization to reduce number of moves: when to_interval is on stack and aoqi@0: // the stack slot is known to be always correct, then no move is necessary aoqi@0: if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { aoqi@0: move_resolver.add_mapping(from_interval, to_interval); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); aoqi@0: aoqi@0: DEBUG_ONLY(move_resolver.check_empty()); aoqi@0: assert(handler->lir_op_id() == -1, "already processed this xhandler"); aoqi@0: DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); aoqi@0: assert(handler->entry_code() == NULL, "code already present"); aoqi@0: aoqi@0: // visit all registers where the live_in bit is set aoqi@0: BlockBegin* block = handler->entry_block(); aoqi@0: int size = live_set_size(); aoqi@0: for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { aoqi@0: resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); aoqi@0: } aoqi@0: aoqi@0: // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately aoqi@0: for_each_phi_fun(block, phi, aoqi@0: resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) aoqi@0: ); aoqi@0: aoqi@0: if (move_resolver.has_mappings()) { aoqi@0: LIR_List* entry_code = new LIR_List(compilation()); aoqi@0: move_resolver.set_insert_position(entry_code, 0); aoqi@0: move_resolver.resolve_and_append_moves(); aoqi@0: aoqi@0: entry_code->jump(handler->entry_block()); aoqi@0: handler->set_entry_code(entry_code); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::resolve_exception_handlers() { aoqi@0: MoveResolver move_resolver(this); aoqi@0: LIR_OpVisitState visitor; aoqi@0: int num_blocks = block_count(); aoqi@0: aoqi@0: int i; aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: if (block->is_set(BlockBegin::exception_entry_flag)) { aoqi@0: resolve_exception_entry(block, move_resolver); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: for (i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: LIR_List* ops = block->lir(); aoqi@0: int num_ops = ops->length(); aoqi@0: aoqi@0: // iterate all instructions of the block. skip the first because it is always a label aoqi@0: assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); aoqi@0: for (int j = 1; j < num_ops; j++) { aoqi@0: LIR_Op* op = ops->at(j); aoqi@0: int op_id = op->id(); aoqi@0: aoqi@0: if (op_id != -1 && has_info(op_id)) { aoqi@0: // visit operation to collect all operands aoqi@0: visitor.visit(op); aoqi@0: assert(visitor.info_count() > 0, "should not visit otherwise"); aoqi@0: aoqi@0: XHandlers* xhandlers = visitor.all_xhandler(); aoqi@0: int n = xhandlers->length(); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: } else { aoqi@0: visitor.visit(op); aoqi@0: assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); aoqi@0: #endif aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Phase 7: assign register numbers back to LIR aoqi@0: // (includes computation of debug information and oop maps) aoqi@0: aoqi@0: VMReg LinearScan::vm_reg_for_interval(Interval* interval) { aoqi@0: VMReg reg = interval->cached_vm_reg(); aoqi@0: if (!reg->is_valid() ) { aoqi@0: reg = vm_reg_for_operand(operand_for_interval(interval)); aoqi@0: interval->set_cached_vm_reg(reg); aoqi@0: } aoqi@0: assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); aoqi@0: return reg; aoqi@0: } aoqi@0: aoqi@0: VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { aoqi@0: assert(opr->is_oop(), "currently only implemented for oop operands"); aoqi@0: return frame_map()->regname(opr); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: LIR_Opr LinearScan::operand_for_interval(Interval* interval) { aoqi@0: LIR_Opr opr = interval->cached_opr(); aoqi@0: if (opr->is_illegal()) { aoqi@0: opr = calc_operand_for_interval(interval); aoqi@0: interval->set_cached_opr(opr); aoqi@0: } aoqi@0: aoqi@0: assert(opr == calc_operand_for_interval(interval), "wrong cached value"); aoqi@0: return opr; aoqi@0: } aoqi@0: aoqi@0: LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { aoqi@0: int assigned_reg = interval->assigned_reg(); aoqi@0: BasicType type = interval->type(); aoqi@0: aoqi@0: if (assigned_reg >= nof_regs) { aoqi@0: // stack slot aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::stack(assigned_reg - nof_regs, type); aoqi@0: aoqi@0: } else { aoqi@0: // register aoqi@0: switch (type) { aoqi@0: case T_OBJECT: { aoqi@0: assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_cpu_oop(assigned_reg); aoqi@0: } aoqi@0: aoqi@0: case T_ADDRESS: { aoqi@0: assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_cpu_address(assigned_reg); aoqi@0: } aoqi@0: aoqi@0: case T_METADATA: { aoqi@0: assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_cpu_metadata(assigned_reg); aoqi@0: } aoqi@0: aoqi@0: #ifdef __SOFTFP__ aoqi@0: case T_FLOAT: // fall through aoqi@0: #endif // __SOFTFP__ aoqi@0: case T_INT: { aoqi@0: assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_cpu(assigned_reg); aoqi@0: } aoqi@0: aoqi@0: #ifdef __SOFTFP__ aoqi@0: case T_DOUBLE: // fall through aoqi@0: #endif // __SOFTFP__ aoqi@0: case T_LONG: { aoqi@0: int assigned_regHi = interval->assigned_regHi(); aoqi@0: assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); aoqi@0: assert(num_physical_regs(T_LONG) == 1 || aoqi@0: (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); aoqi@0: aoqi@0: assert(assigned_reg != assigned_regHi, "invalid allocation"); aoqi@0: assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, aoqi@0: "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); aoqi@0: assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); aoqi@0: if (requires_adjacent_regs(T_LONG)) { aoqi@0: assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); aoqi@0: } aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); aoqi@0: #else aoqi@0: #if defined(SPARC) || defined(PPC) aoqi@0: return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); aoqi@0: #else aoqi@0: return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); aoqi@0: #endif // SPARC aoqi@0: #endif // LP64 aoqi@0: } aoqi@0: aoqi@0: #ifndef __SOFTFP__ aoqi@0: case T_FLOAT: { aoqi@0: #ifdef X86 aoqi@0: if (UseSSE >= 1) { aoqi@0: assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register"); aoqi@0: return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); aoqi@0: } aoqi@0: aoqi@0: case T_DOUBLE: { aoqi@0: #ifdef X86 aoqi@0: if (UseSSE >= 2) { aoqi@0: assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); aoqi@0: return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: #ifdef SPARC aoqi@0: assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); aoqi@0: LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); aoqi@0: #elif defined(ARM) aoqi@0: assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); aoqi@0: LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); aoqi@0: #else aoqi@0: assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); aoqi@0: LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); aoqi@0: #endif aoqi@0: return result; aoqi@0: } aoqi@0: #endif // __SOFTFP__ aoqi@0: aoqi@0: default: { aoqi@0: ShouldNotReachHere(); aoqi@0: return LIR_OprFact::illegalOpr; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { aoqi@0: assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); aoqi@0: return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); aoqi@0: } aoqi@0: aoqi@0: LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { aoqi@0: assert(opr->is_virtual(), "should not call this otherwise"); aoqi@0: aoqi@0: Interval* interval = interval_at(opr->vreg_number()); aoqi@0: assert(interval != NULL, "interval must exist"); aoqi@0: aoqi@0: if (op_id != -1) { aoqi@0: #ifdef ASSERT aoqi@0: BlockBegin* block = block_of_op_with_id(op_id); aoqi@0: if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { aoqi@0: // check if spill moves could have been appended at the end of this block, but aoqi@0: // before the branch instruction. So the split child information for this branch would aoqi@0: // be incorrect. aoqi@0: LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); aoqi@0: if (branch != NULL) { aoqi@0: if (block->live_out().at(opr->vreg_number())) { aoqi@0: assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); aoqi@0: assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // operands are not changed when an interval is split during allocation, aoqi@0: // so search the right interval here aoqi@0: interval = split_child_at_op_id(interval, op_id, mode); aoqi@0: } aoqi@0: aoqi@0: LIR_Opr res = operand_for_interval(interval); aoqi@0: aoqi@0: #ifdef X86 aoqi@0: // new semantic for is_last_use: not only set on definite end of interval, aoqi@0: // but also before hole aoqi@0: // This may still miss some cases (e.g. for dead values), but it is not necessary that the aoqi@0: // last use information is completely correct aoqi@0: // information is only needed for fpu stack allocation aoqi@0: if (res->is_fpu_register()) { aoqi@0: if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { aoqi@0: assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); aoqi@0: res = res->make_last_use(); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); aoqi@0: aoqi@0: return res; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // some methods used to check correctness of debug information aoqi@0: aoqi@0: void assert_no_register_values(GrowableArray* values) { aoqi@0: if (values == NULL) { aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: for (int i = 0; i < values->length(); i++) { aoqi@0: ScopeValue* value = values->at(i); aoqi@0: aoqi@0: if (value->is_location()) { aoqi@0: Location location = ((LocationValue*)value)->location(); aoqi@0: assert(location.where() == Location::on_stack, "value is in register"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void assert_no_register_values(GrowableArray* values) { aoqi@0: if (values == NULL) { aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: for (int i = 0; i < values->length(); i++) { aoqi@0: MonitorValue* value = values->at(i); aoqi@0: aoqi@0: if (value->owner()->is_location()) { aoqi@0: Location location = ((LocationValue*)value->owner())->location(); aoqi@0: assert(location.where() == Location::on_stack, "owner is in register"); aoqi@0: } aoqi@0: assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void assert_equal(Location l1, Location l2) { aoqi@0: assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); aoqi@0: } aoqi@0: aoqi@0: void assert_equal(ScopeValue* v1, ScopeValue* v2) { aoqi@0: if (v1->is_location()) { aoqi@0: assert(v2->is_location(), ""); aoqi@0: assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); aoqi@0: } else if (v1->is_constant_int()) { aoqi@0: assert(v2->is_constant_int(), ""); aoqi@0: assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); aoqi@0: } else if (v1->is_constant_double()) { aoqi@0: assert(v2->is_constant_double(), ""); aoqi@0: assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); aoqi@0: } else if (v1->is_constant_long()) { aoqi@0: assert(v2->is_constant_long(), ""); aoqi@0: assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); aoqi@0: } else if (v1->is_constant_oop()) { aoqi@0: assert(v2->is_constant_oop(), ""); aoqi@0: assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void assert_equal(MonitorValue* m1, MonitorValue* m2) { aoqi@0: assert_equal(m1->owner(), m2->owner()); aoqi@0: assert_equal(m1->basic_lock(), m2->basic_lock()); aoqi@0: } aoqi@0: aoqi@0: void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { aoqi@0: assert(d1->scope() == d2->scope(), "not equal"); aoqi@0: assert(d1->bci() == d2->bci(), "not equal"); aoqi@0: aoqi@0: if (d1->locals() != NULL) { aoqi@0: assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); aoqi@0: assert(d1->locals()->length() == d2->locals()->length(), "not equal"); aoqi@0: for (int i = 0; i < d1->locals()->length(); i++) { aoqi@0: assert_equal(d1->locals()->at(i), d2->locals()->at(i)); aoqi@0: } aoqi@0: } else { aoqi@0: assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); aoqi@0: } aoqi@0: aoqi@0: if (d1->expressions() != NULL) { aoqi@0: assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); aoqi@0: assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); aoqi@0: for (int i = 0; i < d1->expressions()->length(); i++) { aoqi@0: assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); aoqi@0: } aoqi@0: } else { aoqi@0: assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); aoqi@0: } aoqi@0: aoqi@0: if (d1->monitors() != NULL) { aoqi@0: assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); aoqi@0: assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); aoqi@0: for (int i = 0; i < d1->monitors()->length(); i++) { aoqi@0: assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); aoqi@0: } aoqi@0: } else { aoqi@0: assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); aoqi@0: } aoqi@0: aoqi@0: if (d1->caller() != NULL) { aoqi@0: assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); aoqi@0: assert_equal(d1->caller(), d2->caller()); aoqi@0: } else { aoqi@0: assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void check_stack_depth(CodeEmitInfo* info, int stack_end) { aoqi@0: if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { aoqi@0: Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); aoqi@0: switch (code) { aoqi@0: case Bytecodes::_ifnull : // fall through aoqi@0: case Bytecodes::_ifnonnull : // fall through aoqi@0: case Bytecodes::_ifeq : // fall through aoqi@0: case Bytecodes::_ifne : // fall through aoqi@0: case Bytecodes::_iflt : // fall through aoqi@0: case Bytecodes::_ifge : // fall through aoqi@0: case Bytecodes::_ifgt : // fall through aoqi@0: case Bytecodes::_ifle : // fall through aoqi@0: case Bytecodes::_if_icmpeq : // fall through aoqi@0: case Bytecodes::_if_icmpne : // fall through aoqi@0: case Bytecodes::_if_icmplt : // fall through aoqi@0: case Bytecodes::_if_icmpge : // fall through aoqi@0: case Bytecodes::_if_icmpgt : // fall through aoqi@0: case Bytecodes::_if_icmple : // fall through aoqi@0: case Bytecodes::_if_acmpeq : // fall through aoqi@0: case Bytecodes::_if_acmpne : aoqi@0: assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: aoqi@0: IntervalWalker* LinearScan::init_compute_oop_maps() { aoqi@0: // setup lists of potential oops for walking aoqi@0: Interval* oop_intervals; aoqi@0: Interval* non_oop_intervals; aoqi@0: aoqi@0: create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); aoqi@0: aoqi@0: // intervals that have no oops inside need not to be processed aoqi@0: // to ensure a walking until the last instruction id, add a dummy interval aoqi@0: // with a high operation id aoqi@0: non_oop_intervals = new Interval(any_reg); aoqi@0: non_oop_intervals->add_range(max_jint - 2, max_jint - 1); aoqi@0: aoqi@0: return new IntervalWalker(this, oop_intervals, non_oop_intervals); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); aoqi@0: aoqi@0: // walk before the current operation -> intervals that start at aoqi@0: // the operation (= output operands of the operation) are not aoqi@0: // included in the oop map aoqi@0: iw->walk_before(op->id()); aoqi@0: aoqi@0: int frame_size = frame_map()->framesize(); aoqi@0: int arg_count = frame_map()->oop_map_arg_count(); aoqi@0: OopMap* map = new OopMap(frame_size, arg_count); aoqi@0: aoqi@0: // Iterate through active intervals aoqi@0: for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { aoqi@0: int assigned_reg = interval->assigned_reg(); aoqi@0: aoqi@0: assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); aoqi@0: assert(interval->assigned_regHi() == any_reg, "oop must be single word"); aoqi@0: assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); aoqi@0: aoqi@0: // Check if this range covers the instruction. Intervals that aoqi@0: // start or end at the current operation are not included in the aoqi@0: // oop map, except in the case of patching moves. For patching aoqi@0: // moves, any intervals which end at this instruction are included aoqi@0: // in the oop map since we may safepoint while doing the patch aoqi@0: // before we've consumed the inputs. aoqi@0: if (op->is_patching() || op->id() < interval->current_to()) { aoqi@0: aoqi@0: // caller-save registers must not be included into oop-maps at calls aoqi@0: assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); aoqi@0: aoqi@0: VMReg name = vm_reg_for_interval(interval); aoqi@0: set_oop(map, name); aoqi@0: aoqi@0: // Spill optimization: when the stack value is guaranteed to be always correct, aoqi@0: // then it must be added to the oop map even if the interval is currently in a register aoqi@0: if (interval->always_in_memory() && aoqi@0: op->id() > interval->spill_definition_pos() && aoqi@0: interval->assigned_reg() != interval->canonical_spill_slot()) { aoqi@0: assert(interval->spill_definition_pos() > 0, "position not set correctly"); aoqi@0: assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); aoqi@0: assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); aoqi@0: aoqi@0: set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // add oops from lock stack aoqi@0: assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); aoqi@0: int locks_count = info->stack()->total_locks_size(); aoqi@0: for (int i = 0; i < locks_count; i++) { aoqi@0: set_oop(map, frame_map()->monitor_object_regname(i)); aoqi@0: } aoqi@0: aoqi@0: return map; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { aoqi@0: assert(visitor.info_count() > 0, "no oop map needed"); aoqi@0: aoqi@0: // compute oop_map only for first CodeEmitInfo aoqi@0: // because it is (in most cases) equal for all other infos of the same operation aoqi@0: CodeEmitInfo* first_info = visitor.info_at(0); aoqi@0: OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); aoqi@0: aoqi@0: for (int i = 0; i < visitor.info_count(); i++) { aoqi@0: CodeEmitInfo* info = visitor.info_at(i); aoqi@0: OopMap* oop_map = first_oop_map; aoqi@0: aoqi@0: // compute worst case interpreter size in case of a deoptimization aoqi@0: _compilation->update_interpreter_frame_size(info->interpreter_frame_size()); aoqi@0: aoqi@0: if (info->stack()->locks_size() != first_info->stack()->locks_size()) { aoqi@0: // this info has a different number of locks then the precomputed oop map aoqi@0: // (possible for lock and unlock instructions) -> compute oop map with aoqi@0: // correct lock information aoqi@0: oop_map = compute_oop_map(iw, op, info, visitor.has_call()); aoqi@0: } aoqi@0: aoqi@0: if (info->_oop_map == NULL) { aoqi@0: info->_oop_map = oop_map; aoqi@0: } else { aoqi@0: // a CodeEmitInfo can not be shared between different LIR-instructions aoqi@0: // because interval splitting can occur anywhere between two instructions aoqi@0: // and so the oop maps must be different aoqi@0: // -> check if the already set oop_map is exactly the one calculated for this operation aoqi@0: assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // frequently used constants aoqi@0: // Allocate them with new so they are never destroyed (otherwise, a aoqi@0: // forced exit could destroy these objects while they are still in aoqi@0: // use). aoqi@0: ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL); aoqi@0: ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1); aoqi@0: ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0); aoqi@0: ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1); aoqi@0: ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2); aoqi@0: LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location()); aoqi@0: aoqi@0: void LinearScan::init_compute_debug_info() { aoqi@0: // cache for frequently used scope values aoqi@0: // (cpu registers and stack slots) aoqi@0: _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL); aoqi@0: } aoqi@0: aoqi@0: MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { aoqi@0: Location loc; aoqi@0: if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { aoqi@0: bailout("too large frame"); aoqi@0: } aoqi@0: ScopeValue* object_scope_value = new LocationValue(loc); aoqi@0: aoqi@0: if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { aoqi@0: bailout("too large frame"); aoqi@0: } aoqi@0: return new MonitorValue(object_scope_value, loc); aoqi@0: } aoqi@0: aoqi@0: LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { aoqi@0: Location loc; aoqi@0: if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { aoqi@0: bailout("too large frame"); aoqi@0: } aoqi@0: return new LocationValue(loc); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray* scope_values) { aoqi@0: assert(opr->is_constant(), "should not be called otherwise"); aoqi@0: aoqi@0: LIR_Const* c = opr->as_constant_ptr(); aoqi@0: BasicType t = c->type(); aoqi@0: switch (t) { aoqi@0: case T_OBJECT: { aoqi@0: jobject value = c->as_jobject(); aoqi@0: if (value == NULL) { aoqi@0: scope_values->append(_oop_null_scope_value); aoqi@0: } else { aoqi@0: scope_values->append(new ConstantOopWriteValue(c->as_jobject())); aoqi@0: } aoqi@0: return 1; aoqi@0: } aoqi@0: aoqi@0: case T_INT: // fall through aoqi@0: case T_FLOAT: { aoqi@0: int value = c->as_jint_bits(); aoqi@0: switch (value) { aoqi@0: case -1: scope_values->append(_int_m1_scope_value); break; aoqi@0: case 0: scope_values->append(_int_0_scope_value); break; aoqi@0: case 1: scope_values->append(_int_1_scope_value); break; aoqi@0: case 2: scope_values->append(_int_2_scope_value); break; aoqi@0: default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; aoqi@0: } aoqi@0: return 1; aoqi@0: } aoqi@0: aoqi@0: case T_LONG: // fall through aoqi@0: case T_DOUBLE: { aoqi@0: #ifdef _LP64 aoqi@0: scope_values->append(_int_0_scope_value); aoqi@0: scope_values->append(new ConstantLongValue(c->as_jlong_bits())); aoqi@0: #else aoqi@0: if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { aoqi@0: scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); aoqi@0: scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); aoqi@0: } else { aoqi@0: scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); aoqi@0: scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); aoqi@0: } aoqi@0: #endif aoqi@0: return 2; aoqi@0: } aoqi@0: aoqi@0: case T_ADDRESS: { aoqi@0: #ifdef _LP64 aoqi@0: scope_values->append(new ConstantLongValue(c->as_jint())); aoqi@0: #else aoqi@0: scope_values->append(new ConstantIntValue(c->as_jint())); aoqi@0: #endif aoqi@0: return 1; aoqi@0: } aoqi@0: aoqi@0: default: aoqi@0: ShouldNotReachHere(); aoqi@0: return -1; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray* scope_values) { aoqi@0: if (opr->is_single_stack()) { aoqi@0: int stack_idx = opr->single_stack_ix(); aoqi@0: bool is_oop = opr->is_oop_register(); aoqi@0: int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); aoqi@0: aoqi@0: ScopeValue* sv = _scope_value_cache.at(cache_idx); aoqi@0: if (sv == NULL) { aoqi@0: Location::Type loc_type = is_oop ? Location::oop : Location::normal; aoqi@0: sv = location_for_name(stack_idx, loc_type); aoqi@0: _scope_value_cache.at_put(cache_idx, sv); aoqi@0: } aoqi@0: aoqi@0: // check if cached value is correct aoqi@0: DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); aoqi@0: aoqi@0: scope_values->append(sv); aoqi@0: return 1; aoqi@0: aoqi@0: } else if (opr->is_single_cpu()) { aoqi@0: bool is_oop = opr->is_oop_register(); aoqi@0: int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); aoqi@0: Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); aoqi@0: aoqi@0: ScopeValue* sv = _scope_value_cache.at(cache_idx); aoqi@0: if (sv == NULL) { aoqi@0: Location::Type loc_type = is_oop ? Location::oop : int_loc_type; aoqi@0: VMReg rname = frame_map()->regname(opr); aoqi@0: sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); aoqi@0: _scope_value_cache.at_put(cache_idx, sv); aoqi@0: } aoqi@0: aoqi@0: // check if cached value is correct aoqi@0: DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); aoqi@0: aoqi@0: scope_values->append(sv); aoqi@0: return 1; aoqi@0: aoqi@0: #ifdef X86 aoqi@0: } else if (opr->is_single_xmm()) { aoqi@0: VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); aoqi@0: LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); aoqi@0: aoqi@0: scope_values->append(sv); aoqi@0: return 1; aoqi@0: #endif aoqi@0: aoqi@0: } else if (opr->is_single_fpu()) { aoqi@0: #ifdef X86 aoqi@0: // the exact location of fpu stack values is only known aoqi@0: // during fpu stack allocation, so the stack allocator object aoqi@0: // must be present aoqi@0: assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); aoqi@0: assert(_fpu_stack_allocator != NULL, "must be present"); aoqi@0: opr = _fpu_stack_allocator->to_fpu_stack(opr); aoqi@0: #endif aoqi@0: aoqi@0: Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; aoqi@0: VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); aoqi@0: #ifndef __SOFTFP__ aoqi@0: #ifndef VM_LITTLE_ENDIAN aoqi@0: if (! float_saved_as_double) { aoqi@0: // On big endian system, we may have an issue if float registers use only aoqi@0: // the low half of the (same) double registers. aoqi@0: // Both the float and the double could have the same regnr but would correspond aoqi@0: // to two different addresses once saved. aoqi@0: aoqi@0: // get next safely (no assertion checks) aoqi@0: VMReg next = VMRegImpl::as_VMReg(1+rname->value()); aoqi@0: if (next->is_reg() && aoqi@0: (next->as_FloatRegister() == rname->as_FloatRegister())) { aoqi@0: // the back-end does use the same numbering for the double and the float aoqi@0: rname = next; // VMReg for the low bits, e.g. the real VMReg for the float aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: #endif aoqi@0: LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); aoqi@0: aoqi@0: scope_values->append(sv); aoqi@0: return 1; aoqi@0: aoqi@0: } else { aoqi@0: // double-size operands aoqi@0: aoqi@0: ScopeValue* first; aoqi@0: ScopeValue* second; aoqi@0: aoqi@0: if (opr->is_double_stack()) { aoqi@0: #ifdef _LP64 aoqi@0: Location loc1; aoqi@0: Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; aoqi@0: if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { aoqi@0: bailout("too large frame"); aoqi@0: } aoqi@0: // Does this reverse on x86 vs. sparc? aoqi@0: first = new LocationValue(loc1); aoqi@0: second = _int_0_scope_value; aoqi@0: #else aoqi@0: Location loc1, loc2; aoqi@0: if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { aoqi@0: bailout("too large frame"); aoqi@0: } aoqi@0: first = new LocationValue(loc1); aoqi@0: second = new LocationValue(loc2); aoqi@0: #endif // _LP64 aoqi@0: aoqi@0: } else if (opr->is_double_cpu()) { aoqi@0: #ifdef _LP64 aoqi@0: VMReg rname_first = opr->as_register_lo()->as_VMReg(); aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); aoqi@0: second = _int_0_scope_value; aoqi@0: #else aoqi@0: VMReg rname_first = opr->as_register_lo()->as_VMReg(); aoqi@0: VMReg rname_second = opr->as_register_hi()->as_VMReg(); aoqi@0: aoqi@0: if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { aoqi@0: // lo/hi and swapped relative to first and second, so swap them aoqi@0: VMReg tmp = rname_first; aoqi@0: rname_first = rname_second; aoqi@0: rname_second = tmp; aoqi@0: } aoqi@0: aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); aoqi@0: second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); aoqi@0: #endif //_LP64 aoqi@0: aoqi@0: aoqi@0: #ifdef X86 aoqi@0: } else if (opr->is_double_xmm()) { aoqi@0: assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); aoqi@0: VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); aoqi@0: # ifdef _LP64 aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); aoqi@0: second = _int_0_scope_value; aoqi@0: # else aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); aoqi@0: // %%% This is probably a waste but we'll keep things as they were for now aoqi@0: if (true) { aoqi@0: VMReg rname_second = rname_first->next(); aoqi@0: second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); aoqi@0: } aoqi@0: # endif aoqi@0: #endif aoqi@0: aoqi@0: } else if (opr->is_double_fpu()) { aoqi@0: // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of aoqi@0: // the double as float registers in the native ordering. On X86, aoqi@0: // fpu_regnrLo is a FPU stack slot whose VMReg represents aoqi@0: // the low-order word of the double and fpu_regnrLo + 1 is the aoqi@0: // name for the other half. *first and *second must represent the aoqi@0: // least and most significant words, respectively. aoqi@0: aoqi@0: #ifdef X86 aoqi@0: // the exact location of fpu stack values is only known aoqi@0: // during fpu stack allocation, so the stack allocator object aoqi@0: // must be present aoqi@0: assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); aoqi@0: assert(_fpu_stack_allocator != NULL, "must be present"); aoqi@0: opr = _fpu_stack_allocator->to_fpu_stack(opr); aoqi@0: aoqi@0: assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); aoqi@0: #endif aoqi@0: #ifdef SPARC aoqi@0: assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); aoqi@0: #endif aoqi@0: #ifdef ARM aoqi@0: assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); aoqi@0: #endif aoqi@0: #ifdef PPC aoqi@0: assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); aoqi@0: #endif aoqi@0: aoqi@0: #ifdef VM_LITTLE_ENDIAN aoqi@0: VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo()); aoqi@0: #else aoqi@0: VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); aoqi@0: #endif aoqi@0: aoqi@0: #ifdef _LP64 aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); aoqi@0: second = _int_0_scope_value; aoqi@0: #else aoqi@0: first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); aoqi@0: // %%% This is probably a waste but we'll keep things as they were for now aoqi@0: if (true) { aoqi@0: VMReg rname_second = rname_first->next(); aoqi@0: second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: first = NULL; aoqi@0: second = NULL; aoqi@0: } aoqi@0: aoqi@0: assert(first != NULL && second != NULL, "must be set"); aoqi@0: // The convention the interpreter uses is that the second local aoqi@0: // holds the first raw word of the native double representation. aoqi@0: // This is actually reasonable, since locals and stack arrays aoqi@0: // grow downwards in all implementations. aoqi@0: // (If, on some machine, the interpreter's Java locals or stack aoqi@0: // were to grow upwards, the embedded doubles would be word-swapped.) aoqi@0: scope_values->append(second); aoqi@0: scope_values->append(first); aoqi@0: return 2; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScan::append_scope_value(int op_id, Value value, GrowableArray* scope_values) { aoqi@0: if (value != NULL) { aoqi@0: LIR_Opr opr = value->operand(); aoqi@0: Constant* con = value->as_Constant(); aoqi@0: aoqi@0: assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); aoqi@0: assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); aoqi@0: aoqi@0: if (con != NULL && !con->is_pinned() && !opr->is_constant()) { aoqi@0: // Unpinned constants may have a virtual operand for a part of the lifetime aoqi@0: // or may be illegal when it was optimized away, aoqi@0: // so always use a constant operand aoqi@0: opr = LIR_OprFact::value_type(con->type()); aoqi@0: } aoqi@0: assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); aoqi@0: aoqi@0: if (opr->is_virtual()) { aoqi@0: LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; aoqi@0: aoqi@0: BlockBegin* block = block_of_op_with_id(op_id); aoqi@0: if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { aoqi@0: // generating debug information for the last instruction of a block. aoqi@0: // if this instruction is a branch, spill moves are inserted before this branch aoqi@0: // and so the wrong operand would be returned (spill moves at block boundaries are not aoqi@0: // considered in the live ranges of intervals) aoqi@0: // Solution: use the first op_id of the branch target block instead. aoqi@0: if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { aoqi@0: if (block->live_out().at(opr->vreg_number())) { aoqi@0: op_id = block->sux_at(0)->first_lir_instruction_id(); aoqi@0: mode = LIR_OpVisitState::outputMode; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // Get current location of operand aoqi@0: // The operand must be live because debug information is considered when building the intervals aoqi@0: // if the interval is not live, color_lir_opr will cause an assertion failure aoqi@0: opr = color_lir_opr(opr, op_id, mode); aoqi@0: assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); aoqi@0: aoqi@0: // Append to ScopeValue array aoqi@0: return append_scope_value_for_operand(opr, scope_values); aoqi@0: aoqi@0: } else { aoqi@0: assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); aoqi@0: assert(opr->is_constant(), "operand must be constant"); aoqi@0: aoqi@0: return append_scope_value_for_constant(opr, scope_values); aoqi@0: } aoqi@0: } else { aoqi@0: // append a dummy value because real value not needed aoqi@0: scope_values->append(_illegal_value); aoqi@0: return 1; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) { aoqi@0: IRScopeDebugInfo* caller_debug_info = NULL; aoqi@0: aoqi@0: ValueStack* caller_state = cur_state->caller_state(); aoqi@0: if (caller_state != NULL) { aoqi@0: // process recursively to compute outermost scope first aoqi@0: caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state); aoqi@0: } aoqi@0: aoqi@0: // initialize these to null. aoqi@0: // If we don't need deopt info or there are no locals, expressions or monitors, aoqi@0: // then these get recorded as no information and avoids the allocation of 0 length arrays. aoqi@0: GrowableArray* locals = NULL; aoqi@0: GrowableArray* expressions = NULL; aoqi@0: GrowableArray* monitors = NULL; aoqi@0: aoqi@0: // describe local variable values aoqi@0: int nof_locals = cur_state->locals_size(); aoqi@0: if (nof_locals > 0) { aoqi@0: locals = new GrowableArray(nof_locals); aoqi@0: aoqi@0: int pos = 0; aoqi@0: while (pos < nof_locals) { aoqi@0: assert(pos < cur_state->locals_size(), "why not?"); aoqi@0: aoqi@0: Value local = cur_state->local_at(pos); aoqi@0: pos += append_scope_value(op_id, local, locals); aoqi@0: aoqi@0: assert(locals->length() == pos, "must match"); aoqi@0: } aoqi@0: assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); aoqi@0: assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); aoqi@0: } else if (cur_scope->method()->max_locals() > 0) { aoqi@0: assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be"); aoqi@0: nof_locals = cur_scope->method()->max_locals(); aoqi@0: locals = new GrowableArray(nof_locals); aoqi@0: for(int i = 0; i < nof_locals; i++) { aoqi@0: locals->append(_illegal_value); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // describe expression stack aoqi@0: int nof_stack = cur_state->stack_size(); aoqi@0: if (nof_stack > 0) { aoqi@0: expressions = new GrowableArray(nof_stack); aoqi@0: aoqi@0: int pos = 0; aoqi@0: while (pos < nof_stack) { aoqi@0: Value expression = cur_state->stack_at_inc(pos); aoqi@0: append_scope_value(op_id, expression, expressions); aoqi@0: aoqi@0: assert(expressions->length() == pos, "must match"); aoqi@0: } aoqi@0: assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries"); aoqi@0: } aoqi@0: aoqi@0: // describe monitors aoqi@0: int nof_locks = cur_state->locks_size(); aoqi@0: if (nof_locks > 0) { aoqi@0: int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0; aoqi@0: monitors = new GrowableArray(nof_locks); aoqi@0: for (int i = 0; i < nof_locks; i++) { aoqi@0: monitors->append(location_for_monitor_index(lock_offset + i)); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); aoqi@0: aoqi@0: IRScope* innermost_scope = info->scope(); aoqi@0: ValueStack* innermost_state = info->stack(); aoqi@0: aoqi@0: assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); aoqi@0: aoqi@0: DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size())); aoqi@0: aoqi@0: if (info->_scope_debug_info == NULL) { aoqi@0: // compute debug information aoqi@0: info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state); aoqi@0: } else { aoqi@0: // debug information already set. Check that it is correct from the current point of view aoqi@0: DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state))); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { aoqi@0: LIR_OpVisitState visitor; aoqi@0: int num_inst = instructions->length(); aoqi@0: bool has_dead = false; aoqi@0: aoqi@0: for (int j = 0; j < num_inst; j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves aoqi@0: has_dead = true; aoqi@0: continue; aoqi@0: } aoqi@0: int op_id = op->id(); aoqi@0: aoqi@0: // visit instruction to get list of operands aoqi@0: visitor.visit(op); aoqi@0: aoqi@0: // iterate all modes of the visitor and process all virtual operands aoqi@0: for_each_visitor_mode(mode) { aoqi@0: int n = visitor.opr_count(mode); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(mode, k); aoqi@0: if (opr->is_virtual_register()) { aoqi@0: visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (visitor.info_count() > 0) { aoqi@0: // exception handling aoqi@0: if (compilation()->has_exception_handlers()) { aoqi@0: XHandlers* xhandlers = visitor.all_xhandler(); aoqi@0: int n = xhandlers->length(); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: XHandler* handler = xhandlers->handler_at(k); aoqi@0: if (handler->entry_code() != NULL) { aoqi@0: assign_reg_num(handler->entry_code()->instructions_list(), NULL); aoqi@0: } aoqi@0: } aoqi@0: } else { aoqi@0: assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); aoqi@0: } aoqi@0: aoqi@0: // compute oop map aoqi@0: assert(iw != NULL, "needed for compute_oop_map"); aoqi@0: compute_oop_map(iw, visitor, op); aoqi@0: aoqi@0: // compute debug information aoqi@0: if (!use_fpu_stack_allocation()) { aoqi@0: // compute debug information if fpu stack allocation is not needed. aoqi@0: // when fpu stack allocation is needed, the debug information can not aoqi@0: // be computed here because the exact location of fpu operands is not known aoqi@0: // -> debug information is created inside the fpu stack allocator aoqi@0: int n = visitor.info_count(); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: compute_debug_info(visitor.info_at(k), op_id); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // make sure we haven't made the op invalid. aoqi@0: op->verify(); aoqi@0: #endif aoqi@0: aoqi@0: // remove useless moves aoqi@0: if (op->code() == lir_move) { aoqi@0: assert(op->as_Op1() != NULL, "move must be LIR_Op1"); aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: LIR_Opr src = move->in_opr(); aoqi@0: LIR_Opr dst = move->result_opr(); aoqi@0: if (dst == src || aoqi@0: !dst->is_pointer() && !src->is_pointer() && aoqi@0: src->is_same_register(dst)) { aoqi@0: instructions->at_put(j, NULL); aoqi@0: has_dead = true; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (has_dead) { aoqi@0: // iterate all instructions of the block and remove all null-values. aoqi@0: int insert_point = 0; aoqi@0: for (int j = 0; j < num_inst; j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: if (op != NULL) { aoqi@0: if (insert_point != j) { aoqi@0: instructions->at_put(insert_point, op); aoqi@0: } aoqi@0: insert_point++; aoqi@0: } aoqi@0: } aoqi@0: instructions->truncate(insert_point); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::assign_reg_num() { aoqi@0: TIME_LINEAR_SCAN(timer_assign_reg_num); aoqi@0: aoqi@0: init_compute_debug_info(); aoqi@0: IntervalWalker* iw = init_compute_oop_maps(); aoqi@0: aoqi@0: int num_blocks = block_count(); aoqi@0: for (int i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: assign_reg_num(block->lir()->instructions_list(), iw); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::do_linear_scan() { aoqi@0: NOT_PRODUCT(_total_timer.begin_method()); aoqi@0: aoqi@0: number_instructions(); aoqi@0: aoqi@0: NOT_PRODUCT(print_lir(1, "Before Register Allocation")); aoqi@0: aoqi@0: compute_local_live_sets(); aoqi@0: compute_global_live_sets(); aoqi@0: CHECK_BAILOUT(); aoqi@0: aoqi@0: build_intervals(); aoqi@0: CHECK_BAILOUT(); aoqi@0: sort_intervals_before_allocation(); aoqi@0: aoqi@0: NOT_PRODUCT(print_intervals("Before Register Allocation")); aoqi@0: NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); aoqi@0: aoqi@0: allocate_registers(); aoqi@0: CHECK_BAILOUT(); aoqi@0: aoqi@0: resolve_data_flow(); aoqi@0: if (compilation()->has_exception_handlers()) { aoqi@0: resolve_exception_handlers(); aoqi@0: } aoqi@0: // fill in number of spill slots into frame_map aoqi@0: propagate_spill_slots(); aoqi@0: CHECK_BAILOUT(); aoqi@0: aoqi@0: NOT_PRODUCT(print_intervals("After Register Allocation")); aoqi@0: NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); aoqi@0: aoqi@0: sort_intervals_after_allocation(); aoqi@0: aoqi@0: DEBUG_ONLY(verify()); aoqi@0: aoqi@0: eliminate_spill_moves(); aoqi@0: assign_reg_num(); aoqi@0: CHECK_BAILOUT(); aoqi@0: aoqi@0: NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); aoqi@0: NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); aoqi@0: aoqi@0: { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); aoqi@0: aoqi@0: if (use_fpu_stack_allocation()) { aoqi@0: allocate_fpu_stack(); // Only has effect on Intel aoqi@0: NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: { TIME_LINEAR_SCAN(timer_optimize_lir); aoqi@0: aoqi@0: EdgeMoveOptimizer::optimize(ir()->code()); aoqi@0: ControlFlowOptimizer::optimize(ir()->code()); aoqi@0: // check that cfg is still correct after optimizations aoqi@0: ir()->verify(); aoqi@0: } aoqi@0: aoqi@0: NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); aoqi@0: NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); aoqi@0: NOT_PRODUCT(_total_timer.end_method(this)); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // ********** Printing functions aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: aoqi@0: void LinearScan::print_timers(double total) { aoqi@0: _total_timer.print(total); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::print_statistics() { aoqi@0: _stat_before_alloc.print("before allocation"); aoqi@0: _stat_after_asign.print("after assignment of register"); aoqi@0: _stat_final.print("after optimization"); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::print_bitmap(BitMap& b) { aoqi@0: for (unsigned int i = 0; i < b.size(); i++) { aoqi@0: if (b.at(i)) tty->print("%d ", i); aoqi@0: } aoqi@0: tty->cr(); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::print_intervals(const char* label) { aoqi@0: if (TraceLinearScanLevel >= 1) { aoqi@0: int i; aoqi@0: tty->cr(); aoqi@0: tty->print_cr("%s", label); aoqi@0: aoqi@0: for (i = 0; i < interval_count(); i++) { aoqi@0: Interval* interval = interval_at(i); aoqi@0: if (interval != NULL) { aoqi@0: interval->print(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: tty->cr(); aoqi@0: tty->print_cr("--- Basic Blocks ---"); aoqi@0: for (i = 0; i < block_count(); i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); aoqi@0: } aoqi@0: tty->cr(); aoqi@0: tty->cr(); aoqi@0: } aoqi@0: aoqi@0: if (PrintCFGToFile) { aoqi@0: CFGPrinter::print_intervals(&_intervals, label); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScan::print_lir(int level, const char* label, bool hir_valid) { aoqi@0: if (TraceLinearScanLevel >= level) { aoqi@0: tty->cr(); aoqi@0: tty->print_cr("%s", label); aoqi@0: print_LIR(ir()->linear_scan_order()); aoqi@0: tty->cr(); aoqi@0: } aoqi@0: aoqi@0: if (level == 1 && PrintCFGToFile) { aoqi@0: CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #endif //PRODUCT aoqi@0: aoqi@0: aoqi@0: // ********** verification functions for allocation aoqi@0: // (check that all intervals have a correct register and that no registers are overwritten) aoqi@0: #ifdef ASSERT aoqi@0: aoqi@0: void LinearScan::verify() { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); aoqi@0: verify_intervals(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); aoqi@0: verify_no_oops_in_fixed_intervals(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); aoqi@0: verify_constants(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); aoqi@0: verify_registers(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); aoqi@0: } aoqi@0: aoqi@0: void LinearScan::verify_intervals() { aoqi@0: int len = interval_count(); aoqi@0: bool has_error = false; aoqi@0: aoqi@0: for (int i = 0; i < len; i++) { aoqi@0: Interval* i1 = interval_at(i); aoqi@0: if (i1 == NULL) continue; aoqi@0: aoqi@0: i1->check_split_children(); aoqi@0: aoqi@0: if (i1->reg_num() != i) { aoqi@0: tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { aoqi@0: tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: if (i1->assigned_reg() == any_reg) { aoqi@0: tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: if (i1->assigned_reg() == i1->assigned_regHi()) { aoqi@0: tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: if (!is_processed_reg_num(i1->assigned_reg())) { aoqi@0: tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: if (i1->first() == Range::end()) { aoqi@0: tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: aoqi@0: for (Range* r = i1->first(); r != Range::end(); r = r->next()) { aoqi@0: if (r->from() >= r->to()) { aoqi@0: tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: for (int j = i + 1; j < len; j++) { aoqi@0: Interval* i2 = interval_at(j); aoqi@0: if (i2 == NULL) continue; aoqi@0: aoqi@0: // special intervals that are created in MoveResolver aoqi@0: // -> ignore them because the range information has no meaning there aoqi@0: if (i1->from() == 1 && i1->to() == 2) continue; aoqi@0: if (i2->from() == 1 && i2->to() == 2) continue; aoqi@0: aoqi@0: int r1 = i1->assigned_reg(); aoqi@0: int r1Hi = i1->assigned_regHi(); aoqi@0: int r2 = i2->assigned_reg(); aoqi@0: int r2Hi = i2->assigned_regHi(); aoqi@0: if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) { aoqi@0: tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); aoqi@0: i1->print(); tty->cr(); aoqi@0: i2->print(); tty->cr(); aoqi@0: has_error = true; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: assert(has_error == false, "register allocation invalid"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::verify_no_oops_in_fixed_intervals() { aoqi@0: Interval* fixed_intervals; aoqi@0: Interval* other_intervals; aoqi@0: create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); aoqi@0: aoqi@0: // to ensure a walking until the last instruction id, add a dummy interval aoqi@0: // with a high operation id aoqi@0: other_intervals = new Interval(any_reg); aoqi@0: other_intervals->add_range(max_jint - 2, max_jint - 1); aoqi@0: IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); aoqi@0: aoqi@0: LIR_OpVisitState visitor; aoqi@0: for (int i = 0; i < block_count(); i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: for (int j = 0; j < instructions->length(); j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: int op_id = op->id(); aoqi@0: aoqi@0: visitor.visit(op); aoqi@0: aoqi@0: if (visitor.info_count() > 0) { aoqi@0: iw->walk_before(op->id()); aoqi@0: bool check_live = true; aoqi@0: if (op->code() == lir_move) { aoqi@0: LIR_Op1* move = (LIR_Op1*)op; aoqi@0: check_live = (move->patch_code() == lir_patch_none); aoqi@0: } aoqi@0: LIR_OpBranch* branch = op->as_OpBranch(); aoqi@0: if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { aoqi@0: // Don't bother checking the stub in this case since the aoqi@0: // exception stub will never return to normal control flow. aoqi@0: check_live = false; aoqi@0: } aoqi@0: aoqi@0: // Make sure none of the fixed registers is live across an aoqi@0: // oopmap since we can't handle that correctly. aoqi@0: if (check_live) { aoqi@0: for (Interval* interval = iw->active_first(fixedKind); aoqi@0: interval != Interval::end(); aoqi@0: interval = interval->next()) { aoqi@0: if (interval->current_to() > op->id() + 1) { aoqi@0: // This interval is live out of this op so make sure aoqi@0: // that this interval represents some value that's aoqi@0: // referenced by this op either as an input or output. aoqi@0: bool ok = false; aoqi@0: for_each_visitor_mode(mode) { aoqi@0: int n = visitor.opr_count(mode); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(mode, k); aoqi@0: if (opr->is_fixed_cpu()) { aoqi@0: if (interval_at(reg_num(opr)) == interval) { aoqi@0: ok = true; aoqi@0: break; aoqi@0: } aoqi@0: int hi = reg_numHi(opr); aoqi@0: if (hi != -1 && interval_at(hi) == interval) { aoqi@0: ok = true; aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: assert(ok, "fixed intervals should never be live across an oopmap point"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // oop-maps at calls do not contain registers, so check is not needed aoqi@0: if (!visitor.has_call()) { aoqi@0: aoqi@0: for_each_visitor_mode(mode) { aoqi@0: int n = visitor.opr_count(mode); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: LIR_Opr opr = visitor.opr_at(mode, k); aoqi@0: aoqi@0: if (opr->is_fixed_cpu() && opr->is_oop()) { aoqi@0: // operand is a non-virtual cpu register and contains an oop aoqi@0: TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); aoqi@0: aoqi@0: Interval* interval = interval_at(reg_num(opr)); aoqi@0: assert(interval != NULL, "no interval"); aoqi@0: aoqi@0: if (mode == LIR_OpVisitState::inputMode) { aoqi@0: if (interval->to() >= op_id + 1) { aoqi@0: assert(interval->to() < op_id + 2 || aoqi@0: interval->has_hole_between(op_id, op_id + 2), aoqi@0: "oop input operand live after instruction"); aoqi@0: } aoqi@0: } else if (mode == LIR_OpVisitState::outputMode) { aoqi@0: if (interval->from() <= op_id - 1) { aoqi@0: assert(interval->has_hole_between(op_id - 1, op_id), aoqi@0: "oop input operand live after instruction"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScan::verify_constants() { aoqi@0: int num_regs = num_virtual_regs(); aoqi@0: int size = live_set_size(); aoqi@0: int num_blocks = block_count(); aoqi@0: aoqi@0: for (int i = 0; i < num_blocks; i++) { aoqi@0: BlockBegin* block = block_at(i); aoqi@0: BitMap live_at_edge = block->live_in(); aoqi@0: aoqi@0: // visit all registers where the live_at_edge bit is set aoqi@0: for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); aoqi@0: aoqi@0: Value value = gen()->instruction_for_vreg(r); aoqi@0: aoqi@0: assert(value != NULL, "all intervals live across block boundaries must have Value"); aoqi@0: assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); aoqi@0: assert(value->operand()->vreg_number() == r, "register number must match"); aoqi@0: // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: class RegisterVerifier: public StackObj { aoqi@0: private: aoqi@0: LinearScan* _allocator; aoqi@0: BlockList _work_list; // all blocks that must be processed aoqi@0: IntervalsList _saved_states; // saved information of previous check aoqi@0: aoqi@0: // simplified access to methods of LinearScan aoqi@0: Compilation* compilation() const { return _allocator->compilation(); } aoqi@0: Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } aoqi@0: int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } aoqi@0: aoqi@0: // currently, only registers are processed aoqi@0: int state_size() { return LinearScan::nof_regs; } aoqi@0: aoqi@0: // accessors aoqi@0: IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } aoqi@0: void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } aoqi@0: void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } aoqi@0: aoqi@0: // helper functions aoqi@0: IntervalList* copy(IntervalList* input_state); aoqi@0: void state_put(IntervalList* input_state, int reg, Interval* interval); aoqi@0: bool check_state(IntervalList* input_state, int reg, Interval* interval); aoqi@0: aoqi@0: void process_block(BlockBegin* block); aoqi@0: void process_xhandler(XHandler* xhandler, IntervalList* input_state); aoqi@0: void process_successor(BlockBegin* block, IntervalList* input_state); aoqi@0: void process_operations(LIR_List* ops, IntervalList* input_state); aoqi@0: aoqi@0: public: aoqi@0: RegisterVerifier(LinearScan* allocator) aoqi@0: : _allocator(allocator) aoqi@0: , _work_list(16) aoqi@0: , _saved_states(BlockBegin::number_of_blocks(), NULL) aoqi@0: { } aoqi@0: aoqi@0: void verify(BlockBegin* start); aoqi@0: }; aoqi@0: aoqi@0: aoqi@0: // entry function from LinearScan that starts the verification aoqi@0: void LinearScan::verify_registers() { aoqi@0: RegisterVerifier verifier(this); aoqi@0: verifier.verify(block_at(0)); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void RegisterVerifier::verify(BlockBegin* start) { aoqi@0: // setup input registers (method arguments) for first block aoqi@0: IntervalList* input_state = new IntervalList(state_size(), NULL); aoqi@0: CallingConvention* args = compilation()->frame_map()->incoming_arguments(); aoqi@0: for (int n = 0; n < args->length(); n++) { aoqi@0: LIR_Opr opr = args->at(n); aoqi@0: if (opr->is_register()) { aoqi@0: Interval* interval = interval_at(reg_num(opr)); aoqi@0: aoqi@0: if (interval->assigned_reg() < state_size()) { aoqi@0: input_state->at_put(interval->assigned_reg(), interval); aoqi@0: } aoqi@0: if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { aoqi@0: input_state->at_put(interval->assigned_regHi(), interval); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: set_state_for_block(start, input_state); aoqi@0: add_to_work_list(start); aoqi@0: aoqi@0: // main loop for verification aoqi@0: do { aoqi@0: BlockBegin* block = _work_list.at(0); aoqi@0: _work_list.remove_at(0); aoqi@0: aoqi@0: process_block(block); aoqi@0: } while (!_work_list.is_empty()); aoqi@0: } aoqi@0: aoqi@0: void RegisterVerifier::process_block(BlockBegin* block) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); aoqi@0: aoqi@0: // must copy state because it is modified aoqi@0: IntervalList* input_state = copy(state_for_block(block)); aoqi@0: aoqi@0: if (TraceLinearScanLevel >= 4) { aoqi@0: tty->print_cr("Input-State of intervals:"); aoqi@0: tty->print(" "); aoqi@0: for (int i = 0; i < state_size(); i++) { aoqi@0: if (input_state->at(i) != NULL) { aoqi@0: tty->print(" %4d", input_state->at(i)->reg_num()); aoqi@0: } else { aoqi@0: tty->print(" __"); aoqi@0: } aoqi@0: } aoqi@0: tty->cr(); aoqi@0: tty->cr(); aoqi@0: } aoqi@0: aoqi@0: // process all operations of the block aoqi@0: process_operations(block->lir(), input_state); aoqi@0: aoqi@0: // iterate all successors aoqi@0: for (int i = 0; i < block->number_of_sux(); i++) { aoqi@0: process_successor(block->sux_at(i), input_state); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); aoqi@0: aoqi@0: // must copy state because it is modified aoqi@0: input_state = copy(input_state); aoqi@0: aoqi@0: if (xhandler->entry_code() != NULL) { aoqi@0: process_operations(xhandler->entry_code(), input_state); aoqi@0: } aoqi@0: process_successor(xhandler->entry_block(), input_state); aoqi@0: } aoqi@0: aoqi@0: void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) { aoqi@0: IntervalList* saved_state = state_for_block(block); aoqi@0: aoqi@0: if (saved_state != NULL) { aoqi@0: // this block was already processed before. aoqi@0: // check if new input_state is consistent with saved_state aoqi@0: aoqi@0: bool saved_state_correct = true; aoqi@0: for (int i = 0; i < state_size(); i++) { aoqi@0: if (input_state->at(i) != saved_state->at(i)) { aoqi@0: // current input_state and previous saved_state assume a different aoqi@0: // interval in this register -> assume that this register is invalid aoqi@0: if (saved_state->at(i) != NULL) { aoqi@0: // invalidate old calculation only if it assumed that aoqi@0: // register was valid. when the register was already invalid, aoqi@0: // then the old calculation was correct. aoqi@0: saved_state_correct = false; aoqi@0: saved_state->at_put(i, NULL); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (saved_state_correct) { aoqi@0: // already processed block with correct input_state aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); aoqi@0: } else { aoqi@0: // must re-visit this block aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); aoqi@0: add_to_work_list(block); aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // block was not processed before, so set initial input_state aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); aoqi@0: aoqi@0: set_state_for_block(block, copy(input_state)); aoqi@0: add_to_work_list(block); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: IntervalList* RegisterVerifier::copy(IntervalList* input_state) { aoqi@0: IntervalList* copy_state = new IntervalList(input_state->length()); aoqi@0: copy_state->push_all(input_state); aoqi@0: return copy_state; aoqi@0: } aoqi@0: aoqi@0: void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) { aoqi@0: if (reg != LinearScan::any_reg && reg < state_size()) { aoqi@0: if (interval != NULL) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); aoqi@0: } else if (input_state->at(reg) != NULL) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); aoqi@0: } aoqi@0: aoqi@0: input_state->at_put(reg, interval); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) { aoqi@0: if (reg != LinearScan::any_reg && reg < state_size()) { aoqi@0: if (input_state->at(reg) != interval) { aoqi@0: tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); aoqi@0: return true; aoqi@0: } aoqi@0: } aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) { aoqi@0: // visit all instructions of the block aoqi@0: LIR_OpVisitState visitor; aoqi@0: bool has_error = false; aoqi@0: aoqi@0: for (int i = 0; i < ops->length(); i++) { aoqi@0: LIR_Op* op = ops->at(i); aoqi@0: visitor.visit(op); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, op->print_on(tty)); aoqi@0: aoqi@0: // check if input operands are correct aoqi@0: int j; aoqi@0: int n = visitor.opr_count(LIR_OpVisitState::inputMode); aoqi@0: for (j = 0; j < n; j++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); aoqi@0: if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { aoqi@0: Interval* interval = interval_at(reg_num(opr)); aoqi@0: if (op->id() != -1) { aoqi@0: interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); aoqi@0: } aoqi@0: aoqi@0: has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); aoqi@0: has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); aoqi@0: aoqi@0: // When an operand is marked with is_last_use, then the fpu stack allocator aoqi@0: // removes the register from the fpu stack -> the register contains no value aoqi@0: if (opr->is_last_use()) { aoqi@0: state_put(input_state, interval->assigned_reg(), NULL); aoqi@0: state_put(input_state, interval->assigned_regHi(), NULL); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // invalidate all caller save registers at calls aoqi@0: if (visitor.has_call()) { aoqi@0: for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) { aoqi@0: state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); aoqi@0: } aoqi@0: for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { aoqi@0: state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); aoqi@0: } aoqi@0: aoqi@0: #ifdef X86 aoqi@0: for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) { aoqi@0: state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: // process xhandler before output and temp operands aoqi@0: XHandlers* xhandlers = visitor.all_xhandler(); aoqi@0: n = xhandlers->length(); aoqi@0: for (int k = 0; k < n; k++) { aoqi@0: process_xhandler(xhandlers->handler_at(k), input_state); aoqi@0: } aoqi@0: aoqi@0: // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) aoqi@0: n = visitor.opr_count(LIR_OpVisitState::tempMode); aoqi@0: for (j = 0; j < n; j++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); aoqi@0: if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { aoqi@0: Interval* interval = interval_at(reg_num(opr)); aoqi@0: if (op->id() != -1) { aoqi@0: interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); aoqi@0: } aoqi@0: aoqi@0: state_put(input_state, interval->assigned_reg(), interval->split_parent()); aoqi@0: state_put(input_state, interval->assigned_regHi(), interval->split_parent()); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // set output operands aoqi@0: n = visitor.opr_count(LIR_OpVisitState::outputMode); aoqi@0: for (j = 0; j < n; j++) { aoqi@0: LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); aoqi@0: if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { aoqi@0: Interval* interval = interval_at(reg_num(opr)); aoqi@0: if (op->id() != -1) { aoqi@0: interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); aoqi@0: } aoqi@0: aoqi@0: state_put(input_state, interval->assigned_reg(), interval->split_parent()); aoqi@0: state_put(input_state, interval->assigned_regHi(), interval->split_parent()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: assert(has_error == false, "Error in register allocation"); aoqi@0: } aoqi@0: aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: aoqi@0: aoqi@0: // **** Implementation of MoveResolver ****************************** aoqi@0: aoqi@0: MoveResolver::MoveResolver(LinearScan* allocator) : aoqi@0: _allocator(allocator), aoqi@0: _multiple_reads_allowed(false), aoqi@0: _mapping_from(8), aoqi@0: _mapping_from_opr(8), aoqi@0: _mapping_to(8), aoqi@0: _insert_list(NULL), aoqi@0: _insert_idx(-1), aoqi@0: _insertion_buffer() aoqi@0: { aoqi@0: for (int i = 0; i < LinearScan::nof_regs; i++) { aoqi@0: _register_blocked[i] = 0; aoqi@0: } aoqi@0: DEBUG_ONLY(check_empty()); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: aoqi@0: void MoveResolver::check_empty() { aoqi@0: assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); aoqi@0: for (int i = 0; i < LinearScan::nof_regs; i++) { aoqi@0: assert(register_blocked(i) == 0, "register map must be empty before and after processing"); aoqi@0: } aoqi@0: assert(_multiple_reads_allowed == false, "must have default value"); aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::verify_before_resolve() { aoqi@0: assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); aoqi@0: assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); aoqi@0: assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); aoqi@0: aoqi@0: int i, j; aoqi@0: if (!_multiple_reads_allowed) { aoqi@0: for (i = 0; i < _mapping_from.length(); i++) { aoqi@0: for (j = i + 1; j < _mapping_from.length(); j++) { aoqi@0: assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: for (i = 0; i < _mapping_to.length(); i++) { aoqi@0: for (j = i + 1; j < _mapping_to.length(); j++) { aoqi@0: assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); aoqi@0: used_regs.clear(); aoqi@0: if (!_multiple_reads_allowed) { aoqi@0: for (i = 0; i < _mapping_from.length(); i++) { aoqi@0: Interval* it = _mapping_from.at(i); aoqi@0: if (it != NULL) { aoqi@0: assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); aoqi@0: used_regs.set_bit(it->assigned_reg()); aoqi@0: aoqi@0: if (it->assigned_regHi() != LinearScan::any_reg) { aoqi@0: assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); aoqi@0: used_regs.set_bit(it->assigned_regHi()); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: used_regs.clear(); aoqi@0: for (i = 0; i < _mapping_to.length(); i++) { aoqi@0: Interval* it = _mapping_to.at(i); aoqi@0: assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); aoqi@0: used_regs.set_bit(it->assigned_reg()); aoqi@0: aoqi@0: if (it->assigned_regHi() != LinearScan::any_reg) { aoqi@0: assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); aoqi@0: used_regs.set_bit(it->assigned_regHi()); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: used_regs.clear(); aoqi@0: for (i = 0; i < _mapping_from.length(); i++) { aoqi@0: Interval* it = _mapping_from.at(i); aoqi@0: if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { aoqi@0: used_regs.set_bit(it->assigned_reg()); aoqi@0: } aoqi@0: } aoqi@0: for (i = 0; i < _mapping_to.length(); i++) { aoqi@0: Interval* it = _mapping_to.at(i); aoqi@0: assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: aoqi@0: // mark assigned_reg and assigned_regHi of the interval as blocked aoqi@0: void MoveResolver::block_registers(Interval* it) { aoqi@0: int reg = it->assigned_reg(); aoqi@0: if (reg < LinearScan::nof_regs) { aoqi@0: assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); aoqi@0: set_register_blocked(reg, 1); aoqi@0: } aoqi@0: reg = it->assigned_regHi(); aoqi@0: if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { aoqi@0: assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); aoqi@0: set_register_blocked(reg, 1); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // mark assigned_reg and assigned_regHi of the interval as unblocked aoqi@0: void MoveResolver::unblock_registers(Interval* it) { aoqi@0: int reg = it->assigned_reg(); aoqi@0: if (reg < LinearScan::nof_regs) { aoqi@0: assert(register_blocked(reg) > 0, "register already marked as unused"); aoqi@0: set_register_blocked(reg, -1); aoqi@0: } aoqi@0: reg = it->assigned_regHi(); aoqi@0: if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { aoqi@0: assert(register_blocked(reg) > 0, "register already marked as unused"); aoqi@0: set_register_blocked(reg, -1); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) aoqi@0: bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { aoqi@0: int from_reg = -1; aoqi@0: int from_regHi = -1; aoqi@0: if (from != NULL) { aoqi@0: from_reg = from->assigned_reg(); aoqi@0: from_regHi = from->assigned_regHi(); aoqi@0: } aoqi@0: aoqi@0: int reg = to->assigned_reg(); aoqi@0: if (reg < LinearScan::nof_regs) { aoqi@0: if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: reg = to->assigned_regHi(); aoqi@0: if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { aoqi@0: if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void MoveResolver::create_insertion_buffer(LIR_List* list) { aoqi@0: assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); aoqi@0: _insertion_buffer.init(list); aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::append_insertion_buffer() { aoqi@0: if (_insertion_buffer.initialized()) { aoqi@0: _insertion_buffer.lir_list()->append(&_insertion_buffer); aoqi@0: } aoqi@0: assert(!_insertion_buffer.initialized(), "must be uninitialized now"); aoqi@0: aoqi@0: _insert_list = NULL; aoqi@0: _insert_idx = -1; aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { aoqi@0: assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); aoqi@0: assert(from_interval->type() == to_interval->type(), "move between different types"); aoqi@0: assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); aoqi@0: assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); aoqi@0: aoqi@0: LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); aoqi@0: LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); aoqi@0: aoqi@0: if (!_multiple_reads_allowed) { aoqi@0: // the last_use flag is an optimization for FPU stack allocation. When the same aoqi@0: // input interval is used in more than one move, then it is too difficult to determine aoqi@0: // if this move is really the last use. aoqi@0: from_opr = from_opr->make_last_use(); aoqi@0: } aoqi@0: _insertion_buffer.move(_insert_idx, from_opr, to_opr); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { aoqi@0: assert(from_opr->type() == to_interval->type(), "move between different types"); aoqi@0: assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); aoqi@0: assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); aoqi@0: aoqi@0: LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); aoqi@0: _insertion_buffer.move(_insert_idx, from_opr, to_opr); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void MoveResolver::resolve_mappings() { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); aoqi@0: DEBUG_ONLY(verify_before_resolve()); aoqi@0: aoqi@0: // Block all registers that are used as input operands of a move. aoqi@0: // When a register is blocked, no move to this register is emitted. aoqi@0: // This is necessary for detecting cycles in moves. aoqi@0: int i; aoqi@0: for (i = _mapping_from.length() - 1; i >= 0; i--) { aoqi@0: Interval* from_interval = _mapping_from.at(i); aoqi@0: if (from_interval != NULL) { aoqi@0: block_registers(from_interval); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int spill_candidate = -1; aoqi@0: while (_mapping_from.length() > 0) { aoqi@0: bool processed_interval = false; aoqi@0: aoqi@0: for (i = _mapping_from.length() - 1; i >= 0; i--) { aoqi@0: Interval* from_interval = _mapping_from.at(i); aoqi@0: Interval* to_interval = _mapping_to.at(i); aoqi@0: aoqi@0: if (save_to_process_move(from_interval, to_interval)) { aoqi@0: // this inverval can be processed because target is free aoqi@0: if (from_interval != NULL) { aoqi@0: insert_move(from_interval, to_interval); aoqi@0: unblock_registers(from_interval); aoqi@0: } else { aoqi@0: insert_move(_mapping_from_opr.at(i), to_interval); aoqi@0: } aoqi@0: _mapping_from.remove_at(i); aoqi@0: _mapping_from_opr.remove_at(i); aoqi@0: _mapping_to.remove_at(i); aoqi@0: aoqi@0: processed_interval = true; aoqi@0: } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { aoqi@0: // this interval cannot be processed now because target is not free aoqi@0: // it starts in a register, so it is a possible candidate for spilling aoqi@0: spill_candidate = i; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (!processed_interval) { aoqi@0: // no move could be processed because there is a cycle in the move list aoqi@0: // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory aoqi@0: assert(spill_candidate != -1, "no interval in register for spilling found"); aoqi@0: aoqi@0: // create a new spill interval and assign a stack slot to it aoqi@0: Interval* from_interval = _mapping_from.at(spill_candidate); aoqi@0: Interval* spill_interval = new Interval(-1); aoqi@0: spill_interval->set_type(from_interval->type()); aoqi@0: aoqi@0: // add a dummy range because real position is difficult to calculate aoqi@0: // Note: this range is a special case when the integrity of the allocation is checked aoqi@0: spill_interval->add_range(1, 2); aoqi@0: aoqi@0: // do not allocate a new spill slot for temporary interval, but aoqi@0: // use spill slot assigned to from_interval. Otherwise moves from aoqi@0: // one stack slot to another can happen (not allowed by LIR_Assembler aoqi@0: int spill_slot = from_interval->canonical_spill_slot(); aoqi@0: if (spill_slot < 0) { aoqi@0: spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); aoqi@0: from_interval->set_canonical_spill_slot(spill_slot); aoqi@0: } aoqi@0: spill_interval->assign_reg(spill_slot); aoqi@0: allocator()->append_interval(spill_interval); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); aoqi@0: aoqi@0: // insert a move from register to stack and update the mapping aoqi@0: insert_move(from_interval, spill_interval); aoqi@0: _mapping_from.at_put(spill_candidate, spill_interval); aoqi@0: unblock_registers(from_interval); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // reset to default value aoqi@0: _multiple_reads_allowed = false; aoqi@0: aoqi@0: // check that all intervals have been processed aoqi@0: DEBUG_ONLY(check_empty()); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); aoqi@0: assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); aoqi@0: aoqi@0: create_insertion_buffer(insert_list); aoqi@0: _insert_list = insert_list; aoqi@0: _insert_idx = insert_idx; aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); aoqi@0: aoqi@0: if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { aoqi@0: // insert position changed -> resolve current mappings aoqi@0: resolve_mappings(); aoqi@0: } aoqi@0: aoqi@0: if (insert_list != _insert_list) { aoqi@0: // block changed -> append insertion_buffer because it is aoqi@0: // bound to a specific block and create a new insertion_buffer aoqi@0: append_insertion_buffer(); aoqi@0: create_insertion_buffer(insert_list); aoqi@0: } aoqi@0: aoqi@0: _insert_list = insert_list; aoqi@0: _insert_idx = insert_idx; aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); aoqi@0: aoqi@0: _mapping_from.append(from_interval); aoqi@0: _mapping_from_opr.append(LIR_OprFact::illegalOpr); aoqi@0: _mapping_to.append(to_interval); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); aoqi@0: assert(from_opr->is_constant(), "only for constants"); aoqi@0: aoqi@0: _mapping_from.append(NULL); aoqi@0: _mapping_from_opr.append(from_opr); aoqi@0: _mapping_to.append(to_interval); aoqi@0: } aoqi@0: aoqi@0: void MoveResolver::resolve_and_append_moves() { aoqi@0: if (has_mappings()) { aoqi@0: resolve_mappings(); aoqi@0: } aoqi@0: append_insertion_buffer(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: aoqi@0: // **** Implementation of Range ************************************* aoqi@0: aoqi@0: Range::Range(int from, int to, Range* next) : aoqi@0: _from(from), aoqi@0: _to(to), aoqi@0: _next(next) aoqi@0: { aoqi@0: } aoqi@0: aoqi@0: // initialize sentinel aoqi@0: Range* Range::_end = NULL; aoqi@0: void Range::initialize(Arena* arena) { aoqi@0: _end = new (arena) Range(max_jint, max_jint, NULL); aoqi@0: } aoqi@0: aoqi@0: int Range::intersects_at(Range* r2) const { aoqi@0: const Range* r1 = this; aoqi@0: aoqi@0: assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); aoqi@0: assert(r1 != _end && r2 != _end, "empty ranges not allowed"); aoqi@0: aoqi@0: do { aoqi@0: if (r1->from() < r2->from()) { aoqi@0: if (r1->to() <= r2->from()) { aoqi@0: r1 = r1->next(); if (r1 == _end) return -1; aoqi@0: } else { aoqi@0: return r2->from(); aoqi@0: } aoqi@0: } else if (r2->from() < r1->from()) { aoqi@0: if (r2->to() <= r1->from()) { aoqi@0: r2 = r2->next(); if (r2 == _end) return -1; aoqi@0: } else { aoqi@0: return r1->from(); aoqi@0: } aoqi@0: } else { // r1->from() == r2->from() aoqi@0: if (r1->from() == r1->to()) { aoqi@0: r1 = r1->next(); if (r1 == _end) return -1; aoqi@0: } else if (r2->from() == r2->to()) { aoqi@0: r2 = r2->next(); if (r2 == _end) return -1; aoqi@0: } else { aoqi@0: return r1->from(); aoqi@0: } aoqi@0: } aoqi@0: } while (true); aoqi@0: } aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: void Range::print(outputStream* out) const { aoqi@0: out->print("[%d, %d[ ", _from, _to); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: aoqi@0: // **** Implementation of Interval ********************************** aoqi@0: aoqi@0: // initialize sentinel aoqi@0: Interval* Interval::_end = NULL; aoqi@0: void Interval::initialize(Arena* arena) { aoqi@0: Range::initialize(arena); aoqi@0: _end = new (arena) Interval(-1); aoqi@0: } aoqi@0: aoqi@0: Interval::Interval(int reg_num) : aoqi@0: _reg_num(reg_num), aoqi@0: _type(T_ILLEGAL), aoqi@0: _first(Range::end()), aoqi@0: _use_pos_and_kinds(12), aoqi@0: _current(Range::end()), aoqi@0: _next(_end), aoqi@0: _state(invalidState), aoqi@0: _assigned_reg(LinearScan::any_reg), aoqi@0: _assigned_regHi(LinearScan::any_reg), aoqi@0: _cached_to(-1), aoqi@0: _cached_opr(LIR_OprFact::illegalOpr), aoqi@0: _cached_vm_reg(VMRegImpl::Bad()), aoqi@0: _split_children(0), aoqi@0: _canonical_spill_slot(-1), aoqi@0: _insert_move_when_activated(false), aoqi@0: _register_hint(NULL), aoqi@0: _spill_state(noDefinitionFound), aoqi@0: _spill_definition_pos(-1) aoqi@0: { aoqi@0: _split_parent = this; aoqi@0: _current_split_child = this; aoqi@0: } aoqi@0: aoqi@0: int Interval::calc_to() { aoqi@0: assert(_first != Range::end(), "interval has no range"); aoqi@0: aoqi@0: Range* r = _first; aoqi@0: while (r->next() != Range::end()) { aoqi@0: r = r->next(); aoqi@0: } aoqi@0: return r->to(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: // consistency check of split-children aoqi@0: void Interval::check_split_children() { aoqi@0: if (_split_children.length() > 0) { aoqi@0: assert(is_split_parent(), "only split parents can have children"); aoqi@0: aoqi@0: for (int i = 0; i < _split_children.length(); i++) { aoqi@0: Interval* i1 = _split_children.at(i); aoqi@0: aoqi@0: assert(i1->split_parent() == this, "not a split child of this interval"); aoqi@0: assert(i1->type() == type(), "must be equal for all split children"); aoqi@0: assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); aoqi@0: aoqi@0: for (int j = i + 1; j < _split_children.length(); j++) { aoqi@0: Interval* i2 = _split_children.at(j); aoqi@0: aoqi@0: assert(i1->reg_num() != i2->reg_num(), "same register number"); aoqi@0: aoqi@0: if (i1->from() < i2->from()) { aoqi@0: assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); aoqi@0: } else { aoqi@0: assert(i2->from() < i1->from(), "intervals start at same op_id"); aoqi@0: assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: #endif // ASSERT aoqi@0: aoqi@0: Interval* Interval::register_hint(bool search_split_child) const { aoqi@0: if (!search_split_child) { aoqi@0: return _register_hint; aoqi@0: } aoqi@0: aoqi@0: if (_register_hint != NULL) { aoqi@0: assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); aoqi@0: aoqi@0: if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { aoqi@0: return _register_hint; aoqi@0: aoqi@0: } else if (_register_hint->_split_children.length() > 0) { aoqi@0: // search the first split child that has a register assigned aoqi@0: int len = _register_hint->_split_children.length(); aoqi@0: for (int i = 0; i < len; i++) { aoqi@0: Interval* cur = _register_hint->_split_children.at(i); aoqi@0: aoqi@0: if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { aoqi@0: return cur; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // no hint interval found that has a register assigned aoqi@0: return NULL; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { aoqi@0: assert(is_split_parent(), "can only be called for split parents"); aoqi@0: assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); aoqi@0: aoqi@0: Interval* result; aoqi@0: if (_split_children.length() == 0) { aoqi@0: result = this; aoqi@0: } else { aoqi@0: result = NULL; aoqi@0: int len = _split_children.length(); aoqi@0: aoqi@0: // in outputMode, the end of the interval (op_id == cur->to()) is not valid aoqi@0: int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); aoqi@0: aoqi@0: int i; aoqi@0: for (i = 0; i < len; i++) { aoqi@0: Interval* cur = _split_children.at(i); aoqi@0: if (cur->from() <= op_id && op_id < cur->to() + to_offset) { aoqi@0: if (i > 0) { aoqi@0: // exchange current split child to start of list (faster access for next call) aoqi@0: _split_children.at_put(i, _split_children.at(0)); aoqi@0: _split_children.at_put(0, cur); aoqi@0: } aoqi@0: aoqi@0: // interval found aoqi@0: result = cur; aoqi@0: break; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: for (i = 0; i < len; i++) { aoqi@0: Interval* tmp = _split_children.at(i); aoqi@0: if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { aoqi@0: tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); aoqi@0: result->print(); aoqi@0: tmp->print(); aoqi@0: assert(false, "two valid result intervals found"); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: assert(result != NULL, "no matching interval found"); aoqi@0: assert(result->covers(op_id, mode), "op_id not covered by interval"); aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // returns the last split child that ends before the given op_id aoqi@0: Interval* Interval::split_child_before_op_id(int op_id) { aoqi@0: assert(op_id >= 0, "invalid op_id"); aoqi@0: aoqi@0: Interval* parent = split_parent(); aoqi@0: Interval* result = NULL; aoqi@0: aoqi@0: int len = parent->_split_children.length(); aoqi@0: assert(len > 0, "no split children available"); aoqi@0: aoqi@0: for (int i = len - 1; i >= 0; i--) { aoqi@0: Interval* cur = parent->_split_children.at(i); aoqi@0: if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { aoqi@0: result = cur; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: assert(result != NULL, "no split child found"); aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // checks if op_id is covered by any split child aoqi@0: bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { aoqi@0: assert(is_split_parent(), "can only be called for split parents"); aoqi@0: assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); aoqi@0: aoqi@0: if (_split_children.length() == 0) { aoqi@0: // simple case if interval was not split aoqi@0: return covers(op_id, mode); aoqi@0: aoqi@0: } else { aoqi@0: // extended case: check all split children aoqi@0: int len = _split_children.length(); aoqi@0: for (int i = 0; i < len; i++) { aoqi@0: Interval* cur = _split_children.at(i); aoqi@0: if (cur->covers(op_id, mode)) { aoqi@0: return true; aoqi@0: } aoqi@0: } aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Note: use positions are sorted descending -> first use has highest index aoqi@0: int Interval::first_usage(IntervalUseKind min_use_kind) const { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); aoqi@0: aoqi@0: for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { aoqi@0: if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { aoqi@0: return _use_pos_and_kinds.at(i); aoqi@0: } aoqi@0: } aoqi@0: return max_jint; aoqi@0: } aoqi@0: aoqi@0: int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); aoqi@0: aoqi@0: for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { aoqi@0: if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { aoqi@0: return _use_pos_and_kinds.at(i); aoqi@0: } aoqi@0: } aoqi@0: return max_jint; aoqi@0: } aoqi@0: aoqi@0: int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); aoqi@0: aoqi@0: for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { aoqi@0: if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { aoqi@0: return _use_pos_and_kinds.at(i); aoqi@0: } aoqi@0: } aoqi@0: return max_jint; aoqi@0: } aoqi@0: aoqi@0: int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); aoqi@0: aoqi@0: int prev = 0; aoqi@0: for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { aoqi@0: if (_use_pos_and_kinds.at(i) > from) { aoqi@0: return prev; aoqi@0: } aoqi@0: if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { aoqi@0: prev = _use_pos_and_kinds.at(i); aoqi@0: } aoqi@0: } aoqi@0: return prev; aoqi@0: } aoqi@0: aoqi@0: void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { aoqi@0: assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); aoqi@0: aoqi@0: // do not add use positions for precolored intervals because aoqi@0: // they are never used aoqi@0: if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { aoqi@0: #ifdef ASSERT aoqi@0: assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); aoqi@0: for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { aoqi@0: assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); aoqi@0: assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); aoqi@0: if (i > 0) { aoqi@0: assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // Note: add_use is called in descending order, so list gets sorted aoqi@0: // automatically by just appending new use positions aoqi@0: int len = _use_pos_and_kinds.length(); aoqi@0: if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { aoqi@0: _use_pos_and_kinds.append(pos); aoqi@0: _use_pos_and_kinds.append(use_kind); aoqi@0: } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { aoqi@0: assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); aoqi@0: _use_pos_and_kinds.at_put(len - 1, use_kind); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void Interval::add_range(int from, int to) { aoqi@0: assert(from < to, "invalid range"); aoqi@0: assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); aoqi@0: assert(from <= first()->to(), "not inserting at begin of interval"); aoqi@0: aoqi@0: if (first()->from() <= to) { aoqi@0: // join intersecting ranges aoqi@0: first()->set_from(MIN2(from, first()->from())); aoqi@0: first()->set_to (MAX2(to, first()->to())); aoqi@0: } else { aoqi@0: // insert new range aoqi@0: _first = new Range(from, to, first()); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: Interval* Interval::new_split_child() { aoqi@0: // allocate new interval aoqi@0: Interval* result = new Interval(-1); aoqi@0: result->set_type(type()); aoqi@0: aoqi@0: Interval* parent = split_parent(); aoqi@0: result->_split_parent = parent; aoqi@0: result->set_register_hint(parent); aoqi@0: aoqi@0: // insert new interval in children-list of parent aoqi@0: if (parent->_split_children.length() == 0) { aoqi@0: assert(is_split_parent(), "list must be initialized at first split"); aoqi@0: aoqi@0: parent->_split_children = IntervalList(4); aoqi@0: parent->_split_children.append(this); aoqi@0: } aoqi@0: parent->_split_children.append(result); aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: // split this interval at the specified position and return aoqi@0: // the remainder as a new interval. aoqi@0: // aoqi@0: // when an interval is split, a bi-directional link is established between the original interval aoqi@0: // (the split parent) and the intervals that are split off this interval (the split children) aoqi@0: // When a split child is split again, the new created interval is also a direct child aoqi@0: // of the original parent (there is no tree of split children stored, but a flat list) aoqi@0: // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) aoqi@0: // aoqi@0: // Note: The new interval has no valid reg_num aoqi@0: Interval* Interval::split(int split_pos) { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); aoqi@0: aoqi@0: // allocate new interval aoqi@0: Interval* result = new_split_child(); aoqi@0: aoqi@0: // split the ranges aoqi@0: Range* prev = NULL; aoqi@0: Range* cur = _first; aoqi@0: while (cur != Range::end() && cur->to() <= split_pos) { aoqi@0: prev = cur; aoqi@0: cur = cur->next(); aoqi@0: } aoqi@0: assert(cur != Range::end(), "split interval after end of last range"); aoqi@0: aoqi@0: if (cur->from() < split_pos) { aoqi@0: result->_first = new Range(split_pos, cur->to(), cur->next()); aoqi@0: cur->set_to(split_pos); aoqi@0: cur->set_next(Range::end()); aoqi@0: aoqi@0: } else { aoqi@0: assert(prev != NULL, "split before start of first range"); aoqi@0: result->_first = cur; aoqi@0: prev->set_next(Range::end()); aoqi@0: } aoqi@0: result->_current = result->_first; aoqi@0: _cached_to = -1; // clear cached value aoqi@0: aoqi@0: // split list of use positions aoqi@0: int total_len = _use_pos_and_kinds.length(); aoqi@0: int start_idx = total_len - 2; aoqi@0: while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { aoqi@0: start_idx -= 2; aoqi@0: } aoqi@0: aoqi@0: intStack new_use_pos_and_kinds(total_len - start_idx); aoqi@0: int i; aoqi@0: for (i = start_idx + 2; i < total_len; i++) { aoqi@0: new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); aoqi@0: } aoqi@0: aoqi@0: _use_pos_and_kinds.truncate(start_idx + 2); aoqi@0: result->_use_pos_and_kinds = _use_pos_and_kinds; aoqi@0: _use_pos_and_kinds = new_use_pos_and_kinds; aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); aoqi@0: assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); aoqi@0: assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); aoqi@0: aoqi@0: for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { aoqi@0: assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); aoqi@0: assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); aoqi@0: } aoqi@0: for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { aoqi@0: assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); aoqi@0: assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: // split this interval at the specified position and return aoqi@0: // the head as a new interval (the original interval is the tail) aoqi@0: // aoqi@0: // Currently, only the first range can be split, and the new interval aoqi@0: // must not have split positions aoqi@0: Interval* Interval::split_from_start(int split_pos) { aoqi@0: assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); aoqi@0: assert(split_pos > from() && split_pos < to(), "can only split inside interval"); aoqi@0: assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); aoqi@0: assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); aoqi@0: aoqi@0: // allocate new interval aoqi@0: Interval* result = new_split_child(); aoqi@0: aoqi@0: // the new created interval has only one range (checked by assertion above), aoqi@0: // so the splitting of the ranges is very simple aoqi@0: result->add_range(_first->from(), split_pos); aoqi@0: aoqi@0: if (split_pos == _first->to()) { aoqi@0: assert(_first->next() != Range::end(), "must not be at end"); aoqi@0: _first = _first->next(); aoqi@0: } else { aoqi@0: _first->set_from(split_pos); aoqi@0: } aoqi@0: aoqi@0: return result; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // returns true if the op_id is inside the interval aoqi@0: bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { aoqi@0: Range* cur = _first; aoqi@0: aoqi@0: while (cur != Range::end() && cur->to() < op_id) { aoqi@0: cur = cur->next(); aoqi@0: } aoqi@0: if (cur != Range::end()) { aoqi@0: assert(cur->to() != cur->next()->from(), "ranges not separated"); aoqi@0: aoqi@0: if (mode == LIR_OpVisitState::outputMode) { aoqi@0: return cur->from() <= op_id && op_id < cur->to(); aoqi@0: } else { aoqi@0: return cur->from() <= op_id && op_id <= cur->to(); aoqi@0: } aoqi@0: } aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: // returns true if the interval has any hole between hole_from and hole_to aoqi@0: // (even if the hole has only the length 1) aoqi@0: bool Interval::has_hole_between(int hole_from, int hole_to) { aoqi@0: assert(hole_from < hole_to, "check"); aoqi@0: assert(from() <= hole_from && hole_to <= to(), "index out of interval"); aoqi@0: aoqi@0: Range* cur = _first; aoqi@0: while (cur != Range::end()) { aoqi@0: assert(cur->to() < cur->next()->from(), "no space between ranges"); aoqi@0: aoqi@0: // hole-range starts before this range -> hole aoqi@0: if (hole_from < cur->from()) { aoqi@0: return true; aoqi@0: aoqi@0: // hole-range completely inside this range -> no hole aoqi@0: } else if (hole_to <= cur->to()) { aoqi@0: return false; aoqi@0: aoqi@0: // overlapping of hole-range with this range -> hole aoqi@0: } else if (hole_from <= cur->to()) { aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: cur = cur->next(); aoqi@0: } aoqi@0: aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: void Interval::print(outputStream* out) const { aoqi@0: const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; aoqi@0: const char* UseKind2Name[] = { "N", "L", "S", "M" }; aoqi@0: aoqi@0: const char* type_name; aoqi@0: LIR_Opr opr = LIR_OprFact::illegal(); aoqi@0: if (reg_num() < LIR_OprDesc::vreg_base) { aoqi@0: type_name = "fixed"; aoqi@0: // need a temporary operand for fixed intervals because type() cannot be called aoqi@0: if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { aoqi@0: opr = LIR_OprFact::single_cpu(assigned_reg()); aoqi@0: } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { aoqi@0: opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); aoqi@0: #ifdef X86 aoqi@0: } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) { aoqi@0: opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); aoqi@0: #endif aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: } else { aoqi@0: type_name = type2name(type()); aoqi@0: if (assigned_reg() != -1 && aoqi@0: (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) { aoqi@0: opr = LinearScan::calc_operand_for_interval(this); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: out->print("%d %s ", reg_num(), type_name); aoqi@0: if (opr->is_valid()) { aoqi@0: out->print("\""); aoqi@0: opr->print(out); aoqi@0: out->print("\" "); aoqi@0: } aoqi@0: out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); aoqi@0: aoqi@0: // print ranges aoqi@0: Range* cur = _first; aoqi@0: while (cur != Range::end()) { aoqi@0: cur->print(out); aoqi@0: cur = cur->next(); aoqi@0: assert(cur != NULL, "range list not closed with range sentinel"); aoqi@0: } aoqi@0: aoqi@0: // print use positions aoqi@0: int prev = 0; aoqi@0: assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); aoqi@0: for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { aoqi@0: assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); aoqi@0: assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); aoqi@0: aoqi@0: out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); aoqi@0: prev = _use_pos_and_kinds.at(i); aoqi@0: } aoqi@0: aoqi@0: out->print(" \"%s\"", SpillState2Name[spill_state()]); aoqi@0: out->cr(); aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: aoqi@0: // **** Implementation of IntervalWalker **************************** aoqi@0: aoqi@0: IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) aoqi@0: : _compilation(allocator->compilation()) aoqi@0: , _allocator(allocator) aoqi@0: { aoqi@0: _unhandled_first[fixedKind] = unhandled_fixed_first; aoqi@0: _unhandled_first[anyKind] = unhandled_any_first; aoqi@0: _active_first[fixedKind] = Interval::end(); aoqi@0: _inactive_first[fixedKind] = Interval::end(); aoqi@0: _active_first[anyKind] = Interval::end(); aoqi@0: _inactive_first[anyKind] = Interval::end(); aoqi@0: _current_position = -1; aoqi@0: _current = NULL; aoqi@0: next_interval(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // append interval at top of list aoqi@0: void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { aoqi@0: interval->set_next(*list); *list = interval; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // append interval in order of current range from() aoqi@0: void IntervalWalker::append_sorted(Interval** list, Interval* interval) { aoqi@0: Interval* prev = NULL; aoqi@0: Interval* cur = *list; aoqi@0: while (cur->current_from() < interval->current_from()) { aoqi@0: prev = cur; cur = cur->next(); aoqi@0: } aoqi@0: if (prev == NULL) { aoqi@0: *list = interval; aoqi@0: } else { aoqi@0: prev->set_next(interval); aoqi@0: } aoqi@0: interval->set_next(cur); aoqi@0: } aoqi@0: aoqi@0: void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { aoqi@0: assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); aoqi@0: aoqi@0: Interval* prev = NULL; aoqi@0: Interval* cur = *list; aoqi@0: while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { aoqi@0: prev = cur; cur = cur->next(); aoqi@0: } aoqi@0: if (prev == NULL) { aoqi@0: *list = interval; aoqi@0: } else { aoqi@0: prev->set_next(interval); aoqi@0: } aoqi@0: interval->set_next(cur); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { aoqi@0: while (*list != Interval::end() && *list != i) { aoqi@0: list = (*list)->next_addr(); aoqi@0: } aoqi@0: if (*list != Interval::end()) { aoqi@0: assert(*list == i, "check"); aoqi@0: *list = (*list)->next(); aoqi@0: return true; aoqi@0: } else { aoqi@0: return false; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void IntervalWalker::remove_from_list(Interval* i) { aoqi@0: bool deleted; aoqi@0: aoqi@0: if (i->state() == activeState) { aoqi@0: deleted = remove_from_list(active_first_addr(anyKind), i); aoqi@0: } else { aoqi@0: assert(i->state() == inactiveState, "invalid state"); aoqi@0: deleted = remove_from_list(inactive_first_addr(anyKind), i); aoqi@0: } aoqi@0: aoqi@0: assert(deleted, "interval has not been found in list"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void IntervalWalker::walk_to(IntervalState state, int from) { aoqi@0: assert (state == activeState || state == inactiveState, "wrong state"); aoqi@0: for_each_interval_kind(kind) { aoqi@0: Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); aoqi@0: Interval* next = *prev; aoqi@0: while (next->current_from() <= from) { aoqi@0: Interval* cur = next; aoqi@0: next = cur->next(); aoqi@0: aoqi@0: bool range_has_changed = false; aoqi@0: while (cur->current_to() <= from) { aoqi@0: cur->next_range(); aoqi@0: range_has_changed = true; aoqi@0: } aoqi@0: aoqi@0: // also handle move from inactive list to active list aoqi@0: range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); aoqi@0: aoqi@0: if (range_has_changed) { aoqi@0: // remove cur from list aoqi@0: *prev = next; aoqi@0: if (cur->current_at_end()) { aoqi@0: // move to handled state (not maintained as a list) aoqi@0: cur->set_state(handledState); aoqi@0: interval_moved(cur, kind, state, handledState); aoqi@0: } else if (cur->current_from() <= from){ aoqi@0: // sort into active list aoqi@0: append_sorted(active_first_addr(kind), cur); aoqi@0: cur->set_state(activeState); aoqi@0: if (*prev == cur) { aoqi@0: assert(state == activeState, "check"); aoqi@0: prev = cur->next_addr(); aoqi@0: } aoqi@0: interval_moved(cur, kind, state, activeState); aoqi@0: } else { aoqi@0: // sort into inactive list aoqi@0: append_sorted(inactive_first_addr(kind), cur); aoqi@0: cur->set_state(inactiveState); aoqi@0: if (*prev == cur) { aoqi@0: assert(state == inactiveState, "check"); aoqi@0: prev = cur->next_addr(); aoqi@0: } aoqi@0: interval_moved(cur, kind, state, inactiveState); aoqi@0: } aoqi@0: } else { aoqi@0: prev = cur->next_addr(); aoqi@0: continue; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void IntervalWalker::next_interval() { aoqi@0: IntervalKind kind; aoqi@0: Interval* any = _unhandled_first[anyKind]; aoqi@0: Interval* fixed = _unhandled_first[fixedKind]; aoqi@0: aoqi@0: if (any != Interval::end()) { aoqi@0: // intervals may start at same position -> prefer fixed interval aoqi@0: kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; aoqi@0: aoqi@0: assert (kind == fixedKind && fixed->from() <= any->from() || aoqi@0: kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); aoqi@0: assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); aoqi@0: aoqi@0: } else if (fixed != Interval::end()) { aoqi@0: kind = fixedKind; aoqi@0: } else { aoqi@0: _current = NULL; return; aoqi@0: } aoqi@0: _current_kind = kind; aoqi@0: _current = _unhandled_first[kind]; aoqi@0: _unhandled_first[kind] = _current->next(); aoqi@0: _current->set_next(Interval::end()); aoqi@0: _current->rewind_range(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void IntervalWalker::walk_to(int lir_op_id) { aoqi@0: assert(_current_position <= lir_op_id, "can not walk backwards"); aoqi@0: while (current() != NULL) { aoqi@0: bool is_active = current()->from() <= lir_op_id; aoqi@0: int id = is_active ? current()->from() : lir_op_id; aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) aoqi@0: aoqi@0: // set _current_position prior to call of walk_to aoqi@0: _current_position = id; aoqi@0: aoqi@0: // call walk_to even if _current_position == id aoqi@0: walk_to(activeState, id); aoqi@0: walk_to(inactiveState, id); aoqi@0: aoqi@0: if (is_active) { aoqi@0: current()->set_state(activeState); aoqi@0: if (activate_current()) { aoqi@0: append_sorted(active_first_addr(current_kind()), current()); aoqi@0: interval_moved(current(), current_kind(), unhandledState, activeState); aoqi@0: } aoqi@0: aoqi@0: next_interval(); aoqi@0: } else { aoqi@0: return; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { aoqi@0: #ifndef PRODUCT aoqi@0: if (TraceLinearScanLevel >= 4) { aoqi@0: #define print_state(state) \ aoqi@0: switch(state) {\ aoqi@0: case unhandledState: tty->print("unhandled"); break;\ aoqi@0: case activeState: tty->print("active"); break;\ aoqi@0: case inactiveState: tty->print("inactive"); break;\ aoqi@0: case handledState: tty->print("handled"); break;\ aoqi@0: default: ShouldNotReachHere(); \ aoqi@0: } aoqi@0: aoqi@0: print_state(from); tty->print(" to "); print_state(to); aoqi@0: tty->fill_to(23); aoqi@0: interval->print(); aoqi@0: aoqi@0: #undef print_state aoqi@0: } aoqi@0: #endif aoqi@0: } aoqi@0: aoqi@0: aoqi@0: aoqi@0: // **** Implementation of LinearScanWalker ************************** aoqi@0: aoqi@0: LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) aoqi@0: : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) aoqi@0: , _move_resolver(allocator) aoqi@0: { aoqi@0: for (int i = 0; i < LinearScan::nof_regs; i++) { aoqi@0: _spill_intervals[i] = new IntervalList(2); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { aoqi@0: for (int i = _first_reg; i <= _last_reg; i++) { aoqi@0: _use_pos[i] = max_jint; aoqi@0: aoqi@0: if (!only_process_use_pos) { aoqi@0: _block_pos[i] = max_jint; aoqi@0: _spill_intervals[i]->clear(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: inline void LinearScanWalker::exclude_from_use(int reg) { aoqi@0: assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); aoqi@0: if (reg >= _first_reg && reg <= _last_reg) { aoqi@0: _use_pos[reg] = 0; aoqi@0: } aoqi@0: } aoqi@0: inline void LinearScanWalker::exclude_from_use(Interval* i) { aoqi@0: assert(i->assigned_reg() != any_reg, "interval has no register assigned"); aoqi@0: aoqi@0: exclude_from_use(i->assigned_reg()); aoqi@0: exclude_from_use(i->assigned_regHi()); aoqi@0: } aoqi@0: aoqi@0: inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { aoqi@0: assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); aoqi@0: aoqi@0: if (reg >= _first_reg && reg <= _last_reg) { aoqi@0: if (_use_pos[reg] > use_pos) { aoqi@0: _use_pos[reg] = use_pos; aoqi@0: } aoqi@0: if (!only_process_use_pos) { aoqi@0: _spill_intervals[reg]->append(i); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { aoqi@0: assert(i->assigned_reg() != any_reg, "interval has no register assigned"); aoqi@0: if (use_pos != -1) { aoqi@0: set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); aoqi@0: set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { aoqi@0: if (reg >= _first_reg && reg <= _last_reg) { aoqi@0: if (_block_pos[reg] > block_pos) { aoqi@0: _block_pos[reg] = block_pos; aoqi@0: } aoqi@0: if (_use_pos[reg] > block_pos) { aoqi@0: _use_pos[reg] = block_pos; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { aoqi@0: assert(i->assigned_reg() != any_reg, "interval has no register assigned"); aoqi@0: if (block_pos != -1) { aoqi@0: set_block_pos(i->assigned_reg(), i, block_pos); aoqi@0: set_block_pos(i->assigned_regHi(), i, block_pos); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScanWalker::free_exclude_active_fixed() { aoqi@0: Interval* list = active_first(fixedKind); aoqi@0: while (list != Interval::end()) { aoqi@0: assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); aoqi@0: exclude_from_use(list); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::free_exclude_active_any() { aoqi@0: Interval* list = active_first(anyKind); aoqi@0: while (list != Interval::end()) { aoqi@0: exclude_from_use(list); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { aoqi@0: Interval* list = inactive_first(fixedKind); aoqi@0: while (list != Interval::end()) { aoqi@0: if (cur->to() <= list->current_from()) { aoqi@0: assert(list->current_intersects_at(cur) == -1, "must not intersect"); aoqi@0: set_use_pos(list, list->current_from(), true); aoqi@0: } else { aoqi@0: set_use_pos(list, list->current_intersects_at(cur), true); aoqi@0: } aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::free_collect_inactive_any(Interval* cur) { aoqi@0: Interval* list = inactive_first(anyKind); aoqi@0: while (list != Interval::end()) { aoqi@0: set_use_pos(list, list->current_intersects_at(cur), true); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { aoqi@0: Interval* list = unhandled_first(kind); aoqi@0: while (list != Interval::end()) { aoqi@0: set_use_pos(list, list->intersects_at(cur), true); aoqi@0: if (kind == fixedKind && cur->to() <= list->from()) { aoqi@0: set_use_pos(list, list->from(), true); aoqi@0: } aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::spill_exclude_active_fixed() { aoqi@0: Interval* list = active_first(fixedKind); aoqi@0: while (list != Interval::end()) { aoqi@0: exclude_from_use(list); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { aoqi@0: Interval* list = unhandled_first(fixedKind); aoqi@0: while (list != Interval::end()) { aoqi@0: set_block_pos(list, list->intersects_at(cur)); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { aoqi@0: Interval* list = inactive_first(fixedKind); aoqi@0: while (list != Interval::end()) { aoqi@0: if (cur->to() > list->current_from()) { aoqi@0: set_block_pos(list, list->current_intersects_at(cur)); aoqi@0: } else { aoqi@0: assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); aoqi@0: } aoqi@0: aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::spill_collect_active_any() { aoqi@0: Interval* list = active_first(anyKind); aoqi@0: while (list != Interval::end()) { aoqi@0: set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { aoqi@0: Interval* list = inactive_first(anyKind); aoqi@0: while (list != Interval::end()) { aoqi@0: if (list->current_intersects(cur)) { aoqi@0: set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); aoqi@0: } aoqi@0: list = list->next(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { aoqi@0: // output all moves here. When source and target are equal, the move is aoqi@0: // optimized away later in assign_reg_nums aoqi@0: aoqi@0: op_id = (op_id + 1) & ~1; aoqi@0: BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); aoqi@0: assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); aoqi@0: aoqi@0: // calculate index of instruction inside instruction list of current block aoqi@0: // the minimal index (for a block with no spill moves) can be calculated because the aoqi@0: // numbering of instructions is known. aoqi@0: // When the block already contains spill moves, the index must be increased until the aoqi@0: // correct index is reached. aoqi@0: LIR_OpList* list = op_block->lir()->instructions_list(); aoqi@0: int index = (op_id - list->at(0)->id()) / 2; aoqi@0: assert(list->at(index)->id() <= op_id, "error in calculation"); aoqi@0: aoqi@0: while (list->at(index)->id() != op_id) { aoqi@0: index++; aoqi@0: assert(0 <= index && index < list->length(), "index out of bounds"); aoqi@0: } aoqi@0: assert(1 <= index && index < list->length(), "index out of bounds"); aoqi@0: assert(list->at(index)->id() == op_id, "error in calculation"); aoqi@0: aoqi@0: // insert new instruction before instruction at position index aoqi@0: _move_resolver.move_insert_position(op_block->lir(), index - 1); aoqi@0: _move_resolver.add_mapping(src_it, dst_it); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { aoqi@0: int from_block_nr = min_block->linear_scan_number(); aoqi@0: int to_block_nr = max_block->linear_scan_number(); aoqi@0: aoqi@0: assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); aoqi@0: assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); aoqi@0: assert(from_block_nr < to_block_nr, "must cross block boundary"); aoqi@0: aoqi@0: // Try to split at end of max_block. If this would be after aoqi@0: // max_split_pos, then use the begin of max_block aoqi@0: int optimal_split_pos = max_block->last_lir_instruction_id() + 2; aoqi@0: if (optimal_split_pos > max_split_pos) { aoqi@0: optimal_split_pos = max_block->first_lir_instruction_id(); aoqi@0: } aoqi@0: aoqi@0: int min_loop_depth = max_block->loop_depth(); aoqi@0: for (int i = to_block_nr - 1; i >= from_block_nr; i--) { aoqi@0: BlockBegin* cur = block_at(i); aoqi@0: aoqi@0: if (cur->loop_depth() < min_loop_depth) { aoqi@0: // block with lower loop-depth found -> split at the end of this block aoqi@0: min_loop_depth = cur->loop_depth(); aoqi@0: optimal_split_pos = cur->last_lir_instruction_id() + 2; aoqi@0: } aoqi@0: } aoqi@0: assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); aoqi@0: aoqi@0: return optimal_split_pos; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { aoqi@0: int optimal_split_pos = -1; aoqi@0: if (min_split_pos == max_split_pos) { aoqi@0: // trivial case, no optimization of split position possible aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); aoqi@0: optimal_split_pos = min_split_pos; aoqi@0: aoqi@0: } else { aoqi@0: assert(min_split_pos < max_split_pos, "must be true then"); aoqi@0: assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); aoqi@0: aoqi@0: // reason for using min_split_pos - 1: when the minimal split pos is exactly at the aoqi@0: // beginning of a block, then min_split_pos is also a possible split position. aoqi@0: // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos aoqi@0: BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); aoqi@0: aoqi@0: // reason for using max_split_pos - 1: otherwise there would be an assertion failure aoqi@0: // when an interval ends at the end of the last block of the method aoqi@0: // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no aoqi@0: // block at this op_id) aoqi@0: BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); aoqi@0: aoqi@0: assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); aoqi@0: if (min_block == max_block) { aoqi@0: // split position cannot be moved to block boundary, so split as late as possible aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); aoqi@0: optimal_split_pos = max_split_pos; aoqi@0: aoqi@0: } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { aoqi@0: // Do not move split position if the interval has a hole before max_split_pos. aoqi@0: // Intervals resulting from Phi-Functions have more than one definition (marked aoqi@0: // as mustHaveRegister) with a hole before each definition. When the register is needed aoqi@0: // for the second definition, an earlier reloading is unnecessary. aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); aoqi@0: optimal_split_pos = max_split_pos; aoqi@0: aoqi@0: } else { aoqi@0: // seach optimal block boundary between min_split_pos and max_split_pos aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); aoqi@0: aoqi@0: if (do_loop_optimization) { aoqi@0: // Loop optimization: if a loop-end marker is found between min- and max-position, aoqi@0: // then split before this loop aoqi@0: int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); aoqi@0: aoqi@0: assert(loop_end_pos > min_split_pos, "invalid order"); aoqi@0: if (loop_end_pos < max_split_pos) { aoqi@0: // loop-end marker found between min- and max-position aoqi@0: // if it is not the end marker for the same loop as the min-position, then move aoqi@0: // the max-position to this loop block. aoqi@0: // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading aoqi@0: // of the interval (normally, only mustHaveRegister causes a reloading) aoqi@0: BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); aoqi@0: assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); aoqi@0: aoqi@0: optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); aoqi@0: if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { aoqi@0: optimal_split_pos = -1; aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); aoqi@0: } else { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (optimal_split_pos == -1) { aoqi@0: // not calculated by loop optimization aoqi@0: optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); aoqi@0: aoqi@0: return optimal_split_pos; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: /* aoqi@0: split an interval at the optimal position between min_split_pos and aoqi@0: max_split_pos in two parts: aoqi@0: 1) the left part has already a location assigned aoqi@0: 2) the right part is sorted into to the unhandled-list aoqi@0: */ aoqi@0: void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); aoqi@0: aoqi@0: assert(it->from() < min_split_pos, "cannot split at start of interval"); aoqi@0: assert(current_position() < min_split_pos, "cannot split before current position"); aoqi@0: assert(min_split_pos <= max_split_pos, "invalid order"); aoqi@0: assert(max_split_pos <= it->to(), "cannot split after end of interval"); aoqi@0: aoqi@0: int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); aoqi@0: aoqi@0: assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); aoqi@0: assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); aoqi@0: assert(optimal_split_pos > it->from(), "cannot split at start of interval"); aoqi@0: aoqi@0: if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { aoqi@0: // the split position would be just before the end of the interval aoqi@0: // -> no split at all necessary aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: // must calculate this before the actual split is performed and before split position is moved to odd op_id aoqi@0: bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); aoqi@0: aoqi@0: if (!allocator()->is_block_begin(optimal_split_pos)) { aoqi@0: // move position before actual instruction (odd op_id) aoqi@0: optimal_split_pos = (optimal_split_pos - 1) | 1; aoqi@0: } aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); aoqi@0: assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); aoqi@0: assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); aoqi@0: aoqi@0: Interval* split_part = it->split(optimal_split_pos); aoqi@0: aoqi@0: allocator()->append_interval(split_part); aoqi@0: allocator()->copy_register_flags(it, split_part); aoqi@0: split_part->set_insert_move_when_activated(move_necessary); aoqi@0: append_to_unhandled(unhandled_first_addr(anyKind), split_part); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); aoqi@0: } aoqi@0: aoqi@0: /* aoqi@0: split an interval at the optimal position between min_split_pos and aoqi@0: max_split_pos in two parts: aoqi@0: 1) the left part has already a location assigned aoqi@0: 2) the right part is always on the stack and therefore ignored in further processing aoqi@0: */ aoqi@0: void LinearScanWalker::split_for_spilling(Interval* it) { aoqi@0: // calculate allowed range of splitting position aoqi@0: int max_split_pos = current_position(); aoqi@0: int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); aoqi@0: aoqi@0: assert(it->state() == activeState, "why spill interval that is not active?"); aoqi@0: assert(it->from() <= min_split_pos, "cannot split before start of interval"); aoqi@0: assert(min_split_pos <= max_split_pos, "invalid order"); aoqi@0: assert(max_split_pos < it->to(), "cannot split at end end of interval"); aoqi@0: assert(current_position() < it->to(), "interval must not end before current position"); aoqi@0: aoqi@0: if (min_split_pos == it->from()) { aoqi@0: // the whole interval is never used, so spill it entirely to memory aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); aoqi@0: assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); aoqi@0: aoqi@0: allocator()->assign_spill_slot(it); aoqi@0: allocator()->change_spill_state(it, min_split_pos); aoqi@0: aoqi@0: // Also kick parent intervals out of register to memory when they have no use aoqi@0: // position. This avoids short interval in register surrounded by intervals in aoqi@0: // memory -> avoid useless moves from memory to register and back aoqi@0: Interval* parent = it; aoqi@0: while (parent != NULL && parent->is_split_child()) { aoqi@0: parent = parent->split_child_before_op_id(parent->from()); aoqi@0: aoqi@0: if (parent->assigned_reg() < LinearScan::nof_regs) { aoqi@0: if (parent->first_usage(shouldHaveRegister) == max_jint) { aoqi@0: // parent is never used, so kick it out of its assigned register aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); aoqi@0: allocator()->assign_spill_slot(parent); aoqi@0: } else { aoqi@0: // do not go further back because the register is actually used by the interval aoqi@0: parent = NULL; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: } else { aoqi@0: // search optimal split pos, split interval and spill only the right hand part aoqi@0: int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); aoqi@0: aoqi@0: assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); aoqi@0: assert(optimal_split_pos < it->to(), "cannot split at end of interval"); aoqi@0: assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); aoqi@0: aoqi@0: if (!allocator()->is_block_begin(optimal_split_pos)) { aoqi@0: // move position before actual instruction (odd op_id) aoqi@0: optimal_split_pos = (optimal_split_pos - 1) | 1; aoqi@0: } aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); aoqi@0: assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); aoqi@0: assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); aoqi@0: aoqi@0: Interval* spilled_part = it->split(optimal_split_pos); aoqi@0: allocator()->append_interval(spilled_part); aoqi@0: allocator()->assign_spill_slot(spilled_part); aoqi@0: allocator()->change_spill_state(spilled_part, optimal_split_pos); aoqi@0: aoqi@0: if (!allocator()->is_block_begin(optimal_split_pos)) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); aoqi@0: insert_move(optimal_split_pos, it, spilled_part); aoqi@0: } aoqi@0: aoqi@0: // the current_split_child is needed later when moves are inserted for reloading aoqi@0: assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); aoqi@0: spilled_part->make_current_split_child(); aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void LinearScanWalker::split_stack_interval(Interval* it) { aoqi@0: int min_split_pos = current_position() + 1; aoqi@0: int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); aoqi@0: aoqi@0: split_before_usage(it, min_split_pos, max_split_pos); aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { aoqi@0: int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); aoqi@0: int max_split_pos = register_available_until; aoqi@0: aoqi@0: split_before_usage(it, min_split_pos, max_split_pos); aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::split_and_spill_interval(Interval* it) { aoqi@0: assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); aoqi@0: aoqi@0: int current_pos = current_position(); aoqi@0: if (it->state() == inactiveState) { aoqi@0: // the interval is currently inactive, so no spill slot is needed for now. aoqi@0: // when the split part is activated, the interval has a new chance to get a register, aoqi@0: // so in the best case no stack slot is necessary aoqi@0: assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); aoqi@0: split_before_usage(it, current_pos + 1, current_pos + 1); aoqi@0: aoqi@0: } else { aoqi@0: // search the position where the interval must have a register and split aoqi@0: // at the optimal position before. aoqi@0: // The new created part is added to the unhandled list and will get a register aoqi@0: // when it is activated aoqi@0: int min_split_pos = current_pos + 1; aoqi@0: int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); aoqi@0: aoqi@0: split_before_usage(it, min_split_pos, max_split_pos); aoqi@0: aoqi@0: assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); aoqi@0: split_for_spilling(it); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { aoqi@0: int min_full_reg = any_reg; aoqi@0: int max_partial_reg = any_reg; aoqi@0: aoqi@0: for (int i = _first_reg; i <= _last_reg; i++) { aoqi@0: if (i == ignore_reg) { aoqi@0: // this register must be ignored aoqi@0: aoqi@0: } else if (_use_pos[i] >= interval_to) { aoqi@0: // this register is free for the full interval aoqi@0: if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { aoqi@0: min_full_reg = i; aoqi@0: } aoqi@0: } else if (_use_pos[i] > reg_needed_until) { aoqi@0: // this register is at least free until reg_needed_until aoqi@0: if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { aoqi@0: max_partial_reg = i; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (min_full_reg != any_reg) { aoqi@0: return min_full_reg; aoqi@0: } else if (max_partial_reg != any_reg) { aoqi@0: *need_split = true; aoqi@0: return max_partial_reg; aoqi@0: } else { aoqi@0: return any_reg; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { aoqi@0: assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); aoqi@0: aoqi@0: int min_full_reg = any_reg; aoqi@0: int max_partial_reg = any_reg; aoqi@0: aoqi@0: for (int i = _first_reg; i < _last_reg; i+=2) { aoqi@0: if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { aoqi@0: // this register is free for the full interval aoqi@0: if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { aoqi@0: min_full_reg = i; aoqi@0: } aoqi@0: } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { aoqi@0: // this register is at least free until reg_needed_until aoqi@0: if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { aoqi@0: max_partial_reg = i; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (min_full_reg != any_reg) { aoqi@0: return min_full_reg; aoqi@0: } else if (max_partial_reg != any_reg) { aoqi@0: *need_split = true; aoqi@0: return max_partial_reg; aoqi@0: } else { aoqi@0: return any_reg; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: bool LinearScanWalker::alloc_free_reg(Interval* cur) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); aoqi@0: aoqi@0: init_use_lists(true); aoqi@0: free_exclude_active_fixed(); aoqi@0: free_exclude_active_any(); aoqi@0: free_collect_inactive_fixed(cur); aoqi@0: free_collect_inactive_any(cur); aoqi@0: // free_collect_unhandled(fixedKind, cur); aoqi@0: assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); aoqi@0: aoqi@0: // _use_pos contains the start of the next interval that has this register assigned aoqi@0: // (either as a fixed register or a normal allocated register in the past) aoqi@0: // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); aoqi@0: TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); aoqi@0: aoqi@0: int hint_reg, hint_regHi; aoqi@0: Interval* register_hint = cur->register_hint(); aoqi@0: if (register_hint != NULL) { aoqi@0: hint_reg = register_hint->assigned_reg(); aoqi@0: hint_regHi = register_hint->assigned_regHi(); aoqi@0: aoqi@0: if (allocator()->is_precolored_cpu_interval(register_hint)) { aoqi@0: assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); aoqi@0: hint_regHi = hint_reg + 1; // connect e.g. eax-edx aoqi@0: } aoqi@0: TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); aoqi@0: aoqi@0: } else { aoqi@0: hint_reg = any_reg; aoqi@0: hint_regHi = any_reg; aoqi@0: } aoqi@0: assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); aoqi@0: assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); aoqi@0: aoqi@0: // the register must be free at least until this position aoqi@0: int reg_needed_until = cur->from() + 1; aoqi@0: int interval_to = cur->to(); aoqi@0: aoqi@0: bool need_split = false; aoqi@0: int split_pos = -1; aoqi@0: int reg = any_reg; aoqi@0: int regHi = any_reg; aoqi@0: aoqi@0: if (_adjacent_regs) { aoqi@0: reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); aoqi@0: regHi = reg + 1; aoqi@0: if (reg == any_reg) { aoqi@0: return false; aoqi@0: } aoqi@0: split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); aoqi@0: aoqi@0: } else { aoqi@0: reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); aoqi@0: if (reg == any_reg) { aoqi@0: return false; aoqi@0: } aoqi@0: split_pos = _use_pos[reg]; aoqi@0: aoqi@0: if (_num_phys_regs == 2) { aoqi@0: regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); aoqi@0: aoqi@0: if (_use_pos[reg] < interval_to && regHi == any_reg) { aoqi@0: // do not split interval if only one register can be assigned until the split pos aoqi@0: // (when one register is found for the whole interval, split&spill is only aoqi@0: // performed for the hi register) aoqi@0: return false; aoqi@0: aoqi@0: } else if (regHi != any_reg) { aoqi@0: split_pos = MIN2(split_pos, _use_pos[regHi]); aoqi@0: aoqi@0: // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax aoqi@0: if (reg > regHi) { aoqi@0: int temp = reg; aoqi@0: reg = regHi; aoqi@0: regHi = temp; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: cur->assign_reg(reg, regHi); aoqi@0: TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); aoqi@0: aoqi@0: assert(split_pos > 0, "invalid split_pos"); aoqi@0: if (need_split) { aoqi@0: // register not available for full interval, so split it aoqi@0: split_when_partial_register_available(cur, split_pos); aoqi@0: } aoqi@0: aoqi@0: // only return true if interval is completely assigned aoqi@0: return _num_phys_regs == 1 || regHi != any_reg; aoqi@0: } aoqi@0: aoqi@0: aoqi@0: int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { aoqi@0: int max_reg = any_reg; aoqi@0: aoqi@0: for (int i = _first_reg; i <= _last_reg; i++) { aoqi@0: if (i == ignore_reg) { aoqi@0: // this register must be ignored aoqi@0: aoqi@0: } else if (_use_pos[i] > reg_needed_until) { aoqi@0: if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { aoqi@0: max_reg = i; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { aoqi@0: *need_split = true; aoqi@0: } aoqi@0: aoqi@0: return max_reg; aoqi@0: } aoqi@0: aoqi@0: int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { aoqi@0: assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); aoqi@0: aoqi@0: int max_reg = any_reg; aoqi@0: aoqi@0: for (int i = _first_reg; i < _last_reg; i+=2) { aoqi@0: if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { aoqi@0: if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { aoqi@0: max_reg = i; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) { aoqi@0: *need_split = true; aoqi@0: } aoqi@0: aoqi@0: return max_reg; aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { aoqi@0: assert(reg != any_reg, "no register assigned"); aoqi@0: aoqi@0: for (int i = 0; i < _spill_intervals[reg]->length(); i++) { aoqi@0: Interval* it = _spill_intervals[reg]->at(i); aoqi@0: remove_from_list(it); aoqi@0: split_and_spill_interval(it); aoqi@0: } aoqi@0: aoqi@0: if (regHi != any_reg) { aoqi@0: IntervalList* processed = _spill_intervals[reg]; aoqi@0: for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { aoqi@0: Interval* it = _spill_intervals[regHi]->at(i); aoqi@0: if (processed->index_of(it) == -1) { aoqi@0: remove_from_list(it); aoqi@0: split_and_spill_interval(it); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Split an Interval and spill it to memory so that cur can be placed in a register aoqi@0: void LinearScanWalker::alloc_locked_reg(Interval* cur) { aoqi@0: TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); aoqi@0: aoqi@0: // collect current usage of registers aoqi@0: init_use_lists(false); aoqi@0: spill_exclude_active_fixed(); aoqi@0: // spill_block_unhandled_fixed(cur); aoqi@0: assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); aoqi@0: spill_block_inactive_fixed(cur); aoqi@0: spill_collect_active_any(); aoqi@0: spill_collect_inactive_any(cur); aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: if (TraceLinearScanLevel >= 4) { aoqi@0: tty->print_cr(" state of registers:"); aoqi@0: for (int i = _first_reg; i <= _last_reg; i++) { aoqi@0: tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); aoqi@0: for (int j = 0; j < _spill_intervals[i]->length(); j++) { aoqi@0: tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); aoqi@0: } aoqi@0: tty->cr(); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // the register must be free at least until this position aoqi@0: int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); aoqi@0: int interval_to = cur->to(); aoqi@0: assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); aoqi@0: aoqi@0: int split_pos = 0; aoqi@0: int use_pos = 0; aoqi@0: bool need_split = false; aoqi@0: int reg, regHi; aoqi@0: aoqi@0: if (_adjacent_regs) { aoqi@0: reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); aoqi@0: regHi = reg + 1; aoqi@0: aoqi@0: if (reg != any_reg) { aoqi@0: use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); aoqi@0: split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); aoqi@0: } aoqi@0: } else { aoqi@0: reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); aoqi@0: regHi = any_reg; aoqi@0: aoqi@0: if (reg != any_reg) { aoqi@0: use_pos = _use_pos[reg]; aoqi@0: split_pos = _block_pos[reg]; aoqi@0: aoqi@0: if (_num_phys_regs == 2) { aoqi@0: if (cur->assigned_reg() != any_reg) { aoqi@0: regHi = reg; aoqi@0: reg = cur->assigned_reg(); aoqi@0: } else { aoqi@0: regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); aoqi@0: if (regHi != any_reg) { aoqi@0: use_pos = MIN2(use_pos, _use_pos[regHi]); aoqi@0: split_pos = MIN2(split_pos, _block_pos[regHi]); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (regHi != any_reg && reg > regHi) { aoqi@0: // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax aoqi@0: int temp = reg; aoqi@0: reg = regHi; aoqi@0: regHi = temp; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { aoqi@0: // the first use of cur is later than the spilling position -> spill cur aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); aoqi@0: aoqi@0: if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { aoqi@0: assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); aoqi@0: // assign a reasonable register and do a bailout in product mode to avoid errors aoqi@0: allocator()->assign_spill_slot(cur); aoqi@0: BAILOUT("LinearScan: no register found"); aoqi@0: } aoqi@0: aoqi@0: split_and_spill_interval(cur); aoqi@0: } else { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); aoqi@0: assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); aoqi@0: assert(split_pos > 0, "invalid split_pos"); aoqi@0: assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); aoqi@0: aoqi@0: cur->assign_reg(reg, regHi); aoqi@0: if (need_split) { aoqi@0: // register not available for full interval, so split it aoqi@0: split_when_partial_register_available(cur, split_pos); aoqi@0: } aoqi@0: aoqi@0: // perform splitting and spilling for all affected intervalls aoqi@0: split_and_spill_intersecting_intervals(reg, regHi); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: bool LinearScanWalker::no_allocation_possible(Interval* cur) { aoqi@0: #ifdef X86 aoqi@0: // fast calculation of intervals that can never get a register because the aoqi@0: // the next instruction is a call that blocks all registers aoqi@0: // Note: this does not work if callee-saved registers are available (e.g. on Sparc) aoqi@0: aoqi@0: // check if this interval is the result of a split operation aoqi@0: // (an interval got a register until this position) aoqi@0: int pos = cur->from(); aoqi@0: if ((pos & 1) == 1) { aoqi@0: // the current instruction is a call that blocks all registers aoqi@0: if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); aoqi@0: aoqi@0: // safety check that there is really no register available aoqi@0: assert(alloc_free_reg(cur) == false, "found a register for this interval"); aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: } aoqi@0: #endif aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: void LinearScanWalker::init_vars_for_alloc(Interval* cur) { aoqi@0: BasicType type = cur->type(); aoqi@0: _num_phys_regs = LinearScan::num_physical_regs(type); aoqi@0: _adjacent_regs = LinearScan::requires_adjacent_regs(type); aoqi@0: aoqi@0: if (pd_init_regs_for_alloc(cur)) { aoqi@0: // the appropriate register range was selected. aoqi@0: } else if (type == T_FLOAT || type == T_DOUBLE) { aoqi@0: _first_reg = pd_first_fpu_reg; aoqi@0: _last_reg = pd_last_fpu_reg; aoqi@0: } else { aoqi@0: _first_reg = pd_first_cpu_reg; aoqi@0: _last_reg = FrameMap::last_cpu_reg(); aoqi@0: } aoqi@0: aoqi@0: assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); aoqi@0: assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { aoqi@0: if (op->code() != lir_move) { aoqi@0: return false; aoqi@0: } aoqi@0: assert(op->as_Op1() != NULL, "move must be LIR_Op1"); aoqi@0: aoqi@0: LIR_Opr in = ((LIR_Op1*)op)->in_opr(); aoqi@0: LIR_Opr res = ((LIR_Op1*)op)->result_opr(); aoqi@0: return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); aoqi@0: } aoqi@0: aoqi@0: // optimization (especially for phi functions of nested loops): aoqi@0: // assign same spill slot to non-intersecting intervals aoqi@0: void LinearScanWalker::combine_spilled_intervals(Interval* cur) { aoqi@0: if (cur->is_split_child()) { aoqi@0: // optimization is only suitable for split parents aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: Interval* register_hint = cur->register_hint(false); aoqi@0: if (register_hint == NULL) { aoqi@0: // cur is not the target of a move, otherwise register_hint would be set aoqi@0: return; aoqi@0: } aoqi@0: assert(register_hint->is_split_parent(), "register hint must be split parent"); aoqi@0: aoqi@0: if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { aoqi@0: // combining the stack slots for intervals where spill move optimization is applied aoqi@0: // is not benefitial and would cause problems aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: int begin_pos = cur->from(); aoqi@0: int end_pos = cur->to(); aoqi@0: if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { aoqi@0: // safety check that lir_op_with_id is allowed aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { aoqi@0: // cur and register_hint are not connected with two moves aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); aoqi@0: Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); aoqi@0: if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { aoqi@0: // register_hint must be split, otherwise the re-writing of use positions does not work aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); aoqi@0: assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); aoqi@0: assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); aoqi@0: assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); aoqi@0: aoqi@0: if (begin_hint->assigned_reg() < LinearScan::nof_regs) { aoqi@0: // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur aoqi@0: return; aoqi@0: } aoqi@0: assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); aoqi@0: aoqi@0: // modify intervals such that cur gets the same stack slot as register_hint aoqi@0: // delete use positions to prevent the intervals to get a register at beginning aoqi@0: cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); aoqi@0: cur->remove_first_use_pos(); aoqi@0: end_hint->remove_first_use_pos(); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // allocate a physical register or memory location to an interval aoqi@0: bool LinearScanWalker::activate_current() { aoqi@0: Interval* cur = current(); aoqi@0: bool result = true; aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); aoqi@0: aoqi@0: if (cur->assigned_reg() >= LinearScan::nof_regs) { aoqi@0: // activating an interval that has a stack slot assigned -> split it at first use position aoqi@0: // used for method parameters aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); aoqi@0: aoqi@0: split_stack_interval(cur); aoqi@0: result = false; aoqi@0: aoqi@0: } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { aoqi@0: // activating an interval that must start in a stack slot, but may get a register later aoqi@0: // used for lir_roundfp: rounding is done by store to stack and reload later aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); aoqi@0: assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); aoqi@0: aoqi@0: allocator()->assign_spill_slot(cur); aoqi@0: split_stack_interval(cur); aoqi@0: result = false; aoqi@0: aoqi@0: } else if (cur->assigned_reg() == any_reg) { aoqi@0: // interval has not assigned register -> normal allocation aoqi@0: // (this is the normal case for most intervals) aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); aoqi@0: aoqi@0: // assign same spill slot to non-intersecting intervals aoqi@0: combine_spilled_intervals(cur); aoqi@0: aoqi@0: init_vars_for_alloc(cur); aoqi@0: if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { aoqi@0: // no empty register available. aoqi@0: // split and spill another interval so that this interval gets a register aoqi@0: alloc_locked_reg(cur); aoqi@0: } aoqi@0: aoqi@0: // spilled intervals need not be move to active-list aoqi@0: if (cur->assigned_reg() >= LinearScan::nof_regs) { aoqi@0: result = false; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // load spilled values that become active from stack slot to register aoqi@0: if (cur->insert_move_when_activated()) { aoqi@0: assert(cur->is_split_child(), "must be"); aoqi@0: assert(cur->current_split_child() != NULL, "must be"); aoqi@0: assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); aoqi@0: aoqi@0: insert_move(cur->from(), cur->current_split_child(), cur); aoqi@0: } aoqi@0: cur->make_current_split_child(); aoqi@0: aoqi@0: return result; // true = interval is moved to active list aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Implementation of EdgeMoveOptimizer aoqi@0: aoqi@0: EdgeMoveOptimizer::EdgeMoveOptimizer() : aoqi@0: _edge_instructions(4), aoqi@0: _edge_instructions_idx(4) aoqi@0: { aoqi@0: } aoqi@0: aoqi@0: void EdgeMoveOptimizer::optimize(BlockList* code) { aoqi@0: EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); aoqi@0: aoqi@0: // ignore the first block in the list (index 0 is not processed) aoqi@0: for (int i = code->length() - 1; i >= 1; i--) { aoqi@0: BlockBegin* block = code->at(i); aoqi@0: aoqi@0: if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { aoqi@0: optimizer.optimize_moves_at_block_end(block); aoqi@0: } aoqi@0: if (block->number_of_sux() == 2) { aoqi@0: optimizer.optimize_moves_at_block_begin(block); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // clear all internal data structures aoqi@0: void EdgeMoveOptimizer::init_instructions() { aoqi@0: _edge_instructions.clear(); aoqi@0: _edge_instructions_idx.clear(); aoqi@0: } aoqi@0: aoqi@0: // append a lir-instruction-list and the index of the current operation in to the list aoqi@0: void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { aoqi@0: _edge_instructions.append(instructions); aoqi@0: _edge_instructions_idx.append(instructions_idx); aoqi@0: } aoqi@0: aoqi@0: // return the current operation of the given edge (predecessor or successor) aoqi@0: LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { aoqi@0: LIR_OpList* instructions = _edge_instructions.at(edge); aoqi@0: int idx = _edge_instructions_idx.at(edge); aoqi@0: aoqi@0: if (idx < instructions->length()) { aoqi@0: return instructions->at(idx); aoqi@0: } else { aoqi@0: return NULL; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: // removes the current operation of the given edge (predecessor or successor) aoqi@0: void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { aoqi@0: LIR_OpList* instructions = _edge_instructions.at(edge); aoqi@0: int idx = _edge_instructions_idx.at(edge); aoqi@0: instructions->remove_at(idx); aoqi@0: aoqi@0: if (decrement_index) { aoqi@0: _edge_instructions_idx.at_put(edge, idx - 1); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { aoqi@0: if (op1 == NULL || op2 == NULL) { aoqi@0: // at least one block is already empty -> no optimization possible aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: if (op1->code() == lir_move && op2->code() == lir_move) { aoqi@0: assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); aoqi@0: assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); aoqi@0: LIR_Op1* move1 = (LIR_Op1*)op1; aoqi@0: LIR_Op1* move2 = (LIR_Op1*)op2; aoqi@0: if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { aoqi@0: // these moves are exactly equal and can be optimized aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { aoqi@0: assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); aoqi@0: assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); aoqi@0: LIR_Op1* fxch1 = (LIR_Op1*)op1; aoqi@0: LIR_Op1* fxch2 = (LIR_Op1*)op2; aoqi@0: if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { aoqi@0: // equal FPU stack operations can be optimized aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { aoqi@0: // equal FPU stack operations can be optimized aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: // no optimization possible aoqi@0: return true; aoqi@0: } aoqi@0: aoqi@0: void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); aoqi@0: aoqi@0: if (block->is_predecessor(block)) { aoqi@0: // currently we can't handle this correctly. aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: init_instructions(); aoqi@0: int num_preds = block->number_of_preds(); aoqi@0: assert(num_preds > 1, "do not call otherwise"); aoqi@0: assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); aoqi@0: aoqi@0: // setup a list with the lir-instructions of all predecessors aoqi@0: int i; aoqi@0: for (i = 0; i < num_preds; i++) { aoqi@0: BlockBegin* pred = block->pred_at(i); aoqi@0: LIR_OpList* pred_instructions = pred->lir()->instructions_list(); aoqi@0: aoqi@0: if (pred->number_of_sux() != 1) { aoqi@0: // this can happen with switch-statements where multiple edges are between aoqi@0: // the same blocks. aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: assert(pred->number_of_sux() == 1, "can handle only one successor"); aoqi@0: assert(pred->sux_at(0) == block, "invalid control flow"); aoqi@0: assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); aoqi@0: assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); aoqi@0: assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); aoqi@0: aoqi@0: if (pred_instructions->last()->info() != NULL) { aoqi@0: // can not optimize instructions when debug info is needed aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: // ignore the unconditional branch at the end of the block aoqi@0: append_instructions(pred_instructions, pred_instructions->length() - 2); aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // process lir-instructions while all predecessors end with the same instruction aoqi@0: while (true) { aoqi@0: LIR_Op* op = instruction_at(0); aoqi@0: for (i = 1; i < num_preds; i++) { aoqi@0: if (operations_different(op, instruction_at(i))) { aoqi@0: // these instructions are different and cannot be optimized -> aoqi@0: // no further optimization possible aoqi@0: return; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); aoqi@0: aoqi@0: // insert the instruction at the beginning of the current block aoqi@0: block->lir()->insert_before(1, op); aoqi@0: aoqi@0: // delete the instruction at the end of all predecessors aoqi@0: for (i = 0; i < num_preds; i++) { aoqi@0: remove_cur_instruction(i, true); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { aoqi@0: TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); aoqi@0: aoqi@0: init_instructions(); aoqi@0: int num_sux = block->number_of_sux(); aoqi@0: aoqi@0: LIR_OpList* cur_instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: assert(num_sux == 2, "method should not be called otherwise"); aoqi@0: assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); aoqi@0: assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); aoqi@0: assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); aoqi@0: aoqi@0: if (cur_instructions->last()->info() != NULL) { aoqi@0: // can no optimize instructions when debug info is needed aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); aoqi@0: if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { aoqi@0: // not a valid case for optimization aoqi@0: // currently, only blocks that end with two branches (conditional branch followed aoqi@0: // by unconditional branch) are optimized aoqi@0: return; aoqi@0: } aoqi@0: aoqi@0: // now it is guaranteed that the block ends with two branch instructions. aoqi@0: // the instructions are inserted at the end of the block before these two branches aoqi@0: int insert_idx = cur_instructions->length() - 2; aoqi@0: aoqi@0: int i; aoqi@0: #ifdef ASSERT aoqi@0: for (i = insert_idx - 1; i >= 0; i--) { aoqi@0: LIR_Op* op = cur_instructions->at(i); aoqi@0: if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { aoqi@0: assert(false, "block with two successors can have only two branch instructions"); aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: // setup a list with the lir-instructions of all successors aoqi@0: for (i = 0; i < num_sux; i++) { aoqi@0: BlockBegin* sux = block->sux_at(i); aoqi@0: LIR_OpList* sux_instructions = sux->lir()->instructions_list(); aoqi@0: aoqi@0: assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); aoqi@0: aoqi@0: if (sux->number_of_preds() != 1) { aoqi@0: // this can happen with switch-statements where multiple edges are between aoqi@0: // the same blocks. aoqi@0: return; aoqi@0: } aoqi@0: assert(sux->pred_at(0) == block, "invalid control flow"); aoqi@0: assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); aoqi@0: aoqi@0: // ignore the label at the beginning of the block aoqi@0: append_instructions(sux_instructions, 1); aoqi@0: } aoqi@0: aoqi@0: // process lir-instructions while all successors begin with the same instruction aoqi@0: while (true) { aoqi@0: LIR_Op* op = instruction_at(0); aoqi@0: for (i = 1; i < num_sux; i++) { aoqi@0: if (operations_different(op, instruction_at(i))) { aoqi@0: // these instructions are different and cannot be optimized -> aoqi@0: // no further optimization possible aoqi@0: return; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); aoqi@0: aoqi@0: // insert instruction at end of current block aoqi@0: block->lir()->insert_before(insert_idx, op); aoqi@0: insert_idx++; aoqi@0: aoqi@0: // delete the instructions at the beginning of all successors aoqi@0: for (i = 0; i < num_sux; i++) { aoqi@0: remove_cur_instruction(i, false); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Implementation of ControlFlowOptimizer aoqi@0: aoqi@0: ControlFlowOptimizer::ControlFlowOptimizer() : aoqi@0: _original_preds(4) aoqi@0: { aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::optimize(BlockList* code) { aoqi@0: ControlFlowOptimizer optimizer = ControlFlowOptimizer(); aoqi@0: aoqi@0: // push the OSR entry block to the end so that we're not jumping over it. aoqi@0: BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); aoqi@0: if (osr_entry) { aoqi@0: int index = osr_entry->linear_scan_number(); aoqi@0: assert(code->at(index) == osr_entry, "wrong index"); aoqi@0: code->remove_at(index); aoqi@0: code->append(osr_entry); aoqi@0: } aoqi@0: aoqi@0: optimizer.reorder_short_loops(code); aoqi@0: optimizer.delete_empty_blocks(code); aoqi@0: optimizer.delete_unnecessary_jumps(code); aoqi@0: optimizer.delete_jumps_to_return(code); aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { aoqi@0: int i = header_idx + 1; aoqi@0: int max_end = MIN2(header_idx + ShortLoopSize, code->length()); aoqi@0: while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { aoqi@0: i++; aoqi@0: } aoqi@0: aoqi@0: if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { aoqi@0: int end_idx = i - 1; aoqi@0: BlockBegin* end_block = code->at(end_idx); aoqi@0: aoqi@0: if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { aoqi@0: // short loop from header_idx to end_idx found -> reorder blocks such that aoqi@0: // the header_block is the last block instead of the first block of the loop aoqi@0: TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", aoqi@0: end_idx - header_idx + 1, aoqi@0: header_block->block_id(), end_block->block_id())); aoqi@0: aoqi@0: for (int j = header_idx; j < end_idx; j++) { aoqi@0: code->at_put(j, code->at(j + 1)); aoqi@0: } aoqi@0: code->at_put(end_idx, header_block); aoqi@0: aoqi@0: // correct the flags so that any loop alignment occurs in the right place. aoqi@0: assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); aoqi@0: code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); aoqi@0: code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { aoqi@0: for (int i = code->length() - 1; i >= 0; i--) { aoqi@0: BlockBegin* block = code->at(i); aoqi@0: aoqi@0: if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { aoqi@0: reorder_short_loop(code, block, i); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: DEBUG_ONLY(verify(code)); aoqi@0: } aoqi@0: aoqi@0: // only blocks with exactly one successor can be deleted. Such blocks aoqi@0: // must always end with an unconditional branch to this successor aoqi@0: bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { aoqi@0: if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: assert(instructions->length() >= 2, "block must have label and branch"); aoqi@0: assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); aoqi@0: assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); aoqi@0: assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); aoqi@0: assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); aoqi@0: aoqi@0: // block must have exactly one successor aoqi@0: aoqi@0: if (instructions->length() == 2 && instructions->last()->info() == NULL) { aoqi@0: return true; aoqi@0: } aoqi@0: return false; aoqi@0: } aoqi@0: aoqi@0: // substitute branch targets in all branch-instructions of this blocks aoqi@0: void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); aoqi@0: aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); aoqi@0: for (int i = instructions->length() - 1; i >= 1; i--) { aoqi@0: LIR_Op* op = instructions->at(i); aoqi@0: aoqi@0: if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { aoqi@0: assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); aoqi@0: LIR_OpBranch* branch = (LIR_OpBranch*)op; aoqi@0: aoqi@0: if (branch->block() == target_from) { aoqi@0: branch->change_block(target_to); aoqi@0: } aoqi@0: if (branch->ublock() == target_from) { aoqi@0: branch->change_ublock(target_to); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { aoqi@0: int old_pos = 0; aoqi@0: int new_pos = 0; aoqi@0: int num_blocks = code->length(); aoqi@0: aoqi@0: while (old_pos < num_blocks) { aoqi@0: BlockBegin* block = code->at(old_pos); aoqi@0: aoqi@0: if (can_delete_block(block)) { aoqi@0: BlockBegin* new_target = block->sux_at(0); aoqi@0: aoqi@0: // propagate backward branch target flag for correct code alignment aoqi@0: if (block->is_set(BlockBegin::backward_branch_target_flag)) { aoqi@0: new_target->set(BlockBegin::backward_branch_target_flag); aoqi@0: } aoqi@0: aoqi@0: // collect a list with all predecessors that contains each predecessor only once aoqi@0: // the predecessors of cur are changed during the substitution, so a copy of the aoqi@0: // predecessor list is necessary aoqi@0: int j; aoqi@0: _original_preds.clear(); aoqi@0: for (j = block->number_of_preds() - 1; j >= 0; j--) { aoqi@0: BlockBegin* pred = block->pred_at(j); aoqi@0: if (_original_preds.index_of(pred) == -1) { aoqi@0: _original_preds.append(pred); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: for (j = _original_preds.length() - 1; j >= 0; j--) { aoqi@0: BlockBegin* pred = _original_preds.at(j); aoqi@0: substitute_branch_target(pred, block, new_target); aoqi@0: pred->substitute_sux(block, new_target); aoqi@0: } aoqi@0: } else { aoqi@0: // adjust position of this block in the block list if blocks before aoqi@0: // have been deleted aoqi@0: if (new_pos != old_pos) { aoqi@0: code->at_put(new_pos, code->at(old_pos)); aoqi@0: } aoqi@0: new_pos++; aoqi@0: } aoqi@0: old_pos++; aoqi@0: } aoqi@0: code->truncate(new_pos); aoqi@0: aoqi@0: DEBUG_ONLY(verify(code)); aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { aoqi@0: // skip the last block because there a branch is always necessary aoqi@0: for (int i = code->length() - 2; i >= 0; i--) { aoqi@0: BlockBegin* block = code->at(i); aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: LIR_Op* last_op = instructions->last(); aoqi@0: if (last_op->code() == lir_branch) { aoqi@0: assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); aoqi@0: LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; aoqi@0: aoqi@0: assert(last_branch->block() != NULL, "last branch must always have a block as target"); aoqi@0: assert(last_branch->label() == last_branch->block()->label(), "must be equal"); aoqi@0: aoqi@0: if (last_branch->info() == NULL) { aoqi@0: if (last_branch->block() == code->at(i + 1)) { aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); aoqi@0: aoqi@0: // delete last branch instruction aoqi@0: instructions->truncate(instructions->length() - 1); aoqi@0: aoqi@0: } else { aoqi@0: LIR_Op* prev_op = instructions->at(instructions->length() - 2); aoqi@0: if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { aoqi@0: assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); aoqi@0: LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; aoqi@0: aoqi@0: if (prev_branch->stub() == NULL) { aoqi@0: aoqi@1: #ifndef MIPS64 //MIPS64 not support lir_cmp. same as openjdk6. aoqi@0: LIR_Op2* prev_cmp = NULL; aoqi@0: aoqi@0: for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { aoqi@0: prev_op = instructions->at(j); aoqi@0: if (prev_op->code() == lir_cmp) { aoqi@0: assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); aoqi@0: prev_cmp = (LIR_Op2*)prev_op; aoqi@0: assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); aoqi@0: } aoqi@0: } aoqi@0: assert(prev_cmp != NULL, "should have found comp instruction for branch"); aoqi@1: #endif aoqi@0: if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { aoqi@0: aoqi@0: TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); aoqi@0: aoqi@0: // eliminate a conditional branch to the immediate successor aoqi@0: prev_branch->change_block(last_branch->block()); aoqi@0: prev_branch->negate_cond(); aoqi@1: #ifndef MIPS64 //MIPS64 not support lir_cmp. same as openjdk6. aoqi@0: prev_cmp->set_condition(prev_branch->cond()); aoqi@1: #endif aoqi@0: instructions->truncate(instructions->length() - 1); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: DEBUG_ONLY(verify(code)); aoqi@0: } aoqi@0: aoqi@0: void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { aoqi@0: #ifdef ASSERT aoqi@0: BitMap return_converted(BlockBegin::number_of_blocks()); aoqi@0: return_converted.clear(); aoqi@0: #endif aoqi@0: aoqi@0: for (int i = code->length() - 1; i >= 0; i--) { aoqi@0: BlockBegin* block = code->at(i); aoqi@0: LIR_OpList* cur_instructions = block->lir()->instructions_list(); aoqi@0: LIR_Op* cur_last_op = cur_instructions->last(); aoqi@0: aoqi@0: assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); aoqi@0: if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { aoqi@0: // the block contains only a label and a return aoqi@0: // if a predecessor ends with an unconditional jump to this block, then the jump aoqi@0: // can be replaced with a return instruction aoqi@0: // aoqi@0: // Note: the original block with only a return statement cannot be deleted completely aoqi@0: // because the predecessors might have other (conditional) jumps to this block aoqi@0: // -> this may lead to unnecesary return instructions in the final code aoqi@0: aoqi@0: assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); aoqi@0: assert(block->number_of_sux() == 0 || aoqi@0: (return_converted.at(block->block_id()) && block->number_of_sux() == 1), aoqi@0: "blocks that end with return must not have successors"); aoqi@0: aoqi@0: assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); aoqi@0: LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); aoqi@0: aoqi@0: for (int j = block->number_of_preds() - 1; j >= 0; j--) { aoqi@0: BlockBegin* pred = block->pred_at(j); aoqi@0: LIR_OpList* pred_instructions = pred->lir()->instructions_list(); aoqi@0: LIR_Op* pred_last_op = pred_instructions->last(); aoqi@0: aoqi@0: if (pred_last_op->code() == lir_branch) { aoqi@0: assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); aoqi@0: LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; aoqi@0: aoqi@0: if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { aoqi@0: // replace the jump to a return with a direct return aoqi@0: // Note: currently the edge between the blocks is not deleted aoqi@0: pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); aoqi@0: #ifdef ASSERT aoqi@0: return_converted.set_bit(pred->block_id()); aoqi@0: #endif aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: void ControlFlowOptimizer::verify(BlockList* code) { aoqi@0: for (int i = 0; i < code->length(); i++) { aoqi@0: BlockBegin* block = code->at(i); aoqi@0: LIR_OpList* instructions = block->lir()->instructions_list(); aoqi@0: aoqi@0: int j; aoqi@0: for (j = 0; j < instructions->length(); j++) { aoqi@0: LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); aoqi@0: aoqi@0: if (op_branch != NULL) { aoqi@0: assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid"); aoqi@0: assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid"); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: for (j = 0; j < block->number_of_sux() - 1; j++) { aoqi@0: BlockBegin* sux = block->sux_at(j); aoqi@0: assert(code->index_of(sux) != -1, "successor not valid"); aoqi@0: } aoqi@0: aoqi@0: for (j = 0; j < block->number_of_preds() - 1; j++) { aoqi@0: BlockBegin* pred = block->pred_at(j); aoqi@0: assert(code->index_of(pred) != -1, "successor not valid"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: #endif aoqi@0: aoqi@0: aoqi@0: #ifndef PRODUCT aoqi@0: aoqi@0: // Implementation of LinearStatistic aoqi@0: aoqi@0: const char* LinearScanStatistic::counter_name(int counter_idx) { aoqi@0: switch (counter_idx) { aoqi@0: case counter_method: return "compiled methods"; aoqi@0: case counter_fpu_method: return "methods using fpu"; aoqi@0: case counter_loop_method: return "methods with loops"; aoqi@0: case counter_exception_method:return "methods with xhandler"; aoqi@0: aoqi@0: case counter_loop: return "loops"; aoqi@0: case counter_block: return "blocks"; aoqi@0: case counter_loop_block: return "blocks inside loop"; aoqi@0: case counter_exception_block: return "exception handler entries"; aoqi@0: case counter_interval: return "intervals"; aoqi@0: case counter_fixed_interval: return "fixed intervals"; aoqi@0: case counter_range: return "ranges"; aoqi@0: case counter_fixed_range: return "fixed ranges"; aoqi@0: case counter_use_pos: return "use positions"; aoqi@0: case counter_fixed_use_pos: return "fixed use positions"; aoqi@0: case counter_spill_slots: return "spill slots"; aoqi@0: aoqi@0: // counter for classes of lir instructions aoqi@0: case counter_instruction: return "total instructions"; aoqi@0: case counter_label: return "labels"; aoqi@0: case counter_entry: return "method entries"; aoqi@0: case counter_return: return "method returns"; aoqi@0: case counter_call: return "method calls"; aoqi@0: case counter_move: return "moves"; aoqi@0: case counter_cmp: return "compare"; aoqi@0: case counter_cond_branch: return "conditional branches"; aoqi@0: case counter_uncond_branch: return "unconditional branches"; aoqi@0: case counter_stub_branch: return "branches to stub"; aoqi@0: case counter_alu: return "artithmetic + logic"; aoqi@0: case counter_alloc: return "allocations"; aoqi@0: case counter_sync: return "synchronisation"; aoqi@0: case counter_throw: return "throw"; aoqi@0: case counter_unwind: return "unwind"; aoqi@0: case counter_typecheck: return "type+null-checks"; aoqi@0: case counter_fpu_stack: return "fpu-stack"; aoqi@0: case counter_misc_inst: return "other instructions"; aoqi@0: case counter_other_inst: return "misc. instructions"; aoqi@0: aoqi@0: // counter for different types of moves aoqi@0: case counter_move_total: return "total moves"; aoqi@0: case counter_move_reg_reg: return "register->register"; aoqi@0: case counter_move_reg_stack: return "register->stack"; aoqi@0: case counter_move_stack_reg: return "stack->register"; aoqi@0: case counter_move_stack_stack:return "stack->stack"; aoqi@0: case counter_move_reg_mem: return "register->memory"; aoqi@0: case counter_move_mem_reg: return "memory->register"; aoqi@0: case counter_move_const_any: return "constant->any"; aoqi@0: aoqi@0: case blank_line_1: return ""; aoqi@0: case blank_line_2: return ""; aoqi@0: aoqi@0: default: ShouldNotReachHere(); return ""; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { aoqi@0: if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { aoqi@0: return counter_method; aoqi@0: } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { aoqi@0: return counter_block; aoqi@0: } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { aoqi@0: return counter_instruction; aoqi@0: } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { aoqi@0: return counter_move_total; aoqi@0: } aoqi@0: return invalid_counter; aoqi@0: } aoqi@0: aoqi@0: LinearScanStatistic::LinearScanStatistic() { aoqi@0: for (int i = 0; i < number_of_counters; i++) { aoqi@0: _counters_sum[i] = 0; aoqi@0: _counters_max[i] = -1; aoqi@0: } aoqi@0: aoqi@0: } aoqi@0: aoqi@0: // add the method-local numbers to the total sum aoqi@0: void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { aoqi@0: for (int i = 0; i < number_of_counters; i++) { aoqi@0: _counters_sum[i] += method_statistic._counters_sum[i]; aoqi@0: _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanStatistic::print(const char* title) { aoqi@0: if (CountLinearScan || TraceLinearScanLevel > 0) { aoqi@0: tty->cr(); aoqi@0: tty->print_cr("***** LinearScan statistic - %s *****", title); aoqi@0: aoqi@0: for (int i = 0; i < number_of_counters; i++) { aoqi@0: if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { aoqi@0: tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); aoqi@0: aoqi@0: if (base_counter(i) != invalid_counter) { aoqi@0: tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]); aoqi@0: } else { aoqi@0: tty->print(" "); aoqi@0: } aoqi@0: aoqi@0: if (_counters_max[i] >= 0) { aoqi@0: tty->print("%8d", _counters_max[i]); aoqi@0: } aoqi@0: } aoqi@0: tty->cr(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanStatistic::collect(LinearScan* allocator) { aoqi@0: inc_counter(counter_method); aoqi@0: if (allocator->has_fpu_registers()) { aoqi@0: inc_counter(counter_fpu_method); aoqi@0: } aoqi@0: if (allocator->num_loops() > 0) { aoqi@0: inc_counter(counter_loop_method); aoqi@0: } aoqi@0: inc_counter(counter_loop, allocator->num_loops()); aoqi@0: inc_counter(counter_spill_slots, allocator->max_spills()); aoqi@0: aoqi@0: int i; aoqi@0: for (i = 0; i < allocator->interval_count(); i++) { aoqi@0: Interval* cur = allocator->interval_at(i); aoqi@0: aoqi@0: if (cur != NULL) { aoqi@0: inc_counter(counter_interval); aoqi@0: inc_counter(counter_use_pos, cur->num_use_positions()); aoqi@0: if (LinearScan::is_precolored_interval(cur)) { aoqi@0: inc_counter(counter_fixed_interval); aoqi@0: inc_counter(counter_fixed_use_pos, cur->num_use_positions()); aoqi@0: } aoqi@0: aoqi@0: Range* range = cur->first(); aoqi@0: while (range != Range::end()) { aoqi@0: inc_counter(counter_range); aoqi@0: if (LinearScan::is_precolored_interval(cur)) { aoqi@0: inc_counter(counter_fixed_range); aoqi@0: } aoqi@0: range = range->next(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: bool has_xhandlers = false; aoqi@0: // Note: only count blocks that are in code-emit order aoqi@0: for (i = 0; i < allocator->ir()->code()->length(); i++) { aoqi@0: BlockBegin* cur = allocator->ir()->code()->at(i); aoqi@0: aoqi@0: inc_counter(counter_block); aoqi@0: if (cur->loop_depth() > 0) { aoqi@0: inc_counter(counter_loop_block); aoqi@0: } aoqi@0: if (cur->is_set(BlockBegin::exception_entry_flag)) { aoqi@0: inc_counter(counter_exception_block); aoqi@0: has_xhandlers = true; aoqi@0: } aoqi@0: aoqi@0: LIR_OpList* instructions = cur->lir()->instructions_list(); aoqi@0: for (int j = 0; j < instructions->length(); j++) { aoqi@0: LIR_Op* op = instructions->at(j); aoqi@0: aoqi@0: inc_counter(counter_instruction); aoqi@0: aoqi@0: switch (op->code()) { aoqi@0: case lir_label: inc_counter(counter_label); break; aoqi@0: case lir_std_entry: aoqi@0: case lir_osr_entry: inc_counter(counter_entry); break; aoqi@0: case lir_return: inc_counter(counter_return); break; aoqi@0: aoqi@0: case lir_rtcall: aoqi@0: case lir_static_call: aoqi@0: case lir_optvirtual_call: aoqi@0: case lir_virtual_call: inc_counter(counter_call); break; aoqi@0: aoqi@0: case lir_move: { aoqi@0: inc_counter(counter_move); aoqi@0: inc_counter(counter_move_total); aoqi@0: aoqi@0: LIR_Opr in = op->as_Op1()->in_opr(); aoqi@0: LIR_Opr res = op->as_Op1()->result_opr(); aoqi@0: if (in->is_register()) { aoqi@0: if (res->is_register()) { aoqi@0: inc_counter(counter_move_reg_reg); aoqi@0: } else if (res->is_stack()) { aoqi@0: inc_counter(counter_move_reg_stack); aoqi@0: } else if (res->is_address()) { aoqi@0: inc_counter(counter_move_reg_mem); aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: } else if (in->is_stack()) { aoqi@0: if (res->is_register()) { aoqi@0: inc_counter(counter_move_stack_reg); aoqi@0: } else { aoqi@0: inc_counter(counter_move_stack_stack); aoqi@0: } aoqi@0: } else if (in->is_address()) { aoqi@0: assert(res->is_register(), "must be"); aoqi@0: inc_counter(counter_move_mem_reg); aoqi@0: } else if (in->is_constant()) { aoqi@0: inc_counter(counter_move_const_any); aoqi@0: } else { aoqi@0: ShouldNotReachHere(); aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: aoqi@1: #ifndef MIPS64 aoqi@0: case lir_cmp: inc_counter(counter_cmp); break; aoqi@0: aoqi@1: #endif aoqi@0: case lir_branch: aoqi@0: case lir_cond_float_branch: { aoqi@0: LIR_OpBranch* branch = op->as_OpBranch(); aoqi@0: if (branch->block() == NULL) { aoqi@0: inc_counter(counter_stub_branch); aoqi@0: } else if (branch->cond() == lir_cond_always) { aoqi@0: inc_counter(counter_uncond_branch); aoqi@0: } else { aoqi@0: inc_counter(counter_cond_branch); aoqi@0: } aoqi@0: break; aoqi@0: } aoqi@0: aoqi@0: case lir_neg: aoqi@0: case lir_add: aoqi@0: case lir_sub: aoqi@0: case lir_mul: aoqi@0: case lir_mul_strictfp: aoqi@0: case lir_div: aoqi@0: case lir_div_strictfp: aoqi@0: case lir_rem: aoqi@0: case lir_sqrt: aoqi@0: case lir_sin: aoqi@0: case lir_cos: aoqi@0: case lir_abs: aoqi@0: case lir_log10: aoqi@0: case lir_log: aoqi@0: case lir_pow: aoqi@0: case lir_exp: aoqi@0: case lir_logic_and: aoqi@0: case lir_logic_or: aoqi@0: case lir_logic_xor: aoqi@0: case lir_shl: aoqi@0: case lir_shr: aoqi@0: case lir_ushr: inc_counter(counter_alu); break; aoqi@0: aoqi@0: case lir_alloc_object: aoqi@0: case lir_alloc_array: inc_counter(counter_alloc); break; aoqi@0: aoqi@0: case lir_monaddr: aoqi@0: case lir_lock: aoqi@0: case lir_unlock: inc_counter(counter_sync); break; aoqi@0: aoqi@0: case lir_throw: inc_counter(counter_throw); break; aoqi@0: aoqi@0: case lir_unwind: inc_counter(counter_unwind); break; aoqi@0: aoqi@0: case lir_null_check: aoqi@0: case lir_leal: aoqi@0: case lir_instanceof: aoqi@0: case lir_checkcast: aoqi@0: case lir_store_check: inc_counter(counter_typecheck); break; aoqi@0: aoqi@0: case lir_fpop_raw: aoqi@0: case lir_fxch: aoqi@0: case lir_fld: inc_counter(counter_fpu_stack); break; aoqi@0: aoqi@0: case lir_nop: aoqi@0: case lir_push: aoqi@0: case lir_pop: aoqi@0: case lir_convert: aoqi@0: case lir_roundfp: aoqi@0: case lir_cmove: inc_counter(counter_misc_inst); break; aoqi@0: aoqi@0: default: inc_counter(counter_other_inst); break; aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: if (has_xhandlers) { aoqi@0: inc_counter(counter_exception_method); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { aoqi@0: if (CountLinearScan || TraceLinearScanLevel > 0) { aoqi@0: aoqi@0: LinearScanStatistic local_statistic = LinearScanStatistic(); aoqi@0: aoqi@0: local_statistic.collect(allocator); aoqi@0: global_statistic.sum_up(local_statistic); aoqi@0: aoqi@0: if (TraceLinearScanLevel > 2) { aoqi@0: local_statistic.print("current local statistic"); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: aoqi@0: // Implementation of LinearTimers aoqi@0: aoqi@0: LinearScanTimers::LinearScanTimers() { aoqi@0: for (int i = 0; i < number_of_timers; i++) { aoqi@0: timer(i)->reset(); aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: const char* LinearScanTimers::timer_name(int idx) { aoqi@0: switch (idx) { aoqi@0: case timer_do_nothing: return "Nothing (Time Check)"; aoqi@0: case timer_number_instructions: return "Number Instructions"; aoqi@0: case timer_compute_local_live_sets: return "Local Live Sets"; aoqi@0: case timer_compute_global_live_sets: return "Global Live Sets"; aoqi@0: case timer_build_intervals: return "Build Intervals"; aoqi@0: case timer_sort_intervals_before: return "Sort Intervals Before"; aoqi@0: case timer_allocate_registers: return "Allocate Registers"; aoqi@0: case timer_resolve_data_flow: return "Resolve Data Flow"; aoqi@0: case timer_sort_intervals_after: return "Sort Intervals After"; aoqi@0: case timer_eliminate_spill_moves: return "Spill optimization"; aoqi@0: case timer_assign_reg_num: return "Assign Reg Num"; aoqi@0: case timer_allocate_fpu_stack: return "Allocate FPU Stack"; aoqi@0: case timer_optimize_lir: return "Optimize LIR"; aoqi@0: default: ShouldNotReachHere(); return ""; aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanTimers::begin_method() { aoqi@0: if (TimeEachLinearScan) { aoqi@0: // reset all timers to measure only current method aoqi@0: for (int i = 0; i < number_of_timers; i++) { aoqi@0: timer(i)->reset(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanTimers::end_method(LinearScan* allocator) { aoqi@0: if (TimeEachLinearScan) { aoqi@0: aoqi@0: double c = timer(timer_do_nothing)->seconds(); aoqi@0: double total = 0; aoqi@0: for (int i = 1; i < number_of_timers; i++) { aoqi@0: total += timer(i)->seconds() - c; aoqi@0: } aoqi@0: aoqi@0: if (total >= 0.0005) { aoqi@0: // print all information in one line for automatic processing aoqi@0: tty->print("@"); allocator->compilation()->method()->print_name(); aoqi@0: aoqi@0: tty->print("@ %d ", allocator->compilation()->method()->code_size()); aoqi@0: tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); aoqi@0: tty->print("@ %d ", allocator->block_count()); aoqi@0: tty->print("@ %d ", allocator->num_virtual_regs()); aoqi@0: tty->print("@ %d ", allocator->interval_count()); aoqi@0: tty->print("@ %d ", allocator->_num_calls); aoqi@0: tty->print("@ %d ", allocator->num_loops()); aoqi@0: aoqi@0: tty->print("@ %6.6f ", total); aoqi@0: for (int i = 1; i < number_of_timers; i++) { aoqi@0: tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); aoqi@0: } aoqi@0: tty->cr(); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: void LinearScanTimers::print(double total_time) { aoqi@0: if (TimeLinearScan) { aoqi@0: // correction value: sum of dummy-timer that only measures the time that aoqi@0: // is necesary to start and stop itself aoqi@0: double c = timer(timer_do_nothing)->seconds(); aoqi@0: aoqi@0: for (int i = 0; i < number_of_timers; i++) { aoqi@0: double t = timer(i)->seconds(); aoqi@0: tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); aoqi@0: } aoqi@0: } aoqi@0: } aoqi@0: aoqi@0: #endif // #ifndef PRODUCT