aoqi@0: /* aoqi@0: * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. aoqi@0: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. aoqi@0: * aoqi@0: * This code is free software; you can redistribute it and/or modify it aoqi@0: * under the terms of the GNU General Public License version 2 only, as aoqi@0: * published by the Free Software Foundation. aoqi@0: * aoqi@0: * This code is distributed in the hope that it will be useful, but WITHOUT aoqi@0: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or aoqi@0: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License aoqi@0: * version 2 for more details (a copy is included in the LICENSE file that aoqi@0: * accompanied this code). aoqi@0: * aoqi@0: * You should have received a copy of the GNU General Public License version aoqi@0: * 2 along with this work; if not, write to the Free Software Foundation, aoqi@0: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. aoqi@0: * aoqi@0: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA aoqi@0: * or visit www.oracle.com if you need additional information or have any aoqi@0: * questions. aoqi@0: * aoqi@0: */ aoqi@0: aoqi@1: /* aoqi@1: * This file has been modified by Loongson Technology in 2015. These aoqi@1: * modifications are Copyright (c) 2015 Loongson Technology, and are made aoqi@1: * available on the same license terms set forth above. aoqi@1: */ aoqi@1: aoqi@0: #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP aoqi@0: #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP aoqi@0: aoqi@0: #include "c1/c1_CodeStubs.hpp" aoqi@0: #include "ci/ciMethodData.hpp" aoqi@0: #include "oops/methodData.hpp" aoqi@0: #include "utilities/top.hpp" aoqi@0: aoqi@0: class Compilation; aoqi@0: class ScopeValue; aoqi@0: class BarrierSet; aoqi@0: aoqi@0: class LIR_Assembler: public CompilationResourceObj { aoqi@0: private: aoqi@0: C1_MacroAssembler* _masm; aoqi@0: CodeStubList* _slow_case_stubs; aoqi@0: BarrierSet* _bs; aoqi@0: aoqi@0: Compilation* _compilation; aoqi@0: FrameMap* _frame_map; aoqi@0: BlockBegin* _current_block; aoqi@0: aoqi@0: Instruction* _pending_non_safepoint; aoqi@0: int _pending_non_safepoint_offset; aoqi@0: aoqi@0: Label _unwind_handler_entry; aoqi@0: aoqi@0: #ifdef ASSERT aoqi@0: BlockList _branch_target_blocks; aoqi@0: void check_no_unbound_labels(); aoqi@0: #endif aoqi@0: aoqi@0: FrameMap* frame_map() const { return _frame_map; } aoqi@0: aoqi@0: void set_current_block(BlockBegin* b) { _current_block = b; } aoqi@0: BlockBegin* current_block() const { return _current_block; } aoqi@0: aoqi@0: // non-safepoint debug info management aoqi@0: void flush_debug_info(int before_pc_offset) { aoqi@0: if (_pending_non_safepoint != NULL) { aoqi@0: if (_pending_non_safepoint_offset < before_pc_offset) aoqi@0: record_non_safepoint_debug_info(); aoqi@0: _pending_non_safepoint = NULL; aoqi@0: } aoqi@0: } aoqi@0: void process_debug_info(LIR_Op* op); aoqi@0: void record_non_safepoint_debug_info(); aoqi@0: aoqi@0: // unified bailout support aoqi@0: void bailout(const char* msg) const { compilation()->bailout(msg); } aoqi@0: bool bailed_out() const { return compilation()->bailed_out(); } aoqi@0: aoqi@0: // code emission patterns and accessors aoqi@0: void check_codespace(); aoqi@0: bool needs_icache(ciMethod* method) const; aoqi@0: aoqi@0: // returns offset of icache check aoqi@0: int check_icache(); aoqi@0: aoqi@0: void jobject2reg(jobject o, Register reg); aoqi@0: void jobject2reg_with_patching(Register reg, CodeEmitInfo* info); aoqi@0: aoqi@0: void metadata2reg(Metadata* o, Register reg); aoqi@0: void klass2reg_with_patching(Register reg, CodeEmitInfo* info); aoqi@0: aoqi@0: void emit_stubs(CodeStubList* stub_list); aoqi@0: aoqi@0: // addresses aoqi@0: Address as_Address(LIR_Address* addr); aoqi@0: Address as_Address_lo(LIR_Address* addr); aoqi@0: Address as_Address_hi(LIR_Address* addr); aoqi@0: aoqi@0: // debug information aoqi@0: void add_call_info(int pc_offset, CodeEmitInfo* cinfo); aoqi@0: void add_debug_info_for_branch(CodeEmitInfo* info); aoqi@0: void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); aoqi@0: void add_debug_info_for_div0_here(CodeEmitInfo* info); aoqi@0: void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); aoqi@0: void add_debug_info_for_null_check_here(CodeEmitInfo* info); aoqi@0: aoqi@0: void set_24bit_FPU(); aoqi@0: void reset_FPU(); aoqi@0: void fpop(); aoqi@0: void fxch(int i); aoqi@0: void fld(int i); aoqi@0: void ffree(int i); aoqi@0: aoqi@0: void breakpoint(); aoqi@0: void push(LIR_Opr opr); aoqi@0: void pop(LIR_Opr opr); aoqi@0: aoqi@0: // patching aoqi@0: void append_patching_stub(PatchingStub* stub); aoqi@0: void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info); aoqi@0: aoqi@0: void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op); aoqi@0: aoqi@0: PatchingStub::PatchID patching_id(CodeEmitInfo* info); aoqi@0: aoqi@0: public: aoqi@0: LIR_Assembler(Compilation* c); aoqi@0: ~LIR_Assembler(); aoqi@0: C1_MacroAssembler* masm() const { return _masm; } aoqi@0: Compilation* compilation() const { return _compilation; } aoqi@0: ciMethod* method() const { return compilation()->method(); } aoqi@0: aoqi@0: CodeOffsets* offsets() const { return _compilation->offsets(); } aoqi@0: int code_offset() const; aoqi@0: address pc() const; aoqi@0: aoqi@0: int initial_frame_size_in_bytes() const; aoqi@0: int bang_size_in_bytes() const; aoqi@0: aoqi@0: // test for constants which can be encoded directly in instructions aoqi@0: static bool is_small_constant(LIR_Opr opr); aoqi@0: aoqi@0: static LIR_Opr receiverOpr(); aoqi@0: static LIR_Opr osrBufferPointer(); aoqi@0: aoqi@0: // stubs aoqi@0: void emit_slow_case_stubs(); aoqi@0: void emit_static_call_stub(); aoqi@0: void append_code_stub(CodeStub* op); aoqi@0: void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); } aoqi@0: aoqi@0: // code patterns aoqi@0: int emit_exception_handler(); aoqi@0: int emit_unwind_handler(); aoqi@0: void emit_exception_entries(ExceptionInfoList* info_list); aoqi@0: int emit_deopt_handler(); aoqi@0: aoqi@0: void emit_code(BlockList* hir); aoqi@0: void emit_block(BlockBegin* block); aoqi@0: void emit_lir_list(LIR_List* list); aoqi@0: aoqi@0: // any last minute peephole optimizations are performed here. In aoqi@0: // particular sparc uses this for delay slot filling. aoqi@0: void peephole(LIR_List* list); aoqi@0: aoqi@0: void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info); aoqi@0: aoqi@0: void return_op(LIR_Opr result); aoqi@0: aoqi@0: // returns offset of poll instruction aoqi@0: int safepoint_poll(LIR_Opr result, CodeEmitInfo* info); aoqi@0: aoqi@0: void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); aoqi@0: void const2stack(LIR_Opr src, LIR_Opr dest); aoqi@0: void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide); aoqi@0: void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); aoqi@0: void reg2reg (LIR_Opr src, LIR_Opr dest); aoqi@0: void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, aoqi@0: LIR_PatchCode patch_code, CodeEmitInfo* info, aoqi@0: bool pop_fpu_stack, bool wide, bool unaligned); aoqi@0: void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); aoqi@0: void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); aoqi@0: void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, aoqi@0: LIR_PatchCode patch_code, aoqi@0: CodeEmitInfo* info, bool wide, bool unaligned); aoqi@0: aoqi@0: void prefetchr (LIR_Opr src); aoqi@0: void prefetchw (LIR_Opr src); aoqi@0: aoqi@0: void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp); aoqi@0: void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest); aoqi@0: aoqi@0: void move_regs(Register from_reg, Register to_reg); aoqi@0: void swap_reg(Register a, Register b); aoqi@0: aoqi@0: void emit_op0(LIR_Op0* op); aoqi@0: void emit_op1(LIR_Op1* op); aoqi@0: void emit_op2(LIR_Op2* op); aoqi@0: void emit_op3(LIR_Op3* op); aoqi@0: void emit_opBranch(LIR_OpBranch* op); aoqi@0: void emit_opLabel(LIR_OpLabel* op); aoqi@0: void emit_arraycopy(LIR_OpArrayCopy* op); aoqi@0: void emit_updatecrc32(LIR_OpUpdateCRC32* op); aoqi@0: void emit_opConvert(LIR_OpConvert* op); aoqi@0: void emit_alloc_obj(LIR_OpAllocObj* op); aoqi@0: void emit_alloc_array(LIR_OpAllocArray* op); aoqi@0: void emit_opTypeCheck(LIR_OpTypeCheck* op); aoqi@0: void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null); aoqi@0: void emit_compare_and_swap(LIR_OpCompareAndSwap* op); aoqi@0: void emit_lock(LIR_OpLock* op); aoqi@0: void emit_call(LIR_OpJavaCall* op); aoqi@0: void emit_rtcall(LIR_OpRTCall* op); aoqi@0: void emit_profile_call(LIR_OpProfileCall* op); aoqi@0: void emit_profile_type(LIR_OpProfileType* op); aoqi@0: void emit_delay(LIR_OpDelay* op); aoqi@0: aoqi@0: void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); aoqi@1: #ifdef MIPS64 aoqi@1: void arithmetic_frem(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info = NULL); aoqi@1: #endif aoqi@0: void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); aoqi@0: void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); aoqi@0: #ifdef ASSERT aoqi@0: void emit_assert(LIR_OpAssert* op); aoqi@0: #endif aoqi@0: aoqi@0: void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); aoqi@0: aoqi@0: void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack); aoqi@0: void move_op(LIR_Opr src, LIR_Opr result, BasicType type, aoqi@0: LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide); aoqi@0: void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); aoqi@0: void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions aoqi@0: void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); aoqi@0: void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); aoqi@0: aoqi@0: void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); aoqi@0: void ic_call( LIR_OpJavaCall* op); aoqi@0: void vtable_call( LIR_OpJavaCall* op); aoqi@0: aoqi@0: void osr_entry(); aoqi@0: aoqi@0: void build_frame(); aoqi@0: aoqi@0: void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info); aoqi@0: void unwind_op(LIR_Opr exceptionOop); aoqi@0: void monitor_address(int monitor_ix, LIR_Opr dst); aoqi@0: aoqi@0: void align_backward_branch_target(); aoqi@0: void align_call(LIR_Code code); aoqi@0: aoqi@0: void negate(LIR_Opr left, LIR_Opr dest); aoqi@0: void leal(LIR_Opr left, LIR_Opr dest); aoqi@0: aoqi@0: void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info); aoqi@0: aoqi@0: void membar(); aoqi@0: void membar_acquire(); aoqi@0: void membar_release(); aoqi@0: void membar_loadload(); aoqi@0: void membar_storestore(); aoqi@0: void membar_loadstore(); aoqi@0: void membar_storeload(); aoqi@0: void get_thread(LIR_Opr result); aoqi@0: aoqi@0: void verify_oop_map(CodeEmitInfo* info); aoqi@0: aoqi@0: void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp); aoqi@0: aoqi@0: #ifdef TARGET_ARCH_x86 aoqi@0: # include "c1_LIRAssembler_x86.hpp" aoqi@0: #endif aoqi@1: #ifdef TARGET_ARCH_mips aoqi@1: # include "c1_LIRAssembler_mips.hpp" aoqi@1: #endif aoqi@0: #ifdef TARGET_ARCH_sparc aoqi@0: # include "c1_LIRAssembler_sparc.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_arm aoqi@0: # include "c1_LIRAssembler_arm.hpp" aoqi@0: #endif aoqi@0: #ifdef TARGET_ARCH_ppc aoqi@0: # include "c1_LIRAssembler_ppc.hpp" aoqi@0: #endif aoqi@0: aoqi@0: }; aoqi@0: aoqi@0: #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP