aoqi@0: /*
aoqi@0:  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
aoqi@0:  *
aoqi@0:  */
aoqi@0: 
aoqi@1: /*
aoqi@1:  * This file has been modified by Loongson Technology in 2015. These
aoqi@1:  * modifications are Copyright (c) 2015 Loongson Technology, and are made
aoqi@1:  * available on the same license terms set forth above.
aoqi@1:  */
aoqi@1: 
aoqi@0: #include "precompiled.hpp"
aoqi@0: #include "c1/c1_Compilation.hpp"
aoqi@0: #include "c1/c1_Instruction.hpp"
aoqi@0: #include "c1/c1_InstructionPrinter.hpp"
aoqi@0: #include "c1/c1_LIRAssembler.hpp"
aoqi@0: #include "c1/c1_MacroAssembler.hpp"
aoqi@0: #include "c1/c1_ValueStack.hpp"
aoqi@0: #include "ci/ciInstance.hpp"
aoqi@0: #ifdef TARGET_ARCH_x86
aoqi@0: # include "nativeInst_x86.hpp"
aoqi@0: # include "vmreg_x86.inline.hpp"
aoqi@0: #endif
aoqi@1: #ifdef TARGET_ARCH_mips
aoqi@1: # include "nativeInst_mips.hpp"
aoqi@1: # include "vmreg_mips.inline.hpp"
aoqi@1: #endif
aoqi@0: #ifdef TARGET_ARCH_sparc
aoqi@0: # include "nativeInst_sparc.hpp"
aoqi@0: # include "vmreg_sparc.inline.hpp"
aoqi@0: #endif
aoqi@0: #ifdef TARGET_ARCH_zero
aoqi@0: # include "nativeInst_zero.hpp"
aoqi@0: # include "vmreg_zero.inline.hpp"
aoqi@0: #endif
aoqi@0: #ifdef TARGET_ARCH_arm
aoqi@0: # include "nativeInst_arm.hpp"
aoqi@0: # include "vmreg_arm.inline.hpp"
aoqi@0: #endif
aoqi@0: #ifdef TARGET_ARCH_ppc
aoqi@0: # include "nativeInst_ppc.hpp"
aoqi@0: # include "vmreg_ppc.inline.hpp"
aoqi@0: #endif
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
aoqi@0:   // we must have enough patching space so that call can be inserted
aoqi@0:   while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeCall::instruction_size) {
aoqi@0:     _masm->nop();
aoqi@0:   }
aoqi@0:   patch->install(_masm, patch_code, obj, info);
aoqi@0:   append_code_stub(patch);
aoqi@0: 
aoqi@0: #ifdef ASSERT
aoqi@0:   Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
aoqi@0:   if (patch->id() == PatchingStub::access_field_id) {
aoqi@0:     switch (code) {
aoqi@0:       case Bytecodes::_putstatic:
aoqi@0:       case Bytecodes::_getstatic:
aoqi@0:       case Bytecodes::_putfield:
aoqi@0:       case Bytecodes::_getfield:
aoqi@0:         break;
aoqi@0:       default:
aoqi@0:         ShouldNotReachHere();
aoqi@0:     }
aoqi@0:   } else if (patch->id() == PatchingStub::load_klass_id) {
aoqi@0:     switch (code) {
aoqi@0:       case Bytecodes::_new:
aoqi@0:       case Bytecodes::_anewarray:
aoqi@0:       case Bytecodes::_multianewarray:
aoqi@0:       case Bytecodes::_instanceof:
aoqi@0:       case Bytecodes::_checkcast:
aoqi@0:         break;
aoqi@0:       default:
aoqi@0:         ShouldNotReachHere();
aoqi@0:     }
aoqi@0:   } else if (patch->id() == PatchingStub::load_mirror_id) {
aoqi@0:     switch (code) {
aoqi@0:       case Bytecodes::_putstatic:
aoqi@0:       case Bytecodes::_getstatic:
aoqi@0:       case Bytecodes::_ldc:
aoqi@0:       case Bytecodes::_ldc_w:
aoqi@0:         break;
aoqi@0:       default:
aoqi@0:         ShouldNotReachHere();
aoqi@0:     }
aoqi@0:   } else if (patch->id() == PatchingStub::load_appendix_id) {
aoqi@0:     Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
aoqi@0:     assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
aoqi@0:   } else {
aoqi@0:     ShouldNotReachHere();
aoqi@0:   }
aoqi@0: #endif
aoqi@0: }
aoqi@0: 
aoqi@0: PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
aoqi@0:   IRScope* scope = info->scope();
aoqi@0:   Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
aoqi@0:   if (Bytecodes::has_optional_appendix(bc_raw)) {
aoqi@0:     return PatchingStub::load_appendix_id;
aoqi@0:   }
aoqi@0:   return PatchingStub::load_mirror_id;
aoqi@0: }
aoqi@0: 
aoqi@0: //---------------------------------------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: LIR_Assembler::LIR_Assembler(Compilation* c):
aoqi@0:    _compilation(c)
aoqi@0:  , _masm(c->masm())
aoqi@0:  , _bs(Universe::heap()->barrier_set())
aoqi@0:  , _frame_map(c->frame_map())
aoqi@0:  , _current_block(NULL)
aoqi@0:  , _pending_non_safepoint(NULL)
aoqi@0:  , _pending_non_safepoint_offset(0)
aoqi@0: {
aoqi@0:   _slow_case_stubs = new CodeStubList();
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: LIR_Assembler::~LIR_Assembler() {
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::check_codespace() {
aoqi@0:   CodeSection* cs = _masm->code_section();
aoqi@0:   if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
aoqi@0:     BAILOUT("CodeBuffer overflow");
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::append_code_stub(CodeStub* stub) {
aoqi@0:   _slow_case_stubs->append(stub);
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
aoqi@0:   for (int m = 0; m < stub_list->length(); m++) {
aoqi@0:     CodeStub* s = (*stub_list)[m];
aoqi@0: 
aoqi@0:     check_codespace();
aoqi@0:     CHECK_BAILOUT();
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:     if (CommentedAssembly) {
aoqi@0:       stringStream st;
aoqi@0:       s->print_name(&st);
aoqi@0:       st.print(" slow case");
aoqi@0:       _masm->block_comment(st.as_string());
aoqi@0:     }
aoqi@0: #endif
aoqi@0:     s->emit_code(this);
aoqi@0: #ifdef ASSERT
aoqi@0:     s->assert_no_unbound_labels();
aoqi@0: #endif
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_slow_case_stubs() {
aoqi@0:   emit_stubs(_slow_case_stubs);
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: bool LIR_Assembler::needs_icache(ciMethod* method) const {
aoqi@0:   return !method->is_static();
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: int LIR_Assembler::code_offset() const {
aoqi@0:   return _masm->offset();
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: address LIR_Assembler::pc() const {
aoqi@0:   return _masm->pc();
aoqi@0: }
aoqi@0: 
aoqi@0: // To bang the stack of this compiled method we use the stack size
aoqi@0: // that the interpreter would need in case of a deoptimization. This
aoqi@0: // removes the need to bang the stack in the deoptimization blob which
aoqi@0: // in turn simplifies stack overflow handling.
aoqi@0: int LIR_Assembler::bang_size_in_bytes() const {
aoqi@0:   return MAX2(initial_frame_size_in_bytes(), _compilation->interpreter_frame_size());
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
aoqi@0:   for (int i = 0; i < info_list->length(); i++) {
aoqi@0:     XHandlers* handlers = info_list->at(i)->exception_handlers();
aoqi@0: 
aoqi@0:     for (int j = 0; j < handlers->length(); j++) {
aoqi@0:       XHandler* handler = handlers->handler_at(j);
aoqi@0:       assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
aoqi@0:       assert(handler->entry_code() == NULL ||
aoqi@0:              handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
aoqi@0:              handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
aoqi@0: 
aoqi@0:       if (handler->entry_pco() == -1) {
aoqi@0:         // entry code not emitted yet
aoqi@0:         if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) {
aoqi@0:           handler->set_entry_pco(code_offset());
aoqi@0:           if (CommentedAssembly) {
aoqi@0:             _masm->block_comment("Exception adapter block");
aoqi@0:           }
aoqi@0:           emit_lir_list(handler->entry_code());
aoqi@0:         } else {
aoqi@0:           handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
aoqi@0:         }
aoqi@0: 
aoqi@0:         assert(handler->entry_pco() != -1, "must be set now");
aoqi@0:       }
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_code(BlockList* hir) {
aoqi@0:   if (PrintLIR) {
aoqi@0:     print_LIR(hir);
aoqi@0:   }
aoqi@0: 
aoqi@0:   int n = hir->length();
aoqi@0:   for (int i = 0; i < n; i++) {
aoqi@0:     emit_block(hir->at(i));
aoqi@0:     CHECK_BAILOUT();
aoqi@0:   }
aoqi@0: 
aoqi@0:   flush_debug_info(code_offset());
aoqi@0: 
aoqi@0:   DEBUG_ONLY(check_no_unbound_labels());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_block(BlockBegin* block) {
aoqi@0:   if (block->is_set(BlockBegin::backward_branch_target_flag)) {
aoqi@0:     align_backward_branch_target();
aoqi@0:   }
aoqi@0: 
aoqi@0:   // if this block is the start of an exception handler, record the
aoqi@0:   // PC offset of the first instruction for later construction of
aoqi@0:   // the ExceptionHandlerTable
aoqi@0:   if (block->is_set(BlockBegin::exception_entry_flag)) {
aoqi@0:     block->set_exception_handler_pco(code_offset());
aoqi@0:   }
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:   if (PrintLIRWithAssembly) {
aoqi@0:     // don't print Phi's
aoqi@0:     InstructionPrinter ip(false);
aoqi@0:     block->print(ip);
aoqi@0:   }
aoqi@0: #endif /* PRODUCT */
aoqi@0: 
aoqi@0:   assert(block->lir() != NULL, "must have LIR");
aoqi@0:   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:   if (CommentedAssembly) {
aoqi@0:     stringStream st;
aoqi@0:     st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
aoqi@0:     _masm->block_comment(st.as_string());
aoqi@0:   }
aoqi@0: #endif
aoqi@0: 
aoqi@0:   emit_lir_list(block->lir());
aoqi@0: 
aoqi@0:   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_lir_list(LIR_List* list) {
aoqi@0:   peephole(list);
aoqi@0: 
aoqi@0:   int n = list->length();
aoqi@0:   for (int i = 0; i < n; i++) {
aoqi@0:     LIR_Op* op = list->at(i);
aoqi@0: 
aoqi@0:     check_codespace();
aoqi@0:     CHECK_BAILOUT();
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:     if (CommentedAssembly) {
aoqi@0:       // Don't record out every op since that's too verbose.  Print
aoqi@0:       // branches since they include block and stub names.  Also print
aoqi@0:       // patching moves since they generate funny looking code.
aoqi@0:       if (op->code() == lir_branch ||
aoqi@0:           (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) {
aoqi@0:         stringStream st;
aoqi@0:         op->print_on(&st);
aoqi@0:         _masm->block_comment(st.as_string());
aoqi@0:       }
aoqi@0:     }
aoqi@0:     if (PrintLIRWithAssembly) {
aoqi@0:       // print out the LIR operation followed by the resulting assembly
aoqi@0:       list->at(i)->print(); tty->cr();
aoqi@0:     }
aoqi@0: #endif /* PRODUCT */
aoqi@0: 
aoqi@0:     op->emit_code(this);
aoqi@0: 
aoqi@0:     if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
aoqi@0:       process_debug_info(op);
aoqi@0:     }
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:     if (PrintLIRWithAssembly) {
aoqi@0:       _masm->code()->decode();
aoqi@0:     }
aoqi@0: #endif /* PRODUCT */
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: #ifdef ASSERT
aoqi@0: void LIR_Assembler::check_no_unbound_labels() {
aoqi@0:   CHECK_BAILOUT();
aoqi@0: 
aoqi@0:   for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
aoqi@0:     if (!_branch_target_blocks.at(i)->label()->is_bound()) {
aoqi@0:       tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
aoqi@0:       assert(false, "unbound label");
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: #endif
aoqi@0: 
aoqi@0: //----------------------------------debug info--------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
aoqi@0:   _masm->code_section()->relocate(pc(), relocInfo::poll_type);
aoqi@0:   int pc_offset = code_offset();
aoqi@0:   flush_debug_info(pc_offset);
aoqi@0:   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
aoqi@0:   if (info->exception_handlers() != NULL) {
aoqi@0:     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
aoqi@0:   flush_debug_info(pc_offset);
aoqi@0:   cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
aoqi@0:   if (cinfo->exception_handlers() != NULL) {
aoqi@0:     compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: static ValueStack* debug_info(Instruction* ins) {
aoqi@0:   StateSplit* ss = ins->as_StateSplit();
aoqi@0:   if (ss != NULL) return ss->state();
aoqi@0:   return ins->state_before();
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::process_debug_info(LIR_Op* op) {
aoqi@0:   Instruction* src = op->source();
aoqi@0:   if (src == NULL)  return;
aoqi@0:   int pc_offset = code_offset();
aoqi@0:   if (_pending_non_safepoint == src) {
aoqi@0:     _pending_non_safepoint_offset = pc_offset;
aoqi@0:     return;
aoqi@0:   }
aoqi@0:   ValueStack* vstack = debug_info(src);
aoqi@0:   if (vstack == NULL)  return;
aoqi@0:   if (_pending_non_safepoint != NULL) {
aoqi@0:     // Got some old debug info.  Get rid of it.
aoqi@0:     if (debug_info(_pending_non_safepoint) == vstack) {
aoqi@0:       _pending_non_safepoint_offset = pc_offset;
aoqi@0:       return;
aoqi@0:     }
aoqi@0:     if (_pending_non_safepoint_offset < pc_offset) {
aoqi@0:       record_non_safepoint_debug_info();
aoqi@0:     }
aoqi@0:     _pending_non_safepoint = NULL;
aoqi@0:   }
aoqi@0:   // Remember the debug info.
aoqi@0:   if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
aoqi@0:     _pending_non_safepoint = src;
aoqi@0:     _pending_non_safepoint_offset = pc_offset;
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
aoqi@0: // Return NULL if n is too large.
aoqi@0: // Returns the caller_bci for the next-younger state, also.
aoqi@0: static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
aoqi@0:   ValueStack* t = s;
aoqi@0:   for (int i = 0; i < n; i++) {
aoqi@0:     if (t == NULL)  break;
aoqi@0:     t = t->caller_state();
aoqi@0:   }
aoqi@0:   if (t == NULL)  return NULL;
aoqi@0:   for (;;) {
aoqi@0:     ValueStack* tc = t->caller_state();
aoqi@0:     if (tc == NULL)  return s;
aoqi@0:     t = tc;
aoqi@0:     bci_result = tc->bci();
aoqi@0:     s = s->caller_state();
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::record_non_safepoint_debug_info() {
aoqi@0:   int         pc_offset = _pending_non_safepoint_offset;
aoqi@0:   ValueStack* vstack    = debug_info(_pending_non_safepoint);
aoqi@0:   int         bci       = vstack->bci();
aoqi@0: 
aoqi@0:   DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
aoqi@0:   assert(debug_info->recording_non_safepoints(), "sanity");
aoqi@0: 
aoqi@0:   debug_info->add_non_safepoint(pc_offset);
aoqi@0: 
aoqi@0:   // Visit scopes from oldest to youngest.
aoqi@0:   for (int n = 0; ; n++) {
aoqi@0:     int s_bci = bci;
aoqi@0:     ValueStack* s = nth_oldest(vstack, n, s_bci);
aoqi@0:     if (s == NULL)  break;
aoqi@0:     IRScope* scope = s->scope();
aoqi@0:     //Always pass false for reexecute since these ScopeDescs are never used for deopt
aoqi@0:     debug_info->describe_scope(pc_offset, scope->method(), s->bci(), false/*reexecute*/);
aoqi@0:   }
aoqi@0: 
aoqi@0:   debug_info->end_non_safepoint(pc_offset);
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
aoqi@0:   add_debug_info_for_null_check(code_offset(), cinfo);
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
aoqi@0:   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
aoqi@0:   append_code_stub(stub);
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
aoqi@0:   add_debug_info_for_div0(code_offset(), info);
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
aoqi@0:   DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
aoqi@0:   append_code_stub(stub);
aoqi@0: }
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
aoqi@0:   rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
aoqi@0:   verify_oop_map(op->info());
aoqi@0: 
aoqi@0:   if (os::is_MP()) {
aoqi@0:     // must align calls sites, otherwise they can't be updated atomically on MP hardware
aoqi@0:     align_call(op->code());
aoqi@0:   }
aoqi@0: 
aoqi@0:   // emit the static call stub stuff out of line
aoqi@0:   emit_static_call_stub();
aoqi@0: 
aoqi@0:   switch (op->code()) {
aoqi@0:   case lir_static_call:
aoqi@0:   case lir_dynamic_call:
aoqi@0:     call(op, relocInfo::static_call_type);
aoqi@0:     break;
aoqi@0:   case lir_optvirtual_call:
aoqi@0:     call(op, relocInfo::opt_virtual_call_type);
aoqi@0:     break;
aoqi@0:   case lir_icvirtual_call:
aoqi@0:     ic_call(op);
aoqi@0:     break;
aoqi@0:   case lir_virtual_call:
aoqi@0:     vtable_call(op);
aoqi@0:     break;
aoqi@0:   default:
aoqi@0:     fatal(err_msg_res("unexpected op code: %s", op->name()));
aoqi@0:     break;
aoqi@0:   }
aoqi@0: 
aoqi@0:   // JSR 292
aoqi@0:   // Record if this method has MethodHandle invokes.
aoqi@0:   if (op->is_method_handle_invoke()) {
aoqi@0:     compilation()->set_has_method_handle_invokes(true);
aoqi@0:   }
aoqi@0: 
aoqi@0: #if defined(X86) && defined(TIERED)
aoqi@0:   // C2 leave fpu stack dirty clean it
aoqi@0:   if (UseSSE < 2) {
aoqi@0:     int i;
aoqi@0:     for ( i = 1; i <= 7 ; i++ ) {
aoqi@0:       ffree(i);
aoqi@0:     }
aoqi@0:     if (!op->result_opr()->is_float_kind()) {
aoqi@0:       ffree(0);
aoqi@0:     }
aoqi@0:   }
aoqi@0: #endif // X86 && TIERED
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
aoqi@0:   _masm->bind (*(op->label()));
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_op1(LIR_Op1* op) {
aoqi@0:   switch (op->code()) {
aoqi@0:     case lir_move:
aoqi@0:       if (op->move_kind() == lir_move_volatile) {
aoqi@0:         assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
aoqi@0:         volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
aoqi@0:       } else {
aoqi@0:         move_op(op->in_opr(), op->result_opr(), op->type(),
aoqi@0:                 op->patch_code(), op->info(), op->pop_fpu_stack(),
aoqi@0:                 op->move_kind() == lir_move_unaligned,
aoqi@0:                 op->move_kind() == lir_move_wide);
aoqi@0:       }
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_prefetchr:
aoqi@0:       prefetchr(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_prefetchw:
aoqi@0:       prefetchw(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_roundfp: {
aoqi@0:       LIR_OpRoundFP* round_op = op->as_OpRoundFP();
aoqi@0:       roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
aoqi@0:       break;
aoqi@0:     }
aoqi@0: 
aoqi@0:     case lir_return:
aoqi@0:       return_op(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_safepoint:
aoqi@0:       if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
aoqi@0:         _masm->nop();
aoqi@0:       }
aoqi@0:       safepoint_poll(op->in_opr(), op->info());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_fxch:
aoqi@0:       fxch(op->in_opr()->as_jint());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_fld:
aoqi@0:       fld(op->in_opr()->as_jint());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_ffree:
aoqi@0:       ffree(op->in_opr()->as_jint());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_branch:
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_push:
aoqi@0:       push(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_pop:
aoqi@0:       pop(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_neg:
aoqi@0:       negate(op->in_opr(), op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_leal:
aoqi@0:       leal(op->in_opr(), op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_null_check:
aoqi@0:       if (GenerateCompilerNullChecks) {
aoqi@0:         add_debug_info_for_null_check_here(op->info());
aoqi@0: 
aoqi@0:         if (op->in_opr()->is_single_cpu()) {
aoqi@0:           _masm->null_check(op->in_opr()->as_register());
aoqi@0:         } else {
aoqi@0:           Unimplemented();
aoqi@0:         }
aoqi@0:       }
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_monaddr:
aoqi@0:       monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0: #ifdef SPARC
aoqi@0:     case lir_pack64:
aoqi@0:       pack64(op->in_opr(), op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_unpack64:
aoqi@0:       unpack64(op->in_opr(), op->result_opr());
aoqi@0:       break;
aoqi@0: #endif
aoqi@0: 
aoqi@0:     case lir_unwind:
aoqi@0:       unwind_op(op->in_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     default:
aoqi@0:       Unimplemented();
aoqi@0:       break;
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_op0(LIR_Op0* op) {
aoqi@0:   switch (op->code()) {
aoqi@0:     case lir_word_align: {
aoqi@0:       while (code_offset() % BytesPerWord != 0) {
aoqi@0:         _masm->nop();
aoqi@0:       }
aoqi@0:       break;
aoqi@0:     }
aoqi@0: 
aoqi@0:     case lir_nop:
aoqi@0:       assert(op->info() == NULL, "not supported");
aoqi@0:       _masm->nop();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_label:
aoqi@0:       Unimplemented();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_build_frame:
aoqi@0:       build_frame();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_std_entry:
aoqi@0:       // init offsets
aoqi@0:       offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
aoqi@0:       _masm->align(CodeEntryAlignment);
aoqi@0:       if (needs_icache(compilation()->method())) {
aoqi@0:         check_icache();
aoqi@0:       }
aoqi@0:       offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
aoqi@0:       _masm->verified_entry();
aoqi@0:       build_frame();
aoqi@0:       offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_osr_entry:
aoqi@0:       offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
aoqi@0:       osr_entry();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_24bit_FPU:
aoqi@0:       set_24bit_FPU();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_reset_FPU:
aoqi@0:       reset_FPU();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_breakpoint:
aoqi@0:       breakpoint();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_fpop_raw:
aoqi@0:       fpop();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar:
aoqi@0:       membar();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_acquire:
aoqi@0:       membar_acquire();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_release:
aoqi@0:       membar_release();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_loadload:
aoqi@0:       membar_loadload();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_storestore:
aoqi@0:       membar_storestore();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_loadstore:
aoqi@0:       membar_loadstore();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_membar_storeload:
aoqi@0:       membar_storeload();
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_get_thread:
aoqi@0:       get_thread(op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     default:
aoqi@0:       ShouldNotReachHere();
aoqi@0:       break;
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::emit_op2(LIR_Op2* op) {
aoqi@0:   switch (op->code()) {
aoqi@1: #ifndef MIPS64
aoqi@0:     case lir_cmp:
aoqi@0:       if (op->info() != NULL) {
aoqi@0:         assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
aoqi@0:                "shouldn't be codeemitinfo for non-address operands");
aoqi@0:         add_debug_info_for_null_check_here(op->info()); // exception possible
aoqi@0:       }
aoqi@0:       comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
aoqi@0:       break;
aoqi@1: #else
aoqi@1:    case lir_null_check_for_branch:
aoqi@1:         if (op->info() != NULL) {
aoqi@1:                                 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
aoqi@1:                                                 "shouldn't be codeemitinfo for non-address operands");
aoqi@1:                                 add_debug_info_for_null_check_here(op->info()); // exception possible
aoqi@1:                         }
aoqi@1:       break;
aoqi@1: #endif
aoqi@0: 
aoqi@0:     case lir_cmp_l2i:
aoqi@0:     case lir_cmp_fd2i:
aoqi@0:     case lir_ucmp_fd2i:
aoqi@0:       comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_cmove:
aoqi@1: #ifndef MIPS64
aoqi@0:       cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
aoqi@1: #endif
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_shl:
aoqi@0:     case lir_shr:
aoqi@0:     case lir_ushr:
aoqi@0:       if (op->in_opr2()->is_constant()) {
aoqi@0:         shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
aoqi@0:       } else {
aoqi@0:         shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
aoqi@0:       }
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_add:
aoqi@0:     case lir_sub:
aoqi@0:     case lir_mul:
aoqi@0:     case lir_mul_strictfp:
aoqi@0:     case lir_div:
aoqi@0:     case lir_div_strictfp:
aoqi@0:     case lir_rem:
aoqi@0:       assert(op->fpu_pop_count() < 2, "");
aoqi@0:       arith_op(
aoqi@0:         op->code(),
aoqi@0:         op->in_opr1(),
aoqi@0:         op->in_opr2(),
aoqi@0:         op->result_opr(),
aoqi@0:         op->info(),
aoqi@0:         op->fpu_pop_count() == 1);
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_abs:
aoqi@0:     case lir_sqrt:
aoqi@0:     case lir_sin:
aoqi@0:     case lir_tan:
aoqi@0:     case lir_cos:
aoqi@0:     case lir_log:
aoqi@0:     case lir_log10:
aoqi@0:     case lir_exp:
aoqi@0:     case lir_pow:
aoqi@0:       intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_logic_and:
aoqi@0:     case lir_logic_or:
aoqi@0:     case lir_logic_xor:
aoqi@0:       logic_op(
aoqi@0:         op->code(),
aoqi@0:         op->in_opr1(),
aoqi@0:         op->in_opr2(),
aoqi@0:         op->result_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_throw:
aoqi@0:       throw_op(op->in_opr1(), op->in_opr2(), op->info());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     case lir_xadd:
aoqi@0:     case lir_xchg:
aoqi@0:       atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
aoqi@0:       break;
aoqi@0: 
aoqi@0:     default:
aoqi@0:       Unimplemented();
aoqi@0:       break;
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::build_frame() {
aoqi@0:   _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
aoqi@0:   assert((src->is_single_fpu() && dest->is_single_stack()) ||
aoqi@0:          (src->is_double_fpu() && dest->is_double_stack()),
aoqi@0:          "round_fp: rounds register -> stack location");
aoqi@0: 
aoqi@0:   reg2stack (src, dest, src->type(), pop_fpu_stack);
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
aoqi@0:   if (src->is_register()) {
aoqi@0:     if (dest->is_register()) {
aoqi@0:       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
aoqi@0:       reg2reg(src,  dest);
aoqi@0:     } else if (dest->is_stack()) {
aoqi@0:       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
aoqi@0:       reg2stack(src, dest, type, pop_fpu_stack);
aoqi@0:     } else if (dest->is_address()) {
aoqi@0:       reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
aoqi@0:     } else {
aoqi@0:       ShouldNotReachHere();
aoqi@0:     }
aoqi@0: 
aoqi@0:   } else if (src->is_stack()) {
aoqi@0:     assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
aoqi@0:     if (dest->is_register()) {
aoqi@0:       stack2reg(src, dest, type);
aoqi@0:     } else if (dest->is_stack()) {
aoqi@0:       stack2stack(src, dest, type);
aoqi@0:     } else {
aoqi@0:       ShouldNotReachHere();
aoqi@0:     }
aoqi@0: 
aoqi@0:   } else if (src->is_constant()) {
aoqi@0:     if (dest->is_register()) {
aoqi@0:       const2reg(src, dest, patch_code, info); // patching is possible
aoqi@0:     } else if (dest->is_stack()) {
aoqi@0:       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
aoqi@0:       const2stack(src, dest);
aoqi@0:     } else if (dest->is_address()) {
aoqi@0:       assert(patch_code == lir_patch_none, "no patching allowed here");
aoqi@0:       const2mem(src, dest, type, info, wide);
aoqi@0:     } else {
aoqi@0:       ShouldNotReachHere();
aoqi@0:     }
aoqi@0: 
aoqi@0:   } else if (src->is_address()) {
aoqi@0:     mem2reg(src, dest, type, patch_code, info, wide, unaligned);
aoqi@0: 
aoqi@0:   } else {
aoqi@0:     ShouldNotReachHere();
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
aoqi@0: #ifndef PRODUCT
aoqi@0:   if (VerifyOops) {
aoqi@0:     OopMapStream s(info->oop_map());
aoqi@0:     while (!s.is_done()) {
aoqi@0:       OopMapValue v = s.current();
aoqi@0:       if (v.is_oop()) {
aoqi@0:         VMReg r = v.reg();
aoqi@0:         if (!r->is_stack()) {
aoqi@0:           stringStream st;
aoqi@0:           st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset());
aoqi@0: #ifdef SPARC
aoqi@0:           _masm->_verify_oop(r->as_Register(), strdup(st.as_string()), __FILE__, __LINE__);
aoqi@0: #else
aoqi@0:           _masm->verify_oop(r->as_Register());
aoqi@0: #endif
aoqi@0:         } else {
aoqi@0:           _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
aoqi@0:         }
aoqi@0:       }
aoqi@0:       check_codespace();
aoqi@0:       CHECK_BAILOUT();
aoqi@0: 
aoqi@0:       s.next();
aoqi@0:     }
aoqi@0:   }
aoqi@0: #endif
aoqi@0: }