aoqi@0: /*
aoqi@0:  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
aoqi@0:  *
aoqi@0:  */
aoqi@0: 
aoqi@0: #include "precompiled.hpp"
aoqi@0: #include "asm/macroAssembler.hpp"
aoqi@0: #include "memory/resourceArea.hpp"
aoqi@0: #include "nativeInst_sparc.hpp"
aoqi@0: #include "oops/oop.inline.hpp"
aoqi@0: #include "runtime/handles.hpp"
aoqi@0: #include "runtime/sharedRuntime.hpp"
aoqi@0: #include "runtime/stubRoutines.hpp"
aoqi@0: #include "utilities/ostream.hpp"
aoqi@0: #ifdef COMPILER1
aoqi@0: #include "c1/c1_Runtime1.hpp"
aoqi@0: #endif
aoqi@0: 
aoqi@0: 
aoqi@0: bool NativeInstruction::is_dtrace_trap() {
aoqi@0:   return !is_nop();
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) {
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer buf(instaddr, 10 * BytesPerInstWord );
aoqi@0:   MacroAssembler* _masm = new MacroAssembler(&buf);
aoqi@0:   Register destreg;
aoqi@0: 
aoqi@0:   destreg = inv_rd(*(unsigned int *)instaddr);
aoqi@0:   // Generate a the new sequence
aoqi@0:   _masm->patchable_sethi(x, destreg);
aoqi@0:   ICache::invalidate_range(instaddr, 7 * BytesPerInstWord);
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::verify_data64_sethi(address instaddr, intptr_t x) {
aoqi@0:   ResourceMark rm;
aoqi@0:   unsigned char buffer[10 * BytesPerInstWord];
aoqi@0:   CodeBuffer buf(buffer, 10 * BytesPerInstWord);
aoqi@0:   MacroAssembler masm(&buf);
aoqi@0: 
aoqi@0:   Register destreg = inv_rd(*(unsigned int *)instaddr);
aoqi@0:   // Generate the proper sequence into a temporary buffer and compare
aoqi@0:   // it with the original sequence.
aoqi@0:   masm.patchable_sethi(x, destreg);
aoqi@0:   int len = buffer - masm.pc();
aoqi@0:   for (int i = 0; i < len; i++) {
aoqi@0:     assert(instaddr[i] == buffer[i], "instructions must match");
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::verify() {
aoqi@0:   // make sure code pattern is actually an instruction address
aoqi@0:   address addr = addr_at(0);
aoqi@0:   if (addr == 0 || ((intptr_t)addr & 3) != 0) {
aoqi@0:     fatal("not an instruction address");
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0));
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::set_long_at(int offset, int i) {
aoqi@0:   address addr = addr_at(offset);
aoqi@0:   *(int*)addr = i;
aoqi@0:   ICache::invalidate_word(addr);
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::set_jlong_at(int offset, jlong i) {
aoqi@0:   address addr = addr_at(offset);
aoqi@0:   *(jlong*)addr = i;
aoqi@0:   // Don't need to invalidate 2 words here, because
aoqi@0:   // the flush instruction operates on doublewords.
aoqi@0:   ICache::invalidate_word(addr);
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeInstruction::set_addr_at(int offset, address x) {
aoqi@0:   address addr = addr_at(offset);
aoqi@0:   assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment");
aoqi@0:   *(uintptr_t*)addr = (uintptr_t)x;
aoqi@0:   // Don't need to invalidate 2 words here in the 64-bit case,
aoqi@0:   // because the flush instruction operates on doublewords.
aoqi@0:   ICache::invalidate_word(addr);
aoqi@0:   // The Intel code has this assertion for NativeCall::set_destination,
aoqi@0:   // NativeMovConstReg::set_data, NativeMovRegMem::set_offset,
aoqi@0:   // NativeJump::set_jump_destination, and NativePushImm32::set_data
aoqi@0:   //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction")
aoqi@0: }
aoqi@0: 
aoqi@0: bool NativeInstruction::is_zero_test(Register &reg) {
aoqi@0:   int x = long_at(0);
aoqi@0:   Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3);
aoqi@0:   if (is_op3(x, temp, Assembler::arith_op) &&
aoqi@0:       inv_immed(x) && inv_rd(x) == G0) {
aoqi@0:       if (inv_rs1(x) == G0) {
aoqi@0:         reg = inv_rs2(x);
aoqi@0:         return true;
aoqi@0:       } else if (inv_rs2(x) == G0) {
aoqi@0:         reg = inv_rs1(x);
aoqi@0:         return true;
aoqi@0:       }
aoqi@0:   }
aoqi@0:   return false;
aoqi@0: }
aoqi@0: 
aoqi@0: bool NativeInstruction::is_load_store_with_small_offset(Register reg) {
aoqi@0:   int x = long_at(0);
aoqi@0:   if (is_op(x, Assembler::ldst_op) &&
aoqi@0:       inv_rs1(x) == reg && inv_immed(x)) {
aoqi@0:     return true;
aoqi@0:   }
aoqi@0:   return false;
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeCall::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   // make sure code pattern is actually a call instruction
aoqi@0:   if (!is_op(long_at(0), Assembler::call_op)) {
aoqi@0:     fatal("not a call");
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeCall::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // MT-safe patching of a call instruction (and following word).
aoqi@0: // First patches the second word, and then atomicly replaces
aoqi@0: // the first word with the first new instruction word.
aoqi@0: // Other processors might briefly see the old first word
aoqi@0: // followed by the new second word.  This is OK if the old
aoqi@0: // second word is harmless, and the new second word may be
aoqi@0: // harmlessly executed in the delay slot of the call.
aoqi@0: void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
aoqi@0:   assert(Patching_lock->is_locked() ||
aoqi@0:          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
aoqi@0:    assert (instr_addr != NULL, "illegal address for code patching");
aoqi@0:    NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
aoqi@0:    assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
aoqi@0:    int i0 = ((int*)code_buffer)[0];
aoqi@0:    int i1 = ((int*)code_buffer)[1];
aoqi@0:    int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
aoqi@0:    assert(inv_op(*contention_addr) == Assembler::arith_op ||
aoqi@0:           *contention_addr == nop_instruction(),
aoqi@0:           "must not interfere with original call");
aoqi@0:    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
aoqi@0:    n_call->set_long_at(1*BytesPerInstWord, i1);
aoqi@0:    n_call->set_long_at(0*BytesPerInstWord, i0);
aoqi@0:    // NOTE:  It is possible that another thread T will execute
aoqi@0:    // only the second patched word.
aoqi@0:    // In other words, since the original instruction is this
aoqi@0:    //    call patching_stub; nop                   (NativeCall)
aoqi@0:    // and the new sequence from the buffer is this:
aoqi@0:    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
aoqi@0:    // what T will execute is this:
aoqi@0:    //    call patching_stub; add %r, %lo(K), %r
aoqi@0:    // thereby putting garbage into %r before calling the patching stub.
aoqi@0:    // This is OK, because the patching stub ignores the value of %r.
aoqi@0: 
aoqi@0:    // Make sure the first-patched instruction, which may co-exist
aoqi@0:    // briefly with the call, will do something harmless.
aoqi@0:    assert(inv_op(*contention_addr) == Assembler::arith_op ||
aoqi@0:           *contention_addr == nop_instruction(),
aoqi@0:           "must not interfere with original call");
aoqi@0: }
aoqi@0: 
aoqi@0: // Similar to replace_mt_safe, but just changes the destination.  The
aoqi@0: // important thing is that free-running threads are able to execute this
aoqi@0: // call instruction at all times.  Thus, the displacement field must be
aoqi@0: // instruction-word-aligned.  This is always true on SPARC.
aoqi@0: //
aoqi@0: // Used in the runtime linkage of calls; see class CompiledIC.
aoqi@0: void NativeCall::set_destination_mt_safe(address dest) {
aoqi@0:   assert(Patching_lock->is_locked() ||
aoqi@0:          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
aoqi@0:   // set_destination uses set_long_at which does the ICache::invalidate
aoqi@0:   set_destination(dest);
aoqi@0: }
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeCall class
aoqi@0: void NativeCall::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 100, 100);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeCall  *nc;
aoqi@0:   uint idx;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0xfffffff0,
aoqi@0:     0x7ffffff0,
aoqi@0:     0x80000000,
aoqi@0:     0x20,
aoqi@0:     0x4000,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   a->call( a->pc(), relocInfo::none );
aoqi@0:   a->delayed()->nop();
aoqi@0:   nc = nativeCall_at( cb.insts_begin() );
aoqi@0:   nc->print();
aoqi@0: 
aoqi@0:   nc = nativeCall_overwriting_at( nc->next_instruction_address() );
aoqi@0:   for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
aoqi@0:     nc->set_destination( cb.insts_begin() + offsets[idx] );
aoqi@0:     assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test");
aoqi@0:     nc->print();
aoqi@0:   }
aoqi@0: 
aoqi@0:   nc = nativeCall_before( cb.insts_begin() + 8 );
aoqi@0:   nc->print();
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeCall class
aoqi@0: 
aoqi@0: //-------------------------------------------------------------------
aoqi@0: 
aoqi@0: #ifdef _LP64
aoqi@0: 
aoqi@0: void NativeFarCall::set_destination(address dest) {
aoqi@0:   // Address materialized in the instruction stream, so nothing to do.
aoqi@0:   return;
aoqi@0: #if 0 // What we'd do if we really did want to change the destination
aoqi@0:   if (destination() == dest) {
aoqi@0:     return;
aoqi@0:   }
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer buf(addr_at(0), instruction_size + 1);
aoqi@0:   MacroAssembler* _masm = new MacroAssembler(&buf);
aoqi@0:   // Generate the new sequence
aoqi@0:   AddressLiteral(dest);
aoqi@0:   _masm->jumpl_to(dest, O7, O7);
aoqi@0:   ICache::invalidate_range(addr_at(0), instruction_size );
aoqi@0: #endif
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeFarCall::verify() {
aoqi@0:   // make sure code pattern is actually a jumpl_to instruction
aoqi@0:   assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to");
aoqi@0:   assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
aoqi@0:   nativeJump_at(addr_at(0))->verify();
aoqi@0: }
aoqi@0: 
aoqi@0: bool NativeFarCall::is_call_at(address instr) {
aoqi@0:   return nativeInstruction_at(instr)->is_sethi();
aoqi@0: }
aoqi@0: 
aoqi@0: void NativeFarCall::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
aoqi@0: }
aoqi@0: 
aoqi@0: bool NativeFarCall::destination_is_compiled_verified_entry_point() {
aoqi@0:   nmethod* callee = CodeCache::find_nmethod(destination());
aoqi@0:   if (callee == NULL) {
aoqi@0:     return false;
aoqi@0:   } else {
aoqi@0:     return destination() == callee->verified_entry_point();
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: // MT-safe patching of a far call.
aoqi@0: void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) {
aoqi@0:   Unimplemented();
aoqi@0: }
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeFarCall class
aoqi@0: void NativeFarCall::test() {
aoqi@0:   Unimplemented();
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeFarCall class
aoqi@0: 
aoqi@0: #endif // _LP64
aoqi@0: 
aoqi@0: //-------------------------------------------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovConstReg::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   // make sure code pattern is actually a "set_metadata" synthetic instruction
aoqi@0:   // see MacroAssembler::set_oop()
aoqi@0:   int i0 = long_at(sethi_offset);
aoqi@0:   int i1 = long_at(add_offset);
aoqi@0: 
aoqi@0:   // verify the pattern "sethi %hi22(imm), reg ;  add reg, %lo10(imm), reg"
aoqi@0:   Register rd = inv_rd(i0);
aoqi@0: #ifndef _LP64
aoqi@0:   if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
aoqi@0:         is_op3(i1, Assembler::add_op3, Assembler::arith_op) &&
aoqi@0:         inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
aoqi@0:         rd == inv_rs1(i1) && rd == inv_rd(i1))) {
aoqi@0:     fatal("not a set_metadata");
aoqi@0:   }
aoqi@0: #else
aoqi@0:   if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
aoqi@0:     fatal("not a set_metadata");
aoqi@0:   }
aoqi@0: #endif
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovConstReg::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: #ifdef _LP64
aoqi@0: intptr_t NativeMovConstReg::data() const {
aoqi@0:   return data64(addr_at(sethi_offset), long_at(add_offset));
aoqi@0: }
aoqi@0: #else
aoqi@0: intptr_t NativeMovConstReg::data() const {
aoqi@0:   return data32(long_at(sethi_offset), long_at(add_offset));
aoqi@0: }
aoqi@0: #endif
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovConstReg::set_data(intptr_t x) {
aoqi@0: #ifdef _LP64
aoqi@0:   set_data64_sethi(addr_at(sethi_offset), x);
aoqi@0: #else
aoqi@0:   set_long_at(sethi_offset, set_data32_sethi(  long_at(sethi_offset), x));
aoqi@0: #endif
aoqi@0:   set_long_at(add_offset,   set_data32_simm13( long_at(add_offset),   x));
aoqi@0: 
aoqi@0:   // also store the value into an oop_Relocation cell, if any
aoqi@0:   CodeBlob* cb = CodeCache::find_blob(instruction_address());
aoqi@0:   nmethod*  nm = cb ? cb->as_nmethod_or_null() : NULL;
aoqi@0:   if (nm != NULL) {
aoqi@0:     RelocIterator iter(nm, instruction_address(), next_instruction_address());
aoqi@0:     oop* oop_addr = NULL;
aoqi@0:     Metadata** metadata_addr = NULL;
aoqi@0:     while (iter.next()) {
aoqi@0:       if (iter.type() == relocInfo::oop_type) {
aoqi@0:         oop_Relocation *r = iter.oop_reloc();
aoqi@0:         if (oop_addr == NULL) {
aoqi@0:           oop_addr = r->oop_addr();
aoqi@0:           *oop_addr = cast_to_oop(x);
aoqi@0:         } else {
aoqi@0:           assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
aoqi@0:         }
aoqi@0:       }
aoqi@0:       if (iter.type() == relocInfo::metadata_type) {
aoqi@0:         metadata_Relocation *r = iter.metadata_reloc();
aoqi@0:         if (metadata_addr == NULL) {
aoqi@0:           metadata_addr = r->metadata_addr();
aoqi@0:           *metadata_addr = (Metadata*)x;
aoqi@0:         } else {
aoqi@0:           assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here");
aoqi@0:         }
aoqi@0:       }
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeMovConstReg class
aoqi@0: void NativeMovConstReg::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 100, 100);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeMovConstReg* nm;
aoqi@0:   uint idx;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0x7fffffff,
aoqi@0:     0x80000000,
aoqi@0:     0xffffffff,
aoqi@0:     0x20,
aoqi@0:     4096,
aoqi@0:     4097,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
aoqi@0:   a->sethi(al1, I3);
aoqi@0:   a->add(I3, al1.low10(), I3);
aoqi@0:   AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
aoqi@0:   a->sethi(al2, O2);
aoqi@0:   a->add(O2, al2.low10(), O2);
aoqi@0: 
aoqi@0:   nm = nativeMovConstReg_at( cb.insts_begin() );
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   nm = nativeMovConstReg_at( nm->next_instruction_address() );
aoqi@0:   for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
aoqi@0:     nm->set_data( offsets[idx] );
aoqi@0:     assert(nm->data() == offsets[idx], "check unit test");
aoqi@0:   }
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeMovConstReg class
aoqi@0: 
aoqi@0: //-------------------------------------------------------------------
aoqi@0: 
aoqi@0: void NativeMovConstRegPatching::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   // Make sure code pattern is sethi/nop/add.
aoqi@0:   int i0 = long_at(sethi_offset);
aoqi@0:   int i1 = long_at(nop_offset);
aoqi@0:   int i2 = long_at(add_offset);
aoqi@0:   assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
aoqi@0: 
aoqi@0:   // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg"
aoqi@0:   // The casual reader should note that on Sparc a nop is a special case if sethi
aoqi@0:   // in which the destination register is %g0.
aoqi@0:   Register rd0 = inv_rd(i0);
aoqi@0:   Register rd1 = inv_rd(i1);
aoqi@0:   if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 &&
aoqi@0:         is_op2(i1, Assembler::sethi_op2) && rd1 == G0 &&        // nop is a special case of sethi
aoqi@0:         is_op3(i2, Assembler::add_op3, Assembler::arith_op) &&
aoqi@0:         inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) &&
aoqi@0:         rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) {
aoqi@0:     fatal("not a set_metadata");
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovConstRegPatching::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: int NativeMovConstRegPatching::data() const {
aoqi@0: #ifdef _LP64
aoqi@0:   return data64(addr_at(sethi_offset), long_at(add_offset));
aoqi@0: #else
aoqi@0:   return data32(long_at(sethi_offset), long_at(add_offset));
aoqi@0: #endif
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovConstRegPatching::set_data(int x) {
aoqi@0: #ifdef _LP64
aoqi@0:   set_data64_sethi(addr_at(sethi_offset), x);
aoqi@0: #else
aoqi@0:   set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x));
aoqi@0: #endif
aoqi@0:   set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x));
aoqi@0: 
aoqi@0:   // also store the value into an oop_Relocation cell, if any
aoqi@0:   CodeBlob* cb = CodeCache::find_blob(instruction_address());
aoqi@0:   nmethod*  nm = cb ? cb->as_nmethod_or_null() : NULL;
aoqi@0:   if (nm != NULL) {
aoqi@0:     RelocIterator iter(nm, instruction_address(), next_instruction_address());
aoqi@0:     oop* oop_addr = NULL;
aoqi@0:     Metadata** metadata_addr = NULL;
aoqi@0:     while (iter.next()) {
aoqi@0:       if (iter.type() == relocInfo::oop_type) {
aoqi@0:         oop_Relocation *r = iter.oop_reloc();
aoqi@0:         if (oop_addr == NULL) {
aoqi@0:           oop_addr = r->oop_addr();
aoqi@0:           *oop_addr = cast_to_oop(x);
aoqi@0:         } else {
aoqi@0:           assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
aoqi@0:         }
aoqi@0:       }
aoqi@0:       if (iter.type() == relocInfo::metadata_type) {
aoqi@0:         metadata_Relocation *r = iter.metadata_reloc();
aoqi@0:         if (metadata_addr == NULL) {
aoqi@0:           metadata_addr = r->metadata_addr();
aoqi@0:           *metadata_addr = (Metadata*)x;
aoqi@0:         } else {
aoqi@0:           assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here");
aoqi@0:         }
aoqi@0:       }
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeMovConstRegPatching class
aoqi@0: void NativeMovConstRegPatching::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 100, 100);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeMovConstRegPatching* nm;
aoqi@0:   uint idx;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0x7fffffff,
aoqi@0:     0x80000000,
aoqi@0:     0xffffffff,
aoqi@0:     0x20,
aoqi@0:     4096,
aoqi@0:     4097,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type);
aoqi@0:   a->sethi(al1, I3);
aoqi@0:   a->nop();
aoqi@0:   a->add(I3, al1.low10(), I3);
aoqi@0:   AddressLiteral al2(0xccccdddd, relocInfo::external_word_type);
aoqi@0:   a->sethi(al2, O2);
aoqi@0:   a->nop();
aoqi@0:   a->add(O2, al2.low10(), O2);
aoqi@0: 
aoqi@0:   nm = nativeMovConstRegPatching_at( cb.insts_begin() );
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   nm = nativeMovConstRegPatching_at( nm->next_instruction_address() );
aoqi@0:   for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
aoqi@0:     nm->set_data( offsets[idx] );
aoqi@0:     assert(nm->data() == offsets[idx], "check unit test");
aoqi@0:   }
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif // ASSERT
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeMovConstRegPatching class
aoqi@0: 
aoqi@0: 
aoqi@0: //-------------------------------------------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
aoqi@0:   Untested("copy_instruction_to");
aoqi@0:   int instruction_size = next_instruction_address() - instruction_address();
aoqi@0:   for (int i = 0; i < instruction_size; i += BytesPerInstWord) {
aoqi@0:     *(int*)(new_instruction_address + i) = *(int*)(address(this) + i);
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMem::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   // make sure code pattern is actually a "ld" or "st" of some sort.
aoqi@0:   int i0 = long_at(0);
aoqi@0:   int op3 = inv_op3(i0);
aoqi@0: 
aoqi@0:   assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok");
aoqi@0: 
aoqi@0:   if (!(is_op(i0, Assembler::ldst_op) &&
aoqi@0:         inv_immed(i0) &&
aoqi@0:         0 != (op3 < op3_ldst_int_limit
aoqi@0:          ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
aoqi@0:          : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))))
aoqi@0:   {
aoqi@0:     int i1 = long_at(ldst_offset);
aoqi@0:     Register rd = inv_rd(i0);
aoqi@0: 
aoqi@0:     op3 = inv_op3(i1);
aoqi@0:     if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
aoqi@0:          0 != (op3 < op3_ldst_int_limit
aoqi@0:               ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
aoqi@0:                : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
aoqi@0:       fatal("not a ld* or st* op");
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMem::print() {
aoqi@0:   if (is_immediate()) {
aoqi@0:     tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
aoqi@0:   } else {
aoqi@0:     tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeMovRegMem class
aoqi@0: void NativeMovRegMem::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 1000, 1000);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeMovRegMem* nm;
aoqi@0:   uint idx = 0;
aoqi@0:   uint idx1;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0xffffffff,
aoqi@0:     0x7fffffff,
aoqi@0:     0x80000000,
aoqi@0:     4096,
aoqi@0:     4097,
aoqi@0:     0x20,
aoqi@0:     0x4000,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   AddressLiteral al1(0xffffffff, relocInfo::external_word_type);
aoqi@0:   AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type);
aoqi@0:   a->ldsw( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldsw( G5, I3, G4 ); idx++;
aoqi@0:   a->ldsb( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldsb( G5, I3, G4 ); idx++;
aoqi@0:   a->ldsh( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldsh( G5, I3, G4 ); idx++;
aoqi@0:   a->lduw( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->lduw( G5, I3, G4 ); idx++;
aoqi@0:   a->ldub( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldub( G5, I3, G4 ); idx++;
aoqi@0:   a->lduh( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->lduh( G5, I3, G4 ); idx++;
aoqi@0:   a->ldx( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldx( G5, I3, G4 ); idx++;
aoqi@0:   a->ldd( G5, al1.low10(), G4 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldd( G5, I3, G4 ); idx++;
aoqi@0:   a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
aoqi@0: 
aoqi@0:   a->stw( G5, G4, al1.low10() ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->stw( G5, G4, I3 ); idx++;
aoqi@0:   a->stb( G5, G4, al1.low10() ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->stb( G5, G4, I3 ); idx++;
aoqi@0:   a->sth( G5, G4, al1.low10() ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->sth( G5, G4, I3 ); idx++;
aoqi@0:   a->stx( G5, G4, al1.low10() ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->stx( G5, G4, I3 ); idx++;
aoqi@0:   a->std( G5, G4, al1.low10() ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->std( G5, G4, I3 ); idx++;
aoqi@0:   a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
aoqi@0:   a->sethi(al2, I3); a->add(I3, al2.low10(), I3);
aoqi@0:   a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
aoqi@0: 
aoqi@0:   nm = nativeMovRegMem_at( cb.insts_begin() );
aoqi@0:   nm->print();
aoqi@0:   nm->set_offset( low10(0) );
aoqi@0:   nm->print();
aoqi@0:   nm->add_offset_in_bytes( low10(0xbb) * wordSize );
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   while (--idx) {
aoqi@0:     nm = nativeMovRegMem_at( nm->next_instruction_address() );
aoqi@0:     nm->print();
aoqi@0:     for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
aoqi@0:       nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
aoqi@0:       assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
aoqi@0:              "check unit test");
aoqi@0:       nm->print();
aoqi@0:     }
aoqi@0:     nm->add_offset_in_bytes( low10(0xbb) * wordSize );
aoqi@0:     nm->print();
aoqi@0:   }
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif // ASSERT
aoqi@0: }
aoqi@0: 
aoqi@0: // End code for unit testing implementation of NativeMovRegMem class
aoqi@0: 
aoqi@0: //--------------------------------------------------------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) {
aoqi@0:   Untested("copy_instruction_to");
aoqi@0:   int instruction_size = next_instruction_address() - instruction_address();
aoqi@0:   for (int i = 0; i < instruction_size; i += wordSize) {
aoqi@0:     *(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMemPatching::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   // make sure code pattern is actually a "ld" or "st" of some sort.
aoqi@0:   int i0 = long_at(0);
aoqi@0:   int op3 = inv_op3(i0);
aoqi@0: 
aoqi@0:   assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
aoqi@0: 
aoqi@0:   if (!(is_op(i0, Assembler::ldst_op) &&
aoqi@0:         inv_immed(i0) &&
aoqi@0:         0 != (op3 < op3_ldst_int_limit
aoqi@0:          ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
aoqi@0:          : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) {
aoqi@0:     int i1 = long_at(ldst_offset);
aoqi@0:     Register rd = inv_rd(i0);
aoqi@0: 
aoqi@0:     op3 = inv_op3(i1);
aoqi@0:     if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
aoqi@0:          0 != (op3 < op3_ldst_int_limit
aoqi@0:               ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
aoqi@0:               : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
aoqi@0:       fatal("not a ld* or st* op");
aoqi@0:     }
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeMovRegMemPatching::print() {
aoqi@0:   if (is_immediate()) {
aoqi@0:     tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
aoqi@0:   } else {
aoqi@0:     tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
aoqi@0:   }
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeMovRegMemPatching class
aoqi@0: void NativeMovRegMemPatching::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 1000, 1000);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeMovRegMemPatching* nm;
aoqi@0:   uint idx = 0;
aoqi@0:   uint idx1;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0xffffffff,
aoqi@0:     0x7fffffff,
aoqi@0:     0x80000000,
aoqi@0:     4096,
aoqi@0:     4097,
aoqi@0:     0x20,
aoqi@0:     0x4000,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   AddressLiteral al(0xffffffff, relocInfo::external_word_type);
aoqi@0:   a->ldsw( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldsw( G5, I3, G4 ); idx++;
aoqi@0:   a->ldsb( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldsb( G5, I3, G4 ); idx++;
aoqi@0:   a->ldsh( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldsh( G5, I3, G4 ); idx++;
aoqi@0:   a->lduw( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->lduw( G5, I3, G4 ); idx++;
aoqi@0:   a->ldub( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldub( G5, I3, G4 ); idx++;
aoqi@0:   a->lduh( G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->lduh( G5, I3, G4 ); idx++;
aoqi@0:   a->ldx(  G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldx(  G5, I3, G4 ); idx++;
aoqi@0:   a->ldd(  G5, al.low10(), G4); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldd(  G5, I3, G4 ); idx++;
aoqi@0:   a->ldf(  FloatRegisterImpl::D, O2, -1, F14 ); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->ldf(  FloatRegisterImpl::S, O0, I3, F15 ); idx++;
aoqi@0: 
aoqi@0:   a->stw( G5, G4, al.low10()); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->stw( G5, G4, I3 ); idx++;
aoqi@0:   a->stb( G5, G4, al.low10()); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->stb( G5, G4, I3 ); idx++;
aoqi@0:   a->sth( G5, G4, al.low10()); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->sth( G5, G4, I3 ); idx++;
aoqi@0:   a->stx( G5, G4, al.low10()); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->stx( G5, G4, I3 ); idx++;
aoqi@0:   a->std( G5, G4, al.low10()); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->std( G5, G4, I3 ); idx++;
aoqi@0:   a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
aoqi@0:   a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
aoqi@0:   a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
aoqi@0: 
aoqi@0:   nm = nativeMovRegMemPatching_at( cb.insts_begin() );
aoqi@0:   nm->print();
aoqi@0:   nm->set_offset( low10(0) );
aoqi@0:   nm->print();
aoqi@0:   nm->add_offset_in_bytes( low10(0xbb) * wordSize );
aoqi@0:   nm->print();
aoqi@0: 
aoqi@0:   while (--idx) {
aoqi@0:     nm = nativeMovRegMemPatching_at( nm->next_instruction_address() );
aoqi@0:     nm->print();
aoqi@0:     for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
aoqi@0:       nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
aoqi@0:       assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
aoqi@0:              "check unit test");
aoqi@0:       nm->print();
aoqi@0:     }
aoqi@0:     nm->add_offset_in_bytes( low10(0xbb) * wordSize );
aoqi@0:     nm->print();
aoqi@0:   }
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif // ASSERT
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeMovRegMemPatching class
aoqi@0: 
aoqi@0: 
aoqi@0: //--------------------------------------------------------------------------------
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeJump::verify() {
aoqi@0:   NativeInstruction::verify();
aoqi@0:   int i0 = long_at(sethi_offset);
aoqi@0:   int i1 = long_at(jmpl_offset);
aoqi@0:   assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
aoqi@0:   // verify the pattern "sethi %hi22(imm), treg ;  jmpl treg, %lo10(imm), lreg"
aoqi@0:   Register rd = inv_rd(i0);
aoqi@0: #ifndef _LP64
aoqi@0:   if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
aoqi@0:         (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) ||
aoqi@0:         (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) &&
aoqi@0:         inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
aoqi@0:         rd == inv_rs1(i1))) {
aoqi@0:     fatal("not a jump_to instruction");
aoqi@0:   }
aoqi@0: #else
aoqi@0:   // In LP64, the jump instruction location varies for non relocatable
aoqi@0:   // jumps, for example is could be sethi, xor, jmp instead of the
aoqi@0:   // 7 instructions for sethi.  So let's check sethi only.
aoqi@0:   if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
aoqi@0:     fatal("not a jump_to instruction");
aoqi@0:   }
aoqi@0: #endif
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeJump::print() {
aoqi@0:   tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination());
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // Code for unit testing implementation of NativeJump class
aoqi@0: void NativeJump::test() {
aoqi@0: #ifdef ASSERT
aoqi@0:   ResourceMark rm;
aoqi@0:   CodeBuffer cb("test", 100, 100);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   NativeJump* nj;
aoqi@0:   uint idx;
aoqi@0:   int offsets[] = {
aoqi@0:     0x0,
aoqi@0:     0xffffffff,
aoqi@0:     0x7fffffff,
aoqi@0:     0x80000000,
aoqi@0:     4096,
aoqi@0:     4097,
aoqi@0:     0x20,
aoqi@0:     0x4000,
aoqi@0:   };
aoqi@0: 
aoqi@0:   VM_Version::allow_all();
aoqi@0: 
aoqi@0:   AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type);
aoqi@0:   a->sethi(al, I3);
aoqi@0:   a->jmpl(I3, al.low10(), G0, RelocationHolder::none);
aoqi@0:   a->delayed()->nop();
aoqi@0:   a->sethi(al, I3);
aoqi@0:   a->jmpl(I3, al.low10(), L3, RelocationHolder::none);
aoqi@0:   a->delayed()->nop();
aoqi@0: 
aoqi@0:   nj = nativeJump_at( cb.insts_begin() );
aoqi@0:   nj->print();
aoqi@0: 
aoqi@0:   nj = nativeJump_at( nj->next_instruction_address() );
aoqi@0:   for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
aoqi@0:     nj->set_jump_destination( nj->instruction_address() + offsets[idx] );
aoqi@0:     assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test");
aoqi@0:     nj->print();
aoqi@0:   }
aoqi@0: 
aoqi@0:   VM_Version::revert();
aoqi@0: #endif // ASSERT
aoqi@0: }
aoqi@0: // End code for unit testing implementation of NativeJump class
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeJump::insert(address code_pos, address entry) {
aoqi@0:   Unimplemented();
aoqi@0: }
aoqi@0: 
aoqi@0: // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
aoqi@0: // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
aoqi@0: // Atomic write can be only with 1 word.
aoqi@0: void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
aoqi@0:   // Here's one way to do it:  Pre-allocate a three-word jump sequence somewhere
aoqi@0:   // in the header of the nmethod, within a short branch's span of the patch point.
aoqi@0:   // Set up the jump sequence using NativeJump::insert, and then use an annulled
aoqi@0:   // unconditional branch at the target site (an atomic 1-word update).
aoqi@0:   // Limitations:  You can only patch nmethods, with any given nmethod patched at
aoqi@0:   // most once, and the patch must be in the nmethod's header.
aoqi@0:   // It's messy, but you can ask the CodeCache for the nmethod containing the
aoqi@0:   // target address.
aoqi@0: 
aoqi@0:   // %%%%% For now, do something MT-stupid:
aoqi@0:   ResourceMark rm;
aoqi@0:   int code_size = 1 * BytesPerInstWord;
aoqi@0:   CodeBuffer cb(verified_entry, code_size + 1);
aoqi@0:   MacroAssembler* a = new MacroAssembler(&cb);
aoqi@0:   a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler
aoqi@0:   ICache::invalidate_range(verified_entry, code_size);
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeIllegalInstruction::insert(address code_pos) {
aoqi@0:   NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
aoqi@0:   nii->set_long_at(0, illegal_instruction());
aoqi@0: }
aoqi@0: 
aoqi@0: static int illegal_instruction_bits = 0;
aoqi@0: 
aoqi@0: int NativeInstruction::illegal_instruction() {
aoqi@0:   if (illegal_instruction_bits == 0) {
aoqi@0:     ResourceMark rm;
aoqi@0:     char buf[40];
aoqi@0:     CodeBuffer cbuf((address)&buf[0], 20);
aoqi@0:     MacroAssembler* a = new MacroAssembler(&cbuf);
aoqi@0:     address ia = a->pc();
aoqi@0:     a->trap(ST_RESERVED_FOR_USER_0 + 1);
aoqi@0:     int bits = *(int*)ia;
aoqi@0:     assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
aoqi@0:     illegal_instruction_bits = bits;
aoqi@0:     assert(illegal_instruction_bits != 0, "oops");
aoqi@0:   }
aoqi@0:   return illegal_instruction_bits;
aoqi@0: }
aoqi@0: 
aoqi@0: static int ic_miss_trap_bits = 0;
aoqi@0: 
aoqi@0: bool NativeInstruction::is_ic_miss_trap() {
aoqi@0:   if (ic_miss_trap_bits == 0) {
aoqi@0:     ResourceMark rm;
aoqi@0:     char buf[40];
aoqi@0:     CodeBuffer cbuf((address)&buf[0], 20);
aoqi@0:     MacroAssembler* a = new MacroAssembler(&cbuf);
aoqi@0:     address ia = a->pc();
aoqi@0:     a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2);
aoqi@0:     int bits = *(int*)ia;
aoqi@0:     assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
aoqi@0:     ic_miss_trap_bits = bits;
aoqi@0:     assert(ic_miss_trap_bits != 0, "oops");
aoqi@0:   }
aoqi@0:   return long_at(0) == ic_miss_trap_bits;
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: bool NativeInstruction::is_illegal() {
aoqi@0:   if (illegal_instruction_bits == 0) {
aoqi@0:     return false;
aoqi@0:   }
aoqi@0:   return long_at(0) == illegal_instruction_bits;
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeGeneralJump::verify() {
aoqi@0:   assert(((NativeInstruction *)this)->is_jump() ||
aoqi@0:          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
aoqi@0:   Assembler::Condition condition = Assembler::always;
aoqi@0:   int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) |
aoqi@0:     Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22);
aoqi@0:   NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos);
aoqi@0:   ni->set_long_at(0, x);
aoqi@0: }
aoqi@0: 
aoqi@0: 
aoqi@0: // MT-safe patching of a jmp instruction (and following word).
aoqi@0: // First patches the second word, and then atomicly replaces
aoqi@0: // the first word with the first new instruction word.
aoqi@0: // Other processors might briefly see the old first word
aoqi@0: // followed by the new second word.  This is OK if the old
aoqi@0: // second word is harmless, and the new second word may be
aoqi@0: // harmlessly executed in the delay slot of the call.
aoqi@0: void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
aoqi@0:    assert(Patching_lock->is_locked() ||
aoqi@0:          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
aoqi@0:    assert (instr_addr != NULL, "illegal address for code patching");
aoqi@0:    NativeGeneralJump* h_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a call
aoqi@0:    assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
aoqi@0:    int i0 = ((int*)code_buffer)[0];
aoqi@0:    int i1 = ((int*)code_buffer)[1];
aoqi@0:    int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
aoqi@0:    assert(inv_op(*contention_addr) == Assembler::arith_op ||
aoqi@0:           *contention_addr == nop_instruction(),
aoqi@0:           "must not interfere with original call");
aoqi@0:    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
aoqi@0:    h_jump->set_long_at(1*BytesPerInstWord, i1);
aoqi@0:    h_jump->set_long_at(0*BytesPerInstWord, i0);
aoqi@0:    // NOTE:  It is possible that another thread T will execute
aoqi@0:    // only the second patched word.
aoqi@0:    // In other words, since the original instruction is this
aoqi@0:    //    jmp patching_stub; nop                    (NativeGeneralJump)
aoqi@0:    // and the new sequence from the buffer is this:
aoqi@0:    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
aoqi@0:    // what T will execute is this:
aoqi@0:    //    jmp patching_stub; add %r, %lo(K), %r
aoqi@0:    // thereby putting garbage into %r before calling the patching stub.
aoqi@0:    // This is OK, because the patching stub ignores the value of %r.
aoqi@0: 
aoqi@0:    // Make sure the first-patched instruction, which may co-exist
aoqi@0:    // briefly with the call, will do something harmless.
aoqi@0:    assert(inv_op(*contention_addr) == Assembler::arith_op ||
aoqi@0:           *contention_addr == nop_instruction(),
aoqi@0:           "must not interfere with original call");
aoqi@0: }