duke@435: /*
duke@435:  * Copyright 1999-2006 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435:  public:
duke@435: 
duke@435:   enum {
duke@435:     nof_reg_args = 6,   // registers o0-o5 are available for parameter passing
duke@435:     first_available_sp_in_frame = frame::memory_parameter_word_sp_offset * BytesPerWord,
duke@435:     frame_pad_in_bytes = 0
duke@435:   };
duke@435: 
duke@435:   static const int pd_c_runtime_reserved_arg_size;
duke@435: 
duke@435:   static LIR_Opr G0_opr;
duke@435:   static LIR_Opr G1_opr;
duke@435:   static LIR_Opr G2_opr;
duke@435:   static LIR_Opr G3_opr;
duke@435:   static LIR_Opr G4_opr;
duke@435:   static LIR_Opr G5_opr;
duke@435:   static LIR_Opr G6_opr;
duke@435:   static LIR_Opr G7_opr;
duke@435:   static LIR_Opr O0_opr;
duke@435:   static LIR_Opr O1_opr;
duke@435:   static LIR_Opr O2_opr;
duke@435:   static LIR_Opr O3_opr;
duke@435:   static LIR_Opr O4_opr;
duke@435:   static LIR_Opr O5_opr;
duke@435:   static LIR_Opr O6_opr;
duke@435:   static LIR_Opr O7_opr;
duke@435:   static LIR_Opr L0_opr;
duke@435:   static LIR_Opr L1_opr;
duke@435:   static LIR_Opr L2_opr;
duke@435:   static LIR_Opr L3_opr;
duke@435:   static LIR_Opr L4_opr;
duke@435:   static LIR_Opr L5_opr;
duke@435:   static LIR_Opr L6_opr;
duke@435:   static LIR_Opr L7_opr;
duke@435:   static LIR_Opr I0_opr;
duke@435:   static LIR_Opr I1_opr;
duke@435:   static LIR_Opr I2_opr;
duke@435:   static LIR_Opr I3_opr;
duke@435:   static LIR_Opr I4_opr;
duke@435:   static LIR_Opr I5_opr;
duke@435:   static LIR_Opr I6_opr;
duke@435:   static LIR_Opr I7_opr;
duke@435: 
duke@435:   static LIR_Opr SP_opr;
duke@435:   static LIR_Opr FP_opr;
duke@435: 
duke@435:   static LIR_Opr G0_oop_opr;
duke@435:   static LIR_Opr G1_oop_opr;
duke@435:   static LIR_Opr G2_oop_opr;
duke@435:   static LIR_Opr G3_oop_opr;
duke@435:   static LIR_Opr G4_oop_opr;
duke@435:   static LIR_Opr G5_oop_opr;
duke@435:   static LIR_Opr G6_oop_opr;
duke@435:   static LIR_Opr G7_oop_opr;
duke@435:   static LIR_Opr O0_oop_opr;
duke@435:   static LIR_Opr O1_oop_opr;
duke@435:   static LIR_Opr O2_oop_opr;
duke@435:   static LIR_Opr O3_oop_opr;
duke@435:   static LIR_Opr O4_oop_opr;
duke@435:   static LIR_Opr O5_oop_opr;
duke@435:   static LIR_Opr O6_oop_opr;
duke@435:   static LIR_Opr O7_oop_opr;
duke@435:   static LIR_Opr L0_oop_opr;
duke@435:   static LIR_Opr L1_oop_opr;
duke@435:   static LIR_Opr L2_oop_opr;
duke@435:   static LIR_Opr L3_oop_opr;
duke@435:   static LIR_Opr L4_oop_opr;
duke@435:   static LIR_Opr L5_oop_opr;
duke@435:   static LIR_Opr L6_oop_opr;
duke@435:   static LIR_Opr L7_oop_opr;
duke@435:   static LIR_Opr I0_oop_opr;
duke@435:   static LIR_Opr I1_oop_opr;
duke@435:   static LIR_Opr I2_oop_opr;
duke@435:   static LIR_Opr I3_oop_opr;
duke@435:   static LIR_Opr I4_oop_opr;
duke@435:   static LIR_Opr I5_oop_opr;
duke@435:   static LIR_Opr I6_oop_opr;
duke@435:   static LIR_Opr I7_oop_opr;
duke@435: 
duke@435:   static LIR_Opr in_long_opr;
duke@435:   static LIR_Opr out_long_opr;
duke@435: 
duke@435:   static LIR_Opr F0_opr;
duke@435:   static LIR_Opr F0_double_opr;
duke@435: 
duke@435:   static LIR_Opr Oexception_opr;
duke@435:   static LIR_Opr Oissuing_pc_opr;
duke@435: 
duke@435:  private:
duke@435:   static FloatRegister  _fpu_regs [nof_fpu_regs];
duke@435: 
duke@435:  public:
duke@435: 
duke@435: #ifdef _LP64
duke@435:   static LIR_Opr as_long_opr(Register r) {
duke@435:     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
duke@435:   }
duke@435:   static LIR_Opr as_pointer_opr(Register r) {
duke@435:     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
duke@435:   }
duke@435: #else
duke@435:   static LIR_Opr as_long_opr(Register r) {
duke@435:     return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r));
duke@435:   }
duke@435:   static LIR_Opr as_pointer_opr(Register r) {
duke@435:     return as_opr(r);
duke@435:   }
duke@435: #endif
duke@435:   static LIR_Opr as_float_opr(FloatRegister r) {
duke@435:     return LIR_OprFact::single_fpu(r->encoding());
duke@435:   }
duke@435:   static LIR_Opr as_double_opr(FloatRegister r) {
duke@435:     return LIR_OprFact::double_fpu(r->successor()->encoding(), r->encoding());
duke@435:   }
duke@435: 
duke@435:   static FloatRegister nr2floatreg (int rnr);
duke@435: 
duke@435:   static VMReg fpu_regname (int n);
duke@435: 
duke@435:   static bool is_caller_save_register (LIR_Opr  reg);
duke@435:   static bool is_caller_save_register (Register r);