twisti@1020: /* kevinw@8729: * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. twisti@1020: * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. twisti@1020: * twisti@1020: * This code is free software; you can redistribute it and/or modify it twisti@1020: * under the terms of the GNU General Public License version 2 only, as twisti@1020: * published by the Free Software Foundation. twisti@1020: * twisti@1020: * This code is distributed in the hope that it will be useful, but WITHOUT twisti@1020: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or twisti@1020: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License twisti@1020: * version 2 for more details (a copy is included in the LICENSE file that twisti@1020: * accompanied this code). twisti@1020: * twisti@1020: * You should have received a copy of the GNU General Public License version twisti@1020: * 2 along with this work; if not, write to the Free Software Foundation, twisti@1020: * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. twisti@1020: * trims@1907: * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA trims@1907: * or visit www.oracle.com if you need additional information or have any trims@1907: * questions. twisti@1020: * twisti@1020: */ twisti@1020: stefank@2314: #ifndef CPU_X86_VM_VM_VERSION_X86_HPP stefank@2314: #define CPU_X86_VM_VM_VERSION_X86_HPP stefank@2314: stefank@2314: #include "runtime/globals_extension.hpp" stefank@2314: #include "runtime/vm_version.hpp" stefank@2314: twisti@1020: class VM_Version : public Abstract_VM_Version { twisti@1020: public: twisti@1020: // cpuid result register layouts. These are all unions of a uint32_t twisti@1020: // (in case anyone wants access to the register as a whole) and a bitfield. twisti@1020: twisti@1020: union StdCpuid1Eax { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t stepping : 4, twisti@1020: model : 4, twisti@1020: family : 4, twisti@1020: proc_type : 2, twisti@1020: : 2, twisti@1020: ext_model : 4, twisti@1020: ext_family : 8, twisti@1020: : 4; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union StdCpuid1Ebx { // example, unused twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t brand_id : 8, twisti@1020: clflush_size : 8, twisti@1020: threads_per_cpu : 8, twisti@1020: apic_id : 8; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union StdCpuid1Ecx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t sse3 : 1, drchase@5353: clmul : 1, drchase@5353: : 1, twisti@1020: monitor : 1, twisti@1020: : 1, twisti@1020: vmx : 1, twisti@1020: : 1, twisti@1020: est : 1, twisti@1020: : 1, twisti@1020: ssse3 : 1, twisti@1020: cid : 1, twisti@1020: : 2, twisti@1020: cmpxchg16: 1, twisti@1020: : 4, twisti@1020: dca : 1, twisti@1020: sse4_1 : 1, twisti@1020: sse4_2 : 1, twisti@1078: : 2, twisti@1078: popcnt : 1, kvn@4205: : 1, kvn@4205: aes : 1, kvn@4205: : 1, kvn@3388: osxsave : 1, kvn@3388: avx : 1, kvn@3388: : 3; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union StdCpuid1Edx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t : 4, twisti@1020: tsc : 1, twisti@1020: : 3, twisti@1020: cmpxchg8 : 1, twisti@1020: : 6, twisti@1020: cmov : 1, kvn@2984: : 3, kvn@2984: clflush : 1, kvn@2984: : 3, twisti@1020: mmx : 1, twisti@1020: fxsr : 1, twisti@1020: sse : 1, twisti@1020: sse2 : 1, twisti@1020: : 1, twisti@1020: ht : 1, twisti@1020: : 3; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union DcpCpuid4Eax { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t cache_type : 5, twisti@1020: : 21, twisti@1020: cores_per_cpu : 6; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union DcpCpuid4Ebx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t L1_line_size : 12, twisti@1020: partitions : 10, twisti@1020: associativity : 10; twisti@1020: } bits; twisti@1020: }; twisti@1020: kvn@1977: union TplCpuidBEbx { kvn@1977: uint32_t value; kvn@1977: struct { kvn@1977: uint32_t logical_cpus : 16, kvn@1977: : 16; kvn@1977: } bits; kvn@1977: }; kvn@1977: twisti@1020: union ExtCpuid1Ecx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t LahfSahf : 1, twisti@1020: CmpLegacy : 1, iveresov@6378: : 3, iveresov@6378: lzcnt_intel : 1, twisti@1210: lzcnt : 1, twisti@1020: sse4a : 1, twisti@1020: misalignsse : 1, twisti@1020: prefetchw : 1, twisti@1020: : 22; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union ExtCpuid1Edx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t : 22, twisti@1020: mmx_amd : 1, twisti@1020: mmx : 1, twisti@1020: fxsr : 1, twisti@1020: : 4, twisti@1020: long_mode : 1, twisti@1020: tdnow2 : 1, twisti@1020: tdnow : 1; twisti@1020: } bits; twisti@1020: }; twisti@1020: twisti@1020: union ExtCpuid5Ex { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t L1_line_size : 8, twisti@1020: L1_tag_lines : 8, twisti@1020: L1_assoc : 8, twisti@1020: L1_size : 8; twisti@1020: } bits; twisti@1020: }; twisti@1020: kvn@3400: union ExtCpuid7Edx { kvn@3400: uint32_t value; kvn@3400: struct { kvn@3400: uint32_t : 8, kvn@3400: tsc_invariance : 1, kvn@3400: : 23; kvn@3400: } bits; kvn@3400: }; kvn@3400: twisti@1020: union ExtCpuid8Ecx { twisti@1020: uint32_t value; twisti@1020: struct { twisti@1020: uint32_t cores_per_cpu : 8, twisti@1020: : 24; twisti@1020: } bits; twisti@1020: }; twisti@1020: kvn@3388: union SefCpuid7Eax { kvn@3388: uint32_t value; kvn@3388: }; kvn@3388: kvn@3388: union SefCpuid7Ebx { kvn@3388: uint32_t value; kvn@3388: struct { kvn@3388: uint32_t fsgsbase : 1, kvn@3388: : 2, kvn@3388: bmi1 : 1, kvn@3388: : 1, kvn@3388: avx2 : 1, kvn@3388: : 2, kvn@3388: bmi2 : 1, kvn@4410: erms : 1, kvn@6429: : 1, kvn@6429: rtm : 1, kvn@7152: : 7, kvn@7152: adx : 1, kvn@7152: : 12; kvn@3388: } bits; kvn@3388: }; kvn@3388: kvn@3388: union XemXcr0Eax { kvn@3388: uint32_t value; kvn@3388: struct { kvn@3388: uint32_t x87 : 1, kvn@3388: sse : 1, kvn@3388: ymm : 1, kvn@3388: : 29; kvn@3388: } bits; kvn@3388: }; kvn@3388: twisti@1020: protected: phh@3378: static int _cpu; phh@3378: static int _model; phh@3378: static int _stepping; phh@3378: static int _cpuFeatures; // features returned by the "cpuid" instruction phh@3378: // 0 if this instruction is not available phh@3378: static const char* _features_str; twisti@1020: kvn@6388: static address _cpuinfo_segv_addr; // address of instruction which causes SEGV kvn@6388: static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV kvn@6388: phh@3378: enum { phh@3378: CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) phh@3378: CPU_CMOV = (1 << 1), phh@3378: CPU_FXSR = (1 << 2), phh@3378: CPU_HT = (1 << 3), phh@3378: CPU_MMX = (1 << 4), phh@3378: CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions phh@3378: // may not necessarily support other 3dnow instructions phh@3378: CPU_SSE = (1 << 6), phh@3378: CPU_SSE2 = (1 << 7), phh@3378: CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) phh@3378: CPU_SSSE3 = (1 << 9), phh@3378: CPU_SSE4A = (1 << 10), phh@3378: CPU_SSE4_1 = (1 << 11), phh@3378: CPU_SSE4_2 = (1 << 12), phh@3378: CPU_POPCNT = (1 << 13), phh@3378: CPU_LZCNT = (1 << 14), phh@3378: CPU_TSC = (1 << 15), kvn@3400: CPU_TSCINV = (1 << 16), kvn@3400: CPU_AVX = (1 << 17), kvn@4205: CPU_AVX2 = (1 << 18), kvn@4410: CPU_AES = (1 << 19), drchase@5353: CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions iveresov@6378: CPU_CLMUL = (1 << 21), // carryless multiply for CRC iveresov@6378: CPU_BMI1 = (1 << 22), kvn@6429: CPU_BMI2 = (1 << 23), kvn@7152: CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions kvn@7152: CPU_ADX = (1 << 25) phh@3378: } cpuFeatureFlags; phh@3378: phh@3378: enum { phh@3378: // AMD phh@3560: CPU_FAMILY_AMD_11H = 0x11, phh@3378: // Intel phh@3378: CPU_FAMILY_INTEL_CORE = 6, phh@3560: CPU_MODEL_NEHALEM = 0x1e, phh@3560: CPU_MODEL_NEHALEM_EP = 0x1a, phh@3560: CPU_MODEL_NEHALEM_EX = 0x2e, phh@3560: CPU_MODEL_WESTMERE = 0x25, phh@3560: CPU_MODEL_WESTMERE_EP = 0x2c, phh@3560: CPU_MODEL_WESTMERE_EX = 0x2f, phh@3560: CPU_MODEL_SANDYBRIDGE = 0x2a, phh@3560: CPU_MODEL_SANDYBRIDGE_EP = 0x2d, kvn@7088: CPU_MODEL_IVYBRIDGE_EP = 0x3a, kvn@7088: CPU_MODEL_HASWELL_E3 = 0x3c, kvn@7088: CPU_MODEL_HASWELL_E7 = 0x3f, kvn@7088: CPU_MODEL_BROADWELL = 0x3d phh@3378: } cpuExtendedFamily; twisti@1020: twisti@1020: // cpuid information block. All info derived from executing cpuid with twisti@1020: // various function numbers is stored here. Intel and AMD info is twisti@1020: // merged in this block: accessor methods disentangle it. twisti@1020: // twisti@1020: // The info block is laid out in subblocks of 4 dwords corresponding to twisti@1020: // eax, ebx, ecx and edx, whether or not they contain anything useful. twisti@1020: struct CpuidInfo { twisti@1020: // cpuid function 0 twisti@1020: uint32_t std_max_function; twisti@1020: uint32_t std_vendor_name_0; twisti@1020: uint32_t std_vendor_name_1; twisti@1020: uint32_t std_vendor_name_2; twisti@1020: twisti@1020: // cpuid function 1 twisti@1020: StdCpuid1Eax std_cpuid1_eax; twisti@1020: StdCpuid1Ebx std_cpuid1_ebx; twisti@1020: StdCpuid1Ecx std_cpuid1_ecx; twisti@1020: StdCpuid1Edx std_cpuid1_edx; twisti@1020: twisti@1020: // cpuid function 4 (deterministic cache parameters) twisti@1020: DcpCpuid4Eax dcp_cpuid4_eax; twisti@1020: DcpCpuid4Ebx dcp_cpuid4_ebx; twisti@1020: uint32_t dcp_cpuid4_ecx; // unused currently twisti@1020: uint32_t dcp_cpuid4_edx; // unused currently twisti@1020: kvn@3388: // cpuid function 7 (structured extended features) kvn@3388: SefCpuid7Eax sef_cpuid7_eax; kvn@3388: SefCpuid7Ebx sef_cpuid7_ebx; kvn@3388: uint32_t sef_cpuid7_ecx; // unused currently kvn@3388: uint32_t sef_cpuid7_edx; // unused currently kvn@3388: kvn@1977: // cpuid function 0xB (processor topology) kvn@1977: // ecx = 0 kvn@1977: uint32_t tpl_cpuidB0_eax; kvn@1977: TplCpuidBEbx tpl_cpuidB0_ebx; kvn@1977: uint32_t tpl_cpuidB0_ecx; // unused currently kvn@1977: uint32_t tpl_cpuidB0_edx; // unused currently kvn@1977: kvn@1977: // ecx = 1 kvn@1977: uint32_t tpl_cpuidB1_eax; kvn@1977: TplCpuidBEbx tpl_cpuidB1_ebx; kvn@1977: uint32_t tpl_cpuidB1_ecx; // unused currently kvn@1977: uint32_t tpl_cpuidB1_edx; // unused currently kvn@1977: kvn@1977: // ecx = 2 kvn@1977: uint32_t tpl_cpuidB2_eax; kvn@1977: TplCpuidBEbx tpl_cpuidB2_ebx; kvn@1977: uint32_t tpl_cpuidB2_ecx; // unused currently kvn@1977: uint32_t tpl_cpuidB2_edx; // unused currently kvn@1977: twisti@1020: // cpuid function 0x80000000 // example, unused twisti@1020: uint32_t ext_max_function; twisti@1020: uint32_t ext_vendor_name_0; twisti@1020: uint32_t ext_vendor_name_1; twisti@1020: uint32_t ext_vendor_name_2; twisti@1020: twisti@1020: // cpuid function 0x80000001 twisti@1020: uint32_t ext_cpuid1_eax; // reserved twisti@1020: uint32_t ext_cpuid1_ebx; // reserved twisti@1020: ExtCpuid1Ecx ext_cpuid1_ecx; twisti@1020: ExtCpuid1Edx ext_cpuid1_edx; twisti@1020: twisti@1020: // cpuid functions 0x80000002 thru 0x80000004: example, unused twisti@1020: uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; twisti@1020: uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; twisti@1020: uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; twisti@1020: phh@3560: // cpuid function 0x80000005 // AMD L1, Intel reserved twisti@1020: uint32_t ext_cpuid5_eax; // unused currently twisti@1020: uint32_t ext_cpuid5_ebx; // reserved twisti@1020: ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) twisti@1020: ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) twisti@1020: phh@3378: // cpuid function 0x80000007 phh@3378: uint32_t ext_cpuid7_eax; // reserved phh@3378: uint32_t ext_cpuid7_ebx; // reserved phh@3378: uint32_t ext_cpuid7_ecx; // reserved phh@3378: ExtCpuid7Edx ext_cpuid7_edx; // tscinv phh@3378: twisti@1020: // cpuid function 0x80000008 twisti@1020: uint32_t ext_cpuid8_eax; // unused currently twisti@1020: uint32_t ext_cpuid8_ebx; // reserved twisti@1020: ExtCpuid8Ecx ext_cpuid8_ecx; twisti@1020: uint32_t ext_cpuid8_edx; // reserved kvn@3388: kvn@3388: // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) kvn@3388: XemXcr0Eax xem_xcr0_eax; kvn@3388: uint32_t xem_xcr0_edx; // reserved kvn@6388: kvn@6388: // Space to save ymm registers after signal handle kvn@6388: int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 twisti@1020: }; twisti@1020: twisti@1020: // The actual cpuid info block twisti@1020: static CpuidInfo _cpuid_info; twisti@1020: twisti@1020: // Extractors and predicates twisti@1020: static uint32_t extended_cpu_family() { twisti@1020: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; twisti@1020: result += _cpuid_info.std_cpuid1_eax.bits.ext_family; twisti@1020: return result; twisti@1020: } phh@3378: twisti@1020: static uint32_t extended_cpu_model() { twisti@1020: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; twisti@1020: result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; twisti@1020: return result; twisti@1020: } phh@3378: twisti@1020: static uint32_t cpu_stepping() { twisti@1020: uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; twisti@1020: return result; twisti@1020: } phh@3378: twisti@1020: static uint logical_processor_count() { twisti@1020: uint result = threads_per_core(); twisti@1020: return result; twisti@1020: } phh@3378: twisti@1020: static uint32_t feature_flags() { twisti@1020: uint32_t result = 0; twisti@1020: if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) twisti@1020: result |= CPU_CX8; twisti@1020: if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) twisti@1020: result |= CPU_CMOV; twisti@2144: if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && twisti@2144: _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) twisti@1020: result |= CPU_FXSR; twisti@1020: // HT flag is set for multi-core processors also. twisti@1020: if (threads_per_core() > 1) twisti@1020: result |= CPU_HT; twisti@2144: if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && twisti@2144: _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) twisti@1020: result |= CPU_MMX; twisti@1020: if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) twisti@1020: result |= CPU_SSE; twisti@1020: if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) twisti@1020: result |= CPU_SSE2; twisti@1020: if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) twisti@1020: result |= CPU_SSE3; twisti@1020: if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) twisti@1020: result |= CPU_SSSE3; twisti@1020: if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) twisti@1020: result |= CPU_SSE4_1; twisti@1020: if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) twisti@1020: result |= CPU_SSE4_2; twisti@1078: if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) twisti@1078: result |= CPU_POPCNT; kvn@3388: if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && kvn@3388: _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && kvn@3388: _cpuid_info.xem_xcr0_eax.bits.sse != 0 && kvn@3388: _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { kvn@3388: result |= CPU_AVX; kvn@3388: if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) kvn@3388: result |= CPU_AVX2; kvn@3388: } iveresov@6378: if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) iveresov@6378: result |= CPU_BMI1; phh@3378: if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) phh@3378: result |= CPU_TSC; phh@3378: if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) phh@3378: result |= CPU_TSCINV; kvn@4205: if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) kvn@4205: result |= CPU_AES; kvn@4410: if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) kvn@4410: result |= CPU_ERMS; drchase@5353: if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) drchase@5353: result |= CPU_CLMUL; kvn@6429: if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) kvn@6429: result |= CPU_RTM; twisti@1210: twisti@1210: // AMD features. twisti@1210: if (is_amd()) { kvn@2761: if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || kvn@2761: (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) kvn@2761: result |= CPU_3DNOW_PREFETCH; twisti@1210: if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) twisti@1210: result |= CPU_LZCNT; twisti@1210: if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) twisti@1210: result |= CPU_SSE4A; twisti@1210: } iveresov@6378: // Intel features. iveresov@6378: if(is_intel()) { kvn@7152: if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) kvn@7152: result |= CPU_ADX; iveresov@6378: if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) iveresov@6378: result |= CPU_BMI2; iveresov@6378: if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) iveresov@6378: result |= CPU_LZCNT; kvn@7152: // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw kvn@7152: if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { kvn@7152: result |= CPU_3DNOW_PREFETCH; kvn@7152: } iveresov@6378: } twisti@1210: twisti@1020: return result; twisti@1020: } twisti@1020: kvn@6388: static bool os_supports_avx_vectors() { kvn@6388: if (!supports_avx()) { kvn@6388: return false; kvn@6388: } kvn@6388: // Verify that OS save/restore all bits of AVX registers kvn@6388: // during signal processing. kvn@6388: int nreg = 2 LP64_ONLY(+2); kvn@6388: for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register kvn@6388: if (_cpuid_info.ymm_save[i] != ymm_test_value()) { kvn@6388: return false; kvn@6388: } kvn@6388: } kvn@6388: return true; kvn@6388: } kvn@6388: twisti@1020: static void get_processor_features(); twisti@1020: twisti@1020: public: twisti@1020: // Offsets for cpuid asm stub twisti@1020: static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } twisti@1020: static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } twisti@1020: static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } kvn@3388: static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } twisti@1020: static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } twisti@1020: static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } phh@3378: static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } twisti@1020: static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } kvn@1977: static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } kvn@1977: static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } kvn@1977: static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } kvn@3388: static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } kvn@6388: static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } kvn@6388: kvn@6388: // The value used to check ymm register after signal handle kvn@6388: static int ymm_test_value() { return 0xCAFEBABE; } kvn@6388: kvn@6537: static void get_cpu_info_wrapper(); kvn@6388: static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } kvn@6388: static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } kvn@6388: static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } kvn@6388: static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } kvn@6388: kvn@6388: static void clean_cpuFeatures() { _cpuFeatures = 0; } kvn@6388: static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } kvn@6388: twisti@1020: twisti@1020: // Initialization twisti@1020: static void initialize(); twisti@1020: kvn@6429: // Override Abstract_VM_Version implementation kvn@6429: static bool use_biased_locking(); kvn@6429: twisti@1020: // Asserts twisti@1020: static void assert_is_initialized() { twisti@1020: assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); twisti@1020: } twisti@1020: twisti@1020: // twisti@1020: // Processor family: twisti@1020: // 3 - 386 twisti@1020: // 4 - 486 twisti@1020: // 5 - Pentium twisti@1020: // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, twisti@1020: // Pentium M, Core Solo, Core Duo, Core2 Duo twisti@1020: // family 6 model: 9, 13, 14, 15 twisti@1020: // 0x0f - Pentium 4, Opteron twisti@1020: // twisti@1020: // Note: The cpu family should be used to select between twisti@1020: // instruction sequences which are valid on all Intel twisti@1020: // processors. Use the feature test functions below to twisti@1020: // determine whether a particular instruction is supported. twisti@1020: // twisti@1020: static int cpu_family() { return _cpu;} twisti@1020: static bool is_P6() { return cpu_family() >= 6; } twisti@1020: static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' twisti@1020: static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' twisti@1020: kvn@2002: static bool supports_processor_topology() { kvn@2002: return (_cpuid_info.std_max_function >= 0xB) && kvn@2002: // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. kvn@2002: // Some cpus have max cpuid >= 0xB but do not support processor topology. kvn@4410: (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); kvn@2002: } kvn@2002: twisti@1020: static uint cores_per_cpu() { twisti@1020: uint result = 1; twisti@1020: if (is_intel()) { vkempik@7541: bool supports_topology = supports_processor_topology(); vkempik@7541: if (supports_topology) { kvn@1977: result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / kvn@1977: _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; vkempik@7541: } vkempik@7541: if (!supports_topology || result == 0) { kvn@1977: result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); kvn@1977: } twisti@1020: } else if (is_amd()) { twisti@1020: result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); twisti@1020: } twisti@1020: return result; twisti@1020: } twisti@1020: twisti@1020: static uint threads_per_core() { twisti@1020: uint result = 1; kvn@2002: if (is_intel() && supports_processor_topology()) { kvn@1977: result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; kvn@1977: } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { twisti@1020: result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / twisti@1020: cores_per_cpu(); twisti@1020: } poonam@8175: return (result == 0 ? 1 : result); twisti@1020: } twisti@1020: kevinw@8729: static intx L1_line_size() { twisti@1020: intx result = 0; twisti@1020: if (is_intel()) { twisti@1020: result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); twisti@1020: } else if (is_amd()) { twisti@1020: result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; twisti@1020: } twisti@1020: if (result < 32) // not defined ? twisti@1020: result = 32; // 32 bytes by default on x86 and other x64 twisti@1020: return result; twisti@1020: } twisti@1020: kevinw@8729: static intx prefetch_data_size() { kevinw@8729: return L1_line_size(); kevinw@8729: } kevinw@8729: twisti@1020: // twisti@1020: // Feature identification twisti@1020: // twisti@1020: static bool supports_cpuid() { return _cpuFeatures != 0; } twisti@1020: static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } twisti@1020: static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } twisti@1020: static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } twisti@1020: static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } twisti@1020: static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } twisti@1020: static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } twisti@1020: static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } twisti@1020: static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } twisti@1020: static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } twisti@1020: static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } twisti@1020: static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } twisti@1078: static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } kvn@3388: static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } kvn@3388: static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } phh@3378: static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } kvn@4205: static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } kvn@4410: static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } drchase@5353: static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } kvn@6429: static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } iveresov@6378: static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } iveresov@6378: static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } kvn@7152: static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; } phh@3378: // Intel features phh@3378: static bool is_intel_family_core() { return is_intel() && phh@3378: extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } phh@3378: phh@3378: static bool is_intel_tsc_synched_at_init() { phh@3378: if (is_intel_family_core()) { phh@3378: uint32_t ext_model = extended_cpu_model(); phh@3560: if (ext_model == CPU_MODEL_NEHALEM_EP || phh@3560: ext_model == CPU_MODEL_WESTMERE_EP || phh@3560: ext_model == CPU_MODEL_SANDYBRIDGE_EP || phh@3560: ext_model == CPU_MODEL_IVYBRIDGE_EP) { phh@3560: // <= 2-socket invariant tsc support. EX versions are usually used phh@3560: // in > 2-socket systems and likely don't synchronize tscs at phh@3560: // initialization. phh@3560: // Code that uses tsc values must be prepared for them to arbitrarily phh@3560: // jump forward or backward. phh@3378: return true; phh@3378: } phh@3378: } phh@3378: return false; phh@3378: } phh@3378: twisti@1020: // AMD features kvn@2761: static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } twisti@1020: static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } twisti@1210: static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } twisti@1020: static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } twisti@1020: phh@3378: static bool is_amd_Barcelona() { return is_amd() && phh@3378: extended_cpu_family() == CPU_FAMILY_AMD_11H; } phh@3378: phh@3378: // Intel and AMD newer cores support fast timestamps well phh@3378: static bool supports_tscinv_bit() { phh@3378: return (_cpuFeatures & CPU_TSCINV) != 0; phh@3378: } phh@3378: static bool supports_tscinv() { phh@3378: return supports_tscinv_bit() && phh@3378: ( (is_amd() && !is_amd_Barcelona()) || phh@3378: is_intel_tsc_synched_at_init() ); phh@3378: } phh@3378: kvn@2269: // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). kvn@2269: static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && kvn@2269: supports_sse3() && _model != 0x1C; } kvn@2269: twisti@1020: static bool supports_compare_and_exchange() { return true; } twisti@1020: twisti@1020: static const char* cpu_features() { return _features_str; } twisti@1020: twisti@1020: static intx allocate_prefetch_distance() { twisti@1020: // This method should be called before allocate_prefetch_style(). twisti@1020: // twisti@1020: // Hardware prefetching (distance/size in bytes): twisti@1020: // Pentium 3 - 64 / 32 twisti@1020: // Pentium 4 - 256 / 128 twisti@1020: // Athlon - 64 / 32 ???? twisti@1020: // Opteron - 128 / 64 only when 2 sequential cache lines accessed twisti@1020: // Core - 128 / 64 twisti@1020: // twisti@1020: // Software prefetching (distance in bytes / instruction with best score): twisti@1020: // Pentium 3 - 128 / prefetchnta twisti@1020: // Pentium 4 - 512 / prefetchnta twisti@1020: // Athlon - 128 / prefetchnta twisti@1020: // Opteron - 256 / prefetchnta twisti@1020: // Core - 256 / prefetchnta twisti@1020: // It will be used only when AllocatePrefetchStyle > 0 twisti@1020: twisti@1020: intx count = AllocatePrefetchDistance; twisti@1020: if (count < 0) { // default ? twisti@1020: if (is_amd()) { // AMD twisti@1020: if (supports_sse2()) twisti@1020: count = 256; // Opteron twisti@1020: else twisti@1020: count = 128; // Athlon twisti@1020: } else { // Intel twisti@1020: if (supports_sse2()) twisti@1020: if (cpu_family() == 6) { twisti@1020: count = 256; // Pentium M, Core, Core2 twisti@1020: } else { twisti@1020: count = 512; // Pentium 4 twisti@1020: } twisti@1020: else twisti@1020: count = 128; // Pentium 3 (and all other old CPUs) twisti@1020: } twisti@1020: } twisti@1020: return count; twisti@1020: } twisti@1020: static intx allocate_prefetch_style() { twisti@1020: assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); twisti@1020: // Return 0 if AllocatePrefetchDistance was not defined. twisti@1020: return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; twisti@1020: } twisti@1020: twisti@1020: // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from twisti@1020: // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. twisti@1020: // Tested intervals from 128 to 2048 in increments of 64 == one cache line. twisti@1020: // 256 bytes (4 dcache lines) was the nearest runner-up to 576. twisti@1020: twisti@1020: // gc copy/scan is disabled if prefetchw isn't supported, because twisti@1020: // Prefetch::write emits an inlined prefetchw on Linux. twisti@1020: // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. twisti@1020: // The used prefetcht0 instruction works for both amd64 and em64t. twisti@1020: static intx prefetch_copy_interval_in_bytes() { twisti@1020: intx interval = PrefetchCopyIntervalInBytes; twisti@1020: return interval >= 0 ? interval : 576; twisti@1020: } twisti@1020: static intx prefetch_scan_interval_in_bytes() { twisti@1020: intx interval = PrefetchScanIntervalInBytes; twisti@1020: return interval >= 0 ? interval : 576; twisti@1020: } twisti@1020: static intx prefetch_fields_ahead() { twisti@1020: intx count = PrefetchFieldsAhead; twisti@1020: return count >= 0 ? count : 1; twisti@1020: } twisti@1020: }; stefank@2314: stefank@2314: #endif // CPU_X86_VM_VM_VERSION_X86_HPP