duke@435: /*
kvn@6653:  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
trims@1907:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907:  * or visit www.oracle.com if you need additional information or have any
trims@1907:  * questions.
duke@435:  *
duke@435:  */
duke@435: 
stefank@2314: #include "precompiled.hpp"
twisti@4323: #include "asm/macroAssembler.inline.hpp"
stefank@2314: #include "memory/resourceArea.hpp"
stefank@2314: #include "runtime/java.hpp"
stefank@2314: #include "runtime/stubCodeGenerator.hpp"
stefank@2314: #include "vm_version_sparc.hpp"
stefank@2314: #ifdef TARGET_OS_FAMILY_linux
stefank@2314: # include "os_linux.inline.hpp"
stefank@2314: #endif
stefank@2314: #ifdef TARGET_OS_FAMILY_solaris
stefank@2314: # include "os_solaris.inline.hpp"
stefank@2314: #endif
duke@435: 
duke@435: int VM_Version::_features = VM_Version::unknown_m;
duke@435: const char* VM_Version::_features_str = "";
iveresov@7767: unsigned int VM_Version::_L2_data_cache_line_size = 0;
duke@435: 
duke@435: void VM_Version::initialize() {
poonam@8329: 
poonam@8329:   assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete.");
poonam@8329:   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
poonam@8329: 
duke@435:   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
duke@435:   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
duke@435:   PrefetchFieldsAhead         = prefetch_fields_ahead();
duke@435: 
kvn@3052:   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
kvn@3052:   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
kvn@3052:   if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
kvn@3052: 
duke@435:   // Allocation prefetch settings
kvn@3052:   intx cache_line_size = prefetch_data_size();
duke@435:   if( cache_line_size > AllocatePrefetchStepSize )
duke@435:     AllocatePrefetchStepSize = cache_line_size;
kvn@3052: 
kvn@3052:   assert(AllocatePrefetchLines > 0, "invalid value");
kvn@3052:   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
kvn@3052:     AllocatePrefetchLines = 3;
kvn@3052:   assert(AllocateInstancePrefetchLines > 0, "invalid value");
kvn@3052:   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
kvn@3052:     AllocateInstancePrefetchLines = 1;
duke@435: 
duke@435:   AllocatePrefetchDistance = allocate_prefetch_distance();
duke@435:   AllocatePrefetchStyle    = allocate_prefetch_style();
duke@435: 
kvn@3052:   assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
kvn@3052:          (AllocatePrefetchDistance > 0), "invalid value");
kvn@3052:   if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
kvn@3052:       (AllocatePrefetchDistance <= 0)) {
kvn@3052:     AllocatePrefetchDistance = AllocatePrefetchStepSize;
kvn@3052:   }
duke@435: 
vkempik@8645:   if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
kvn@3037:     warning("BIS instructions are not available on this CPU");
kvn@3037:     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
kvn@3037:   }
kvn@3037: 
morris@5283:   assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
morris@5283:   if (ArraycopySrcPrefetchDistance >= 4096)
morris@5283:     ArraycopySrcPrefetchDistance = 4064;
morris@5283:   assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
morris@5283:   if (ArraycopyDstPrefetchDistance >= 4096)
morris@5283:     ArraycopyDstPrefetchDistance = 4064;
kvn@3103: 
duke@435:   UseSSE = 0; // Only on x86 and x64
duke@435: 
kvn@3052:   _supports_cx8 = has_v9();
roland@4106:   _supports_atomic_getset4 = true; // swap instruction
duke@435: 
simonis@6154:   // There are Fujitsu Sparc64 CPUs which support blk_init as well so
simonis@6154:   // we have to take this check out of the 'is_niagara()' block below.
simonis@6154:   if (has_blk_init()) {
simonis@6154:     // When using CMS or G1, we cannot use memset() in BOT updates
simonis@6154:     // because the sun4v/CMT version in libc_psr uses BIS which
simonis@6154:     // exposes "phantom zeros" to concurrent readers. See 6948537.
simonis@6154:     if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
simonis@6154:       FLAG_SET_DEFAULT(UseMemSetInBOT, false);
simonis@6154:     }
simonis@6154:     // Issue a stern warning if the user has explicitly set
simonis@6154:     // UseMemSetInBOT (it is known to cause issues), but allow
simonis@6154:     // use for experimentation and debugging.
simonis@6154:     if (UseConcMarkSweepGC || UseG1GC) {
simonis@6154:       if (UseMemSetInBOT) {
simonis@6154:         assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
simonis@6154:         warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
simonis@6154:                 " on sun4v; please understand that you are using at your own risk!");
simonis@6154:       }
simonis@6154:     }
simonis@6154:   }
simonis@6154: 
kvn@2403:   if (is_niagara()) {
duke@435:     // Indirect branch is the same cost as direct
duke@435:     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
kvn@1110:       FLAG_SET_DEFAULT(UseInlineCaches, false);
duke@435:     }
kvn@2403:     // Align loops on a single instruction boundary.
kvn@2403:     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
kvn@2403:       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
kvn@2403:     }
coleenp@548: #ifdef _LP64
kvn@1077:     // 32-bit oops don't make sense for the 64-bit VM on sparc
kvn@1077:     // since the 32-bit VM has the same registers and smaller objects.
kvn@1077:     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
roland@4159:     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
coleenp@548: #endif // _LP64
duke@435: #ifdef COMPILER2
duke@435:     // Indirect branch is the same cost as direct
duke@435:     if (FLAG_IS_DEFAULT(UseJumpTables)) {
kvn@1110:       FLAG_SET_DEFAULT(UseJumpTables, true);
duke@435:     }
duke@435:     // Single-issue, so entry and loop tops are
duke@435:     // aligned on a single instruction boundary
duke@435:     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
kvn@1110:       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
duke@435:     }
kvn@2403:     if (is_niagara_plus()) {
vkempik@8645:       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
kvn@3052:           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
kvn@3052:         // Use BIS instruction for TLAB allocation prefetch.
kvn@3052:         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
kvn@3052:         if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
kvn@3052:           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
kvn@3052:         }
kvn@1802:         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
kvn@3052:           // Use smaller prefetch distance with BIS
kvn@1802:           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
kvn@1802:         }
kvn@1802:       }
kvn@3052:       if (is_T4()) {
kvn@3052:         // Double number of prefetched cache lines on T4
kvn@3052:         // since L2 cache line size is smaller (32 bytes).
kvn@3052:         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
kvn@3052:           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
kvn@3052:         }
kvn@3052:         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
kvn@3052:           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
kvn@3052:         }
kvn@3052:       }
kvn@1802:       if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
kvn@1802:         // Use different prefetch distance without BIS
kvn@1802:         FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
kvn@1802:       }
kvn@3052:       if (AllocatePrefetchInstr == 1) {
kvn@3052:         // Need a space at the end of TLAB for BIS since it
kvn@3052:         // will fault when accessing memory outside of heap.
kvn@3052: 
kvn@3052:         // +1 for rounding up to next cache line, +1 to be safe
kvn@3052:         int lines = AllocatePrefetchLines + 2;
kvn@3052:         int step_size = AllocatePrefetchStepSize;
kvn@3052:         int distance = AllocatePrefetchDistance;
kvn@3052:         _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
kvn@3052:       }
duke@435:     }
duke@435: #endif
duke@435:   }
duke@435: 
twisti@1078:   // Use hardware population count instruction if available.
twisti@1078:   if (has_hardware_popc()) {
twisti@1078:     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
kvn@1110:       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
twisti@1078:     }
kvn@3037:   } else if (UsePopCountInstruction) {
kvn@3037:     warning("POPC instruction is not available on this CPU");
kvn@3037:     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
kvn@3037:   }
kvn@3037: 
kvn@3037:   // T4 and newer Sparc cpus have new compare and branch instruction.
kvn@3037:   if (has_cbcond()) {
kvn@3037:     if (FLAG_IS_DEFAULT(UseCBCond)) {
kvn@3037:       FLAG_SET_DEFAULT(UseCBCond, true);
kvn@3037:     }
kvn@3037:   } else if (UseCBCond) {
kvn@3037:     warning("CBCOND instruction is not available on this CPU");
kvn@3037:     FLAG_SET_DEFAULT(UseCBCond, false);
twisti@1078:   }
twisti@1078: 
kvn@3092:   assert(BlockZeroingLowLimit > 0, "invalid value");
iveresov@7135:   if (has_block_zeroing() && cache_line_size > 0) {
kvn@3092:     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
kvn@3092:       FLAG_SET_DEFAULT(UseBlockZeroing, true);
kvn@3092:     }
kvn@3092:   } else if (UseBlockZeroing) {
kvn@3092:     warning("BIS zeroing instructions are not available on this CPU");
kvn@3092:     FLAG_SET_DEFAULT(UseBlockZeroing, false);
kvn@3092:   }
kvn@3092: 
kvn@3103:   assert(BlockCopyLowLimit > 0, "invalid value");
iveresov@7135:   if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
kvn@3103:     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
kvn@3103:       FLAG_SET_DEFAULT(UseBlockCopy, true);
kvn@3103:     }
kvn@3103:   } else if (UseBlockCopy) {
kvn@3103:     warning("BIS instructions are not available or expensive on this CPU");
kvn@3103:     FLAG_SET_DEFAULT(UseBlockCopy, false);
kvn@3103:   }
kvn@3103: 
never@2085: #ifdef COMPILER2
kvn@3037:   // T4 and newer Sparc cpus have fast RDPC.
kvn@3037:   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
twisti@3249:     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
kvn@3037:   }
kvn@3037: 
never@2085:   // Currently not supported anywhere.
never@2085:   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
kvn@3049: 
kvn@3882:   MaxVectorSize = 8;
kvn@3882: 
kvn@3049:   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
never@2085: #endif
never@2085: 
kvn@3049:   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
kvn@3049:   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
kvn@3049: 
duke@435:   char buf[512];
kvn@7027:   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
kvn@3037:                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
twisti@1078:                (has_hardware_popc() ? ", popc" : ""),
kvn@3037:                (has_vis1() ? ", vis1" : ""),
kvn@3037:                (has_vis2() ? ", vis2" : ""),
kvn@3037:                (has_vis3() ? ", vis3" : ""),
kvn@3037:                (has_blk_init() ? ", blk_init" : ""),
kvn@3037:                (has_cbcond() ? ", cbcond" : ""),
kvn@6312:                (has_aes() ? ", aes" : ""),
kvn@7027:                (has_sha1() ? ", sha1" : ""),
kvn@7027:                (has_sha256() ? ", sha256" : ""),
kvn@7027:                (has_sha512() ? ", sha512" : ""),
kvn@3037:                (is_ultra3() ? ", ultra3" : ""),
kvn@3037:                (is_sun4v() ? ", sun4v" : ""),
kvn@3037:                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
kvn@3037:                (is_sparc64() ? ", sparc64" : ""),
twisti@1076:                (!has_hardware_mul32() ? ", no-mul32" : ""),
twisti@1076:                (!has_hardware_div32() ? ", no-div32" : ""),
duke@435:                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
duke@435: 
duke@435:   // buf is started with ", " or is empty
duke@435:   _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
duke@435: 
kevinw@8729:   // There are three 64-bit SPARC families that do not overlap, e.g.,
kevinw@8729:   // both is_ultra3() and is_sparc64() cannot be true at the same time.
kevinw@8729:   // Within these families, there can be more than one chip, e.g.,
kevinw@8729:   // is_T4() and is_T7() machines are also is_niagara().
kevinw@8729:   if (is_ultra3()) {
kevinw@8729:     assert(_L1_data_cache_line_size == 0, "overlap with Ultra3 family");
kevinw@8729:     // Ref: UltraSPARC III Cu Processor
kevinw@8729:     _L1_data_cache_line_size = 64;
kevinw@8729:   }
kevinw@8729:   if (is_niagara()) {
kevinw@8729:     assert(_L1_data_cache_line_size == 0, "overlap with niagara family");
kevinw@8729:     // All Niagara's are sun4v's, but not all sun4v's are Niagaras, e.g.,
kevinw@8729:     // Fujitsu SPARC64 is sun4v, but we don't want it in this block.
kevinw@8729:     //
kevinw@8729:     // Ref: UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
kevinw@8729:     // Appendix F.1.3.1 Cacheable Accesses
kevinw@8729:     // -> 16-byte L1 cache line size
kevinw@8729:     //
kevinw@8729:     // Ref: UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC
kevinw@8729:     // Section III: SPARC Processor Core
kevinw@8729:     // -> 16-byte L1 cache line size
kevinw@8729:     //
kevinw@8729:     // Ref: Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture
kevinw@8729:     // Section SPARC T4 Processor Cache Architecture
kevinw@8729:     // -> 32-byte L1 cache line size (no longer see that info on this ref)
kevinw@8729:     //
kevinw@8729:     // XXX - still need a T7 reference here
kevinw@8729:     //
kevinw@8729:     if (is_T7()) {  // T7 or newer
kevinw@8729:       _L1_data_cache_line_size = 64;
kevinw@8729:     } else if (is_T4()) {  // T4 or newer (until T7)
kevinw@8729:       _L1_data_cache_line_size = 32;
kevinw@8729:     } else {  // T1 or newer (until T4)
kevinw@8729:       _L1_data_cache_line_size = 16;
kevinw@8729:     }
kevinw@8729:   }
kevinw@8729:   if (is_sparc64()) {
kevinw@8729:     guarantee(_L1_data_cache_line_size == 0, "overlap with SPARC64 family");
kevinw@8729:     // Ref: Fujitsu SPARC64 VII Processor
kevinw@8729:     // Section 4 Cache System
kevinw@8729:     _L1_data_cache_line_size = 64;
kevinw@8729:   }
kevinw@8729: 
kvn@3001:   // UseVIS is set to the smallest of what hardware supports and what
kvn@3001:   // the command line requires.  I.e., you cannot set UseVIS to 3 on
kvn@3001:   // older UltraSparc which do not support it.
kvn@3001:   if (UseVIS > 3) UseVIS=3;
kvn@3001:   if (UseVIS < 0) UseVIS=0;
kvn@3001:   if (!has_vis3()) // Drop to 2 if no VIS3 support
kvn@3001:     UseVIS = MIN2((intx)2,UseVIS);
kvn@3001:   if (!has_vis2()) // Drop to 1 if no VIS2 support
kvn@3001:     UseVIS = MIN2((intx)1,UseVIS);
kvn@3001:   if (!has_vis1()) // Drop to 0 if no VIS1 support
kvn@3001:     UseVIS = 0;
kvn@3001: 
kvn@6653:   // SPARC T4 and above should have support for AES instructions
kvn@6312:   if (has_aes()) {
kvn@6653:     if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
kvn@6312:       if (FLAG_IS_DEFAULT(UseAES)) {
kvn@6312:         FLAG_SET_DEFAULT(UseAES, true);
kvn@6312:       }
kvn@6312:       if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
kvn@6312:         FLAG_SET_DEFAULT(UseAESIntrinsics, true);
kvn@6312:       }
kvn@6312:       // we disable both the AES flags if either of them is disabled on the command line
kvn@6312:       if (!UseAES || !UseAESIntrinsics) {
kvn@6312:         FLAG_SET_DEFAULT(UseAES, false);
kvn@6312:         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
kvn@6312:       }
kvn@6312:     } else {
kvn@6312:         if (UseAES || UseAESIntrinsics) {
kvn@6653:           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
kvn@6312:           if (UseAES) {
kvn@6312:             FLAG_SET_DEFAULT(UseAES, false);
kvn@6312:           }
kvn@6312:           if (UseAESIntrinsics) {
kvn@6312:             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
kvn@6312:           }
kvn@6312:         }
kvn@6312:     }
kvn@6312:   } else if (UseAES || UseAESIntrinsics) {
kvn@6312:     warning("AES instructions are not available on this CPU");
kvn@6312:     if (UseAES) {
kvn@6312:       FLAG_SET_DEFAULT(UseAES, false);
kvn@6312:     }
kvn@6312:     if (UseAESIntrinsics) {
kvn@6312:       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
kvn@6312:     }
kvn@6312:   }
kvn@6312: 
kvn@7027:   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
kvn@7027:   if (has_sha1() || has_sha256() || has_sha512()) {
kvn@7027:     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
kvn@7027:       if (FLAG_IS_DEFAULT(UseSHA)) {
kvn@7027:         FLAG_SET_DEFAULT(UseSHA, true);
kvn@7027:       }
kvn@7027:     } else {
kvn@7027:       if (UseSHA) {
kvn@7027:         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
kvn@7027:         FLAG_SET_DEFAULT(UseSHA, false);
kvn@7027:       }
kvn@7027:     }
kvn@7027:   } else if (UseSHA) {
kvn@7027:     warning("SHA instructions are not available on this CPU");
kvn@7027:     FLAG_SET_DEFAULT(UseSHA, false);
kvn@7027:   }
kvn@7027: 
kvn@7027:   if (!UseSHA) {
kvn@7027:     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
kvn@7027:     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
kvn@7027:     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
kvn@7027:   } else {
kvn@7027:     if (has_sha1()) {
kvn@7027:       if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
kvn@7027:         FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
kvn@7027:       }
kvn@7027:     } else if (UseSHA1Intrinsics) {
kvn@7027:       warning("SHA1 instruction is not available on this CPU.");
kvn@7027:       FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
kvn@7027:     }
kvn@7027:     if (has_sha256()) {
kvn@7027:       if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
kvn@7027:         FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
kvn@7027:       }
kvn@7027:     } else if (UseSHA256Intrinsics) {
kvn@7027:       warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
kvn@7027:       FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
kvn@7027:     }
kvn@7027: 
kvn@7027:     if (has_sha512()) {
kvn@7027:       if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
kvn@7027:         FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
kvn@7027:       }
kvn@7027:     } else if (UseSHA512Intrinsics) {
kvn@7027:       warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
kvn@7027:       FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
kvn@7027:     }
kvn@7027:     if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
kvn@7027:       FLAG_SET_DEFAULT(UseSHA, false);
kvn@7027:     }
kvn@7027:   }
kvn@7027: 
jwilhelm@4430:   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
jwilhelm@4430:     (cache_line_size > ContendedPaddingWidth))
jwilhelm@4430:     ContendedPaddingWidth = cache_line_size;
jwilhelm@4430: 
duke@435: #ifndef PRODUCT
duke@435:   if (PrintMiscellaneous && Verbose) {
kevinw@8729:     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
iveresov@7767:     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
kvn@3052:     tty->print("Allocation");
duke@435:     if (AllocatePrefetchStyle <= 0) {
kvn@3052:       tty->print_cr(": no prefetching");
duke@435:     } else {
kvn@3052:       tty->print(" prefetching: ");
kvn@3052:       if (AllocatePrefetchInstr == 0) {
kvn@3052:           tty->print("PREFETCH");
kvn@3052:       } else if (AllocatePrefetchInstr == 1) {
kvn@3052:           tty->print("BIS");
kvn@3052:       }
duke@435:       if (AllocatePrefetchLines > 1) {
drchase@6680:         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
duke@435:       } else {
drchase@6680:         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
duke@435:       }
duke@435:     }
duke@435:     if (PrefetchCopyIntervalInBytes > 0) {
drchase@6680:       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
duke@435:     }
duke@435:     if (PrefetchScanIntervalInBytes > 0) {
drchase@6680:       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
duke@435:     }
duke@435:     if (PrefetchFieldsAhead > 0) {
drchase@6680:       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
duke@435:     }
jwilhelm@4430:     if (ContendedPaddingWidth > 0) {
drchase@6680:       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
jwilhelm@4430:     }
duke@435:   }
duke@435: #endif // PRODUCT
duke@435: }
duke@435: 
duke@435: void VM_Version::print_features() {
duke@435:   tty->print_cr("Version:%s", cpu_features());
duke@435: }
duke@435: 
duke@435: int VM_Version::determine_features() {
duke@435:   if (UseV8InstrsOnly) {
duke@435:     NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
duke@435:     return generic_v8_m;
duke@435:   }
duke@435: 
duke@435:   int features = platform_features(unknown_m); // platform_features() is os_arch specific
duke@435: 
duke@435:   if (features == unknown_m) {
duke@435:     features = generic_v9_m;
duke@435:     warning("Cannot recognize SPARC version. Default to V9");
duke@435:   }
duke@435: 
kvn@2403:   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
kvn@2403:   if (UseNiagaraInstrs) { // Force code generation for Niagara
kvn@2403:     if (is_T_family(features)) {
duke@435:       // Happy to accomodate...
duke@435:     } else {
duke@435:       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
kvn@2403:       features |= T_family_m;
duke@435:     }
duke@435:   } else {
kvn@2403:     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
duke@435:       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
kvn@2403:       features &= ~(T_family_m | T1_model_m);
duke@435:     } else {
duke@435:       // Happy to accomodate...
duke@435:     }
duke@435:   }
duke@435: 
duke@435:   return features;
duke@435: }
duke@435: 
duke@435: static int saved_features = 0;
duke@435: 
duke@435: void VM_Version::allow_all() {
duke@435:   saved_features = _features;
duke@435:   _features      = all_features_m;
duke@435: }
duke@435: 
duke@435: void VM_Version::revert() {
duke@435:   _features = saved_features;
duke@435: }
jmasa@445: 
jmasa@445: unsigned int VM_Version::calc_parallel_worker_threads() {
jmasa@445:   unsigned int result;
twisti@4108:   if (is_M_series()) {
twisti@4108:     // for now, use same gc thread calculation for M-series as for niagara-plus
twisti@4108:     // in future, we may want to tweak parameters for nof_parallel_worker_thread
twisti@4108:     result = nof_parallel_worker_threads(5, 16, 8);
twisti@4108:   } else if (is_niagara_plus()) {
jmasa@445:     result = nof_parallel_worker_threads(5, 16, 8);
jmasa@445:   } else {
jmasa@445:     result = nof_parallel_worker_threads(5, 8, 8);
jmasa@445:   }
jmasa@445:   return result;
jmasa@445: }