duke@435: /*
duke@435:  * Copyright 2000-2006 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435:  private:
duke@435: 
duke@435:   //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
duke@435:   //
duke@435:   // Sparc load/store emission
duke@435:   //
duke@435:   // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
duke@435:   // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
duke@435:   // by allowing 32 bit displacements:
duke@435:   //
duke@435:   //    When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
duke@435:   //    When disp >  13 bits long, code is emitted to set the displacement into the O7 register,
duke@435:   //       and then a load or store is emitted with ([O7] + [d]).
duke@435:   //
duke@435: 
duke@435:   // some load/store variants return the code_offset for proper positioning of debug info for null checks
duke@435: 
duke@435:   // load/store with 32 bit displacement
duke@435:   int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
duke@435:   void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
duke@435: 
duke@435:   // loadf/storef with 32 bit displacement
duke@435:   void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
duke@435:   void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
duke@435: 
duke@435:   // convienence methods for calling load/store with an Address
duke@435:   void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
duke@435:   void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
duke@435:   void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
duke@435:   void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
duke@435: 
duke@435:   // convienence methods for calling load/store with an LIR_Address
duke@435:   void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
duke@435:   void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
duke@435:   void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
duke@435:   void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
duke@435: 
duke@435:   int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
duke@435:   int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
duke@435: 
duke@435:   int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
duke@435:   int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
duke@435: 
duke@435:   void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
duke@435: 
duke@435:   int shift_amount(BasicType t);
duke@435: 
duke@435:   static bool is_single_instruction(LIR_Op* op);
duke@435: 
duke@435:  public:
duke@435:   void pack64( Register rs, Register rd );
duke@435:   void unpack64( Register rd );
duke@435: 
duke@435: enum {
duke@435: #ifdef _LP64
duke@435:          call_stub_size = 68,
duke@435: #else
duke@435:          call_stub_size = 20,
duke@435: #endif // _LP64
duke@435:          exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
duke@435:          deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };