duke@435: /*
twisti@1162:  * Copyright 1999-2009 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: # include "incls/_precompiled.incl"
duke@435: # include "incls/_c1_FrameMap_sparc.cpp.incl"
duke@435: 
duke@435: 
duke@435: const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
duke@435: 
duke@435: 
duke@435: LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
duke@435:   LIR_Opr opr = LIR_OprFact::illegalOpr;
duke@435:   VMReg r_1 = reg->first();
duke@435:   VMReg r_2 = reg->second();
duke@435:   if (r_1->is_stack()) {
duke@435:     // Convert stack slot to an SP offset
duke@435:     // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
duke@435:     // so we must add it in here.
duke@435:     int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@435:     opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
duke@435:   } else if (r_1->is_Register()) {
duke@435:     Register reg = r_1->as_Register();
duke@435:     if (outgoing) {
duke@435:       assert(!reg->is_in(), "should be using I regs");
duke@435:     } else {
duke@435:       assert(!reg->is_out(), "should be using O regs");
duke@435:     }
duke@435:     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
duke@435:       opr = as_long_opr(reg);
duke@435:     } else if (type == T_OBJECT || type == T_ARRAY) {
duke@435:       opr = as_oop_opr(reg);
duke@435:     } else {
duke@435:       opr = as_opr(reg);
duke@435:     }
duke@435:   } else if (r_1->is_FloatRegister()) {
duke@435:     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
duke@435:     FloatRegister f = r_1->as_FloatRegister();
duke@435:     if (type == T_DOUBLE) {
duke@435:       opr = as_double_opr(f);
duke@435:     } else {
duke@435:       opr = as_float_opr(f);
duke@435:     }
duke@435:   }
duke@435:   return opr;
duke@435: }
duke@435: 
duke@435: //               FrameMap
duke@435: //--------------------------------------------------------
duke@435: 
duke@435: FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
duke@435: 
duke@435: // some useful constant RInfo's:
duke@435: LIR_Opr FrameMap::in_long_opr;
duke@435: LIR_Opr FrameMap::out_long_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::F0_opr;
duke@435: LIR_Opr FrameMap::F0_double_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::G0_opr;
duke@435: LIR_Opr FrameMap::G1_opr;
duke@435: LIR_Opr FrameMap::G2_opr;
duke@435: LIR_Opr FrameMap::G3_opr;
duke@435: LIR_Opr FrameMap::G4_opr;
duke@435: LIR_Opr FrameMap::G5_opr;
duke@435: LIR_Opr FrameMap::G6_opr;
duke@435: LIR_Opr FrameMap::G7_opr;
duke@435: LIR_Opr FrameMap::O0_opr;
duke@435: LIR_Opr FrameMap::O1_opr;
duke@435: LIR_Opr FrameMap::O2_opr;
duke@435: LIR_Opr FrameMap::O3_opr;
duke@435: LIR_Opr FrameMap::O4_opr;
duke@435: LIR_Opr FrameMap::O5_opr;
duke@435: LIR_Opr FrameMap::O6_opr;
duke@435: LIR_Opr FrameMap::O7_opr;
duke@435: LIR_Opr FrameMap::L0_opr;
duke@435: LIR_Opr FrameMap::L1_opr;
duke@435: LIR_Opr FrameMap::L2_opr;
duke@435: LIR_Opr FrameMap::L3_opr;
duke@435: LIR_Opr FrameMap::L4_opr;
duke@435: LIR_Opr FrameMap::L5_opr;
duke@435: LIR_Opr FrameMap::L6_opr;
duke@435: LIR_Opr FrameMap::L7_opr;
duke@435: LIR_Opr FrameMap::I0_opr;
duke@435: LIR_Opr FrameMap::I1_opr;
duke@435: LIR_Opr FrameMap::I2_opr;
duke@435: LIR_Opr FrameMap::I3_opr;
duke@435: LIR_Opr FrameMap::I4_opr;
duke@435: LIR_Opr FrameMap::I5_opr;
duke@435: LIR_Opr FrameMap::I6_opr;
duke@435: LIR_Opr FrameMap::I7_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::G0_oop_opr;
duke@435: LIR_Opr FrameMap::G1_oop_opr;
duke@435: LIR_Opr FrameMap::G2_oop_opr;
duke@435: LIR_Opr FrameMap::G3_oop_opr;
duke@435: LIR_Opr FrameMap::G4_oop_opr;
duke@435: LIR_Opr FrameMap::G5_oop_opr;
duke@435: LIR_Opr FrameMap::G6_oop_opr;
duke@435: LIR_Opr FrameMap::G7_oop_opr;
duke@435: LIR_Opr FrameMap::O0_oop_opr;
duke@435: LIR_Opr FrameMap::O1_oop_opr;
duke@435: LIR_Opr FrameMap::O2_oop_opr;
duke@435: LIR_Opr FrameMap::O3_oop_opr;
duke@435: LIR_Opr FrameMap::O4_oop_opr;
duke@435: LIR_Opr FrameMap::O5_oop_opr;
duke@435: LIR_Opr FrameMap::O6_oop_opr;
duke@435: LIR_Opr FrameMap::O7_oop_opr;
duke@435: LIR_Opr FrameMap::L0_oop_opr;
duke@435: LIR_Opr FrameMap::L1_oop_opr;
duke@435: LIR_Opr FrameMap::L2_oop_opr;
duke@435: LIR_Opr FrameMap::L3_oop_opr;
duke@435: LIR_Opr FrameMap::L4_oop_opr;
duke@435: LIR_Opr FrameMap::L5_oop_opr;
duke@435: LIR_Opr FrameMap::L6_oop_opr;
duke@435: LIR_Opr FrameMap::L7_oop_opr;
duke@435: LIR_Opr FrameMap::I0_oop_opr;
duke@435: LIR_Opr FrameMap::I1_oop_opr;
duke@435: LIR_Opr FrameMap::I2_oop_opr;
duke@435: LIR_Opr FrameMap::I3_oop_opr;
duke@435: LIR_Opr FrameMap::I4_oop_opr;
duke@435: LIR_Opr FrameMap::I5_oop_opr;
duke@435: LIR_Opr FrameMap::I6_oop_opr;
duke@435: LIR_Opr FrameMap::I7_oop_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::SP_opr;
duke@435: LIR_Opr FrameMap::FP_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::Oexception_opr;
duke@435: LIR_Opr FrameMap::Oissuing_pc_opr;
duke@435: 
duke@435: LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
duke@435: LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
duke@435: 
duke@435: 
duke@435: FloatRegister FrameMap::nr2floatreg (int rnr) {
duke@435:   assert(_init_done, "tables not initialized");
duke@435:   debug_only(fpu_range_check(rnr);)
duke@435:   return _fpu_regs[rnr];
duke@435: }
duke@435: 
duke@435: 
duke@435: // returns true if reg could be smashed by a callee.
duke@435: bool FrameMap::is_caller_save_register (LIR_Opr reg) {
duke@435:   if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
duke@435:   if (reg->is_double_cpu()) {
duke@435:     return is_caller_save_register(reg->as_register_lo()) ||
duke@435:            is_caller_save_register(reg->as_register_hi());
duke@435:   }
duke@435:   return is_caller_save_register(reg->as_register());
duke@435: }
duke@435: 
duke@435: 
duke@435: NEEDS_CLEANUP   // once the new calling convention is enabled, we no
duke@435:                 // longer need to treat I5, I4 and L0 specially
duke@435: // Because the interpreter destroys caller's I5, I4 and L0,
duke@435: // we must spill them before doing a Java call as we may land in
duke@435: // interpreter.
duke@435: bool FrameMap::is_caller_save_register (Register r) {
duke@435:   return (r->is_global() && (r != G0)) || r->is_out();
duke@435: }
duke@435: 
duke@435: 
duke@435: void FrameMap::init () {
duke@435:   if (_init_done) return;
duke@435: 
duke@435:   int i=0;
duke@435:   // Register usage:
duke@435:   //  O6: sp
duke@435:   //  I6: fp
duke@435:   //  I7: return address
duke@435:   //  G0: zero
duke@435:   //  G2: thread
duke@435:   //  G7: not available
duke@435:   //  G6: not available
duke@435:   /*  0 */ map_register(i++, L0);
duke@435:   /*  1 */ map_register(i++, L1);
duke@435:   /*  2 */ map_register(i++, L2);
duke@435:   /*  3 */ map_register(i++, L3);
duke@435:   /*  4 */ map_register(i++, L4);
duke@435:   /*  5 */ map_register(i++, L5);
duke@435:   /*  6 */ map_register(i++, L6);
duke@435:   /*  7 */ map_register(i++, L7);
duke@435: 
duke@435:   /*  8 */ map_register(i++, I0);
duke@435:   /*  9 */ map_register(i++, I1);
duke@435:   /* 10 */ map_register(i++, I2);
duke@435:   /* 11 */ map_register(i++, I3);
duke@435:   /* 12 */ map_register(i++, I4);
duke@435:   /* 13 */ map_register(i++, I5);
duke@435:   /* 14 */ map_register(i++, O0);
duke@435:   /* 15 */ map_register(i++, O1);
duke@435:   /* 16 */ map_register(i++, O2);
duke@435:   /* 17 */ map_register(i++, O3);
duke@435:   /* 18 */ map_register(i++, O4);
duke@435:   /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs)
duke@435:   /* 20 */ map_register(i++, G1);
duke@435:   /* 21 */ map_register(i++, G3);
duke@435:   /* 22 */ map_register(i++, G4);
duke@435:   /* 23 */ map_register(i++, G5);
duke@435:   /* 24 */ map_register(i++, G0);
duke@435: 
duke@435:   // the following registers are not normally available
duke@435:   /* 25 */ map_register(i++, O7);
duke@435:   /* 26 */ map_register(i++, G2);
duke@435:   /* 27 */ map_register(i++, O6);
duke@435:   /* 28 */ map_register(i++, I6);
duke@435:   /* 29 */ map_register(i++, I7);
duke@435:   /* 30 */ map_register(i++, G6);
duke@435:   /* 31 */ map_register(i++, G7);
duke@435:   assert(i == nof_cpu_regs, "number of CPU registers");
duke@435: 
duke@435:   for (i = 0; i < nof_fpu_regs; i++) {
duke@435:     _fpu_regs[i] = as_FloatRegister(i);
duke@435:   }
duke@435: 
duke@435:   _init_done = true;
duke@435: 
duke@435:   in_long_opr    = as_long_opr(I0);
duke@435:   out_long_opr   = as_long_opr(O0);
duke@435: 
duke@435:   G0_opr = as_opr(G0);
duke@435:   G1_opr = as_opr(G1);
duke@435:   G2_opr = as_opr(G2);
duke@435:   G3_opr = as_opr(G3);
duke@435:   G4_opr = as_opr(G4);
duke@435:   G5_opr = as_opr(G5);
duke@435:   G6_opr = as_opr(G6);
duke@435:   G7_opr = as_opr(G7);
duke@435:   O0_opr = as_opr(O0);
duke@435:   O1_opr = as_opr(O1);
duke@435:   O2_opr = as_opr(O2);
duke@435:   O3_opr = as_opr(O3);
duke@435:   O4_opr = as_opr(O4);
duke@435:   O5_opr = as_opr(O5);
duke@435:   O6_opr = as_opr(O6);
duke@435:   O7_opr = as_opr(O7);
duke@435:   L0_opr = as_opr(L0);
duke@435:   L1_opr = as_opr(L1);
duke@435:   L2_opr = as_opr(L2);
duke@435:   L3_opr = as_opr(L3);
duke@435:   L4_opr = as_opr(L4);
duke@435:   L5_opr = as_opr(L5);
duke@435:   L6_opr = as_opr(L6);
duke@435:   L7_opr = as_opr(L7);
duke@435:   I0_opr = as_opr(I0);
duke@435:   I1_opr = as_opr(I1);
duke@435:   I2_opr = as_opr(I2);
duke@435:   I3_opr = as_opr(I3);
duke@435:   I4_opr = as_opr(I4);
duke@435:   I5_opr = as_opr(I5);
duke@435:   I6_opr = as_opr(I6);
duke@435:   I7_opr = as_opr(I7);
duke@435: 
duke@435:   G0_oop_opr = as_oop_opr(G0);
duke@435:   G1_oop_opr = as_oop_opr(G1);
duke@435:   G2_oop_opr = as_oop_opr(G2);
duke@435:   G3_oop_opr = as_oop_opr(G3);
duke@435:   G4_oop_opr = as_oop_opr(G4);
duke@435:   G5_oop_opr = as_oop_opr(G5);
duke@435:   G6_oop_opr = as_oop_opr(G6);
duke@435:   G7_oop_opr = as_oop_opr(G7);
duke@435:   O0_oop_opr = as_oop_opr(O0);
duke@435:   O1_oop_opr = as_oop_opr(O1);
duke@435:   O2_oop_opr = as_oop_opr(O2);
duke@435:   O3_oop_opr = as_oop_opr(O3);
duke@435:   O4_oop_opr = as_oop_opr(O4);
duke@435:   O5_oop_opr = as_oop_opr(O5);
duke@435:   O6_oop_opr = as_oop_opr(O6);
duke@435:   O7_oop_opr = as_oop_opr(O7);
duke@435:   L0_oop_opr = as_oop_opr(L0);
duke@435:   L1_oop_opr = as_oop_opr(L1);
duke@435:   L2_oop_opr = as_oop_opr(L2);
duke@435:   L3_oop_opr = as_oop_opr(L3);
duke@435:   L4_oop_opr = as_oop_opr(L4);
duke@435:   L5_oop_opr = as_oop_opr(L5);
duke@435:   L6_oop_opr = as_oop_opr(L6);
duke@435:   L7_oop_opr = as_oop_opr(L7);
duke@435:   I0_oop_opr = as_oop_opr(I0);
duke@435:   I1_oop_opr = as_oop_opr(I1);
duke@435:   I2_oop_opr = as_oop_opr(I2);
duke@435:   I3_oop_opr = as_oop_opr(I3);
duke@435:   I4_oop_opr = as_oop_opr(I4);
duke@435:   I5_oop_opr = as_oop_opr(I5);
duke@435:   I6_oop_opr = as_oop_opr(I6);
duke@435:   I7_oop_opr = as_oop_opr(I7);
duke@435: 
duke@435:   FP_opr = as_pointer_opr(FP);
duke@435:   SP_opr = as_pointer_opr(SP);
duke@435: 
duke@435:   F0_opr = as_float_opr(F0);
duke@435:   F0_double_opr = as_double_opr(F0);
duke@435: 
duke@435:   Oexception_opr = as_oop_opr(Oexception);
duke@435:   Oissuing_pc_opr = as_opr(Oissuing_pc);
duke@435: 
duke@435:   _caller_save_cpu_regs[0] = FrameMap::O0_opr;
duke@435:   _caller_save_cpu_regs[1] = FrameMap::O1_opr;
duke@435:   _caller_save_cpu_regs[2] = FrameMap::O2_opr;
duke@435:   _caller_save_cpu_regs[3] = FrameMap::O3_opr;
duke@435:   _caller_save_cpu_regs[4] = FrameMap::O4_opr;
duke@435:   _caller_save_cpu_regs[5] = FrameMap::O5_opr;
never@1363:   _caller_save_cpu_regs[6] = FrameMap::G1_opr;
never@1363:   _caller_save_cpu_regs[7] = FrameMap::G3_opr;
never@1363:   _caller_save_cpu_regs[8] = FrameMap::G4_opr;
never@1363:   _caller_save_cpu_regs[9] = FrameMap::G5_opr;
duke@435:   for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
duke@435:     _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
duke@435:   }
duke@435: }
duke@435: 
duke@435: 
duke@435: Address FrameMap::make_new_address(ByteSize sp_offset) const {
twisti@1162:   return Address(SP, STACK_BIAS + in_bytes(sp_offset));
duke@435: }
duke@435: 
duke@435: 
duke@435: VMReg FrameMap::fpu_regname (int n) {
duke@435:   return as_FloatRegister(n)->as_VMReg();
duke@435: }
duke@435: 
duke@435: 
duke@435: LIR_Opr FrameMap::stack_pointer() {
duke@435:   return SP_opr;
duke@435: }
duke@435: 
duke@435: 
duke@435: bool FrameMap::validate_frame() {
duke@435:   int max_offset = in_bytes(framesize_in_bytes());
duke@435:   int java_index = 0;
duke@435:   for (int i = 0; i < _incoming_arguments->length(); i++) {
duke@435:     LIR_Opr opr = _incoming_arguments->at(i);
duke@435:     if (opr->is_stack()) {
duke@435:       max_offset = MAX2(_argument_locations->at(java_index), max_offset);
duke@435:     }
duke@435:     java_index += type2size[opr->type()];
duke@435:   }
duke@435:   return Assembler::is_simm13(max_offset + STACK_BIAS);
duke@435: }