duke@435: /*
stefank@2314:  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
trims@1907:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907:  * or visit www.oracle.com if you need additional information or have any
trims@1907:  * questions.
duke@435:  *
duke@435:  */
duke@435: 
stefank@2314: #ifndef CPU_SPARC_VM_ICACHE_SPARC_HPP
stefank@2314: #define CPU_SPARC_VM_ICACHE_SPARC_HPP
stefank@2314: 
duke@435: // Interface for updating the instruction cache.  Whenever the VM modifies
duke@435: // code, part of the processor instruction cache potentially has to be flushed.
duke@435: 
duke@435: 
duke@435: class ICache : public AbstractICache {
duke@435:  public:
duke@435:   enum {
duke@435:     stub_size      = 160, // Size of the icache flush stub in bytes
duke@435:     line_size      = 8,   // flush instruction affects a dword
duke@435:     log2_line_size = 3    // log2(line_size)
duke@435:   };
duke@435: 
duke@435:   // Use default implementation
duke@435: };
stefank@2314: 
stefank@2314: #endif // CPU_SPARC_VM_ICACHE_SPARC_HPP