duke@435: /*
xdono@631:  * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: # include "incls/_precompiled.incl"
duke@435: # include "incls/_nativeInst_x86.cpp.incl"
duke@435: 
duke@435: void NativeInstruction::wrote(int offset) {
duke@435:   ICache::invalidate_word(addr_at(offset));
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeCall::verify() {
duke@435:   // Make sure code pattern is actually a call imm32 instruction.
duke@435:   int inst = ubyte_at(0);
duke@435:   if (inst != instruction_code) {
duke@435:     tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),
duke@435:                                                         inst);
duke@435:     fatal("not a call disp32");
duke@435:   }
duke@435: }
duke@435: 
duke@435: address NativeCall::destination() const {
duke@435:   // Getting the destination of a call isn't safe because that call can
duke@435:   // be getting patched while you're calling this.  There's only special
duke@435:   // places where this can be called but not automatically verifiable by
duke@435:   // checking which locks are held.  The solution is true atomic patching
duke@435:   // on x86, nyi.
duke@435:   return return_address() + displacement();
duke@435: }
duke@435: 
duke@435: void NativeCall::print() {
duke@435:   tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
duke@435:                 instruction_address(), destination());
duke@435: }
duke@435: 
duke@435: // Inserts a native call instruction at a given pc
duke@435: void NativeCall::insert(address code_pos, address entry) {
duke@435:   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@435: #ifdef AMD64
duke@435:   guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
duke@435: #endif // AMD64
duke@435:   *code_pos = instruction_code;
duke@435:   *((int32_t *)(code_pos+1)) = (int32_t) disp;
duke@435:   ICache::invalidate_range(code_pos, instruction_size);
duke@435: }
duke@435: 
duke@435: // MT-safe patching of a call instruction.
duke@435: // First patches first word of instruction to two jmp's that jmps to them
duke@435: // selfs (spinlock). Then patches the last byte, and then atomicly replaces
duke@435: // the jmp's with the first 4 byte of the new instruction.
duke@435: void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
duke@435:   assert(Patching_lock->is_locked() ||
duke@435:          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@435:   assert (instr_addr != NULL, "illegal address for code patching");
duke@435: 
duke@435:   NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
duke@435:   if (os::is_MP()) {
duke@435:     guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
duke@435:   }
duke@435: 
duke@435:   // First patch dummy jmp in place
duke@435:   unsigned char patch[4];
duke@435:   assert(sizeof(patch)==sizeof(jint), "sanity check");
duke@435:   patch[0] = 0xEB;       // jmp rel8
duke@435:   patch[1] = 0xFE;       // jmp to self
duke@435:   patch[2] = 0xEB;
duke@435:   patch[3] = 0xFE;
duke@435: 
duke@435:   // First patch dummy jmp in place
duke@435:   *(jint*)instr_addr = *(jint *)patch;
duke@435: 
duke@435:   // Invalidate.  Opteron requires a flush after every write.
duke@435:   n_call->wrote(0);
duke@435: 
duke@435:   // Patch 4th byte
duke@435:   instr_addr[4] = code_buffer[4];
duke@435: 
duke@435:   n_call->wrote(4);
duke@435: 
duke@435:   // Patch bytes 0-3
duke@435:   *(jint*)instr_addr = *(jint *)code_buffer;
duke@435: 
duke@435:   n_call->wrote(0);
duke@435: 
duke@435: #ifdef ASSERT
duke@435:    // verify patching
duke@435:    for ( int i = 0; i < instruction_size; i++) {
duke@435:      address ptr = (address)((intptr_t)code_buffer + i);
duke@435:      int a_byte = (*ptr) & 0xFF;
duke@435:      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
duke@435:    }
duke@435: #endif
duke@435: 
duke@435: }
duke@435: 
duke@435: 
duke@435: // Similar to replace_mt_safe, but just changes the destination.  The
duke@435: // important thing is that free-running threads are able to execute this
duke@435: // call instruction at all times.  If the displacement field is aligned
duke@435: // we can simply rely on atomicity of 32-bit writes to make sure other threads
duke@435: // will see no intermediate states.  Otherwise, the first two bytes of the
duke@435: // call are guaranteed to be aligned, and can be atomically patched to a
duke@435: // self-loop to guard the instruction while we change the other bytes.
duke@435: 
duke@435: // We cannot rely on locks here, since the free-running threads must run at
duke@435: // full speed.
duke@435: //
duke@435: // Used in the runtime linkage of calls; see class CompiledIC.
duke@435: // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
duke@435: void NativeCall::set_destination_mt_safe(address dest) {
duke@435:   debug_only(verify());
duke@435:   // Make sure patching code is locked.  No two threads can patch at the same
duke@435:   // time but one may be executing this code.
duke@435:   assert(Patching_lock->is_locked() ||
duke@435:          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@435:   // Both C1 and C2 should now be generating code which aligns the patched address
duke@435:   // to be within a single cache line except that C1 does not do the alignment on
duke@435:   // uniprocessor systems.
duke@435:   bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
duke@435:                     ((uintptr_t)displacement_address() + 3) / cache_line_size;
duke@435: 
duke@435:   guarantee(!os::is_MP() || is_aligned, "destination must be aligned");
duke@435: 
duke@435:   if (is_aligned) {
duke@435:     // Simple case:  The destination lies within a single cache line.
duke@435:     set_destination(dest);
duke@435:   } else if ((uintptr_t)instruction_address() / cache_line_size ==
duke@435:              ((uintptr_t)instruction_address()+1) / cache_line_size) {
duke@435:     // Tricky case:  The instruction prefix lies within a single cache line.
duke@435:     intptr_t disp = dest - return_address();
duke@435: #ifdef AMD64
duke@435:     guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
duke@435: #endif // AMD64
duke@435: 
duke@435:     int call_opcode = instruction_address()[0];
duke@435: 
duke@435:     // First patch dummy jump in place:
duke@435:     {
duke@435:       u_char patch_jump[2];
duke@435:       patch_jump[0] = 0xEB;       // jmp rel8
duke@435:       patch_jump[1] = 0xFE;       // jmp to self
duke@435: 
duke@435:       assert(sizeof(patch_jump)==sizeof(short), "sanity check");
duke@435:       *(short*)instruction_address() = *(short*)patch_jump;
duke@435:     }
duke@435:     // Invalidate.  Opteron requires a flush after every write.
duke@435:     wrote(0);
duke@435: 
duke@435:     // (Note: We assume any reader which has already started to read
duke@435:     // the unpatched call will completely read the whole unpatched call
duke@435:     // without seeing the next writes we are about to make.)
duke@435: 
duke@435:     // Next, patch the last three bytes:
duke@435:     u_char patch_disp[5];
duke@435:     patch_disp[0] = call_opcode;
duke@435:     *(int32_t*)&patch_disp[1] = (int32_t)disp;
duke@435:     assert(sizeof(patch_disp)==instruction_size, "sanity check");
duke@435:     for (int i = sizeof(short); i < instruction_size; i++)
duke@435:       instruction_address()[i] = patch_disp[i];
duke@435: 
duke@435:     // Invalidate.  Opteron requires a flush after every write.
duke@435:     wrote(sizeof(short));
duke@435: 
duke@435:     // (Note: We assume that any reader which reads the opcode we are
duke@435:     // about to repatch will also read the writes we just made.)
duke@435: 
duke@435:     // Finally, overwrite the jump:
duke@435:     *(short*)instruction_address() = *(short*)patch_disp;
duke@435:     // Invalidate.  Opteron requires a flush after every write.
duke@435:     wrote(0);
duke@435: 
duke@435:     debug_only(verify());
duke@435:     guarantee(destination() == dest, "patch succeeded");
duke@435:   } else {
duke@435:     // Impossible:  One or the other must be atomically writable.
duke@435:     ShouldNotReachHere();
duke@435:   }
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeMovConstReg::verify() {
duke@435: #ifdef AMD64
duke@435:   // make sure code pattern is actually a mov reg64, imm64 instruction
duke@435:   if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
duke@435:       (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
duke@435:     print();
duke@435:     fatal("not a REX.W[B] mov reg64, imm64");
duke@435:   }
duke@435: #else
duke@435:   // make sure code pattern is actually a mov reg, imm32 instruction
duke@435:   u_char test_byte = *(u_char*)instruction_address();
duke@435:   u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
duke@435:   if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
duke@435: #endif // AMD64
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeMovConstReg::print() {
duke@435:   tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
duke@435:                 instruction_address(), data());
duke@435: }
duke@435: 
duke@435: //-------------------------------------------------------------------
duke@435: 
never@739: int NativeMovRegMem::instruction_start() const {
never@739:   int off = 0;
never@739:   u_char instr_0 = ubyte_at(off);
duke@435: 
never@739:   // First check to see if we have a (prefixed or not) xor
never@739:   if ( instr_0 >= instruction_prefix_wide_lo &&      // 0x40
never@739:        instr_0 <= instruction_prefix_wide_hi) { // 0x4f
never@739:     off++;
never@739:     instr_0 = ubyte_at(off);
never@739:   }
duke@435: 
never@739:   if (instr_0 == instruction_code_xor) {
never@739:     off += 2;
never@739:     instr_0 = ubyte_at(off);
duke@435:   }
duke@435: 
never@739:   // Now look for the real instruction and the many prefix/size specifiers.
never@739: 
never@739:   if (instr_0 == instruction_operandsize_prefix ) {  // 0x66
never@739:     off++; // Not SSE instructions
never@739:     instr_0 = ubyte_at(off);
duke@435:   }
never@739: 
never@739:   if ( instr_0 == instruction_code_xmm_ss_prefix ||      // 0xf3
never@739:        instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
never@739:     off++;
never@739:     instr_0 = ubyte_at(off);
never@739:   }
never@739: 
never@739:   if ( instr_0 >= instruction_prefix_wide_lo &&      // 0x40
never@739:        instr_0 <= instruction_prefix_wide_hi) { // 0x4f
never@739:     off++;
never@739:     instr_0 = ubyte_at(off);
never@739:   }
never@739: 
never@739: 
never@739:   if (instr_0 == instruction_extended_prefix ) {  // 0x0f
never@739:     off++;
never@739:   }
never@739: 
never@739:   return off;
never@739: }
never@739: 
never@739: address NativeMovRegMem::instruction_address() const {
never@739:   return addr_at(instruction_start());
never@739: }
never@739: 
never@739: address NativeMovRegMem::next_instruction_address() const {
never@739:   address ret = instruction_address() + instruction_size;
never@739:   u_char instr_0 =  *(u_char*) instruction_address();
never@739:   switch (instr_0) {
never@739:   case instruction_operandsize_prefix:
never@739: 
never@739:     fatal("should have skipped instruction_operandsize_prefix");
never@739:     break;
never@739: 
never@739:   case instruction_extended_prefix:
never@739:     fatal("should have skipped instruction_extended_prefix");
never@739:     break;
never@739: 
never@739:   case instruction_code_mem2reg_movslq: // 0x63
never@739:   case instruction_code_mem2reg_movzxb: // 0xB6
never@739:   case instruction_code_mem2reg_movsxb: // 0xBE
never@739:   case instruction_code_mem2reg_movzxw: // 0xB7
never@739:   case instruction_code_mem2reg_movsxw: // 0xBF
never@739:   case instruction_code_reg2mem:        // 0x89 (q/l)
never@739:   case instruction_code_mem2reg:        // 0x8B (q/l)
never@739:   case instruction_code_reg2memb:       // 0x88
never@739:   case instruction_code_mem2regb:       // 0x8a
never@739: 
never@739:   case instruction_code_float_s:        // 0xd9 fld_s a
never@739:   case instruction_code_float_d:        // 0xdd fld_d a
never@739: 
never@739:   case instruction_code_xmm_load:       // 0x10
never@739:   case instruction_code_xmm_store:      // 0x11
never@739:   case instruction_code_xmm_lpd:        // 0x12
never@739:     {
never@739:       // If there is an SIB then instruction is longer than expected
never@739:       u_char mod_rm = *(u_char*)(instruction_address() + 1);
never@739:       if ((mod_rm & 7) == 0x4) {
never@739:         ret++;
never@739:       }
never@739:     }
never@739:   case instruction_code_xor:
never@739:     fatal("should have skipped xor lead in");
never@739:     break;
never@739: 
never@739:   default:
never@739:     fatal("not a NativeMovRegMem");
never@739:   }
never@739:   return ret;
never@739: 
never@739: }
never@739: 
never@739: int NativeMovRegMem::offset() const{
never@739:   int off = data_offset + instruction_start();
never@739:   u_char mod_rm = *(u_char*)(instruction_address() + 1);
never@739:   // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
never@739:   // the encoding to use an SIB byte. Which will have the nnnn
never@739:   // field off by one byte
never@739:   if ((mod_rm & 7) == 0x4) {
never@739:     off++;
never@739:   }
never@739:   return int_at(off);
never@739: }
never@739: 
never@739: void NativeMovRegMem::set_offset(int x) {
never@739:   int off = data_offset + instruction_start();
never@739:   u_char mod_rm = *(u_char*)(instruction_address() + 1);
never@739:   // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
never@739:   // the encoding to use an SIB byte. Which will have the nnnn
never@739:   // field off by one byte
never@739:   if ((mod_rm & 7) == 0x4) {
never@739:     off++;
never@739:   }
never@739:   set_int_at(off, x);
duke@435: }
duke@435: 
duke@435: void NativeMovRegMem::verify() {
duke@435:   // make sure code pattern is actually a mov [reg+offset], reg instruction
duke@435:   u_char test_byte = *(u_char*)instruction_address();
never@739:   switch (test_byte) {
never@739:     case instruction_code_reg2memb:  // 0x88 movb a, r
never@739:     case instruction_code_reg2mem:   // 0x89 movl a, r (can be movq in 64bit)
never@739:     case instruction_code_mem2regb:  // 0x8a movb r, a
never@739:     case instruction_code_mem2reg:   // 0x8b movl r, a (can be movq in 64bit)
never@739:       break;
never@739: 
never@739:     case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
never@739:     case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
never@739:     case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
never@739:     case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
never@739:     case instruction_code_mem2reg_movsxw: // 0xbf  movswl r, a (movsxw)
never@739:       break;
never@739: 
never@739:     case instruction_code_float_s:   // 0xd9 fld_s a
never@739:     case instruction_code_float_d:   // 0xdd fld_d a
never@739:     case instruction_code_xmm_load:  // 0x10 movsd xmm, a
never@739:     case instruction_code_xmm_store: // 0x11 movsd a, xmm
never@739:     case instruction_code_xmm_lpd:   // 0x12 movlpd xmm, a
never@739:       break;
never@739: 
never@739:     default:
duke@435:           fatal ("not a mov [reg+offs], reg instruction");
duke@435:   }
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeMovRegMem::print() {
duke@435:   tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
duke@435: }
duke@435: 
duke@435: //-------------------------------------------------------------------
duke@435: 
duke@435: void NativeLoadAddress::verify() {
duke@435:   // make sure code pattern is actually a mov [reg+offset], reg instruction
duke@435:   u_char test_byte = *(u_char*)instruction_address();
never@739: #ifdef _LP64
never@739:   if ( (test_byte == instruction_prefix_wide ||
never@739:         test_byte == instruction_prefix_wide_extended) ) {
never@739:     test_byte = *(u_char*)(instruction_address() + 1);
never@739:   }
never@739: #endif // _LP64
never@739:   if ( ! ((test_byte == lea_instruction_code)
never@739:           LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) {
duke@435:     fatal ("not a lea reg, [reg+offs] instruction");
duke@435:   }
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeLoadAddress::print() {
duke@435:   tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
duke@435: }
duke@435: 
duke@435: //--------------------------------------------------------------------------------
duke@435: 
duke@435: void NativeJump::verify() {
duke@435:   if (*(u_char*)instruction_address() != instruction_code) {
duke@435:     fatal("not a jump instruction");
duke@435:   }
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeJump::insert(address code_pos, address entry) {
duke@435:   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@435: #ifdef AMD64
duke@435:   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@435: #endif // AMD64
duke@435: 
duke@435:   *code_pos = instruction_code;
duke@435:   *((int32_t*)(code_pos + 1)) = (int32_t)disp;
duke@435: 
duke@435:   ICache::invalidate_range(code_pos, instruction_size);
duke@435: }
duke@435: 
duke@435: void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
duke@435:   // Patching to not_entrant can happen while activations of the method are
duke@435:   // in use. The patching in that instance must happen only when certain
duke@435:   // alignment restrictions are true. These guarantees check those
duke@435:   // conditions.
duke@435: #ifdef AMD64
duke@435:   const int linesize = 64;
duke@435: #else
duke@435:   const int linesize = 32;
duke@435: #endif // AMD64
duke@435: 
duke@435:   // Must be wordSize aligned
duke@435:   guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
duke@435:             "illegal address for code patching 2");
duke@435:   // First 5 bytes must be within the same cache line - 4827828
duke@435:   guarantee((uintptr_t) verified_entry / linesize ==
duke@435:             ((uintptr_t) verified_entry + 4) / linesize,
duke@435:             "illegal address for code patching 3");
duke@435: }
duke@435: 
duke@435: 
duke@435: // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
duke@435: // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
duke@435: // First patches the first word atomically to be a jump to itself.
duke@435: // Then patches the last byte  and then atomically patches the first word (4-bytes),
duke@435: // thus inserting the desired jump
duke@435: // This code is mt-safe with the following conditions: entry point is 4 byte aligned,
duke@435: // entry point is in same cache line as unverified entry point, and the instruction being
duke@435: // patched is >= 5 byte (size of patch).
duke@435: //
duke@435: // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
duke@435: // In C1 the restriction is enforced by CodeEmitter::method_entry
duke@435: //
duke@435: void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
duke@435:   // complete jump instruction (to be inserted) is in code_buffer;
duke@435:   unsigned char code_buffer[5];
duke@435:   code_buffer[0] = instruction_code;
duke@435:   intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
duke@435: #ifdef AMD64
duke@435:   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@435: #endif // AMD64
duke@435:   *(int32_t*)(code_buffer + 1) = (int32_t)disp;
duke@435: 
duke@435:   check_verified_entry_alignment(entry, verified_entry);
duke@435: 
duke@435:   // Can't call nativeJump_at() because it's asserts jump exists
duke@435:   NativeJump* n_jump = (NativeJump*) verified_entry;
duke@435: 
duke@435:   //First patch dummy jmp in place
duke@435: 
duke@435:   unsigned char patch[4];
duke@435:   assert(sizeof(patch)==sizeof(int32_t), "sanity check");
duke@435:   patch[0] = 0xEB;       // jmp rel8
duke@435:   patch[1] = 0xFE;       // jmp to self
duke@435:   patch[2] = 0xEB;
duke@435:   patch[3] = 0xFE;
duke@435: 
duke@435:   // First patch dummy jmp in place
duke@435:   *(int32_t*)verified_entry = *(int32_t *)patch;
duke@435: 
duke@435:   n_jump->wrote(0);
duke@435: 
duke@435:   // Patch 5th byte (from jump instruction)
duke@435:   verified_entry[4] = code_buffer[4];
duke@435: 
duke@435:   n_jump->wrote(4);
duke@435: 
duke@435:   // Patch bytes 0-3 (from jump instruction)
duke@435:   *(int32_t*)verified_entry = *(int32_t *)code_buffer;
duke@435:   // Invalidate.  Opteron requires a flush after every write.
duke@435:   n_jump->wrote(0);
duke@435: 
duke@435: }
duke@435: 
duke@435: void NativePopReg::insert(address code_pos, Register reg) {
duke@435:   assert(reg->encoding() < 8, "no space for REX");
duke@435:   assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
duke@435:   *code_pos = (u_char)(instruction_code | reg->encoding());
duke@435:   ICache::invalidate_range(code_pos, instruction_size);
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeIllegalInstruction::insert(address code_pos) {
duke@435:   assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
duke@435:   *(short *)code_pos = instruction_code;
duke@435:   ICache::invalidate_range(code_pos, instruction_size);
duke@435: }
duke@435: 
duke@435: void NativeGeneralJump::verify() {
duke@435:   assert(((NativeInstruction *)this)->is_jump() ||
duke@435:          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
duke@435: }
duke@435: 
duke@435: 
duke@435: void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
duke@435:   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@435: #ifdef AMD64
duke@435:   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@435: #endif // AMD64
duke@435: 
duke@435:   *code_pos = unconditional_long_jump;
duke@435:   *((int32_t *)(code_pos+1)) = (int32_t) disp;
duke@435:   ICache::invalidate_range(code_pos, instruction_size);
duke@435: }
duke@435: 
duke@435: 
duke@435: // MT-safe patching of a long jump instruction.
duke@435: // First patches first word of instruction to two jmp's that jmps to them
duke@435: // selfs (spinlock). Then patches the last byte, and then atomicly replaces
duke@435: // the jmp's with the first 4 byte of the new instruction.
duke@435: void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
duke@435:    assert (instr_addr != NULL, "illegal address for code patching (4)");
duke@435:    NativeGeneralJump* n_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a jump
duke@435: 
duke@435:    // Temporary code
duke@435:    unsigned char patch[4];
duke@435:    assert(sizeof(patch)==sizeof(int32_t), "sanity check");
duke@435:    patch[0] = 0xEB;       // jmp rel8
duke@435:    patch[1] = 0xFE;       // jmp to self
duke@435:    patch[2] = 0xEB;
duke@435:    patch[3] = 0xFE;
duke@435: 
duke@435:    // First patch dummy jmp in place
duke@435:    *(int32_t*)instr_addr = *(int32_t *)patch;
duke@435:     n_jump->wrote(0);
duke@435: 
duke@435:    // Patch 4th byte
duke@435:    instr_addr[4] = code_buffer[4];
duke@435: 
duke@435:     n_jump->wrote(4);
duke@435: 
duke@435:    // Patch bytes 0-3
duke@435:    *(jint*)instr_addr = *(jint *)code_buffer;
duke@435: 
duke@435:     n_jump->wrote(0);
duke@435: 
duke@435: #ifdef ASSERT
duke@435:    // verify patching
duke@435:    for ( int i = 0; i < instruction_size; i++) {
duke@435:      address ptr = (address)((intptr_t)code_buffer + i);
duke@435:      int a_byte = (*ptr) & 0xFF;
duke@435:      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
duke@435:    }
duke@435: #endif
duke@435: 
duke@435: }
duke@435: 
duke@435: 
duke@435: 
duke@435: address NativeGeneralJump::jump_destination() const {
duke@435:   int op_code = ubyte_at(0);
duke@435:   bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
duke@435:   int  offset  = (op_code == 0x0F)  ? 2 : 1;
duke@435:   int  length  = offset + ((is_rel32off) ? 4 : 1);
duke@435: 
duke@435:   if (is_rel32off)
duke@435:     return addr_at(0) + length + int_at(offset);
duke@435:   else
duke@435:     return addr_at(0) + length + sbyte_at(offset);
duke@435: }
kamg@551: 
kamg@551: bool NativeInstruction::is_dtrace_trap() {
kamg@551:   return (*(int32_t*)this & 0xff) == 0xcc;
kamg@551: }