duke@435: /*
duke@435:  * Copyright 1997-2004 Sun Microsystems, Inc.  All Rights Reserved.
duke@435:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435:  *
duke@435:  * This code is free software; you can redistribute it and/or modify it
duke@435:  * under the terms of the GNU General Public License version 2 only, as
duke@435:  * published by the Free Software Foundation.
duke@435:  *
duke@435:  * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
duke@435:  * version 2 for more details (a copy is included in the LICENSE file that
duke@435:  * accompanied this code).
duke@435:  *
duke@435:  * You should have received a copy of the GNU General Public License version
duke@435:  * 2 along with this work; if not, write to the Free Software Foundation,
duke@435:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435:  *
duke@435:  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435:  * CA 95054 USA or visit www.sun.com if you need additional information or
duke@435:  * have any questions.
duke@435:  *
duke@435:  */
duke@435: 
duke@435: // Interface for updating the instruction cache.  Whenever the VM modifies
duke@435: // code, part of the processor instruction cache potentially has to be flushed.
duke@435: 
duke@435: // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
duke@435: // after the next jump, and the VM never modifies instructions directly ahead
duke@435: // of the instruction fetch path.
duke@435: 
duke@435: // [phh] It's not clear that the above comment is correct, because on an MP
duke@435: // system where the dcaches are not snooped, only the thread doing the invalidate
duke@435: // will see the update.  Even in the snooped case, a memory fence would be
duke@435: // necessary if stores weren't ordered.  Fortunately, they are on all known
duke@435: // x86 implementations.
duke@435: 
duke@435: class ICache : public AbstractICache {
duke@435:  public:
duke@435: #ifdef AMD64
duke@435:   enum {
duke@435:     stub_size      = 64, // Size of the icache flush stub in bytes
duke@435:     line_size      = 32, // Icache line size in bytes
duke@435:     log2_line_size = 5   // log2(line_size)
duke@435:   };
duke@435: 
duke@435:   // Use default implementation
duke@435: #else
duke@435:   enum {
duke@435:     stub_size      = 16,                 // Size of the icache flush stub in bytes
duke@435:     line_size      = BytesPerWord,      // conservative
duke@435:     log2_line_size = LogBytesPerWord    // log2(line_size)
duke@435:   };
duke@435: #endif // AMD64
duke@435: };