aoqi@0: /*
dlong@7598:  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
aoqi@0:  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0:  *
aoqi@0:  * This code is free software; you can redistribute it and/or modify it
aoqi@0:  * under the terms of the GNU General Public License version 2 only, as
aoqi@0:  * published by the Free Software Foundation.
aoqi@0:  *
aoqi@0:  * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
aoqi@0:  * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0:  * accompanied this code).
aoqi@0:  *
aoqi@0:  * You should have received a copy of the GNU General Public License version
aoqi@0:  * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0:  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0:  *
aoqi@0:  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0:  * or visit www.oracle.com if you need additional information or have any
aoqi@0:  * questions.
aoqi@0:  *
aoqi@0:  */
aoqi@0: 
aoqi@1: /*
aoqi@1:  * This file has been modified by Loongson Technology in 2015. These
aoqi@1:  * modifications are Copyright (c) 2015 Loongson Technology, and are made
aoqi@1:  * available on the same license terms set forth above.
aoqi@1:  */
aoqi@1: 
aoqi@0: #ifndef SHARE_VM_OPTO_REGMASK_HPP
aoqi@0: #define SHARE_VM_OPTO_REGMASK_HPP
aoqi@0: 
aoqi@0: #include "code/vmreg.hpp"
aoqi@0: #include "libadt/port.hpp"
aoqi@0: #include "opto/optoreg.hpp"
dlong@7598: #if defined ADGLOBALS_MD_HPP
dlong@7598: # include ADGLOBALS_MD_HPP
dlong@7598: #elif defined TARGET_ARCH_MODEL_x86_32
aoqi@0: # include "adfiles/adGlobals_x86_32.hpp"
dlong@7598: #elif defined TARGET_ARCH_MODEL_x86_64
aoqi@0: # include "adfiles/adGlobals_x86_64.hpp"
dlong@7598: #elif defined TARGET_ARCH_MODEL_sparc
goetz@6441: # include "adfiles/adGlobals_sparc.hpp"
dlong@7598: #elif defined TARGET_ARCH_MODEL_zero
goetz@6441: # include "adfiles/adGlobals_zero.hpp"
dlong@7598: #elif defined TARGET_ARCH_MODEL_ppc_64
goetz@6441: # include "adfiles/adGlobals_ppc_64.hpp"
aoqi@7994: #elif defined TARGET_ARCH_MODEL_mips_64
aoqi@1: # include "adfiles/adGlobals_mips_64.hpp"
aoqi@1: #endif
aoqi@0: 
aoqi@0: // Some fun naming (textual) substitutions:
aoqi@0: //
aoqi@0: // RegMask::get_low_elem() ==> RegMask::find_first_elem()
aoqi@0: // RegMask::Special        ==> RegMask::Empty
aoqi@0: // RegMask::_flags         ==> RegMask::is_AllStack()
aoqi@0: // RegMask::operator<<=()  ==> RegMask::Insert()
aoqi@0: // RegMask::operator>>=()  ==> RegMask::Remove()
aoqi@0: // RegMask::Union()        ==> RegMask::OR
aoqi@0: // RegMask::Inter()        ==> RegMask::AND
aoqi@0: //
aoqi@0: // OptoRegister::RegName   ==> OptoReg::Name
aoqi@0: //
aoqi@0: // OptoReg::stack0()       ==> _last_Mach_Reg  or ZERO in core version
aoqi@0: //
aoqi@0: // numregs in chaitin      ==> proper degree in chaitin
aoqi@0: 
aoqi@0: //-------------Non-zero bit search methods used by RegMask---------------------
aoqi@0: // Find lowest 1, or return 32 if empty
aoqi@0: int find_lowest_bit( uint32 mask );
aoqi@0: // Find highest 1, or return 32 if empty
aoqi@0: int find_hihghest_bit( uint32 mask );
aoqi@0: 
aoqi@0: //------------------------------RegMask----------------------------------------
aoqi@0: // The ADL file describes how to print the machine-specific registers, as well
aoqi@0: // as any notion of register classes.  We provide a register mask, which is
aoqi@0: // just a collection of Register numbers.
aoqi@0: 
aoqi@0: // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
aoqi@0: // RM_SIZE is the size of a register mask in words.
aoqi@0: // FORALL_BODY replicates a BODY macro once per word in the register mask.
aoqi@0: // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
aoqi@0: // However, it means the ADLC can redefine the unroll macro and all loops
aoqi@0: // over register masks will be unrolled by the correct amount.
aoqi@0: 
aoqi@0: class RegMask VALUE_OBJ_CLASS_SPEC {
aoqi@0:   union {
aoqi@0:     double _dummy_force_double_alignment[RM_SIZE>>1];
aoqi@0:     // Array of Register Mask bits.  This array is large enough to cover
aoqi@0:     // all the machine registers and all parameters that need to be passed
aoqi@0:     // on the stack (stack registers) up to some interesting limit.  Methods
aoqi@0:     // that need more parameters will NOT be compiled.  On Intel, the limit
aoqi@0:     // is something like 90+ parameters.
aoqi@0:     int _A[RM_SIZE];
aoqi@0:   };
aoqi@0: 
aoqi@0:   enum {
aoqi@0:     _WordBits    = BitsPerInt,
aoqi@0:     _LogWordBits = LogBitsPerInt,
aoqi@0:     _RM_SIZE     = RM_SIZE   // local constant, imported, then hidden by #undef
aoqi@0:   };
aoqi@0: 
aoqi@0: public:
aoqi@0:   enum { CHUNK_SIZE = RM_SIZE*_WordBits };
aoqi@0: 
aoqi@0:   // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
aoqi@0:   // Also, consider the maximum alignment size for a normally allocated
aoqi@0:   // value.  Since we allocate register pairs but not register quads (at
aoqi@0:   // present), this alignment is SlotsPerLong (== 2).  A normally
aoqi@0:   // aligned allocated register is either a single register, or a pair
aoqi@0:   // of adjacent registers, the lower-numbered being even.
aoqi@0:   // See also is_aligned_Pairs() below, and the padding added before
aoqi@0:   // Matcher::_new_SP to keep allocated pairs aligned properly.
aoqi@0:   // If we ever go to quad-word allocations, SlotsPerQuad will become
aoqi@0:   // the controlling alignment constraint.  Note that this alignment
aoqi@0:   // requirement is internal to the allocator, and independent of any
aoqi@0:   // particular platform.
aoqi@0:   enum { SlotsPerLong = 2,
aoqi@0:          SlotsPerVecS = 1,
aoqi@0:          SlotsPerVecD = 2,
aoqi@0:          SlotsPerVecX = 4,
aoqi@0:          SlotsPerVecY = 8 };
aoqi@0: 
aoqi@0:   // A constructor only used by the ADLC output.  All mask fields are filled
aoqi@0:   // in directly.  Calls to this look something like RM(1,2,3,4);
aoqi@0:   RegMask(
aoqi@0: #   define BODY(I) int a##I,
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:     int dummy = 0 ) {
aoqi@0: #   define BODY(I) _A[I] = a##I;
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Handy copying constructor
aoqi@0:   RegMask( RegMask *rm ) {
aoqi@0: #   define BODY(I) _A[I] = rm->_A[I];
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Construct an empty mask
aoqi@0:   RegMask( ) { Clear(); }
aoqi@0: 
aoqi@0:   // Construct a mask with a single bit
aoqi@0:   RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
aoqi@0: 
aoqi@0:   // Check for register being in mask
aoqi@0:   int Member( OptoReg::Name reg ) const {
aoqi@0:     assert( reg < CHUNK_SIZE, "" );
aoqi@0:     return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
aoqi@0:   }
aoqi@0: 
aoqi@0:   // The last bit in the register mask indicates that the mask should repeat
aoqi@0:   // indefinitely with ONE bits.  Returns TRUE if mask is infinite or
aoqi@0:   // unbounded in size.  Returns FALSE if mask is finite size.
aoqi@0:   int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
aoqi@0: 
aoqi@0:   // Work around an -xO3 optimization problme in WS6U1. The old way:
aoqi@0:   //   void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
aoqi@0:   // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
aoqi@0:   // follows an Insert() loop, like the one found in init_spill_mask(). Using
aoqi@0:   // Insert() instead works because the index into _A in computed instead of
aoqi@0:   // constant.  See bug 4665841.
aoqi@0:   void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
aoqi@0: 
aoqi@0:   // Test for being a not-empty mask.
aoqi@0:   int is_NotEmpty( ) const {
aoqi@0:     int tmp = 0;
aoqi@0: #   define BODY(I) tmp |= _A[I];
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:     return tmp;
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Find lowest-numbered register from mask, or BAD if mask is empty.
aoqi@0:   OptoReg::Name find_first_elem() const {
aoqi@0:     int base, bits;
aoqi@0: #   define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:       { base = OptoReg::Bad; bits = 1<<0; }
aoqi@0:     return OptoReg::Name(base + find_lowest_bit(bits));
aoqi@0:   }
aoqi@0:   // Get highest-numbered register from mask, or BAD if mask is empty.
aoqi@0:   OptoReg::Name find_last_elem() const {
aoqi@0:     int base, bits;
aoqi@0: #   define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:       { base = OptoReg::Bad; bits = 1<<0; }
aoqi@0:     return OptoReg::Name(base + find_hihghest_bit(bits));
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Find the lowest-numbered register pair in the mask.  Return the
aoqi@0:   // HIGHEST register number in the pair, or BAD if no pairs.
aoqi@0:   // Assert that the mask contains only bit pairs.
aoqi@0:   OptoReg::Name find_first_pair() const;
aoqi@0: 
aoqi@0:   // Clear out partial bits; leave only aligned adjacent bit pairs.
aoqi@0:   void clear_to_pairs();
aoqi@0:   // Smear out partial bits; leave only aligned adjacent bit pairs.
aoqi@0:   void smear_to_pairs();
aoqi@0:   // Verify that the mask contains only aligned adjacent bit pairs
aoqi@0:   void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
aoqi@0:   // Test that the mask contains only aligned adjacent bit pairs
aoqi@0:   bool is_aligned_pairs() const;
aoqi@0: 
aoqi@0:   // mask is a pair of misaligned registers
aoqi@0:   bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
aoqi@0:   // Test for single register
aoqi@0:   int is_bound1() const;
aoqi@0:   // Test for a single adjacent pair
aoqi@0:   int is_bound_pair() const;
aoqi@0:   // Test for a single adjacent set of ideal register's size.
aoqi@0:   int is_bound(uint ireg) const {
aoqi@0:     if (is_vector(ireg)) {
aoqi@0:       if (is_bound_set(num_registers(ireg)))
aoqi@0:         return true;
aoqi@0:     } else if (is_bound1() || is_bound_pair()) {
aoqi@0:       return true;
aoqi@0:     }
aoqi@0:     return false;
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Find the lowest-numbered register set in the mask.  Return the
aoqi@0:   // HIGHEST register number in the set, or BAD if no sets.
aoqi@0:   // Assert that the mask contains only bit sets.
aoqi@0:   OptoReg::Name find_first_set(const int size) const;
aoqi@0: 
aoqi@0:   // Clear out partial bits; leave only aligned adjacent bit sets of size.
aoqi@0:   void clear_to_sets(const int size);
aoqi@0:   // Smear out partial bits to aligned adjacent bit sets.
aoqi@0:   void smear_to_sets(const int size);
aoqi@0:   // Verify that the mask contains only aligned adjacent bit sets
aoqi@0:   void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
aoqi@0:   // Test that the mask contains only aligned adjacent bit sets
aoqi@0:   bool is_aligned_sets(const int size) const;
aoqi@0: 
aoqi@0:   // mask is a set of misaligned registers
aoqi@0:   bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
aoqi@0: 
aoqi@0:   // Test for a single adjacent set
aoqi@0:   int is_bound_set(const int size) const;
aoqi@0: 
aoqi@0:   static bool is_vector(uint ireg);
aoqi@0:   static int num_registers(uint ireg);
aoqi@0: 
aoqi@0:   // Fast overlap test.  Non-zero if any registers in common.
aoqi@0:   int overlap( const RegMask &rm ) const {
aoqi@0:     return
aoqi@0: #   define BODY(I) (_A[I] & rm._A[I]) |
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:     0 ;
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Special test for register pressure based splitting
aoqi@0:   // UP means register only, Register plus stack, or stack only is DOWN
aoqi@0:   bool is_UP() const;
aoqi@0: 
aoqi@0:   // Clear a register mask
aoqi@0:   void Clear( ) {
aoqi@0: #   define BODY(I) _A[I] = 0;
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Fill a register mask with 1's
aoqi@0:   void Set_All( ) {
aoqi@0: #   define BODY(I) _A[I] = -1;
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Insert register into mask
aoqi@0:   void Insert( OptoReg::Name reg ) {
aoqi@0:     assert( reg < CHUNK_SIZE, "" );
aoqi@0:     _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Remove register from mask
aoqi@0:   void Remove( OptoReg::Name reg ) {
aoqi@0:     assert( reg < CHUNK_SIZE, "" );
aoqi@0:     _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
aoqi@0:   }
aoqi@0: 
aoqi@0:   // OR 'rm' into 'this'
aoqi@0:   void OR( const RegMask &rm ) {
aoqi@0: #   define BODY(I) this->_A[I] |= rm._A[I];
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // AND 'rm' into 'this'
aoqi@0:   void AND( const RegMask &rm ) {
aoqi@0: #   define BODY(I) this->_A[I] &= rm._A[I];
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Subtract 'rm' from 'this'
aoqi@0:   void SUBTRACT( const RegMask &rm ) {
aoqi@0: #   define BODY(I) _A[I] &= ~rm._A[I];
aoqi@0:     FORALL_BODY
aoqi@0: #   undef BODY
aoqi@0:   }
aoqi@0: 
aoqi@0:   // Compute size of register mask: number of bits
aoqi@0:   uint Size() const;
aoqi@0: 
aoqi@0: #ifndef PRODUCT
aoqi@0:   void print() const { dump(); }
aoqi@0:   void dump(outputStream *st = tty) const; // Print a mask
aoqi@0: #endif
aoqi@0: 
aoqi@0:   static const RegMask Empty;   // Common empty mask
aoqi@0: 
aoqi@0:   static bool can_represent(OptoReg::Name reg) {
aoqi@0:     // NOTE: -1 in computation reflects the usage of the last
aoqi@0:     //       bit of the regmask as an infinite stack flag and
aoqi@0:     //       -7 is to keep mask aligned for largest value (VecY).
aoqi@0:     return (int)reg < (int)(CHUNK_SIZE-1);
aoqi@0:   }
aoqi@0:   static bool can_represent_arg(OptoReg::Name reg) {
aoqi@0:     // NOTE: -SlotsPerVecY in computation reflects the need
aoqi@0:     //       to keep mask aligned for largest value (VecY).
aoqi@0:     return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY);
aoqi@0:   }
aoqi@0: };
aoqi@0: 
aoqi@0: // Do not use this constant directly in client code!
aoqi@0: #undef RM_SIZE
aoqi@0: 
aoqi@0: #endif // SHARE_VM_OPTO_REGMASK_HPP